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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
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8MB Double Data Rate HSTL I/O Fast SRAM
The MCM64E918/MCM64E836 are 8M-bit pipelined burst synchronous late write fast static RAMs designed to provide very high data bandwidth in secondary cache applications. The MCM64E918 (organized as 512K words by 18 bits wide) and the MCM64E836 (organized as 256K words by 36 bits wide) are fabricated in Motorola's high performance silicon gate MOS technology. The differential clock (CK) inputs control the timing of read/write operations of the RAM. At the rising edge of CK, all addresses and burst control inputs are registered. An internal buffer and special logic enables the memory to accept write data on the rising or rising and falling edges of the clock, a cycle following address and control signals. Read data is driven on the rising or rising and falling edges of the CK clock and is referenced to echo clock (CQ and CQ) outputs. The MCM64E918/MCM64E836 have HSTL inputs and outputs. The adjustable input trip-point (Vref) and output power supply voltage (V DDQ) gives the system designer greater flexibility in optimizing system performance. The impedance of the output buffers is programmable, allowing the outputs to match the impedance of the circuit traces, which reduces signal reflections. * Single 2.5 V 5% Power Supply * Single Data Rate (SDR) and Double Data Rate (DDR) Burst Read and Write * Pin Selectable Linear or Interleaved Burst Order * Four Tick Burst with Automatic Wrap-Around * Differential Clock Inputs * Active High and Active Low Echo Clock Outputs * 1.8 V Expanded HSTL -- I/O (JEDEC Standard JESD8-6 Class I Compatible) * 1.8 V Expanded HSTL -- Compatible Programmable Impedance Output Drivers * Pipelined (Register to Register) Synchronous Operation * Boundary Scan (JTAG) IEEE 1149.1 Compatible * Stop Clock Functionality Supported * Optional x18 or x36 Organization * MCM64E918/MCM64E836-3.0 = 3.0 ns Clock Cycle Time MCM64E918/MCM64E836-3.3 = 3.3 ns Clock Cycle Time MCM64E918/MCM64E836-4.0 = 4.0 ns Clock Cycle Time * 9 x 17 (153) Bump, 50 mil (1.27 mm) Pitch, 14 mm x 22 mm Flipped Chip Plastic Ball Grid Array (PBGA) package
MCM64E918 MCM64E836
FC PACKAGE FLIPPED CHIP PBGA CASE 1107C-03
REV2 7/2/01
Motorola, Inc. 2001 MOTOROLA FAST SRAM
MCM64E918*MCM64E836 1
PIN ASSIGNMENTS
1 A B C D E F G H J K L M N P R T U VSS NC VSS DQ VSS NC VSS DQ VSS NC VSS DQ VSS NC VSS DQ VSS 2 VDDQ DQ VDDQ NC VDDQ CQ VDDQ NC VDDQ DQ VDDQ NC VDDQ DQ VDDQ NC VDDQ 3 SA SA SA NC VSS NC VSS DQ VSS NC VSS DQ VSS SA VDD SA TMS 4 SA VSS SA VSS VDD VDD VSS VDD VDD VSS LBO VDD VDD VSS SA VSS TDI 5 ZQ B1 G VDD Vref VDD CK CK VDD B2 B3 VDD Vref VDD SA1 SA0 6 SA VSS SA VSS VDD VDD VSS VDD VDD VSS NC VDD VDD VSS SA VSS 7 SA SA SA SA VSS DQ VSS NC VSS DQ VSS NC VSS SA VDD SA NC 8 VDDQ NC VDDQ DQ VDDQ NC VDDQ DQ VDDQ NC VDDQ CQ VDDQ NC VDDQ DQ VDDQ 9 VSS DQ VSS NC VSS DQ VSS NC VSS DQ VSS NC VSS DQ VSS NC VSS A B C D E F G H J K L M N P R T U 1 VSS DQ VSS DQ VSS DQ VSS DQ VSS DQ VSS DQ VSS DQ VSS DQ VSS 2 VDDQ DQ VDDQ DQ 3 SA SA SA NC 4 SA VSS SA VSS VDD VDD VSS VDD VDD VSS LBO VDD VDD VSS SA VSS TDI 5 ZQ B1 G VDD Vref VDD CK CK VDD B2 B3 VDD Vref VDD SA1 SA0 6 SA VSS SA VSS VDD VDD VSS VDD VDD VSS NC VDD VDD VSS SA VSS 7 SA SA SA SA VSS DQ VSS DQ VSS DQ VSS DQ VSS SA VDD SA NC 8 VDDQ DQ VDDQ DQ VDDQ CQ VDDQ DQ VDDQ DQ VDDQ CQ VDDQ DQ VDDQ DQ VDDQ 9 VSS DQ VSS DQ VSS DQ VSS DQ VSS DQ VSS DQ VSS DQ VSS DQ VSS
VDDQ VSS CQ VDDQ DQ DQ VSS DQ
VDDQ VSS DQ DQ
VDDQ VSS CQ VDDQ DQ VDDQ DQ VDDQ DQ VSS NC VDD SA TMS
TCK* TDO
TCK* TDO
MCM64E918 TOP VIEW 153-BUMP * If JTAG is not used, TCK pin must be tied to VDD or VSS.
MCM64E836 TOP VIEW 153-BUMP
MCM64E918*MCM64E836 2
MOTOROLA FAST SRAM
MCM64E918 x18 PIN DESCRIPTIONS
Pin Locations 5B 5K 5L 5G 5H 2F 8M 2B, 9B, 1D, 8D, 7F, 9F, 1H, 3H, 8H, 2K, 7K, 9K, 1M, 3M, 2P, 9P, 1T, 8T 5C 4L Symbol B1 B2 B3 CK CK CQ CQ DQ G LBO Type Input Input Input Input Input Output Output I/O Input Input Description Synchronous Function Control Input: B1 = 0 initiates a load new address. Synchronous Function Control Input: B2 = 0 initiates a WRITE, B2 = 1 initiates a READ. Synchronous Function Control Input: B3 = 0 initiates a double (or burst) operation, B3 = 1 initiates a single operation. Address, data in, and control input register clock. Active high. Address, data in, and control input register clock. Active low. Echo Clock Output: Active high. Echo Clock Output: Active low. Synchronous data I/O. Output Enable functionality not supported. Must be tied to VSS or driven to VIL Max. Linear Burst Order: This is a mode pin. It must be tied to VDD or VSS before power up. LBO = 1 selects interleaved mode. LBO = 0 selects linear mode. Synchronous Address Inputs: Registered on the rising clock edge. Synchronous burst counter preload address inputs: SA0 = LSB. JTAG pin, test clock. If JTAG is not used, TCK must be tied to VSS or VDD. JTAG pin, Test Data In. JTAG, Test Data Out. JTAG pin. Input Supply Supply Supply Supply Output impedance programming input. Input Reference: Provides reference voltage for input buffers. Core Power Supply: These pins act as thermal vias to PCB power plane. Output Power Supply: Provides operating power for output buffers. Ground: These pins act as thermal vias to PCB ground plane.
3A, 4A, 6A, 7A, 3B, 7B, 3C, 4C, 6C, 7C, 7D, 3P, 7P, 4R, 6R, 3T, 7T 5R, 5T 5U 4U 6U 3U 5A 5E, 5N 5D, 4E, 6E, 4F, 5F, 6F, 4H, 6H, 4J, 5J, 6J, 4M, 5M, 6M, 4N, 6N, 5P, 3R, 7R 2A, 8A, 2C, 8C, 2E, 8E, 2G, 8G, 2J, 8J, 2L, 8L, 2N, 8N, 2R, 8R, 2U, 8U 1A, 9A, 4B, 6B, 1C, 9C, 4D, 6D, 1E, 3E, 7E, 9E, 1G, 3G, 4G, 6G, 7G, 9G, 1J, 3J, 7J, 9J, 4K, 6K, 1L, 3L, 7L, 9L, 1N, 3N, 7N, 9N, 4P, 6P, 1R, 9R, 4T, 6T, 1U, 9U 1B, 8B, 2D, 3D, 9D, 1F, 3F, 8F, 2H, 7H, 9H, 1K, 3K, 8K, 6L, 2M, 7M, 9M, 1P, 8P, 2T, 9T, 7U
SA SA1, SA0 TCK TDI TDO TMS ZQ Vref VDD VDDQ VSS
Input Input Input Input Output
NC
--
No Connection: This means there is no connection to the chip.
MOTOROLA FAST SRAM
MCM64E918*MCM64E836 3
MCM64E836 x36 PIN DESCRIPTIONS
Pin Locations 5B 5K 5L 5G 5H 2F, 8F 2M, 8M 1B, 2B, 8B, 9B, 1D, 2D, 8D, 9D, 1F, 3F, 7F, 9F, 1H, 2H, 3H, 7H, 8H, 9H, 1K, 2K, 3K, 7K, 8K, 9K, 1M, 3M, 7M, 9M, 1P, 2P, 8P, 9P, 1T, 2T, 8T, 9T 5C 4L Symbol B1 B2 B3 CK CK CQ CQ DQ Type Input Input Input Input Input Output Output I/O Description Synchronous Function Control Input: B1 = 0 initiates a load new address. Synchronous Function Control Input: B2 = 0 initiates a WRITE, B2 = 1 initiates a READ. Synchronous Function Control Input: B3 = 0 initiates a double (or burst) operation, B3 = 1 initiates a single operation. Address, data in, and control input register clock. Active high. Address, data in, and control input register clock. Active low. Echo Clock Output: Active high. Echo Clock Output: Active low. Synchronous data I/O.
G LBO
Input Input
Output Enable functionality not supported. Must be tied to VSS or driven to VIL Max. Linear Burst Order: This is a mode pin. It must be tied to VDD or VSS before power up. LBO = 1 selects interleaved mode. LBO = 0 selects linear mode. Synchronous Address Inputs: Registered on the rising clock edge. Synchronous burst counter preload address inputs: SA0 = LSB. JTAG pin, test clock. If JTAG is not used, TCK must be tied to VSS or VDD. JTAG pin, Test Data In. JTAG, Test Data Out. JTAG pin.
3A, 4A, 6A, 7A, 3B, 7B, 3C, 4C, 6C, 7C, 7D, 7P, 4R, 6R, 3T, 7T 5R, 5T 5U 4U 6U 3U 5A 5E, 5N 5D, 4E, 6E, 4F, 5F, 6F, 4H, 6H, 4J, 5J, 6J, 4M, 5M, 6M, 4N, 6N, 5P, 3R, 7R 2A, 8A, 2C, 8C, 2E, 8E, 2G, 8G, 2J, 8J, 2L, 8L, 2N, 8N, 2R, 8R, 2U, 8U 1A, 9A, 4B, 6B, 1C, 9C, 4D, 6D, 1E, 3E, 7E, 9E, 1G, 3G, 4G, 6G, 7G, 9G, 1J, 3J, 7J, 9J, 4K, 6K, 1L, 3L, 7L, 9L, 1N, 3N, 7N, 9N, 4P, 6P, 1R, 9R, 4T, 6T, 1U, 9U 3D, 6L, 3P, 7U
SA SA1, SA0 TCK TDI TDO TMS ZQ Vref VDD VDDQ VSS
Input Input Input Input Output
Input Supply Supply Supply Supply
Output impedance programming input. Input Reference: Provides reference voltage for input buffers. Core Power Supply: These pins act as thermal vias to PCB power plane. Output Power Supply: Provides operating power for output buffers. Ground: These pins act as thermal vias to PCB ground plane.
NC
--
No Connection: This means there is no connection to the chip.
MCM64E918*MCM64E836 4
MOTOROLA FAST SRAM
BUS CYCLE STATE DIAGRAM
READ SINGLE B1 B2, B3 B1 B2, B3 LOAD NEW ADDRESS B1 B2, B3 B1 B2, B3 WRITE SINGLE
B1, B2 B1, B2
ADVANCE ADDRESS BY ONE (SEE NOTE 1)
B1, B2 B1, B2 B1, B2
ADVANCE ADDRESS BY ONE (SEE NOTE 1)
B1
DESELECT ADVANCE ADDRESS BY TWO (SEE NOTE 1)
READ DOUBLE B1, B2
B1
SUPPLY VOLTAGE PROVIDED
B1, B2 WRITE DOUBLE B1, B2 ADVANCE ADDRESS BY TWO (SEE NOTE 1)
POWER UP
NOTE: 1. Advance internal address in accordance with burst order with wrap-around. Burst-length of four.
THREE-WIRE SYNCHRONOUS FUNCTION CONTROLS (See Notes 1 through 4)
B1 0 0 0 0 1 1 B2 0 0 1 1 1 0 B3 1 0 1 0 X X Function Launched at Next Clock Write Single, Load New Address Write Double, Load New Address Read Single, Load New Address Read Double, Load New Address Increment Address, Continue Previous Function Deselect, Pipeline High-Z D Next Edge Both Edges High-Z High-Z X X Q (n) High-Z High-Z Next CQ + Edge Both CQ Edges X X Q (n + 1) High-Z High-Z Next CQ + Edge Both CQ Edges X High-Z
NOTES: 1. X = don't care. 2. Deselect usage is discussed in the Functional Description section. 3. Outputs will be in high-Z during power up, except CQ and CQ. 4. Double reads and writes occur per burst sequence.
MOTOROLA FAST SRAM
MCM64E918*MCM64E836 5
BURST SEQUENCES
Interleaved Burst Binary Address Start -- Base Address 2nd Address 3rd Address 4th Address 0 1 2 3 1 0 3 2 Hex 2 3 0 1 3 2 1 0 SA1 0 0 1 1 SA0 0 1 0 1 SA1 0 0 1 1 SA0 1 0 1 0 SA1 1 1 0 0 SA0 0 1 0 1 SA1 1 1 0 0 SA0 1 0 1 0
Linear Burst Binary Address Start -- Base Address 2nd Address 3rd Address 4th Address 0 1 2 3 1 2 3 0 Hex 2 3 0 1 3 0 1 2 SA1 0 0 1 1 SA0 0 1 0 1 SA1 0 1 1 0 SA0 1 0 1 0 SA1 1 1 0 0 SA0 0 1 0 1 SA1 1 0 0 1 SA0 1 0 1 0
ABSOLUTE MAXIMUM RATINGS (See Note)
Rating Power Supply Voltage Relative to VSS Output Supply Voltage Voltage On Any Pin Other Than JTAG Voltage On Any JTAG Pin Input Current (per I/O) Output Current (per I/O) Operating Temperature Storage Temperature Symbol VDD VDDQ Vin VJTAG Iin Iout TA Tstg Value -0.5 to 3.6 -0.5 to 2.5 -0.5 to 2.5 -0.5 to 3.0 50 25 0 to 70 -55 to 125 Unit V V V V mA mA C C This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit. This CMOS memory circuit has been designed to meet the dc and ac specifications shown in the tables, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow of at least 500 linear feet per minute is maintained.
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability.
PBGA PACKAGE THERMAL CHARACTERISTICS
Rating Junction to Ambient (Still Air) Junction to Ambient (@200 ft/min) Junction to Ambient (@200 ft/min) Junction to Board (Bottom) Junction to Case (Top) Single-Layer Board Four-Layer Board Symbol RJA RJA RJA RJB RJC Max 50 39 27 23 1 Unit C/W C/W C/W C/W C/W Notes 1, 2 1, 2 3 4 5
NOTES: 1. Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 2. Per SEMI G38-87. 3. Measured using a four-layer test board with two internal planes. 4. Indicates the average thermal resistance between the die and the printed circuit board as measured by the ring cold plate method. 5. Indicates the average thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1).
MCM64E918*MCM64E836 6
MOTOROLA FAST SRAM
DC OPERATING CONDITIONS AND CHARACTERISTICS
(2.375 V VDD 2.625 V, 0C TA 70C, Unless Otherwise Noted) RECOMMENDED OPERATING CONDITIONS (See Notes 1 through 4)
Parameter Core Power Supply Voltage Output Driver Supply Voltage AC Supply Current (Device Selected, All Outputs Open, Freq = Max, VDD = Max, VDDQ = Max). Includes Supply Currents for VDD. Quiescent Active Power Supply Current (Device Selected, All Outputs Open, Freq = 0, VDD = Max, VDDQ = Max). Includes supply currents for VDD. Active Standby Power Supply Current (Device Deselected, Freq = Max, VDD = Max, VDDQ = Max) Stop Clock Current (Device Deselected, Freq = 0, VDD = Max, VDDQ = Max, All Inputs Static at CMOS Levels) Input Reference DC Voltage Symbol VDD VDDQ IDD1 Min 2.375 1.4 -- -- -- Max -3.0 -- -- 720 Max -3.3 -- -- 700 Max -4.0 -- -- 680 Max 2.625 1.9 -- Unit V V mA 5 Notes
IDD2
200
200
200
--
mA
6
ISB1 ISB2 Vref (dc)
-- -- 0.6
225 200 --
220 200 --
210 200 --
-- -- 1.3
mA mA V
7 6, 7 8
NOTES: 1. All data sheet parameters specified to full range of VDD unless otherwise noted. All voltages are referenced to voltage applied to VSS bumps. 2. Supply voltage applied to VDD connections. 3. Supply voltage applied to VDDQ connections. 4. All power supply currents measured with outputs open or deselected. 5. All inputs are toggling per CMOS I/O levels (see Note 6). 6. Input levels for I/Os are VSS Vin 0.2 V or VDDQ - 0.2 V Vin VDDQ. 7. Device deselected as defined by the Truth Table. 8. Although considerable latitude in the selection of the nominal dc value (i.e., rms value) of Vref is supported, the peak to peak ac component superimposed on Vref may not exceed 5% of the dc component of Vref.
DC CHARACTERISTICS AND POWER SUPPLY CURRENTS (See Notes 1 and 2)
Parameter DC Input Logic High DC Input Logic Low Input Leakage Current (All Inputs, Vin = 0 to VDDQ) Output Low Current (VOL = VDDQ/2) Output High Current (VOH = VDDQ/2) Light Load Output Logic Low IOL 100 A Light Load Output Logic High IOH 100 A Clock Input Signal Voltage Clock Input Differential Voltage (See Figure 2) Clock Input Common Mode Voltage Range (See Figure 2) Symbol VIH (DC) VIL (DC) Ilkg(I) IOL IOH VOL1 VOH1 Vin VDIF (DC) VCM (DC) Min Vref + 0.1 -0.5 -- (VDDQ/2) / [(RQ/5) + 15%] (VDDQ/2) / [(RQ/5) + 15%] VSS VDDQ - 0.2 -0.3 0.1 0.6 Typ -- -- -- -- -- -- -- -- -- -- Max VDDQ + 0.3 Vref - 0.1 5 (VDDQ/2) / [(RQ/5) - 15%] (VDDQ/2) / [(RQ/5) - 15%] 0.2 VDDQ VDDQ + 0.3 VDDQ + 0.6 1.3 Unit V V A V V V V V V V
NOTES: 1. The impedance controlled mode is expected to be used in point-to-point applications, driving high-impedance inputs. 2. The ZQ pin is connected through RQ to VSS for the controlled impedance mode.
MOTOROLA FAST SRAM
MCM64E918*MCM64E836 7
CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, 0C TA 70C, Periodically Sampled Rather Than 100% Tested)
Characteristic Input Capacitance I/O Capacitance All Inputs Except Clocks and DQs G and W DQ Symbol Cin Cck CI/O Typ 3.2 3.7 3.8 Max 5 5 6 Unit pF pF
AC OPERATING CONDITIONS AND CHARACTERISTICS
(2.375 V VDD 2.625 V, 1.4 V VDDQ 1.9 V, Unless Otherwise Noted)
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.25 V to 1.25 V Input Rise/Fall Time . . . . . . . . . . . . . . . . . . 1 V/500 ps (20% to 80%) Input Timing Measurement Reference Level . . . . . . . . . . . . . VDDQ/2 Output Timing Measurement Reference Level . . . . . . . . . . . VDDQ/2 Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . Differential Cross-Point RJA Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ~27C/W
READ AND WRITE CYCLE TIMING
64E918-3.0 64E836-3.0 Parameter Cycle Time CK Clock High Pulse Width CK Clock Low Pulse Width CQ Low to CQ High CQ High to CQ Low Setup Times: Address Valid to CK Crossing Burst Control Valid to CK Crossing Data In Valid to CK Crossing Hold Times: CK Crossing to Address Don't Care CK Crossing to Burst Control Don't Care CK Crossing to Data In Don't Care CK Crossing to CQ High CK Crossing to CQ Low CQ High to Output Valid CQ Low to Output Valid CQ High to Output Hold CQ Low to Output Hold CK High to Output Low-Z CQ High to Output High-Z Symbol tKHKH tKHKL tKLKH tCLCH tCHCL Min 3 1.2 1.2 Max -- -- -- 64E918-3.3 64E836-3.3 Min 3.3 1.3 1.3 Max -- -- -- 64E918-4.0 64E836-4.0 Min 4 1.6 1.6 Max -- -- -- Unit ns ns ns 2 2 1 1 Notes
tKLKH tKLKH tKLKH tKLKH tKLKH tKLKH - 100 ps + 100 ps - 100 ps + 100 ps - 100 ps + 100 ps tKHKL tKHKL tKHKL tKHKL tKHKL tKHKL - 100 ps + 100 ps - 100 ps + 100 ps - 100 ps + 100 ps 0.5 0.5 0.3 0.5 0.5 0.3 0.7 0.7 -- -- - 0.20 - 0.20 0.5 - 0.20 -- -- -- -- -- -- 1.5 1.5 0.20 0.20 -- -- -- 0.25 0.5 0.5 0.3 0.5 0.5 0.3 0.7 0.7 -- -- - 0.20 - 0.20 0.5 - 0.20 -- -- -- -- -- -- 1.65 1.65 0.20 0.20 -- -- -- 0.3 0.5 0.5 0.3 0.5 0.5 0.3 0.7 0.7 -- -- - 0.20 - 0.20 0.5 - 0.20 -- -- -- -- -- -- 2 2 0.20 0.20 -- -- -- 0.35 ns
tAVKH tBVKH tDVKX tKHAX tKHBX tKXDX tKXCH tKXCL tCHQV tCLQV tCHQX tCLQX tKHQX1 tCHQZ
1, 2
ns
1, 2
ns ns ns ns ns ns ns ns
1 1 1 1 1, 2 1, 2 1, 2, 3 1, 2, 4
NOTES: 1. Guaranteed by design and characterization. 2. This parameter sampled and not 100% tested. 3. Measured at 200 mV from steady state. See Figure 1a. 4. Measured at 200 mV from steady state. See Figure 1b. VDDQ/2 Vref DEVICE UNDER TEST ZQ 50 250 VDDQ/2 50 DQ 16.7
16.7
50 5 pF
50
VDDQ/2
16.7
50 5 pF VDDQ/2
50
VDDQ/2
(a) Test Load Figure 1. Test Loads
(b) Test Load
MCM64E918*MCM64E836 8
MOTOROLA FAST SRAM
AC INPUT CHARACTERISTICS (See Notes 1 through 3)
Parameter AC Input Logic High (See Figure 2) AC Input Logic Low (See Figure 3) Input Reference Peak-to-Peak AC Voltage Clock Input Differential Voltage Symbol VIH (ac) VIL (ac) Vref (ac) Vdif (ac) Min Vref + 200 mV -- -- 400 mV Max -- Vref - 200 mV 5% Vref (dc) VDDQ + 600 mV 4 Notes
NOTES: 1. Inputs may undershoot to VSS - 1 V (peak) for up to 35% tKHKH or 1.0 ns, whichever is smaller, and VSS - 1.5 V instantaneous peak undershoot. See Figure 3. 2. Inputs may overshoot to 3.3 V for up to 35% tKHKH or 1.0 ns, whichever is smaller, and 3.6 V instantaneous peak overshoot. 3. Minimum instantaneous differential input voltage required for differential input clock operation. 4. Although considerable latitude in the selection of the nominal dc value (i.e., rms value) of Vref is supported, the peak-to-peak ac component superimposed on Vref may not exceed 5% of the dc component of Vref.
VDDQ VTR CROSSING POINT VDIF VCP VSS * VCM, the Common Mode Input Voltage, equals VTR - [(VTR - VCP)/2]. VCM*
Figure 2. Differential Inputs/Common Mode Input Voltage
VIH
VSS VSS - 1 V VSS - 1.5 V 35% tKHKH or 1.0 ns, which ever is smaller
Figure 3. Undershoot Voltage
VIH(ac) Vref
VIL(ac)
Figure 4. Differential Inputs/Common Mode Input Voltage
MOTOROLA FAST SRAM
MCM64E918*MCM64E836 9
FUNCTIONAL DESCRIPTION
USING DESELECT Function control pins B1:B2 set to 1:0 will be latched on a rising edge of the input clock (CK), and launch a deselect at the next CK clock (pipelined). Deselect puts the data bus into a high-impedance state. Deselect can be used to avoid bus contention by putting the data bus into a high-impedance state before performing a write. The sequence for switching from a read to a write should be: READ, DESELECT, WRITE. COHERENCY This part is fully coherent. This means that when a write is performed at an address, and a read of that same address follows immediately, the data just written is read back. BURSTING Function control pins are used to select single or double reads and writes. When a double read or write is selected, the data is managed on both the rising and falling edges of the echo clock, which is the double data rate feature of this FSRAM. All burst sequences are determined with the LBO pin per the Burst Sequence table. Function control pins B1:B2 set to 1:1 increments the address and continues the previous function. This combination of B1:B2 can immediately follow any of the other read or write functions. As long as the B1:B2 pins are set to 1:1 on rising edges of the input clock, a continuous read or write from sequential addresses can be performed without having to resupply the address (refer to the Bus Cycle State diagram and Three-Wire Synchronous Function Control table). READS/WRITES The DDR latches address and control lines on the rising edge of the input (CK) clock. Single reads are selected by setting function control lines B1:B2:B3 = 0:1:1. This functionality resembles the non-burst read timing of a pipelined BurstRAM (pre-DDR). Only 1 byte of data will result from each address and control clocked into the part. Data changes only on the rising edge of the clock. Double reads are selected by setting B1:B2:B3 = 0:1:0. This will cause a burst of two, but at twice the input clock rate. Data is available after the rising and the falling clock
edges of the output clock (refer to the Double and Single Read Timing diagram). Single writes have late write functionality. Single writes are selected with B1:B2:B3 = 0:0:1. Data In must meet setup and hold times with respect to the rising edge of the input clock, CK. Double writes are also late writes. Double writes are selected with B1:B2:B3 = 0:0:0. The data rate is twice the applied clock in a double write, so Data In must meet setup and hold times with respect to the rising and falling edges of the input clock, CK. ECHO CLOCK This part is equipped with an echo clock. The echo clock is an output clock that aids in the synchronization of data. After power up, the echo clock is free running. The data that is output during a read cycle is referenced to the echo clock outputs. STARTUP CONDITIONS/STOP CLOCK Power up conditions are expected to vary from application to application. Echo clocks (CQ and CQ) are not pipelined, and will respond to the input clock (CK) immediately. One way to design for this situation is to power up and start the DDR, run until all signals are transitioning smoothly, and then stop the clock and start it again, using the echo clock edges after the stop clock and not before the stop clock. This will allow for synchronization of the echo clock. The stop clock can be used anywhere as long as the minimum and maximum clock pulse specifications are not violated. OUTPUT IMPEDANCE CIRCUITRY The designer can program the RAMs output buffer impedance by terminating the ZQ pin to VSS through a precision resistor (RQ). The value of RQ is five times the output impedance desired. For example, a 250 resistor will give an output impedance of 50 . Impedance updates occur during write and deselect cycles. The actual change in the impedance occurs in small increments and is binary. The binary impedance has 256 values and therefore, there are no significant disturbances that occur on the output because of this smooth update method. At power up, the output impedance will take up to 65,000 cycles for the impedance to be completely updated.
MCM64E918*MCM64E836 10
MOTOROLA FAST SRAM
DOUBLE AND SINGLE READ TIMING
READ tKHKH READ tKLKH HIGH-Z
tKHKL CK CK tAVKH SA tKHAX tBVKH FUNCTION CONTROL B1, B2, B3 tKHBX A
B
X
X
B1, B2, B3
B1, B2, X
X
CQ CQ
tKXCH (MIN/MAX) tKXCL (MIN/MAX)
tCHQX (MIN) tCHQV (MAX)
tCLQX (MIN) tCLQV (MAX) A1 A2 B
tCHQX (MIN)
DQ
DOUBLE WRITE TIMING
WRITE WRITE CONTINUE BURST HIGH-Z
CK CK
SA
F
X
X
X
FUNCTION CONTROL
B1, B2, B3
B1, B2, X
B1, B2, X
X
CQ CQ tDVKX DQ tKXDX F1 F2 F3 F4
MOTOROLA FAST SRAM
MCM64E918*MCM64E836 11
SINGLE WRITE TIMING
WRITE WRITE CONTINUE BURST HIGH-Z
CK CK
SA
F
X
X
X
FUNCTION CONTROL
B1, B2, B3
B1, B2, X
B1, B2, X
X
CQ CQ tDVKX DQ F1 tKHDX F2
MCM64E918*MCM64E836 12
MOTOROLA FAST SRAM
WRITE AND READ TIMING
WRITE WRITE READ READ CONTINUE BURST HIGH-Z
CK CK
SA
C
D
E
X
X
FUNCTION CONTROL
B1, B2, B3
B1, B2, B3
B1, B2, B3
B1, B2, X
B1, B2, X
CQ CQ tDVKX DQ tKXDX C1 C2 D1 D2 E1 E2 E3 E4
READ AND WRITE TIMING
READ HIGH-Z WRITE WRITE CONTINUE BURST HIGH-Z
CK CK
SA
C
X
E
X
X
FUNCTION B1, B2, B3 CONTROL
B1, B2, X
B1, B2, B3
B1, B2, X
B1, B2, X
CQ CQ tDVKX DQ C1 C2 tKXDX E1 E2 E3 E4
MOTOROLA FAST SRAM
MCM64E918*MCM64E836 13
SERIAL BOUNDARY SCAN TEST ACCESS PORT OPERATION
OVERVIEW The serial boundary scan test access port (TAP) on this RAM is designed to operate in a manner consistent with IEEE Standard 1149.1-1990 (commonly referred to as JTAG), but does not implement all of the functions required for IEEE 1149.1 compliance. Certain functions have been modified or eliminated because their implementation places extra delays in the RAMs critical speed path. Nevertheless, the RAM supports the standard TAP controller architecture (the TAP controller is the state machine that controls the TAPs operation) and can be expected to function in a manner that does not conflict with the operation of devices with IEEE 1149.1 compliant TAPs. The TAP operates using conventional JEDEC Standard 8-5 (2.5 V) logic level signaling. DISABLING THE TEST ACCESS PORT It is possible to use this device without utilizing the TAP. To disable the TAP controller without interfering with normal operation of the device, TCK must be tied to VSS to preclude mid-level inputs. TDI and TMS are designed so an undriven input will produce a response identical to the application of a logic 1, and may be left unconnected. But they may also be tied to VDD through a 1 k resistor. TDO should be left unconnected.
TAP DC OPERATING CHARACTERISTICS
(2.375 V VDD 2.625 V, 0C TA 70C, Unless Otherwise Noted)
Parameter Logic Input Logic High Logic Input Logic Low Logic Input Leakage Current CMOS Output Logic Low CMOS Output Logic High NOTES: 1. 0 V Vin VDD for all logic input pins. 2. IOL1 100 A @ VOL = 0.2 V. Sampled, not 100% tested. 3. IOH1 100 A @ VDDQ - 0.2 V. Sampled, not 100% tested. Symbol VIH1 VIL1 Ilkg VOL1 VOH1 Min 1.2 - 0.3 -- -- VDDQ - 0.2 Max VDD + 0.3 0.4 5 0.2 -- Unit V V A V V 1 2 3 Notes
MCM64E918*MCM64E836 14
MOTOROLA FAST SRAM
TAP AC OPERATING CONDITIONS AND CHARACTERISTICS
(0C TA 70C, Unless Otherwise Noted)
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 2.2 V Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . 1 V/ns (20% to 80%) Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.1 V Output Timing Reference Level . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 V Output Test Load . . . . . 50 Parallel Terminated T-Line with 20 pF Receiver Input Capacitance Test Load Termination Supply Voltage (VT) . . . . . . . . . . . . . . . . 1.1 V
TAP CONTROLLER TIMING
Parameter Cycle Time Clock High Time Clock Low Time TMS Setup TMS Hold TDI Valid to TCK High TCK High to TDI Don't Care Capture Setup Capture Hold TCK Low to TDO Unknown TCK Low to TDO Valid Symbol tTHTH tTHTL tTLTH tMVTH tTHMX tDVTH tTHDX tCS tCH tTLQX tTLOV Min 100 40 40 10 10 10 10 10 10 0 -- Max -- -- -- -- -- -- -- -- -- -- 20 Unit ns ns ns ns ns ns ns ns ns ns ns 1 1 Notes
NOTE: 1. tCS + tCH defines the minimum pause in RAM I/O pad transitions to assure accurate pad data capture.
AC TEST LOAD
1.1 V DEVICE UNDER TEST 50 50 20 pF
TAP CONTROLLER TIMING DIAGRAM
tTHTH tTLTH TEST CLOCK (TCK) tTHTL tMVTH TEST MODE SELECT (TMS) tTHDX tDVTH TEST DATA IN (TDI) tTLQV tTLQX TEST DATA OUT (TDO) tTHMX
MOTOROLA FAST SRAM
MCM64E918*MCM64E836 15
TEST ACCESS PORT PINS
TCK -- TEST CLOCK (INPUT) Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate from the falling edge of TCK. TMS -- TEST MODE SELECT (INPUT) The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP controller state machine. An undriven TMS input will produce the same result as a logic 1 input level. TDI -- TEST DATA IN (INPUT) The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers placed between TDI and TDO. The register placed between TDI and TDO is determined by the state of the TAP controller state machine and the instruction that is currently loaded in the TAP instruction register (refer to Figure 6). An undriven TDI pin will produce the same result as a logic 1 input level. TDO -- TEST DATA OUT (OUTPUT) Output that is active depending on the state of the TAP state machine (refer to Figure 6). Output changes in response to the falling edge of TCK. This is the output side of the serial registers placed between TDI and TDO. TRST -- TAP RESET This device does not have a TRST pin. TRST is optional in IEEE 1149.1. The test-logic reset state is entered while TMS is held high for five rising edges of TCK. Power on reset circuitry is included internally. This type of reset does not affect the operation of the system logic. The reset affects test logic only.
BOUNDARY SCAN REGISTER The boundary scan register is identical in length to the number of active input and I/O connections on the RAM (not counting the TAP pins). This also includes a number of place holder locations (always set to a logic 1) reserved for density upgrade address pins. There are a total of 68 bits in the case of the x36 device and 49 bits in the case of the x18 device. The boundary scan register, under the control of the TAP controller, is loaded with the contents of the RAMs I/O ring when the controller is in capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to shift-DR state. Several TAP instructions can be used to activate the boundary scan register. The Bump/Bit Scan Order tables describe which device bump connects to each boundary scan register location. The first column defines the bit's position in the boundary scan register. The shift register bit nearest TDO (i.e., first to be shifted out) is defined as bit 1. The second column is the name of the input or I/O at the bump and the third column is the bump number. IDENTIFICATION (ID) REGISTER The ID register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in capture-DR state with the IDCODE command loaded in the instruction register. The code is loaded from a 32-bit on-chip ROM. It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the controller is moved into shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins. ID Register Presence Indicator
Bit No. Value 0 1
TEST ACCESS PORT REGISTERS
OVERVIEW The various TAP registers are selected (one at a time) via the sequences of 1s and 0s input to the TMS pin as the TCK is strobed. Each of the TAP registers are serial shift registers that capture serial input data on the rising edge of TCK and push serial data out on subsequent falling edge of TCK. When a register is selected, it is "placed" between the TDI and TDO pins. INSTRUCTION REGISTER The instruction register holds the instructions that are executed by the TAP controller when it is moved into the run test/ idle or the various data register states. The instructions are 3 bits long. The register can be loaded when it is placed between the TDI and TDO pins. The instruction register is automatically preloaded with the IDCODE instruction at power up or whenever the controller is placed in test-logic-reset state. BYPASS REGISTER The bypass register is a single bit register that can be placed between TDI and TDO. It allows serial test data to be passed through the RAMs TAP to another device in the scan chain with as little delay as possible.
Motorola JEDEC ID Code (Compressed Format, per IEEE Standard 1149.1-1990
Bit No. Value 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 1 3 1 2 1 1 0
Reserved For Future Use
Bit No. Value 17 x 16 x 15 x 14 x 13 x 12 x
Device Width
Configuration 256K x 36 512K x 18 Bit No. Value Value 22 0 0 21 0 0 20 1 0 19 0 1 18 0 1
Device Depth
Configuration 256K x 36 512K x 18 Bit No. Value Value 27 0 0 26 0 0 25 1 1 24 1 1 23 0 1
Revision Number
Bit No. Value 31 x 30 x 29 x 28 x
Figure 5. ID Register Bit Meanings
MCM64E918*MCM64E836 16
MOTOROLA FAST SRAM
MCM64E918 x18 Boundary Scan Order
Bit No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 Signal Name SA1 SA0 SA SA SA DQ DQ CQ1 DQ DQ NC
2, 3
MCM64E836 x36 Boundary Scan Order
Bump ID 1H 5A 5B 5K 5L 4L 2K 1M 3M 2P 1T 3P 3T 4R Bit No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 Signal Name SA1 SA0 SA SA SA DQ DQ DQ DQ DQ CQ1 DQ DQ DQ DQ NC
2, 3
Bump ID 5R 5T 6R 7T 7P 8T 9P 8M 7K 9K 6L 5H 5G 5C 8H 9F 7F 8D 9B 7D 7C 7B 7A 6C 6A 4A 4C 3A 3B 3C 3D 2B 1D 2F 3H
Bit No. 36 37 38 39 40 41 42 43 44 45 46 47 48 49
Signal Name DQ ZQ5 B1 B2 B3 LBO DQ DQ DQ DQ DQ SA SA SA
Bump ID 5R 5T 6R 7T 7P 8T 9T 8P 7M 9P 8M 9M 7K 8K 9K 6L 5H 5G 5C 9H 8H 7H 9F 8F 9D 7F 8D 9B 8B 7D 7C 7B 7A 6C 6A
Bit No. 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68
Signal Name SA SA SA SA SA NC
2, 4
Bump ID 4A 4C 3A 3B 3C 3D 2B 1B 2D 3F 1D 2F 1F 3H 2H 1H 5A 5B 5K 5L 4L 1K 2K 3K 1M 2M 1P 3M 2P 1T 2T 3T 4R
DQ DQ DQ DQ DQ CQ1 DQ DQ DQ DQ ZQ5 B1 B2 B3 LBO DQ DQ DQ DQ CQ1 DQ DQ DQ DQ DQ SA SA
CK CK G DQ DQ DQ DQ DQ SA SA SA SA SA SA SA SA SA SA SA NC
2, 4
CK CK G DQ DQ DQ DQ CQ1 DQ DQ DQ DQ DQ SA SA SA SA SA SA
DQ DQ CQ1 DQ
NOTES: 1. CQ, CQ pins scan to biased level, just like DQs. 2. NC pads are place holder bits and are true no-connects. When reading out the boundary scan register, these bits are forced high. 3. Place holder for Mode pin. 4. Placeholder for 16M DDR. 5. ZQ (5A) scans to biased level.
MOTOROLA FAST SRAM
MCM64E918*MCM64E836 17
TAP CONTROLLER INSTRUCTION SET
OVERVIEW There are two classes of instructions defined in the IEEE Standard 1149.1-1990; the standard (public) instructions and device specific (private) instructions. Some public instructions are mandatory for IEEE 1149.1 compliance. Optional public instructions must be implemented in prescribed ways. Although the TAP controller in this device follows the IEEE 1149.1 conventions, it is not IEEE 1149.1 compliant because some of the mandatory instructions are not fully implemented. The TAP on this device may be used to monitor all input and I/O pads, but can not be used to load address, data, or control signals into the RAM or to preload the I/O buffers. In other words, the device will not perform IEEE 1149.1 EXTEST, INTEST, or the preload portion of the SAMPLE/PRELOAD command. When the TAP controller is placed in capture-IR state, the two least significant bits of the instruction register are loaded with 01. When the controller is moved to the shift-IR state, the instruction register is placed between TDI and TDO. In this state, the desired instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the TAP executes newly loaded instructions only when the controller is moved to update-IR state. The TAP instruction sets for this device are listed in the following tables.
expected. RAM input signals must be stabilized for long enough to meet the TAPs input data capture setup plus hold time (tCS plus tCH). The RAMs clock inputs need not be paused for any other TAP operation except capturing the I/O ring contents into the boundary scan register. Moving the controller to shift-DR state then places the boundary scan register between the TDI and TDO pins. Because the PRELOAD portion of the command is not implemented in this device, moving the controller to the update-DR state with the SAMPLE/PRELOAD instruction loaded in the instruction register, has the same effect as the pause-DR command. This functionality is not IEEE 1149.1 compliant. EXTEST EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register, whatever length it may be in the device, is loaded with all logic 0s. EXTEST is not implemented in this device. Therefore, this device is not IEEE 1149.1 compliant. Nevertheless, this RAMs TAP does respond to an all 0s instruction, as follows. With the EXTEST (000) instruction loaded in the instruction register, the RAM responds just as it does in response to the SAMPLE/PRELOAD instruction described above, except the DQ and CQ pins are forced to High-Z any time the instruction is loaded. IDCODE The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in capture-DR mode and places the ID register between the TDI and TDO pins in shift-DR mode. The IDCODE instruction is the default instruction loaded in at power up and any time the controller is placed in the test-logic-reset state.
STANDARD (PUBLIC) INSTRUCTIONS
BYPASS The BYPASS instruction is loaded in the instruction register when the bypass register is placed between TDI and TDO. This occurs when the TAP controller is moved to the shift-DR state. This allows the board level scan path to be shortened to facilitate testing of other devices in the scan path. SAMPLE/PRELOAD SAMPLE/PRELOAD is an IEEE 1149.1 mandatory public instruction. When the SAMPLE/PRELOAD instruction is loaded in the instruction register, moving the TAP controller into the capture-DR state loads the data in the RAMs input and I/O buffers into the boundary scan register. Because the RAM clock(s) are independent from the TAP clock (TCK), it is possible for the TAP to attempt to capture the I/O ring contents while the input buffers are in transition (i.e., in a metastable state). Although allowing the TAP to sample metastable inputs will not harm the device, repeatable results can not be
DEVICE SPECIFIC (PUBLIC) INSTRUCTION
SAMPLE-Z If the SAMPLE-Z instruction is loaded in the instruction register, all DQ pins are forced to an inactive drive state (High-Z) and the boundary scan register is connected between TDI and TDO when the TAP controller is moved to the shift-DR state.
DEVICE SPECIFIC (PRIVATE) INSTRUCTION
NO OP Do not use these instructions; they are reserved for future use.
MCM64E918*MCM64E836 18
MOTOROLA FAST SRAM
STANDARD (PUBLIC) INSTRUCTION CODES
Instruction EXTEST IDCODE SAMPLE/PRELOAD Code* 000 001** 100 Description Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces all DQ pins to High-Z state. NOT IEEE 1149.1 COMPLIANT. Preloads ID register and places it between TDI and TDO. Does not affect RAM operation. Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Does not affect RAM operation. Does not implement IEEE 1149.1 PRELOAD function. NOT IEEE 1149.1 COMPLIANT. Places bypass register between TDI and TDO. Does not affect RAM operation. Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces all DQ pins to High-Z state.
BYPASS SAMPLE-Z
111 010
* Instruction codes expressed in binary; MSB on left, LSB on right. ** Default instruction automatically loaded at power-up and in test-logic-reset state.
STANDARD (PRIVATE) INSTRUCTION CODES
Instruction NO OP NO OP NO OP Code* 011 101 110 Description Do not use these instructions; they are reserved for future use. Do not use these instructions; they are reserved for future use. Do not use these instructions; they are reserved for future use.
* Instruction codes expressed in binary; MSB on left, LSB on right.
1
TEST-LOGIC RESET 0 RUN-TEST/ IDLE 1 SELECT DR-SCAN 0 1 CAPTURE-DR 0 SHIFT-DR 1 EXIT1-DR 0 PAUSE-DR 1 0 EXIT2-DR 1 UPDATE-DR 1 0 1 0 0 1 0 1 SELECT IR-SCAN 0 CAPTURE-IR 0 SHIFT-IR 1 EXIT1-IR 0 PAUSE-IR 1 EXIT2-IR 1 UPDATE-IR 0 0 1 0
0
1
1
NOTE: The value adjacent to each state transition represents the signal present at TMS at the rising edge of TCK.
Figure 6. TAP Controller State Diagram
MOTOROLA FAST SRAM
MCM64E918*MCM64E836 19
ORDERING INFORMATION
(Order by Full Part Number) MCM
Motorola PowerPC Prefix Part Number
64E918 64E836
FC
X
X
Shipping Method (R = Tape and Reel, Blank = Rails) Speed (3.0 = 3.0 ns, 3.3 = 3.3 ns, 4.0 = 4.0 ns) Package (FC = Flipped Chip PBGA)
Full Part Numbers -- MCM64E918FC3.0 MCM64E918FC3.3 MCM64E918FC4.0
MCM64E918FC3.0R MCM64E918FC3.3R MCM64E918FC4.0R
MCM64E836FC3.0 MCM64E836FC3.3 MCM64E836FC4.0
MCM64E836FC3.0R MCM64E836FC3.3R MCM64E836FC4.0R
MCM64E918*MCM64E836 20
MOTOROLA FAST SRAM
PACKAGE DIMENSIONS
FC PACKAGE 153-BUMP FLIPPED CHIP PBGA CASE 1107C-03
153X
0.2 A 0.25 A A 4
SEATING PLANE
TERMINAL A-1 INDEX
14 1.1 MIN 6 8
B
4X
0.7 MAX 0.2
7
CAPACITOR
6 8 1.1 MIN
0.35 A
5
12.55 11.75
22
7.2 6.9 TOP VIEW (10.16)
8X
5 B 0.7 0.5 0.92 0.80
1.27
U T R P N M L K J H G F E D C B A 1 2 3 45 6 78 9
1.15 0.92
16X
1.27 2.07 1.75 2.77 MAX SIDE VIEW (20.32)
153X
0.9 0.6 0.3 0.15
M M
3 ABC A
BOTTOM VIEW
NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M,1994. 2. ALL DIMENSIONS IN MILLIMETERS. 3. MAXIMUM SOLDER BALL DIAMETER MEASURED PARALLEL TO DATUM A. 4. DATUM A, THE SEATING PLANE, IS DETERMINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. 5. DEFINES THE DIE SIZE. 6. MINIMUM CLEARANCE FROM PACKAGE EDGE TO CHIP CAPACITOR. 7. CAPACITORS MAY NOT BE PRESENT ON ALL DEVICES. 8. CAUTION MUST BE TAKEN NOT TO SHORT EXPOSED METAL CAPACITOR PADS ON PACKAGE TOP.
MOTOROLA FAST SRAM
MCM64E918*MCM64E836 21
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JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center, 3-20-1, Minami-Azabu. Minato-ku, Tokyo 106-8573 Japan. 81-3-3440-3569 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre, 2 Dai King Street, Tai Po Industrial Estate, Tao Po, N.T., Hong Kong. 852-26668334
MCM64E918*MCM64E836 22
MCM64E918/D MOTOROLA FAST SRAM

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