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| MH1 1.6 Million gates Sea of Gates / Embedded Arrays 1. Description The MH1 Series Gate Array and Embedded Array families from TEMIC are fabricated in a 0.35 CMOS process, with up to 3 levels of metal. This family features arrays with up to 1.6 million routable gates and 600 pins. The high density and high pin count capabilities of the MH1 family, coupled with the ability to embed memories on the same silicon, makes the MH1 series of arrays an ideal choice for System Level Integration. The MH1 series is supported by an advance software environment based on industry standards linking proprietary and commercial tools. Cadence, Mentor, Sysnopsys and Vital are the reference front end tools. Floor planning associated with timing driven layout provides a short back end cycle. The MH1 series comes as a dual use of the MH1RT series, without the latch up and total dose immumity features. The MH1 series comes as the TEMIC 6th generation of ASIC series designed for military and avionics types of applications in a 15 years time frame. It is also made available to any of the currently available quality grades: commercial, industrial, automotive and military, and TEMIC will apply for its QML Q certification. 2. Features q q q q q q q High Speed - 150 ps Gate Delay - 2 input NAND, FO=2 (nominal) Up to 2.2 Million Used Gates and 600 Pins 3 and 2.5 V Libraries System Level Integration Technology MEMORY: SRAM, ROM, CAM and FIFO; Gate Level or Embedded I/O Interfaces: CMOS, LVTTL, LVDS, PCI, USB - Output Currents up to 20 mA, 5V compatible Tolerant I/O Deep Submicron CAD Flow Table 1. MH1 Array Organization Device Number Routable Gates Number of pads 332 412 512 596 Max I/O Count 324 404 504 588 Gate Speed(1) 170ps 170ps 170ps 170ps MH1099 519,000 MH1156 768,000 MH1242 1,198,000 MH1332 1,634,000 1. Nominal 2 Input NAND Gate FO=2 at 3 volts. Rev C. - June 26, 2000 1 Preliminary MH1 3. Design 3.1 Design Systems Supported TEMIC supports several major software systems for design with complete macro cell libraries, as well as utilities for checking the netlist and accurate pre-route delay simulations. The following design systems are supported: System Available / Planned Tools PearlTM - Static Path Verilog-XLTM - Verilog Simulator Logic Design PlannerTM - Floorplanner BuildGatesTM - Synthesis (Ambit) Modelsim Verilog and VHDL (VITAL) Simulator Leonardo SpectrumTM - Synthesis Velocity - Static Path VSSTM - VHDL Simulator Design CompilerTM - Synthesis Test CompilerTM - Scan Insertion and ATPG TestGenTM - Scan Insertion and ATPG VCSTM - Verilog Simulator PrimetimeTM - Static Path CadenceTM Mentor/Model TechTM SynopsysTM 4. Design Flow and Tools TEMIC's design flow for Gate Arrays/Embedded Arrays is structured to allow the designer to consolidate the greatest number of system components possible onto the same silicon chip, using available third party design tools. TEMIC's cell library reflects silicon performance over extremes of temperature, voltage, and process, and includes the effects of metal loading, inter-level capacitance, and edge rise and fall times. The Design Flow includes clock tree synthesis to customer specified skew and latency goals. RC extraction is performed on final design database and incorporated into the timing analysis. The Typical Gate Array/Embedded Array Design Flow, shown on page 3, provides a pictorial description of the typical interaction between TEMIC's Gate Array/Embedded Array design staff and the customer. TEMIC will deliver design kits to support the customer's synthesis, verification, floorplanning, and SCAN insertion activities. Tools such as SynopsysTM, CadenceTM, Verilog-HDLTM and CTgenTM are used, and many others are available. Should a design include embedded memory or an embedded core, TEMIC will support a design review with the customer. The purpose of the design review is to permit TEMIC to understand the partition of the Gate Array/Embedded Array, and define the location of the memory blocks and / or cores so that an underlayer layout model can be created. Following a Preliminary Design Review, the design is routed, and post-route RC data is extracted. Following postroute verification and a Final Design Review, the design is taped out for fabrication. 2 Rev C. - June 26, 2000 Preliminary MH1 Temic Temic Temic Personality Temic Temic Temic Temic Temic Figure 1. Typical Gate Array/Embedded Array Design Flow Rev C. - June 26, 2000 3 Preliminary MH1 5. Pin Definition Requirements The corner pads are reserved for Power and Ground only. All other pads are fully programmable as Input, Output, Bidirectional, Power or Ground. When implementing a design with 5 volt tolerant buffers, one buffer site must be reserved for the VDD5 pin, which is used to distribute power to the buffers. Figure 2. Gate Array SRAM Standard Gate Array Architecture ARM RISC Core ROM Figure 3. Embedded Array 5.1 I/O site: Pad and Sub-Sections: The I/O sites are configurable as input, output, 3-state output and bidirectional buffers, each with pullup ur pulldown capability, if required, by utilizing their corresponding sub-section. Bidirectionnal buffers are the result of an input and output buffers placed in adjacent sub-sections in the same I/O site. Special buffers may require multiple I/O sites. Oscillators require 2 I/O sites, each power and ground pin utilizes one I/O site. 4 Rev C. - June 26, 2000 Preliminary MH1 6. Design Options 6.1 ASIC Design Translation TEMIC has successfully translated existing designs from most major ASIC vendors (LSI LogicTM, MotorolaTM, SMOSTM, OkiTM, NECTM, FujitsuTM, AMITM and others) into the gate arrays. These designs have been optimized for speed and gate count and modified to add logic or memory, or replicated for a pin-for-pin compatible, drop-in replacement. 6.2 Design Entry Design entry is performed by the customer using an TEMIC provided macro cell library. A complete netlist and vector set must then be provided to TEMIC. Upon acceptance of this data set, TEMIC continues with the standard design flow. 6.3 FPGA and PLD Conversions TEMIC has successfully translated existing FPGA/PLD designs from most major vendors (XilinxTM, ActelTM, AlteraTM, AMDTM and TEMIC) into the gate arrays. There are four primary reasons to convert from an FPGA/ PLD to a gate array. Conversion of high volume devices for a single or combined design is cost effective. Performance can often be optimized for speed or low power consumption. Several FPGA/PLDs can be combined onto a single chip to minimize cost while reducing on-board space requirements. Finally, in situations where an FPGA/PLD was used for fast cycle time prototyping, a gate array may provide a lower cost answer for longterm volume production. Rev C. - June 26, 2000 5 Preliminary MH1 7. MH1 Series Cell Library TEMIC's MH1 Series gate arrays make use of an extensive library of macro cell structures, including logic cells, buffers and inverters, multiplexers, decoders, and I/O options. Soft macros are also available. The MH1 Series PLL operates at frequencies of up to 250MHz with minimal phase error and jitter, making it ideal for frequency synthesis of high speed on-chip clocks and chip to chip synchronization. Output buffers are programmable to meet the voltage and current requirements of PCI (20mA). These cells are well characterized by use of SPICE modeling at the transistor level, with performance verified on manufactured test arrays. Characterization is performed over the rated temperature and voltage ranges to ensure that the simulation accurately predicts the performance of the finished product. Table 2. Cell Index Cell Name ADD3X AND2 AND2H AND3 AND3H AND4 AND4H AND5 AOI22 AOI22H AOI222 AOI222H AOI2223 AOI2223H AOI23 BUF1 BUF2 BUF2T BUF2Z BUF3 BUF4 BUF4T BUF8 BUF8T BUF12 BUF16 CLA7X DEC4 DEC4N DEC8N DFF Description 1 bit full adder with buffered outputs 2 input AND 2 input AND - high drive 3 input AND 3 input AND - high drive 4 input AND 4 input AND - high drive 5 input AND 2 input AND into 2 input NOR 2 input AND into 2 input NOR - high drive Two, 2 input ANDs into 2 input NOR Two, 2 input ANDs into 2 input NOR - high drive Three, 2 input ANDs into 3 input NOR Three, 2 input ANDs into 3 input NOR - high drive 2 input AND into 3 input NOR 1x buffer 2x buffer 2x Tri State bus driver with active high enable 2x Tri State bus driver with active low enable 3x buffer 4x buffer 4x Tri-State bus driver with active high enable 8x buffer 8x Tri-State bus driver with active high enable 12x buffer 16x buffer 7 input carry lookahead 2:4 decoder 2:4 decoder with active low enable 3:8 decoder with active low enable D flip-flop 10 2 3 3 4 3 4 5 2 4 2 4 4 8 3 2 2 4 4 3 3 6 5 10 8 10 5 8 10 22 8 Gate Count 6 Rev C. - June 26, 2000 Preliminary MH1 Table 2. Cell Index Cell Name DFFBCPX DFFBSRX DFFC DFFR DFFRQ DFFS DFFSR DLY1 DLY2 DLY3 DSS DSSQ DSSBCPY DSSBR DSSBS DSSR DSSRQ DSSS DSSSR INV1 INV2 INV2T INV3 INV4 INV8 INV10 INV1D INV1Q INV1TQ JKF JKFBCPX JKFC LAT LATB LATBG LATBH LATIQ LATR LATS LATSR Description D flip-flop with asynchronous clear and preset with complementary outputs D flip-flop with asynchronous set and reset with complementary outputs D flip flop with asynchronous clear D flip-flop with asynchronous reset Quad D flip-flop with asynchronous reset D flip-flop with asynchronous set D flip-flop with asynchronous set and reset Delay buffer 1.0 ns Delay buffer 1.5 ns Delay buffer 2.0 ns Set scan flip-flop Quad Set scan D flip-flop Set scan flip-flop with clear and preset Set scan flip-flop with reset Set scan flip-flop with set Set scan D flip-flop with reset Quad Set Scan D flip-flop with reset Set scan D flip-flop with set Set scan D flip-flop with set and reset 1x inverter 2x inverter 2x Tri State inverter with active high enable 3x inverter 4x inverter 8x inverter 10x inverter Dual 1x inverter Quad 1x inverter Quad 1x Tri State inverter with active high enable JK flip-flop Clear preset JK flip-flop with asynchronous clear and preset and complementary outputs JK flip-flop with asynchronous clear LATCH LATCH with complementary outputs LATCH with complementary outputs and inverted gate signal LATCH with high drive complementary outputs Quad Latch LATCH with reset LATCH with set LATCH with set and reset 16 16 9 10 40 9 11 6 9 11 12 36 16 14 14 12 48 14 16 1 1 3 2 2 4 8 2 4 8 10 16 12 6 6 6 7 20 5 6 8 Gate Count Rev C. - June 26, 2000 7 Preliminary MH1 Table 2. Cell Index Cell Name MUX2 MUX2H MUX2I MUX2IH MUX2N MUX2NQ MUX2Q MUX3I MUX3IH MUX4 MUX4X MUX4XH MUX5H MUX8 MUX8N MUX8XH NAN2 NAN2D NAN2H NAN3 NAN3H NAN4 NAN4H NAN5 NAN5H NAN6 NAN6H NAN8 NAN8H NOR2 NOR2D NOR2H NOR3 NOR3H NOR4 NOR4H NOR5 NOR8 OAI22 OAI22H OAI222 OAI222H 2:1 MUX 2:1 MUX - high drive 2:1 MUX with inverted output 2:1 MUX with inverted output - high drive 2:1 MUX with active low enable Quad 2:1 MUX with active low enable Quad 2:1 MUX 3:1 MUX with inverted output 3:1 MUX with inverted output - high drive 4:1 MUX 4:1 MUX with transmission gate data inputs 4:1 MUX with transmission gate data inputs - high drive 5:1 MUX - high drive 8:1 MUX 8:1 MUX with active low enable 8:1 MUX with transmission gate data inputs - high drive 2 input NAND Dual 2 input NAND 2 input NAND - high drive 3 input NAND 3 input NAND - high drive 4 input NAND 4 input NAND - high drive 5 input NAND 5 input NAND - high drive 6 input NAND 6 input NAND - high drive 8 input NAND 8 input NAND - high drive 2 input NOR Dual 2 input NOR 2 input NOR - high drive 3 input NOR 3 input NOR - high drive 4 input NOR 4 input NOR - high drive 5 input NOR 8 input NOR 2 input OR into 2 input NAND 2 input OR into 2 input NAND - high drive Two, 2 input ORs into 2 input NAND Two, 2 input ORs into 2 input NAND - high drive Description 4 5 3 4 5 18 16 6 8 10 9 10 14 20 20 16 2 3 2 2 3 3 4 5 6 6 7 7 8 2 3 2 2 3 3 5 5 7 2 4 3 6 Gate Count 8 Rev C. - June 26, 2000 Preliminary MH1 Table 2. Cell Index Cell Name OAI22224 OAI23 ORR2 ORR2H ORR3 ORR3H ORR4 ORR4H ORR5 XNR2 XNR2H XOR2 XOR2H Description Four, 2 input ORs into 4 input NAND 2 input OR into 3 input NAND 2 input OR 2 input OR - high drive 3 input OR 3 input OR - high drive 4 input OR 4 input OR - high drive 5 input OR 2 input exclusive NOR 2 input exclusive NOR - high drive 2 input exclusive OR 2 input exclusive OR - high drive 8 3 2 3 3 4 3 4 5 4 4 4 4 Gate Count Table 3. I/O Buffer Cell Index Buffer PIC PICH PICI PICS PICSI PICSV PICSV5 PICV PICV5 PID PO11 PO11F PO11S PO11V PO11V5 PO11VF PO11VS PO22 PO22F PO22I PO22S PO22V PO22V5 PO22VF PO22VS PO33 AI,P AI,P AI,P AI,P AI,P AI,P AI,P,VCC AI,P AI,P,VCC AI,P,REF,EN P,AO,E0 P,AO,E0 P,AO,E0 P,AO,E0 P,AO,E0,VCC P,AO,E0 P,AO,E0 P,AO,E0 P,AO,E0 P,AO,E0 P,AO,E0 P,AO,E0 P,AO,E0,VCC P,AO,E0 P,AO,E0 P,AO,E0 I/O order Description CMOS input buffer, TTL compatible at 3.0V CMOS input buffer, TTL compatible at 3.0V, high drive CMOS input buffer, TTL compatible at 3.0V, inverted output CMOS input buffer with schmitt trigger, TTL compatible at 3.0V CMOS input buffer with schmitt trigger, TTL compatible at 3.0V, inverted output CMOS input buffer with schmitt trigger, TTL compatible at 3.0V, 5V tolerant CMOS input buffer with schmitt trigger, TTL compatible at 3.0V, 5V compliant CMOS input buffer, TTL compatible at 3.0V, 5V tolerant CMOS input buffer, TTL compatible at 3.0V, 5V compliant Differential input buffer Tristate output buffer, 2mA drive Tristate output buffer, 2mA drive, fast slew rate control Tristate output buffer, 2mA drive, slow slew rate control Tristate output buffer, 2mA drive, 5V tolerant Tristate output buffer, 2mA drive, 5V compliant Tristate output buffer, 2mA drive, fast slew rate control, 5V tolerant Tristate output buffer, 2mA drive, slow slew rate control, 5V tolerant Tristate output buffer, 4mA drive Tristate output buffer, 4mA drive, fast slew rate control Tristate output buffer, 4mA drive, inverted output Tristate output buffer, 4mA drive, slow slew rate control Tristate output buffer, 4mA drive, 5V tolerant Tristate output buffer, 4mA drive, 5V compliant Tristate output buffer, 4mA drive, fast slew rate control, 5V tolerant Tristate output buffer, 4mA drive, slow slew rate control, 5V tolerant Tristate output buffer, 6mA drive Rev C. - June 26, 2000 9 Preliminary MH1 Table 3. I/O Buffer Cell Index Buffer PO33F PO33S PO33V PO33VF PO33VS PO44 PO44F PO44S PO44V PO44V5 PO44VF PO44VS PO55 PO55F PO55S PO55V PO55VF PO55VS PO66 PO66F PO66S PO66V PO66VF PO66VS PO77 PO77F PO77S PO77V PO77VF PO77VS PO88 PO88F PO88S PO88V PO88VF PO88VS PO99 PO99F PO99S PO99V PO99VF PO99VS POAA I/O order P,AO,E0 P,AO,E0 P,AO,E0 P,AO,E0 P,AO,E0 P,AO,E0 P,AO,E0 P,AO,E0 P,AO,E0 P,AO,E0,VCC P,AO,E0 P,AO,E0 P,AO,E0 P,AO,E0 P,AO,E0 P,AO,E0 P,AO,E0 P,AO,E0 P,AO,E0 P,AO,E0 P,AO,E0 P,AO,E0 P,AO,E0 P,AO,E0 P,AO,E0 P,AO,E0 P,AO,E0 P,AO,E0 P,AO,E0 P,AO,E0 P,AO,E0 P,AO,E0 P,AO,E0 P,AO,E0 P,AO,E0 P,AO,E0 P,AO,E0 P,AO,E0 P,AO,E0 P,AO,E0 P,AO,E0 P,AO,E0 P,AO,E0 Description Tristate output buffer, 6mA drive, fast slew rate control Tristate output buffer, 6mA drive, slow slew rate control Tristate output buffer, 6mA drive, 5V tolerant Tristate output buffer, 6mA drive, fast slew rate control, 5V tolerant Tristate output buffer, 6mA drive, slow slew rate control, 5V tolerant Tristate output buffer, 8mA drive Tristate output buffer, 8mA drive, fast slew rate control Tristate output buffer, 8mA drive, slow slew rate control Tristate output buffer, 8mA drive, 5V tolerant Tristate output buffer, 8mA drive, 5V compliant Tristate output buffer, 8mA drive, fast slew rate control, 5V tolerant Tristate output buffer, 8mA drive, slow slew rate control, 5V tolerant Tristate output buffer, 10mA drive Tristate output buffer, 10mA drive, fast slew rate control Tristate output buffer, 10mA drive, slow slew rate control Tristate output buffer, 10mA drive, 5V tolerant Tristate output buffer, 10mA drive, fast slew rate control, 5V tolerant Tristate output buffer, 10mA drive, slow slew rate control, 5V tolerant Tristate output buffer, 12mA drive Tristate output buffer, 12mA drive, fast slew rate control Tristate output buffer, 12mA drive, slow slew rate control Tristate output buffer, 12mA drive, 5V tolerant Tristate output buffer, 12mA drive, fast slew rate control, 5V tolerant Tristate output buffer, 12mA drive, slow slew rate control, 5V tolerant Tristate output buffer, 14mA drive Tristate output buffer, 14mA drive, fast slew rate control Tristate output buffer, 14mA drive, slow slew rate control Tristate output buffer, 14mA drive, 5V tolerant Tristate output buffer, 14mA drive, fast slew rate control, 5V tolerant Tristate output buffer, 14mA drive, slow slew rate control, 5V tolerant Tristate output buffer, 16mA drive Tristate output buffer, 16mA drive, fast slew rate control Tristate output buffer, 16mA drive, slow slew rate control Tristate output buffer, 16mA drive, 5V tolerant Tristate output buffer, 16mA drive, fast slew rate control, 5V tolerant Tristate output buffer, 16mA drive, slow slew rate control, 5V tolerant Tristate output buffer, 18mA drive Tristate output buffer, 18mA drive, fast slew rate control Tristate output buffer, 18mA drive, slow slew rate control Tristate output buffer, 18mA drive, 5V tolerant Tristate output buffer, 18mA drive, fast slew rate control, 5V tolerant Tristate output buffer, 18mA drive, slow slew rate control, 5V tolerant Tristate output buffer, 20mA drive 10 Rev C. - June 26, 2000 Preliminary MH1 Table 3. I/O Buffer Cell Index Buffer POAAF POAAS POAAV POAAVF POAAVS POBB POBBF POBBS POBBV POBBVF POBBVS POCC POCCF POCCS PRD1 PRD10 PRD10V5 PRD11 PRD11V5 PRD12 PRD12V5 PRD13 PRD13V5 PRD14 PRD14V5 PRD15 PRD15V5 PRD16 PRD16V5 PRD17 PRD17V5 PRD18 PRD18V5 PRD19 PRD19V5 PRD1V5 PRD2 PRD20 PRD20V5 PRD21 PRD21V5 PRD22 PRD22V5 I/O order P,AO,E0 P,AO,E0 P,AO,E0 P,AO,E0 P,AO,E0 P,AO,E0 P,AO,E0 P,AO,E0 P,AO,E0 P,AO,E0 P,AO,E0 P,AO,E0 P,AO,E0 P,AO,E0 P P P,VCC P P,VCC P P,VCC P P,VCC P P,VCC P P,VCC P P,VCC P P,VCC P P,VCC P P,VCC P,VCC P P P,VCC P P,VCC P P,VCC Description Tristate output buffer, 20mA drive, fast slew rate control Tristate output buffer, 20mA drive, slow slew rate control Tristate output buffer, 20mA drive, 5V tolerant Tristate output buffer, 20mA drive, fast slew rate control, 5V tolerant Tristate output buffer, 20mA drive, slow slew rate control, 5V tolerant Tristate output buffer, 22mA drive Tristate output buffer, 22mA drive, fast slew rate control Tristate output buffer, 22mA drive, slow slew rate control Tristate output buffer, 22mA drive, 5V tolerant Tristate output buffer, 22mA drive, fast slew rate control, 5V tolerant Tristate output buffer, 22mA drive, slow slew rate control, 5V tolerant Tristate output buffer, 24mA drive Tristate output buffer, 24mA drive, fast slew rate control Tristate output buffer, 24mA drive, slow slew rate control 20KOhms pull-down terminator 200KOhms pull-down terminator 200KOhms pull-down terminator, 5V compliant 220KOhms pull-down terminator 220KOhms pull-down terminator, 5V compliant 240KOhms pull-down terminator 240KOhms pull-down terminator, 5V compliant 260KOhms pull-down terminator 260KOhms pull-down terminator, 5V compliant 280KOhms pull-down terminator 280KOhms pull-down terminator, 5V compliant 300KOhms pull-down terminator 300K pull-down terminator, 5V compliant 320KOhms pull-down terminator 320K pull-down terminator, 5V compliant 340KOhms pull-down terminator 340K pull-down terminator, 5V compliant 360KOhms pull-down terminator 360K pull-down terminator, 5V compliant 380KOhms pull-down terminator 380K pull-down terminator, 5V compliant 20K pull-down terminator, 5V compliant 40KOhms pull-down terminator 400KOhms pull-down terminator 400K pull-down terminator, 5V compliant 420KOhms pull-down terminator 420K pull-down terminator, 5V compliant 440KOhms pull-down terminator 440K pull-down terminator, 5V compliant Rev C. - June 26, 2000 11 Preliminary MH1 Table 3. I/O Buffer Cell Index Buffer PRD23 PRD23V5 PRD24 PRD24V5 PRD25 PRD25V5 PRD26 PRD26V5 PRD27 PRD27V5 PRD28 PRD28V5 PRD29 PRD29V5 PRD2V5 PRD3 PRD30 PRD30V5 PRD31 PRD31V5 PRD3V5 PRD4 PRD4V5 PRD5 PRD5V5 PRD6 PRD6V5 PRD7 PRD7V5 PRD8 PRD8V5 PRD9 PRD9V5 PRU1 PRU10 PRU10V5 PRU11 PRU11V5 PRU12 PRU12V5 PRU13 PRU13V5 PRU14 P P,VCC P P,VCC P P,VCC P P,VCC P P,VCC P P,VCC P P,VCC P,VCC P P P,VCC P P,VCC P,VCC P P,VCC P P,VCC P P,VCC P P,VCC P P,VCC P P,VCC P P P,VCC P P,VCC P P,VCC P P,VCC P I/O order 460KOhms pull-down terminator Description 460K pull-down terminator, 5V compliant 480KOhms pull-down terminator 480K pull-down terminator, 5V compliant 500KOhms pull-down terminator 500K pull-down terminator, 5V compliant 520KOhms pull-down terminator 520K pull-down terminator, 5V compliant 540KOhms pull-down terminator 540K pull-down terminator, 5V compliant 560KOhms pull-down terminator 560K pull-down terminator, 5V compliant 580KOhms pull-down terminator 580K pull-down terminator, 5V compliant 40K pull-down terminator, 5V compliant 60KOhms pull-down terminator 600KOhms pull-down terminator 600K pull-down terminator, 5V compliant 620KOhms pull-down terminator 620K pull-down terminator, 5V compliant 60K pull-down terminator, 5V compliant 80KOhms pull-down terminator 80K pull-down terminator, 5V compliant 100KOhms pull-down terminator 100K pull-down terminator, 5V compliant 120KOhms pull-down terminator 120K pull-down terminator, 5V compliant 140KOhms pull-down terminator 140K pull-down terminator, 5V compliant 160KOhms pull-down terminator 160K pull-down terminator, 5V compliant 180KOhms pull-down terminator 180K pull-down terminator, 5V compliant 20KOhms pull-up terminator 200KOhms pull-up terminator 200KOhms pull-up terminator, 5V compliant 220KOhms pull-up terminator 220KOhms pull-up terminator, 5V compliant 240KOhms pull-up terminator 240KOhms pull-up terminator, 5V compliant 260KOhms pull-up terminator 260KOhms pull-up terminator, 5V compliant 280KOhms pull-up terminator 12 Rev C. - June 26, 2000 Preliminary MH1 Table 3. I/O Buffer Cell Index Buffer PRU14V5 PRU15 PRU15V5 PRU16 PRU16V5 PRU17 PRU17V5 PRU18 PRU18V5 PRU19 PRU19V5 PRU1V5 PRU2 PRU20 PRU20V5 PRU21 PRU21V5 PRU22 PRU22V5 PRU23 PRU23V5 PRU24 PRU24V5 PRU25 PRU25V5 PRU26 PRU26V5 PRU27 PRU27V5 PRU28 PRU28V5 PRU29 PRU29V5 PRU2V5 PRU3 PRU30 PRU30V5 PRU31 PRU31V5 PRU3V5 PRU4 PRU4V5 PRU5 P P,VCC P P,VCC P P,VCC P P,VCC P P,VCC P,VCC P P P,VCC P P,VCC P P,VCC P P,VCC P P,VCC P P,VCC P P,VCC P P,VCC P P,VCC P P,VCC P,VCC P P P,VCC P P,VCC P,VCC P P,VCC P I/O order P,VCC 300KOhms pull-up terminator Description 280KOhms pull-up terminator, 5V compliant 300KOhms pull-up terminator, 5V compliant 320KOhms pull-up terminator 320KOhms pull-up terminator, 5V compliant 340KOhms pull-up terminator 340KOhms pull-up terminator, 5V compliant 360KOhms pull-up terminator 360KOhms pull-up terminator, 5V compliant 380KOhms pull-up terminator 380KOhms pull-up terminator, 5V compliant 20KOhms pull-up terminator, 5V compliant 20KOhms pull-up terminator 400KOhms pull-up terminator 400KOhms pull-up terminator, 5V compliant 420KOhms pull-up terminator 420KOhms pull-up terminator, 5V compliant 440KOhms pull-up terminator 440KOhms pull-up terminator, 5V compliant 460KOhms pull-up terminator 460KOhms pull-up terminator, 5V compliant 480KOhms pull-up terminator 480KOhms pull-up terminator, 5V compliant 500KOhms pull-up terminator 500KOhms pull-up terminator, 5V compliant 520KOhms pull-up terminator 520KOhms pull-up terminator, 5V compliant 540KOhms pull-up terminator 540KOhms pull-up terminator, 5V compliant 560KOhms pull-up terminator 560KOhms pull-up terminator, 5V compliant 580KOhms pull-up terminator 580KOhms pull-up terminator, 5V compliant 40KOhms pull-up terminator, 5V compliant 60KOhms pull-up terminator 600KOhms pull-up terminator 600KOhms pull-up terminator, 5V compliant 620KOhms pull-up terminator 620KOhms pull-up terminator, 5V compliant 60KOhms pull-up terminator, 5V compliant 80KOhms pull-up terminator 80KOhms pull-up terminator, 5V compliant 100KOhms pull-up terminator Rev C. - June 26, 2000 13 Preliminary MH1 Table 3. I/O Buffer Cell Index Buffer PRU5V5 PRU6 PRU6V5 PRU7 PRU7V5 PRU8 PRU8V5 PRU9 PRU9V5 PX1L PX1R PX2L PX3L PX4L P P,VCC P P,VCC P P,VCC P P,VCC AI,PI,GD,GU,REN AI,PI,GD,GU,REN AI,PI,GD,GU,REN AI,PI,GD,GU,REN AI,PI,GD,GU,REN I/O order P,VCC 120KOhms pull-up terminator Description 100KOhms pull-up terminator, 5V compliant 120KOhms pull-up terminator, 5V compliant 140KOhms pull-up terminator 140KOhms pull-up terminator, 5V compliant 160KOhms pull-up terminator 160KOhms pull-up terminator, 5V compliant 180KOhms pull-up terminator 180KOhms pull-up terminator, 5V compliant Crystal Oscillator (frequency range TBD) Crystal Oscillator (frequency range TBD) Crystal Oscillator (frequency range TBD) Crystal Oscillator (frequency range TBD) Crystal Oscillator (frequency range TBD) 8. Absolute Maximum Ratings* Operating Ambient Temperature-55C to +125C Storage Temperature-65C to +150C Maximum Input Voltage: InputsVDD +0.5V 5V tolerantVDD5 +0.5V Maximum Operating Voltage 3.6V Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 14 Rev C. - June 26, 2000 Preliminary MH1 9. DC Characteristics 9.1 2.5V DC Characteristics Applicable over recommended operating temperature and voltage range unless otherwise noted. Symbol TA VDD IIH Parameter Operating Temperature All Supply Voltage All Buffer Test Condition -55 2.3 VIN = VDD, VDD = VDD(max) No Pull up VIN = VSS, VDD = VDD(max), No Pull up -5 -5 Min Typ 25 2.5 1.0 1.0 1.0 9 -6 Max 125 2.7 5 5 5 Units degreesC V A A A mA Low level Input Current CMOS Low-level Input Current CMOS High-Impedance State Output Current Output Short-circuit Current High-level Input Voltage All PO11 PO11 CMOS, LVTTL CMOS Level Schmitt IIL IOZ IOS VIN = VDD or VSS, VDD = VDD(max), -5 No pull up VOUT = VDD, VDD = VDD(max) VOUT = VSS, VDD = VDD(max) 0.7 VDD 0.7 VDD VIH 1.5 0.3 VDD 1.0 0.3 VDD V VIL VOH VOL ICCSB CMOS Low-level Input Voltage CMOS Level Schmitt High-level Output CMOS, LVTTL Voltage Low-level Output PO11 Voltage Leakage current per cell V V IOH = as rated, VDD = VDD(min) IOL = as rated, VDD = VDD(min) VDD = VDD(max) 0.7VDD 0.4 0.5 V nA 9.2 3V DC Characteristics Applicable over recommended operating temperature and voltage range unless otherwise noted. Symbol TA VDD IIH IIL IOZ IOS Parameter Buffer Test Condition -55 2.7 -5 -5 Min Typ 25 3.0 1.0 1.0 1.0 14 -9 Max 125 3.3 5 5 5 Units degreesC V A A A mA Operating Temperature All Supply Voltage All Low level Input Current CMOS Low-level Input Current CMOS High-Impedance State Output Current Output Short-circuit Current High-level Input Voltage All PO11 PO11 CMOS, LVTTL CMOS Level Schmitt VIN = VDD, VDD = VDD(max) VIN = VSS, VDD = VDD(max), Pull up = 620K VIN = VDD or VSS, VDD = VDD(max), -5 No pull up VOUT = VDD, VDD = VDD(max) VOUT = VSS, VDD = VDD(max) 2.0 2.0 VIH 1.7 0.8 1.1 0.8 V VIL VOH VOL ICCSB CMOS Low-level Input Voltage CMOS Level Schmitt High-level Output CMOS, LVTTL Voltage Low-level Output PO11 Voltage Leakage current per cell V V IOH = as rated, VDD = VDD(min) IOL = as rated, VDD = VDD(min) VDD = VDD(max) 0.7VDD 0.4 0.6 5 V nA Rev C. - June 26, 2000 15 Preliminary MH1 9.3 3.3V DC Characteristics Applicable over recommended operating temperature and voltage range unless otherwise noted. Symbol TA VDD IIH IIL IOZ IOS Parameter Buffer Test Condition -55 3.0 -5 -5 Min Typ 25 3.3 1.0 1.0 1.0 15 -10 Max 125 3.6 5 5 5 Units degreesC V A A A mA Operating Temperature All Supply Voltage All Low level Input Current CMOS Low-level Input Current CMOS High-Impedance State Output Current Output Short-circuit Current High-level Input Voltage All PO11 PO11 CMOS, LVTTL CMOS Level Schmitt VIN = VDD, VDD = VDD(max) VIN = VSS, VDD = VDD(max), Pull up = 620K VIN = VDD or VSS, VDD = VDD(max), -5 No pull up VOUT = VDD, VDD = VDD(max) VOUT = VSS, VDD = VDD(max) 2.0 2.0 VIH 1.7 0.8 1.1 0.8 V VIL VOH VOL ICCSB CMOS Low-level Input Voltage CMOS Level Schmitt High-level Output CMOS, LVTTL Voltage Low-level Output PO11 Voltage Leakage current per cell V V IOH = as rated, VDD = VDD(min) IOL = as rated, VDD = VDD(min) VDD = VDD(max) 0.7VDD 0.4 0.6 5 V nA 9.4 5V DC Characteristics Applicable over recommended operating temperature and voltage range unless otherwise noted. Symbol TA VDD IIH IIL IOZ IOS Parameter Buffer Test Condition Min -55 2.7 -5 -5 Typ 25 3.0 1.0 1.0 1.0 8 -7 5.0 1.7 Max 125 3.3 5 5 5 Units degreesC V A A A mA Operating Temperature All Supply Voltage All Low level Input Current CMOS Low-level Input Current CMOS High-Impedance State Output Current Output Short-circuit Current High-level Input Voltage All PO11 PO11 CMOS, LVTTL CMOS Level Schmitt VIN = VDD, VDD = VDD(max) VIN = VSS, VDD = VDD(max), Pull up = 620K VIN = VDD or VSS, VDD = VDD(max), -5 No pull up VOUT = VDD, VDD = VDD(max) VOUT = VSS, VDD = VDD(max) 2.0 2.0 5.5 V VIH VIL VOH VOL ICCSB CMOS Low-level Input Voltage CMOS Level Schmitt High-level Output CMOS, LVTTL Voltage Low-level Output PO11 Voltage Leakage current per cell 0.5VDD 0.8 1.1 IOH = as rated, VDD = VDD(min) IOL = as rated, VDD = VDD(min) VDD = VDD(max) 1.0 0.7VDD 0.7VD5 0.4 10 0.8 V V V nA Table 4. I/O Buffer DC Characteristics Symbol CIN COUT CI/O Parameter Capacitance, Input Buffer (die) Capacitance, Output Buffer (die) Capacitance, Bi-Directional Test Condition 3V 3V 3V Typical 2.4 5.6 6.6 Units pF pF pF 16 Rev C. - June 26, 2000 Preliminary MH1 10. Testability Techniques For complex designs, involving blocks of memory and / or cores, careful attention must be given to design-fortest techniques. The sheer size of complex designs and the number of functional vectors that would need to be created to exercise them fully, strongly suggests the use of more efficient techniques. Combinations of SCAN paths, multiplexed access to memory and/or core blocks, and built-in-self-test logic must be employed, in addition to functional test patterns, to provide both the user and TEMIC the ability to test the finished product. An example of a highly complex design could include a PLL for clock management or synthesis, SRAM and glue logic to support the interconnectivity of each of these blocks. The design of each of these blocks must take into consideration the fact that the manufactured device will be tested on a high performance digital tester. Combinations of parametric, functional, and structural tests, defined for digital testers, should be employed to create a suite of manufacturing tests. The type of block dictates the type of testability technique to be employed. The PLL will, by construction, provide access to key nodes so that functional and / or parametric testing can be performed. Since a digital tester must control all the clocks during the testing of a Gate Array/Embedded Array, provision must be made for the VCO to be bypassed. TEMIC's PLLs include a multiplexing capability for just this purpose. The addition of a few pins will allow other portions of the PLL to be isolated for test, without impinging upon the normal functionality. In a similar vein, access to SRAM blocks must be provided so that controllability and observability of the inputs and outputs to the blocks are achieved with the minimum amount of preconditioning. SRAM blocks need to provide access to both address and data ports so that comprehensive memory tests can be performed. Multiplexing I/O pins provides a method for providing this accessibility. The glue logic can be designed using full SCAN techniques to enhance its testability. It should be noted that, in almost all of these cases, the purpose of the testability technique is to provide TEMIC a means to assess the structural integrity of a Gate Array/Embedded Array, i.e., sort devices with manufacturinginduced defects. All of the techniques described above should be considered supplemental to a set of patterns which exercise the functionality of the design in its anticipated operating modes. Rev C. - June 26, 2000 17 Preliminary MH1 11. Advanced Packaging The MH1 Series gate arrays are offered in a wide variety of standard ceramic packages, including quad flatpacks (CQFP) multi layers quad flatpacks (MQFP), pin grid arrays (CPGA) and land grid arrays (CLGA). High volume onshore and offshore contractors provide assembly and test for commercial and industrial quality grades products. Custom package designs are also available as required to meet a customer's specific needs, and are supported through TEMIC's package design center. When a standard package cannot meet a customer's need, a package can be designed to precisely fit the application and to maintain the performance obtained in silicon. TEMIC has delivered custom-designed packages in a wide variety of configurations. Table 5: Packaging Options Package Type PQFP (*) Power Quad (*) L/TQFP (*) PLCC (*) CPGA CQFP PBGA (*) Super PBGA (*) MQFPF CLGA Pin Count 44, 52, 64, 80, 100, 120, 128, 132, 144, 160, 184, 208, 240, 304 144, 160, 208, 240, 304 32, 44, 48, 64, 80, 100, 120, 128, 144, 160, 176, 216 20, 28, 32, 44, 52, 68, 84 64, 68, 84, 100, 144, 180, 223, 391 64, 68, 84, 100, 120, 132, 144, 160, 224, 340 121, 169, 225, 313, 352, 388 168, 204, 240, 256, 304, 352, 432, 560, 600 196, 256, 352 349, 472, 564 (*) contact factory 18 Rev C. - June 26, 2000 Preliminary |
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