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MIC2550
Micrel
MIC2550
Universal Serial Bus Transceiver Final Information
General Description
The MIC2550 is a single-chip transceiver that complies with the physical layer specifications for Universal Serial Bus (USB). The MIC2550 supports full-speed (12Mbps) dual supply voltage operation (patent pending) and low-speed (1.5Mbps) operation. A unique dual supply voltage operation allows the MIC2550 to reference the system I/F I/O signals to a supply voltage down to 2.5V while independently powered by the USB VBUS. This allows the system interface to operate at its core voltage without addition of buffering logic and also reduce system operating current.
Features
* Compliant to USB Specification Revision 2.0 for low-speed (1.5Mbps) and full-speed (12Mbps) operation * Compliant to IEC-61000-4.2 (Level 2) * Operation down to 2.5V * Dual supply voltage operation * Integrated speed-select termination supply * Very low power consumption meets USB suspendcurrent requirements * Small 14-pin TSSOP and 16-pin MicroLead FrameTM packages
Applications
* Personal digital assistants (PDA) * Palmtop computers * Cellular telephones
Ordering Information
Part Number MIC2550BTS MIC2550BML Package 14-Pin TSSOP 16-Pin MicroLead FrameTM
System Diagram
System Supply Voltage
MIC2550 VIF VTRM D+ D- D- 1F SPD VBUS
1.5k
HIGH SPEED LOW SPEED
VBUS D+ D- GND USB Interface Connector
0.47F
System Interface
OE# RCV VP VM SUS GND
RS 24 RS 24
GND
1F min 10F max
Cooper Electronics Technologies 41206ESDA SurgX (See "Applications Information" for additional suppliers.)
MicroLead Frame and MLF are trademarks of Amkor Technology. SurgX is a registered trademark of Cooper Electronics Technologies.
Micrel, Inc. * 1849 Fortune Drive * San Jose, CA 95131 * USA * tel + 1 (408) 944-0800 * fax + 1 (408) 944-0970 * http://www.micrel.com
May 2002
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Micrel
Pin Configuration
VIF 1 SPD 2 RCV 3 VP 4 VM 5 NC 6 GND 7 14 VBUS 13 NC
16 15 14 13 SPD 1 2 3 4 5678 NC GND SUS NC 12 11 10 9 VTRM D+ D-- OE# RCV VP VM
12 VTRM 11 D+ 10 D- 9 OE# 8 SUS
16-Pin MLFTM (ML) 14-Pin TSSOP (TM)
Pin Description
Pin Name VIF SPD RCV VP VM NC GND SUS OE# Pin Number MIC2550BTS 1 2 3 4 5 6, 13 7 8 9 Pin Number MIC2550BML 15 1 2 3 4 5, 8, 13 16 6 7 9 System Interface Supply Voltage (Input): Determines logic voltage levels for system interface signaling to logic controller. Speed (Input): Edge rate control. Logic high selects full-speed edge rates. Logic low selects low-speed edge rates. Receive Data (Output): System interface receive data interface to logic controller. Plus (Input/Output): System interface signal to logic controller. If OE# is logic 1, VP is a receiver output (+); If OE# is logic 0, VP is a driver input (+). Minus (Input/Output): System interface signal to logic controller. If OE# is logic 1, VM is a receiver output (-); If OE# is logic 0, VM is a driver input (-). Not internally Connected Ground: Power supply return and signal reference. Suspend (Input): Logic high turns off internal circuits to reduce supply current. Output Enable (Input): Active-low system interface input signal from from logic controller. Logic low causes transceiver to transmit data onto the bus. Logic high causes the transceiver to receive data from the bus. USB Differential Data Line - (Input/Output) USB Differential Data Line + (Input/Output) Termination Supply (Output): 3.3V speed termination resistor supply output. USB Supply Voltage (Input): Transceiver supply. Pin Function
D- D+ VTRM VBUS
10 11 12 14
10 11 12 14
MIC2550
2
NC VIF VBUS NC
May 2002
MIC2550
Micrel
Absolute Maximum Ratings (Note 1)
Supply Voltage (VIF) ................................................... +6.5V Input Voltage (VBUS) ........................ -0.5V(min)/5.5V(max) Output Current (ID+, ID-)........................................... 50mA Output Current (all others) ....................................... 15mA Input Current ............................................................ 50mA Power Dissipation (PD) ................................................ TBD Storage Temperature (TS) ......................... -65 to +150C ESD, Note 3 VBUS, D+, D- ......................................................... 10kV All other pins ........................................................... 2kV
Operating Ratings (Note 2)
Supply Voltage (VBUS) ................................. 4.0V to 5.25V Temperature Range (TA) ........................... -40C to +85C Junction Temperature (TJ) ........................................ 160C Package Thermal Resistance TSSOP (JA) ..................................................... 100C/W
Electrical Characteristics
TA = 25C, bold values indicate -40C TA +85C; typical values at VBUS = 5.0V, VIF = 3.0V; minimum and maximum values at VBUS = 4.0V to 5.25V, VIF = 2.5V to 3.6V; unless noted. Symbol Parameter Condition Min Typ Max Units System and USB Interface DC Characteristics VBUS VIF VIL VIH VOH VOL IIL IIF USB Supply Voltage System I/F Supply voltage Low-Level Input Voltage, Note 4 High-Level Input Voltage, Note 4 High-Level Output Voltage, Note 4 Low-Level Output Voltage, Note 4 Input Leakage Current, Note 4 System I/F Supply Current D- and D+ are idle, VIF = 3.6V, VBUS = 5.25V SUS = 1, OE# = 1 D- and D+ are idle, VIF = 3.6V, VBUS = 5.25V SUS = 0, OE# = 1 D- and D+ active, CLOAD = 50pF, SPD = 1, SUS = 0, VIF = 3.6V, OE# = 0, f = 6MHz, Note 7 D- and D+ active, CLOAD = 600pF, SPD = 0, SUS = 0, VIF = 3.6V, OE# = 0, f = 750kHz, Note 7 IBUS USB Supply Current D- and D+ are idle, VBUS = 5.25V, SPD = 0 SUS = 1, OE# = 1 D- and D+ are idle, VBUS = 5.25V, SPD = 1 SUS = 1, OE# = 1 D- and D+ are idle, VBUS = 5.25V, SPD = 0 SUS = 0, OE# = 0 D- and D+ are idle, VBUS = 5.25V, SPD = 1 SUS = 0, OE# = 1 D- and D+ active, CLOAD = 50pF, SPD = 1, SUS = 0, VBUS = 5.25V, f = 6MHz, Note 7 D- and D+ active, CLOAD = 600pF, SPD = 0 SUS = 0, VBUS = 5.25V, f = 750kHz, Note 7 VTRM Termination Voltage ITRM = 2.5mA 10 pulses 10 pulses 3.0 6 6 ESD Protection IEC-1000-4-2 Air Discharge (D+, D-, VBUS only) Contact Discharge kV kV 1 1 325 IOH = 20A IOL = 20A 0.85VIF 0.9VIF 0.1 5 4.0 2.5 5.25 5.25 0.15VIF V V V V V V A A A A
40
A
140 140 140 200 6.75 4.25
200 200 200 350
A A A A mA mA
3.6
V
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Symbol Parameter Condition Min Typ Max
Micrel
Units A V 2.5 2.0 200 OE# = 0, RL = 1.5k to 3.6V OE# = 0, RL = 15k to GND 2.8 1.3 pin to GND steady state drive, Note 6 6 0.3 3.6 2.0 20 18 V V mV V V V pF
Transceiver DC Characteristics ILO VDI VCM VSE VOL VOH VCRS CIN ZDRV tR tF tR/tF VCRS tR tF tR/tF VCRS tPVZ tPZD tPDZ tPZV tPLH tPHL tPLH tPHL tPLH tPHL
Note 1. Note 2. Note 3. Note 4. Note 5. Note 6. Note 7.
Hi-Z State Data Line Leakage Differential Input Sensitivity Differential Common-Mode Range Single-Ended Receiver Threshold Receiver Hysteresis, Note 6 Static Output Low, Note 5 Static Output High, Note 5 Output Signal Crossover Voltage Note 6 Transceiver Capacitance, Note 6 Driver Output Resistance
0V < VBUS < 3.3V, D+, D-, OE# = 1 pins only |(D+) - (D-)|, VIN = 0.8V - 2.5V Includes VDI range
-10 0.2 0.8 0.8
+10
Low-Speed Driver Characteristics, Note 7 Transition Rise Time Transition Fall Time Rise and Fall Time Matching Output Signal Crossover Voltage CL = 50pF CL = 600pF CL = 50pF CL = 600pF TR / TF 75 300 75 300 80 1.3 125 2.0 ns ns ns ns % V
Full-Speed Driver Characteristics, Note 7 Transition Rise Time Transition Fall Time Rise and Fall Time Matching Output Signal Crossover Voltage CL = 50pF CL = 50pF TR / TF 4 4 90 1.3 20 20 111.11 2.0 ns ns % V
Transceiver Timing, Note 7 OE# to RCVR Tri-state Delay Receiver Tri-state to Transmit Delay OE# to DRVR Tri-state Delay Driver Tri-state to Receiver Delay V+/V- to D+/D- Propagation Delay V+/V- to D+/D- Propagation Delay D+/D- to RCV Propagation Delay D+/D- to RCV Propagation Delay D+/D- to V+/D- Propagation Delay D+/D- to V+/D- Propagation Delay Figure 1 Figure 1 Figure 1 Figure 1 Figure 4 Figure 4 Figure 3 Figure 3 Figure 3 Figure 3 15 15 15 15 15 8 8 15 15 15 ns ns ns ns ns ns ns ns ns ns
Exceeding the absolute maximum rating may damage the device. The device is not guaranteed to function outside its operating rating. Devices are ESD sensitive. Handling precautions recommended. Human body model, 1.5k in series with 100pF. Applies to the VP, VM, RCV, OE#, SPD, and SUS pins. Applies to D+, D-. Not production tested. Guaranteed by design. Characterized specification(s), but not production tested.
MIC2550
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Micrel
Timing Diagrams
H
VOE#
L
tPVZ VP VP/VM VM tPZD VD+ VD+/VD- VD-
tPZV
Figure 1. Enable and Disable Times
VD+ Differential 90% Data Lines 10% VD-
VCRS tR tF
Figure 2. Rise and Fall Times
Differential VD+ Data Lines V D- VOH Output V OL VSS
tPLH
tPHL
Figure 3. Receiver Propagaion Delay D+/D- to RCV, VP, and VM
VOI Input V OL VSS Differential VD+ Data Lines V D-
tPLH
tPHL
Figure 4. Driver Propagation Delay VP and VM to D+/D-
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OE# = 0 (Transmit): Input VP 0 0 1 1 OE# = 1 (Receive): Input D+ 0 0 1 1 D- 0 1 0 1 VP 0 0 1 1 Output VM 0 1 0 1 RCV X 0 1 X Result SE0 Logic 0 Logic 1 Undefined VM 0 1 0 1 D+ 0 0 1 1 Output D- 0 1 0 1 RCV X 0 1 X Result SE0 Logic 0 Logic 1 Undefined
Table 1. Truth Table
Test Circuits
Test Point Device Under Test 24 50pF For D+, D--: V = 0V for tPZH and tPHZ V = VBUS for tPZL and tPLZ 500 V
Figure 5. Load for Enable and Disable Time (D+, D-)
Device Under Test
25pF
Figure 6. VP, VM and RCV Load
VTRM 1.5k*
Device Under Test
24 15k CL
CL = 50pF, full speed CL = 50pF, low speed (minimum timing) CL = 600pF, low speed (maximum timing) *1.5k on D- for low speed or D+ for high speed
Figure 7. D+ and D- Load MIC2550 6 May 2002
MIC2550
Micrel
Block Diagram
SYSTEM I/F VOLTAGE DOMAIN USB VOLTAGE DOMAIN
VIF
Regulator
TO INTERNAL CIRCUITS
VBUS VTRM
SPD
D- D+
OE#
RCV
VP
VM SUS GND
May 2002
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MIC2550
Micrel Internal 3.3V source If the device is self-powered and has 3.3V available, the circuit in Figure 10 is yet another power supply configuration option. In this configuration, the internal regulator is disabled and the 3.3V source and not VBUS powers the entire chip.
MIC2550 VIF VBUS 3.3V
Applications Information
The MIC2550 is designed to provide USB connectivity in mobile systems where system supply voltages are not available to satisfy USB requirements. The MIC2550 can operate down to supply voltages of 2.5V and still meet USB physical layer specifications. As shown in the system diagram, the MIC2550 takes advantage of USB's supply voltage, VBUS, to operate the transceiver. The system voltage, VIF, is used to set the reference voltage used by the digital I/O lines (VP, VM, RCV, OE#, SPD, and SUS pins) interfacing to the system. Internal circuitry provides translation between the USB and system voltage domains. VIF will typically be the main supply voltage rail for the system. In addition, a 3.3V, 10% termination supply voltage, VTRM, is provided to support speed selection. A 0.47F (minimum) capacitor from VTRM to ground is required to ensure stability. A 1.5K resistor is required between this pin and the D+ or D- lines to respectively specify full-speed or low-speed operation. Power Supply Configurations VIF/VBUS Switched When the VBUS input pin is pulled to ground a low impedance path between VIF and VBUS can cause a high current flow from VIF to VBUS thereby damaging the MIC2550. This issue can arise in systems where VBUS is driven from a power supply that can be switched off such as in the case of a desktop PC. Adding a Schottky diode, such as the ZHCS1000 by Zetex, in series with VBUS will prevent any current flow during this condition. A solution is shown in Figure 8 below. If the VIF source is current limited to less than 50mA, then diode D1 is not neccessary.
MIC2550 USB Device Power Controller VIF VBUS *(Optional) 1F min D1 ZHCS1000 or equivelant VBUS
VTRM
Figure 10. Powering Chip from Internal 3.3V Source Suspend When the suspend pin (SUS) is high, power consumption is reduced to a minimum. VTRM is not disabled. RCV, VP and VM are still functional to enable the device to detect USB activity. For minimal current consumption in suspend mode, it is recommended that OE# = 1. External ESD Protection The use of ESD transient protection devices is not required for operation, but is recommended. We recommend the following devices or the equivalent: Cooper Electronics Technologies (www.cooperet.com) 41206ESDA SurgX(R) 0805ESDA SurgX(R) Littelfuse (www.littelfuse.com) V0402MHS05 SP0503BAHT Non-multiplexed Bus To save pin count for the USB logic controller interface, the MIC2550 was designed with VP and VM as bidirectional pins. To interface the MIC2550 with a non-multiplexed data bus, resistors can be used for low cost isolation as shown in Figure 11.
USB Logic Controller (SIE)
Note: *(Optional) See Text - Power Supply Configurations
MIC2550 VP 10k
Figure 8. Solution to VIF/VBUS Switching
VP VPO VM 10k VMO
I/O Interface using 3.3V In systems where the I/O interface utilizes a 3.3V USB controller, an alternate solution is shown in Figure 9. This configuration has the advantage over Figure 8, in that no extra components are needed. Ensure that the load on VTRM does not exceed 1mA total.
3.3V MIC2550 VDD USB Controller I/O VP/VM/ VTRM RCV/OE# VIF VBUS VBUS
VM
Figure 11. MIC2550 Interface to Non-multiplexed Data Bus
Figure 9. I/O Interface uses 3.3V
MIC2550
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May 2002
MIC2550
Micrel
PCB Layout Recommendations
Although the USB standard and applications are not based in an impedence controlled environment, a properly designed PCB layout is recommended for optimal transceiver performance. The suggested PCB layout hints are as follows: * Match signal line traces (VP/VM, D+, D-) to 40ps, approximately 1/3 inch if possible. FR-4 PCB material propagation is about 150ps/inch, so to minimize skew try to keep VP/VM, D+/D- traces as short as possible. * For every signal line trace width (w), separate the signal lines by 1.5-2 widths. Place all other traces at >2w from all signal line traces. * Maintain the same number of vias on each differential trace, keeping traces approximately at same separation distance along the line. * Control signal line impedences to 10%. * Keep RS as close to the IC as possible, with equal distance between RS and the IC for both D+ and D-.
May 2002
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MIC2550
Micrel
Package Information
4.50 (0.177) 6.4 BSC (0.252) 4.30 (0.169)
DIMENSIONS: MM (INCH)
0.30 (0.012) 0.19 (0.007) 5.10 (0.200) 4.90 (0.193) 1.10 MAX (0.043) 0.20 (0.008) 0.09 (0.003)
0.65 BSC (0.026)
0.15 (0.006) 0.05 (0.002)
8 0
1.00 (0.039) REF 0.70 (0.028) 0.50 (0.020)
14-Pin TSSOP (TS)
0.85 +0.15 -0.65 3.00BSC 2.75BSC
16 1
0.42 +0.18 -0.18 0.23 +0.07 -0.05 0.01 +0.04 -0.01 1.60 +0.10 -0.10 0.42
+0.18 -0.18
0.65 +0.15 -0.65 0.20 REF.
N
PIN 1 ID
1
0.50 DIA
2 3 4
2.75BSC 3.00BSC
2 3 4
1.60 +0.10 -0.10
12 max SEATING PLANE TOP VIEW CC C L 4 0.23 +0.07 -0.05 0.01 +0.04 -0.01 1. 2. 3. 4.
0.42 +0.18 -0.18
0.5 BSC 1.5 REF BOTTOM VIEW
0.5BSC FOR EVEN TERMINAL/SIDE
SECTION "C-C" SCALE: NONE
DIMENSIONS ARE IN mm. DIE THICKNESS ALLOWABLE IS 0.305mm MAX. PACKAGE WARPAGE MAX 0.05mm. THIS DIMENSION APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.20mm AND 0.25mm FROM TIP. 5. APPLIES ONLY FOR TERMINALS
16-Pin MLFTM (ML)
MICREL INC.
TEL
1849 FORTUNE DRIVE SAN JOSE, CA 95131
FAX
USA
+ 1 (408) 944-0800
+ 1 (408) 944-0970
WEB
http://www.micrel.com
This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc. (c) 2002 Micrel Incorporated
MIC2550
10
May 2002

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