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E2B0050-18-90
Semiconductor
Semiconductor ML9070-02/03
DESCRIPTION
This version: Sep. 1998 ML9070-02/03
DIRECT BUS CONNECTED CMOS REAL TIME CLOCK/CALENDAR
The ML9070-02/03 is a silicon gate CMOS Real Time Clock/Calendar for use in direct busconnection Microcontroller/Microprocessor applications. An on-chip 32.768 kHz crystal oscillator time base is divided to provide addressable 4-bit I/O data for SECONDS, MINUTES, HOURS, DAY OF WEEK, DATE, MONTH and YEAR. Data access is controlled by 4-bit address, chip selects (CS0, CS1), WRITE, READ, and ALE. The ML9070-03 is not provided with the ALE pin. Control Registers D, E and F provide 30 SECOND error adjustment, INTERRUPT REQUEST (IRQ FLAG) and BUSY status bits, clock STOP, HOLD, and RESET FLAG bits, 4 selectable INTERRUPTS rates are available at the STD.P (STANDARD PULSE) output utilizing Control Register inputs T0, T1 and the INT/STND (INTERRUPT/STANDARD). Masking of the interrupt output (STD.P) can be accomplished via the MASK bit. The ML9070-02/03 can operate in a 12/24 hour format and Leap Year timing is automatic. The interface supply voltage is 2.7 V to 5.5 V and the clock supply voltage during battery backup is 2.0 V to 5.5 V. A low current consumption has been realized.
FEATURES
* Real time clock/calendar of SECONDS, MINUTES, HOURS, DAY OF WEEK, DATE, MONTH and YEAR * 4-bit data bus * 4-bit address bus * READ, WRITE ALE, and CHIP SELECT INPUTS * Auto leap year * 30 second error correction by software * Selectable interrupt outputs - 1/64 second, 1second, 1minute, 1hour * Stop and restart of clock * 12/24 hour format * The ML9070-02 can input ALE from a microcontroller. (In case there is no ALE input from a microcontroller, fix ALE to "H" or use ML9070-03.) * Wide range of interface power supply : 2.7 V to 5.5 V * Wide range of clock power supply : 2.0 V to 5.5 V * Low current consumption ML9070-02 * 18-pin plastic DIP (DIP18-P-300-2.54) * 24-pin plastic SOP (SOP24-P-430-1.27-K) ML9070-03 * 16-pin plastic DIP (DIP16-P-300-2.54) * 16-Pin plastic SOP (SOP16-P-300-1.27-K)
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Semiconductor
(Note) The ML9070-03 operates similarly as when CS0 is fixed to "L", and ALE to "H".
XT 32.768 kHz XT OSC COUNTER 1 Hz
RESET bit STOP bit HOLD 30secADJ bit BUSY bit bit
FUNCTIONAL BLOCK DIAGRAM
30 sec ADJ bit S 10 MI 1 MI 10 H1
24/12bit H 10 W
D3 D2 D1 D0 WR RD G A T E G A T E S1
D1
D 10
MO 1 MO 10
Y1
Y 10
A3 A2 A1 A0 CS 0 ALE CS 1
G A T E & L A T C H
D E C O D E R
S1 S CF
CD
CE
CF
64Hz 1-sec carry 1-min carry 1-hour carry
STD.P
GATE
* S1 to W to Y10 are time counter registers. * CD to DF are control registers.
ML9070-02/03
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Semiconductor
ML9070-02/03
PIN CONFIGURATIONS
ML9070-02RA (Top View) 18-Pin Plastic DIP STD.P 1 CS 0 2 ALE 3 A0 4 A1 5 A2 6 A3 7 RD 8 VSS 9 18 VDD 17 XT 16 XT 15 CS1 14 D0 13 D1 12 D2 11 D3 10 WR STD.P 1 CS 0 2 NC 3 ALE 4 A0 5 NC 6 A1 7 NC 8 A2 9 A3 10 RD 11 VSS 12 ML9070-02MA (Top View) 24-Pin Plastic SOP 24 VDD 23 XT 22 XT 21 NC 20 CS1 19 D0 18 NC 17 NC 16 D1 15 D2 14 D3 13 WR
NC : NO CONNECTION (Unused pin)
Note)
"M9070-02" is marked on actual devices.
ML9070-03RA (Top View) 16-Pin Plastic DIP STD.P 1 A0 2 A1 3 A2 4 A3 5 RD 6 WR 7 VSS 8 16 VDD 15 XT 14 XT 13 CS1 12 D0 11 D1 10 D2 9 D3 STD.P 1 A0 2 A1 3 A2 4 A3 5 RD 6 WR 7 VSS 8 ML9070-03MA (Top View) 16-Pin Plastic SOP 16 VDD 15 XT 14 XT 13 CS1 12 D0 11 D1 10 D2 9 D3
Note)
"M9070-03" is marked on actual devices.
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Semiconductor
ML9070-02/03
PIN DESCRIPTION
* D0 to D3 (Data bus 0 to 3) Data bus Input/output pins to be directly connected to a microcontroller bus for reading and writing of the clock/calendar's registers and control registers. The interface is logically positive. When CS0 = "L", CS1 = "H", RD = "L" and WR = "H", these pins are in the output mode. Otherwise these pins are in the high impedance state. The ML9070-03 has no CS0 pin and operates similarly as when CS0 is fixed to "L". In the ML9070-03, input/output of these pins are determined by the same settings as those in the ML9070-02 except setting of the CS0 pin. * A0 to A3 (Address bus 0 to 3) Address input pin for use by a microcontroller to select internal clock/calendar's registers and control registers for Read/Write operations. Address input pins A0 - A3 are used in combination with ALE for addressing registers. * ALE (Address Latch Enable) Address Latch Enable pin. This pin enables writing of address data when ALE = "H" and CS0 = "L" ; address data is latched when ALE = "L". Microcontroller having an ALE output should connect to this pin ; otherwise it should be connected at VDD. CS1 works independently of ALE. When a 4-bit microcontroller and other peripheral ICs share A0 to A3, ALE is also used to specify this IC. The ML9070-03 has no ALE pin and operates similarly as when ALE is fixed to "H". * WR (WRite) Writing of data is performed by this pin. When CS1 = "H" and CS0 = "L", D0 - D3 data is written into the register specified by A0 to A3 and ALE at the rising edge of WR. * RD (ReaD) Reading of register data is accomplished using this pin. When CS1 = "H", CS0 = "L" and RD = "L", the data of this register is output to D0 - D3. It is inhibited to set both RD and WR to "L" simultaneously because this setting causes a malfunction. * CS0, CS1 (Chip Select 0, 1) Chip Select pins. These pins enable or disable ALE, RD and WR operations. CS0 and ALE work in combination with one another. When CS0 = "L" and CS1 = "H", ALE, RD and WR are enabled. Otherwise, the device is unconditionally equivalent to ALE = "L", WR = RD = "H". For details, refer to "CS1 (Chip Select)" in "APPLICATION NOTE". The ML 9070-03 has no CS0 pin and operates similarly as when ALE is fixed to "H" and CS0 to "L". * STD.P (STanDard Pulse) Output pin of N-CH OPEN DRAIN type. The output data is controlled by the D1 data (INT/ STD bit) content of CE register. This pin has a priority to CS0 and CS1. Refer to "CE Register" in "FUNCTIONAL DESCRIPTION OF REGISTERS".
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Semiconductor * XT, XT (X'Tal OSC) 32.768kHz crystals are connected to these pins. The connection diagram is shown below.
ML9070-02/03
XT C1 V DD (or V SS ) C2 XT XT ML9070-XX C1, C2 = 10 to 30pF
The impedance of the crystal should be less than 30kW. When an external clock is used, it is to be input to XT, while XT should be left open. The oscillation crystal and capacitors should be placed as close to the IC as possible. The oscillation circuit and other signal lines on any side of the substrate should be distant from each other. * VDD, VSS Power supply pins. VDD is used for positive supply and VSS is for negative supply.
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ML9070-02/03
ABSOLUTE MAXIMUM RATING
Parameter Power Supply Voltage Input Voltage Output Voltage Storage Temperature Symbol VDD VI VO TSTG -- Ta = 25C Condition Rating -0.3 to +7.0 VSS-0.3 to VDD+0.3 VSS-0.3 to VDD+0.3 -55 to +150 C V Unit
OPERATING CONDITIONS
Parameter Power Supply Voltage Clock Supply Voltage Crystal Frequency Operating Temperature Symbol VDD VCLK f(XT) Top Condition -- -- -- -- Rating 2.7 to 5.5 2.0 to 5.5 32.768 -40 to +85 Unit V V kHz C
(Note) The clock supply voltage assures crystal oscillation and clock.
DC CHARACTERISTICS
(VDD = 2.7 to 5.5V, Ta = -40 to +85C) Parameter "H" Input Voltage (1) "L" Input Voltage (1) "H" Input Current (1) "L" Input Current (1) "H" Input Voltage (2) "L" Input Voltage (2) "H" Input Current (2) "L" Input Current (2) "H" Output Voltage "L" Onput Voltage (2) OFF Leak Current Current Consumption (1) Current Consumption (2) Symbol VIH1 VIL1 IIH1 IIL1 VIH2 VIL2 IIH2 IIL2 VOH VOL2 IOFF IDD1 IDD2 Condition VDD = 2.7 to 4.0 V VDD = 4.0 to 5.5 V VDD = 2.7 to 4.0 V VDD = 4.0 to 5.5 V VI = VDD VI = 0 V VDD = 2.0 to 5.5 V VDD = 2.0 to 5.5 V VI = VDD VI = 0 V IO = 2.5 mA IO = -400 mA IO = 2.5 mA VI = VDD or 0 V, VO = VDD
f(XT) = 32.768 kHz VDD = 5 V VI(CS1) = 0 V VDD = 2 V
Min. 4/5VDD 2.2 VSS VSS -- -- 4/5VDD VSS -- -- -- 2.4 -- -- -- --
Typ. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Max. VDD VDD 1/5VDD 0.8 1 -1 VDD 1/5VDD 10 -10 0.4 -- 0.4 10 20 5
Unit Applicable Terminal V V V V mA mA V V mA mA V V V mA mA mA VDD STD. P D0 to D3 D0 to D3 Input terminals other than D0 to D3, XT CS1 All input terminals except CS1,XT
"L" Output Voltage (1) VOL1
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SWITCHING CHARACTERISTICS
l ML9070-02/03 * WRITE mode (ALE = "H")
(VDD = 2.7 to 5.5 V, Ta = -40 to +85C) Parameter CS1 Setup Time CS1 Hold Time Address Stable Before WRITE Address Stable After WRITE WR Pulse Width Data Setup Time Data Hold Time RD / WR Recovery Time Symbol tC1S tC1H tAW tWA tWW tDS tDH tRCV Condition -- -- -- -- -- -- -- -- Min. 100 100 20 10 120 100 10 60 Max. -- -- -- -- -- -- -- -- ns Unit
CS1 A 0 - A3 CS 0 WR
VIH2 tC1S VIH1 VIL1 tAW VIH1 VIL1 tWW VIH1 VIL1 tDS VIH1 VIH1 VIL1 VIL1 VIH1=2.2V VIL1=0.8V VIH2=
4 V 5 DD
VIH2 tC1H VIH1 VIL1 tWA tRCV VIH1 VIH1 VIL1
tDH
D0 - D 3 (Input)
(Note)
The ML9070-03 has no CS0 input.
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Semiconductor l ML9070-02 * WRITE mode (with use of ALE)
ML9070-02/03
(VDD = 2.7 to 5.5 V, Ta = -40 to +85C) Parameter CS1 Setup Time Address Setup Time Address Hold Time ALE Pulse Width ALE Before WRITE WRITE Pulse Width ALE After WRITE DATA Setup Time DATA Hold Time CS1 Hold Time RD / WR Recovery Time Symbol tC1S tAS tAH tAA tALW tWW tWAL tDS tDH tC1H tRCV Condition -- -- -- -- -- -- -- -- -- -- -- Min. 100 25 25 40 10 120 20 100 10 100 60 Max. -- -- -- -- -- -- -- -- -- -- -- ns Unit
CS1 A0 - A3 CS 0
VIH2 tC1S tAS VIH1 VIL1 tAA tAH VIH1 VIL1
tC1H
VIH2
ALE
VIH1
VIH1
VIL1 tALW tWW VIH1 VIL1 tDS VIH1 VIL1 tDH VIH1 VIL1 VIH2=
4 V 5 DD
VIL1 tWAL tRCV VIH1
WR
D0 - D3 (Input) VIH1=2.2V VIL1=0.8V
VIH1 VIL1
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Semiconductor l ML9070-02/03 * READ mode (ALE = "H")
ML9070-02/03
(VDD = 2.7 to 5.5 V, Ta = -40 to +85C) Parameter CS1 Setup Time CS1 Hold Time Address Stable Before READ Address Stable After READ RD to Data Data Hold RD / WR Recovery Time Symbol tC1S tC1H tAR tRA tRD tDR tRCV Condition -- -- -- -- CL = 150pF -- -- Min. 100 100 -10 0 -- 0 60 Max. -- -- -- -- 120 -- -- ns Unit
CS1 A0 - A 3 CS 0 RD
VIH2 tC1S VIH1 VIL1 VIH1 VIH1 VIL1 tRD VIL1 tDR VOH VOH VOL1 VOL1 VIH1=2.2V VIL1=0.8V VIH2= 4 VDD 5 tAR tRA VIH1 VIL1
tC1H
VIH2
VIH1 VIL1 tRCV VIH1
D0 - D 3 (Output)
"Z"
VOH=2.4V VOL1=0.4V
(Note)
The ML9070-03 has no CS0 input.
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Semiconductor l ML9070-02 * READ mode (with use of ALE)
ML9070-02/03
(VDD = 2.7 to 5.5 V, Ta = -40 to +85C) Parameter CS1 Setup Time Address Setup Time Address Hold Time ALE Pulse Width ALE Before READ ALE After READ RD to Data DATA Hold CS1 Hold Time RD / WR Recovery Time Symbol tC1S tAS tAH tAA tALR tRAL tRD tDR tC1H tRCV Condition -- -- -- -- -- -- CL = 150pF -- -- -- Min. 100 25 25 40 10 10 -- 0 100 60 Max. -- -- -- -- -- -- 120 -- -- -- ns Unit
CS1 A0 - A 3 CS 0
VIH2
tC1S tAS VIH1 VIL1
VIH2 tAH VIH1 VIL1 tC1H
tAA ALE VIH1 VIH1 VIL1 tALR RD VIH1 tRD D0 - D 3 (Output) VIH1=2.2V VIL1=0.8V VIH2= 4 VDD 5 VOH=2.4V VOL1=0.4V VIH1 VIL1 tDR VOH VOL1 VOH VOL1 "Z" tRAL tRCV VIH1 VIL1
VIL1
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ML9070-02/03
REGISTER TABLE
Address Input 0 1 2 3 4 5 6 7 8 9 A B C D E F Address Input Register Name A3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 A2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 S1 S10 MI1 MI10 H1 H10 D1 D10 MO1 MO10 Y1 Y10 W CD CE CF D3 (MSB) s8 f0 mi8 * h8 * d8 * mo8 * y8 y80 D2 s4 s40 mi4 mi40 h4 PM/AM d4 * mo4 * y4 y40 w4 Data D1 s2 s20 mi2 mi20 h2 h20 d2 d20 mo2 * y2 y20 w2 BUSY D0 (LSB) s1 s10 mi1 mi10 h1 h10 d1 d10 mo1 mo10 y1 y10 w1 HOLD Count value 0 to 9 0 to 5 0 to 9 0 to 5 0 to 9 0 to 2 or 0 to 1 0 to 9 0 to 3 0 to 9 0 to 1 0 to 9 0 to 9 0 to 6 -- -- -- Description
1-second digit register 10-second digit register 1-minute digit register 10-minute digit register 1-hour digit register PM/AM, 10-hour digit register 1-day digit register 10-day digit register 1-month digit register 10-month digit register 1-year digit register 10-year digit register Week register Control Register D Control Register E Control Register F
* 30 sec. IRQ-F ADJ t1 TEST t0 24/12
INT MASK /STND STOP REST
REST = RESET INT/STND = INTERRUPT/STANDARD Note 1) -- Bit* does not exist (unrecognized during a write and held at "0" during a read). Note 2) -- Be sure to mask the AM/PM bit when processing 10's of hour's data. Note 3) -- BUSY bit is read only. The IRQ-F bit can only be set to a "0". Setting the IRQ-F to a "1" is done by hardware. Note 4) -- PM at 1 and AM at 0 for PM/AM bit. Note 5) -- "1" or "0" may be written to bit *. Note 6) -- The bit fo (OSC FLAG) memorizes that oscillation stops. This bit is used to monitor the battery. This bit is cleared by writing a "0". A "1" cannot be written into this bit.
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Semiconductor
ML9070-02/03
FUNCTIONAL DESCRIPTION OF REGISTERS
S1, S10, MI1, MI10, H1, H10, D1, D10, MO1, MO10, Y1, Y10,W a) These are abbreviations for SECOND1, SECOND10, MINUTE1, MINUTE10, HOUR1, HOUR10, DAY1, DAY10, MONTH1, MONTH10, YEAR1, YEAR10, and WEEK. These values are in BCD notation. b) All registers are logically positive. For example, (s8, s4, s2, s1) = 1001 which means 9 seconds. c) "1" or "0" may be written to bit* in the Register Table. The bit* automatically reads "0". d) If data is written which is out of the clock register data limits, it can result in erroneous clock data being read back. * PM/AM, h20, h10 a) In 12-hour mode The existent time is AM12 : 00 through AM11 : 00 and PM12 : 00 through PM11 : 00. It is impossble to write data into the h20, bit which is fixed to "0" unconditionally. The h20 bit is not set by clocking. b) In 24-hour mode The existent time is 0 : 00 clock through 23 : 00 clock. The PM/AM bit written is ignored and read out as "0" unconditionally. * Y1, Y10, and leap year The ML9070 automatically recognizes leap years in either Christian Era calendar or Heisei Era (Japanese) calendar. 80, 84, 88... Leap year When invalid month and day values are set (for instance, February 29, 1983 or November 31), the month and day values will be carried to the next month and day values when the carry pulse to the day digit is generated (for instance, the above dates become March 1, 1983 and December 1). The ML9070 recognizes a year whose last two digits can be divided evenly by 4 as leap year. Therefore, year 2100, which does not include a leap day, is excluded from automatic leap year correction. Year 2000 will be corrected automatically since the year contains a leap day. The user must check whether the year is year 2000 or 2100 when Y10, Y1 = "0, 0".
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Semiconductor
ML9070-02/03
The Register W data limits are 0 - 6 (The table below shows a possible bit data definition).
W4 0 0 0 0 1 1 1 W2 0 0 1 1 0 0 1 W1 0 1 0 1 0 1 0 Day of Week Sunday Monday Tuesday Wednesday Thursday Friday Saturday
f0 Flag The f0 flag bit memorizes that oscillation stops and is used to monitor the output of the battery. The "1" of this bit indicates stop of oscillation. This bit is cleared by writing "0". It is not permitted to write "1" into this bit. "0" cannot be written in this bit during stop of oscillation.
CD REGISTER (Control D Register) * 30-sec ADJ (D3) (30-second adjustment bit) When a "1" is written to this bit, if the second digits are smaller than 30, the second digits are reset to 00, and if it is larger than 30, the second digits are reset to 00 and a carry into the minute digit is executed. Data cannot be written into the S1 - W registers and a "1" can not be written into the REST bit of the CF register 125ms after writing into this bit because internal processing is being executed. This bit holds "1" 125ms after writing, and returns to "0" automatically. Therefore, data should be written into the S1 - W registers after checking that this bit has returned to "0". * IRQ-F (D2) (Interrupt ReQuest Flag) This status bit corresponds to the output level of the STD.P output. When STD.P = "L", then IRQ-F = "1", when STD.P = high impedance, then IRQ-F = "0". The IRQ-F indicates that an interrupt has occurred in the microcomputer if IRQ-F = "1". When D0 of register CE (MASK) = "0", then the STD.P output changes from high impedance to "L" and IRQ-F changes from "0" to "1" according to the timing set by D3 (t1) and D2 (t0) of register CE. When D1 of register CE (INT/STND) = "1" (interrupt mode), the STD.P output remains "L" until the IRQ-F is written to a "0". When IRQ-F = "1" and timing for a new interrupt occurs, the new interrupt is ignored. When D1 (INT/STND) = "0" (Standard Pulse Output mode) the STD.P output remains "L" until either "0" is written to the IRQ-F or the IRQ-F automatically goes to "0" after 7.8125ms.
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Semiconductor
ML9070-02/03
* BUSY (D1) Internal status bit that indicates whether interface with a microcontroller is enabled or disabled. To write data in registers S1 to W (addresses 0 to C), the HOLD bit must be set to "1" and the BUSY bit must be set to "0". To read data, the BUSY bit must be set to "0" when the HOLD bit is used. The BUSY bit is kept to "0" while the HOLD bit is "1". When the HOLD bit is set to "0", the BUSY bit is set to "1". The IRQ-F of register CD, CE and CF operations can be performed regardless of the settings of the HOLD bit and the BUSY bit. When the HOLD bit is set to "0", the BUSY bit is set to "1" unconditionally and BUSY/non-BUSY can be checked by writing "1" to the HOLD bit. When BUSY = "1" (BUSY status) is read, check BUSY = "0" as follows : Repeat the BUSY checking routine by writing "0" and then "1" to the HOLD bit (HOLD 0, HOLD 1, BUSY check) or write "1" to the HOLD bit again 190 micro seconds after writing "0" to the HOLD bit. The BUSY status lasts 190 micro seconds per one second. Data cannot be written to the BUSY bit. * HOLD (D0) Bit used for reading and writing registers S1 to W (addresses 0 to C), When "1" is written to this bit and the BUSY bit is "0", the clock of one second digit or more is stopped, enabling Read/ Write operations. When BUSY is "1" or Read/Write is completed, "0" is written to the HOLD bit. If the writing of "0" is omitted, data may be corrupted. By setting this bit to "1", the carry of one-second digit is prohibited inside the IC. However, the carry to the second digit that was generated during the "1" interval will be corrected automatically (+1 second) once only when "0" is written to this bit. However, next and subsequent carry will be ignored and data will not be corrected. (Loss of second) . When CS1 is set to "L", the HOLD bit will become "0" like that "0" is written to the HOLD bit.
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Semiconductor CE REGISTER (Control E Register) * t1 (D3), T0 (D2) (Time 0, 1) INT/STND bit = "1" : Setting of interrupt period INT/STND bit = "0" : Setting of periodic waveform
t1 0 0 1 1 t0 0 1 0 1 Period 1-64 second 1 second 1 minute 1 hour
ML9070-02/03
The duration that the periodic waveform output is at "L" level is about 7.8125ms. t1 and t0 determine the output timing of the STD.P output. e.g.) When t1 = "1", t0 = "1", MASK = "0"
12:00PM 1:00PM
STD.P output when INT/STND = "1"
High impedance "L" level High impedance "L" level
STD.P output when INT/STND = "0"
When a "1" is written to the 30-sec ADJ bit, a carry can occur. Therfore, if (t1, t0) = (1, 0), (1, 1), the STD.P output may sometime be at "L" level. When INT/ STND = "0", this "L" level is kept for a maximum of 9.8ms after under-second digits in 30-sec ADJ is cleared (the 30-sec ADJ flag returns to "0"). If the selected interrupt period is 1 second, 1 minute, or 1 hour, a carry occurs during the time the S1, S10, MI1, MI10 registers are overwritten using the HOLD bit, and data written in these registers determines the interrupt timing set by the carry, the STD.P output will go to "L" level after HOLD = "0". (IRQ-F will is set to "1") In other cases, writing to the S1, S10, MI1, MI10, H1 registers do not change the STD.P output. * INT/STND (D1) (interrupt-to-Standard waveform switching bit) INT/STND = "1" : "1" of the IRQ-F bit and "L" level on the STD.P output are kept until IRQ-F (CD register) is read out. INT/STND = "0" : "1" of the IRQ-F bit returns to "0" after a certain time elapses (after about 7.8ms) or when IRQ-F is read out. "L" level on the STD.P output returns to high impedance after a certain time elapses. 15/23
Semiconductor
ML9070-02/03
* MASK (D0) "1" of the MASK bit inhibits the setting of "1" to the IRQ-F flag and sets the STD.P output to the high impedance state. Interrupt mode (INT/STND = "1")
"1" MASK bit "0" "0"
"1"
No interrupt is generated because of MASK bit = "1". High impedance STD. P output "L" level "1" IRQ-F "0" Interrupt timing IRQ-F is read out.
Periodic timing waveform output mode (INT/STND = "0")
"1" MASK bit "0" "0"
"1"
No "L" level is output because of MASK bit = "1". High impedance STD.P output "L" level "1" IRQ-F "0" Output timing Auto-return (duration of "L" is 7.8125ms)
When the IRQ-F bit is read out before auto-return, the IRQ-F bit goes to "0", and the STD.P output keeps "L" level for 7.8125 ms, then goes into the high impedance state.
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Semiconductor CF REGISTER (Control F Register) * TEST (D3) The TEST bit is used for testing by OKI and should be set to "0".
ML9070-02/03
* 24/12 (D2) (24/12 hour format) This bit is used to switch between 24-hour format and 12-hour format. 24/12 = "1" : 24-hour format without PM/AM 24/12 = "0" : 12-hour format with PM/AM When the 24/12 bit is changed, data in the H1 - W registers may become undefined. Therefore, it is required to set those registers again. * STOP (D1) "1" of this bit stops clocking and "0" restarts clocking. * REST (D0) "1" of this bit clears under-second-time to zero and at the same time stops clocking. "0" of this bit restarts clocking. When CS1 is set to "L", this bet goes to "0" automatically.
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Semiconductor
ML9070-02/03
APPLICATION NOTE
Power Supply
START
VDD = 2.7 to 5.5 V * VDD changes from zero to 2.7 V - 5.5 V (interface voltage). * All registers and STD.P output are undefined.
Power On
TEST Bit 0 REST Bit 0 24/12 Bit 1* STOP Bit 1 BEST Bit 0 24/12 Bit 2*
1* = 2* (1 or 0)
Set the current time HOLD Bit 0 STOP Bit 0 Start Operation
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Semiconductor CS1 (Chip Select)
ML9070-02/03
VIH and VIL of CS1 has 3 functions. a) To accomplish the interface with a microcontroller/microprocessor. b) To inhibit the control bus, data bus and address bus and to reduce input gate pass current in the stand-by mode. c) To protect internal data when the mode is moved to and from standby mode. To realize the above functions: a) More than 4 VDD should be applied to the ML9070 for the interface with a microcontroller/ 5 microprocessor. b) In moving to the standby mode, lessthan 1 VDD should be applied so that all data buses 5 should be disabled. In the standby mode, approx. 0V should be applied. c) When moving to and from the standby mode, obey the following timing chart.
Moving to Standby Mode 2.7 V to 5.5 V VDD 2.7 V 2.0 V to 2.7 V CS1
4 5
Moving from Standby Mode
2.7 V 2 ms (MIN)
1 5
VDD
1 5
2 ms (MIN) VDD
1 5
VDD or less
VDD
4
4 5
VDD
CS 0 = "H" or WR = "H"
More than 5 VDD is required for interface with this IC.
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Semiconductor
ML9070-02/03
PACKAGE DIMENSIONS
(Unit : mm)
DIP18-P-300-2.54
Package material Lead frame material Pin treatment Solder plate thickness Package weight (g)
Epoxy resin 42 alloy Solder plating 5 mm or more 1.30 TYP.
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Semiconductor
ML9070-02/03
(Unit : mm)
SOP24-P-430-1.27-K
Mirror finish
Package material Lead frame material Pin treatment Solder plate thickness Package weight (g)
Epoxy resin 42 alloy Solder plating 5 mm or more 0.58 TYP.
Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
21/23
Semiconductor
ML9070-02/03
(Unit : mm)
DIP16-P-300-2.54
Package material Lead frame material Pin treatment Solder plate thickness Package weight (g)
Epoxy resin 42 alloy Solder plating 5 mm or more 0.99 TYP.
22/23
Semiconductor
ML9070-02/03
(Unit : mm)
SOP16-P-300-1.27-K
Mirror finish
Package material Lead frame material Pin treatment Solder plate thickness Package weight (g)
Epoxy resin Cu alloy Solder plating 5 mm or more 0.21 TYP.
Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
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E2Y0002-28-41
NOTICE
1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. Neither indemnity against nor license of a third party's industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party's right which may result from the use thereof. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. No part of the contents cotained herein may be reprinted or reproduced without our prior permission. MS-DOS is a registered trademark of Microsoft Corporation.
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Copyright 1998 Oki Electric Industry Co., Ltd.
Printed in Japan

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