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MPC8245RZUPNS/D Rev. 0, 3/2002 MPC8245 Part Number Specification for the XPC8245RZUnnnx Series
Motorola Part Numbers Affected: XPC8245RZU400B
This document describes part-number-specific changes to recommended operating conditions and revised electrical specifications, as applicable, from those described in the general MPC8245 Integrated Processor Hardware Specifications (order # MPC8245EC/D). Specifications provided in this document supersede those in the MPC8245 Integrated Processor Hardware Specifications, Rev.0.5 or later, for the part numbers listed in Table A only. Specifications not addressed herein are unchanged. Because this document is frequently updated, refer to http://www.motorola.com/semiconductors or to your Motorola sales office for the latest version. Note that headings and table numbers in this document are not consecutively numbered. They are intended to correspond to the heading or table affected in the general hardware specification. Part numbers addressed in this document are listed in Table A. For more detailed ordering information see Section 1.9, "Ordering Information."
Table A. Part Numbers Addressed by this Data Sheet
Operating Conditions Motorola Part Number XPC8245RZU400B CPU Frequency 400 MHz VDD 2.1 100 mV TJ (C) 0 to 85 Significant Differences from Hardware Specification Modified voltage and temperature Specifications to achieve 400 MHz
Note: The X prefix in a Motorola part number designates a "Pilot Production Prototype" as defined by Motorola SOP 3-13. These are from a limited production volume of prototypes manufactured, tested, and Q.A. inspected on a qualified technology to simulate normal production. These parts have only preliminary reliability and characterization data. Before pilot production prototypes may be shipped, written authorization from the customer must be on file in the applicable sales office acknowledging the qualification status and the fact that product changes may still occur while shipping pilot production prototypes.
1.2 Features
This section summarizes changes to the features of the MPC8245 described in the MPC8245 Integrated Processor Hardware Specifications. * Power management -- 2.1-V processor core
PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE
1.3 General Parameters
This section summarizes changes to the general parameters of the MPC8245 described in the MPC8245 Integrated Processor Hardware Specifications. * Core power supply 2.1 V 100 mV DC nominal
1.4.1.2
DC Electrical Characteristics
Table 2. Recommended Operating Conditions
Characteristic Symbol VDD AVDD AVDD2 Tj Recommended Value 2.1 V 100 mV 2.1 V 100 mV 2.1 V 100 mV 0 to 85 Unit V V V C
Table 2 provides the recommended operating conditions for the MPC8245 part numbers described herein.
Supply voltage CPU PLL supply voltage PLL supply voltage - Peripheral Logic Die-junction temperature
Note: These are the recommended and tested operating conditions. Proper device operation outside of these conditions is not guaranteed.
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MPC825 Part Number Specification for the XPC8245RZUnnnPx Series PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE
MOTOROLA
1.4.1.5
Power Characteristics
The AC electrical characteristics and AC timing for all parts described herein are unaffected and comply with the MPC8245 Integrated Processor Hardware Specifications.
Table 5. Preliminary Power Consumption
PCI Bus Clock / Memory Bus Clock CPU Clock Frequency (MHz) Mode 33/ 132/ 396 2.2 2.8 2.4 1.6 0.6 0.2 40/ 100/ 400 2.3 2.9 2.5 1.7 0.7 0.4 I/O Power Mode Typ-OVdd Typ-GVdd Range 200 - 500 300 - 700 200 - 500 300 - 700 Supplies10 Units mW mW Notes 7,8 7,9 Units Notes
Typical Max - FP Max - INT Doze Nap Sleep
W W W W W W
1, 5 1, 2 1, 3 1, 4, 6 1, 4, 6 1, 4, 6
Notes:
1. The values include Vdd, AVdd, and AVdd2 but do not include I/O Supply Power, see Section 1.7.2, "Power Supply Sizing," for information on OVdd and GVdd supply power. Values shown in parenthesis () indicate power consumption at Vdd/AVdd/AVdd2 = 2.1 V. 2. Maximum - FP power is measured at Vdd = 2.1 V with dynamic power management enabled while running an entirely cache-resident, looping, floating point multiplication instruction. 3. Maximum - INT power is measured at Vdd = 2.1 V with dynamic power management enabled while running entirely cache-resident, looping, integer instructions. 4. Power saving mode maximums are measured at Vdd = 2.1 V while the device is in doze, nap, or sleep mode. 5. Typical power is measured at Vdd = AVdd = 2.1 V, OVdd = 3.3 V where a nominal FP value, a nominal INT value, and a value where there is a continuous flush of cache lines with alternating ones and zeroes on 64 bit boundaries to local memory are averaged. 6. Power saving mode data measured with only two PCI_CLKs and two SDRAM_CLKs enabled. 7. The typical minimum I/O power values were results of the MPC8245 performing cache resident integer operations at the slowest frequency combination of 33:66:200 (PCI:Mem:CPU) MHz. 8. The typical maximum OVdd value resulted from the MPC8245 operating at the fastest frequency combination of 66:100:350 (PCI:Mem:CPU) MHz and performing continuous flushes of cache lines with alternating ones and zeroes to PCI memory. 9. The typical maximum GVdd value resulted from the MPC8245 operating at the fastest frequency combination of 66:100:350 (PCI:Mem:CPU) MHz and performing continuous flushes of cache lines with alternating ones and zeroes on 64 bit boundaries to local memory. 10. Power consumption of PLL supply pins (AVdd and AVdd2) < 15 mW. Guaranteed by design and is not tested.
MOTOROLA
MPC825 Part Number Specification for the XPC8245RZUnnnPx Series PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE
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1.6 PLL Configuration
The MPC8245 internal PLLs are configured by the PLL_CFG[0:4] signals. For a given PCI_SYNC_IN (PCI bus) frequency, the PLL configuration signals set both the Peripheral Logic/Memory Bus PLL (VCO) frequency of operation for the PCI-to-Memory frequency multiplying and the 603e CPU PLL (VCO) frequency of operation for Memory-to-CPU frequency multiplying. The PLL configurations for the MPC8245 is shown in Table 1.
Table 1. MPC8245 PLL Configurations for the 400 MHz Part Offering
400 MHz Part9 Ref PLL_ CFG [0:4]10,13
PCI Clock Input (PCI_ SYNC_IN) Range1 (MHz) Periph Logic/ Mem Bus Clock Range (MHz)
Multipliers
CPU Clock Range (MHz)
PCI to Mem (Mem VCO)
Mem to CPU (CPU VCO)
0 1 2 3 4 6 7 8 9 A B C D E F 10 11 12 13 14 15 16
0000012 0000112 0001011 0001111,14 0010012 0011015 0011114 0100012 0100118 0101012 0101118 0110012 0110118 0111012 0111118 1000012 1000118 1001012 1001118 1010012 1010118 1011012
25 - 442 25 - 445
5017 - 661 5016 - 661 25 - 464
75 - 132 75 - 132
50 - 66 50 - 66 50 - 92 Bypass
188 - 330 225 - 396
225 - 297 100 - 133 100 - 184
3 (2) 3 (2) 1 (4) 1(Bypass) 2 (4) Bypass
2.5 (2) 3 (2) 4.5 (2) 2 (4) 2 (4) Bypass 3 (2) 3 (2) 2 (2) 4.5 (2) 3 (2) 2.5 (2) 3.5 (2) 3 (2) 3.5(2) 2 (2) 2.5(2) 2 (2) 3(2) 3.5 (2) 4 (2) 4 (2)
606 - 661 606 - 661 456 - 661 25 - 445 453 - 661 366 - 464 453 - 661 306 - 464 25 - 385 306 - 442 25 - 332 606 - 661 25 - 335 266 - 474 273 - 405
60 - 66 60 - 66 90 - 132 50 - 88 68 - 99 72 - 92 68 - 99 60 - 92 75 - 114 60 - 132 100 - 132 90 - 99 100 - 132 52 - 94 68 - 100
180 - 198 180 - 198 180 - 264 225 - 396 204 - 297 180 - 230 238 - 347 180 - 276 263 - 399 180 - 264 250 - 330 180 - 198 300 - 396 182 - 329 272 - 400
1(Bypass) 1 (4) 2 (2) 2 (4) 1.5 (2) 2 (4) 1.5 (2) 2 (4) 3(2) 3 (2) 4(2) 1.5 (2) 4(2) 2 (4) 2.5 (2) 2 (4)
25 - 464
50 - 92
200 - 368
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MPC825 Part Number Specification for the XPC8245RZUnnnPx Series PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE
MOTOROLA
Table 1. MPC8245 PLL Configurations for the 400 MHz Part Offering (Continued)
400 MHz Part9 Ref PLL_ CFG [0:4]10,13
PCI Clock Input (PCI_ SYNC_IN) Range1 (MHz) Periph Logic/ Mem Bus Clock Range (MHz)
Multipliers
CPU Clock Range (MHz)
PCI to Mem (Mem VCO)
Mem to CPU (CPU VCO)
17 18 19 1A 1B 1C 1D 1E 1F
1011118 1100012 1100118 1101012 1101118 1110012 1110112 111108 11111
8
25 - 332 273 - 535 366 - 661
5017 - 661 336 - 661 446 - 661 486 - 661
100 - 132 68 - 132 72 - 132
50 - 66 66 - 132 66 - 99 72 - 99 Not Usable Not Usable
200 - 264 204 - 396 180 - 330
200 - 264 198 - 396 198 - 297 180 - 248
4 (2) 2.5 (2) 2 (2) 1 (4) 2 (2) 1.5 (2) 1.5 (2) Off Off
2 (2) 3 (2) 2.5 (2) 4 (2) 3 (2) 3 (2) 2.5(2) Off Off
Notes: 1. Limited by maximum PCI input frequency (66 MHz). 2. Limited by maximum system memory interface operating frequency (133 MHz). 3. Limited by minimum memory VCO frequency. (133 MHz) 4. Limited due to maximum memory VCO frequency. (372 MHz) 5. Limited by maximum CPU operating frequency. (400 MHz) 6. Limited by minimum CPU VCO frequency. (360 MHz) 7. Limited by maximum CPU VCO frequency. (800) 8. In Clock Off mode, no clocking occurs inside the MPC8245 regardless of the PCI_SYNC_IN input. 9. Range values are shown rounded down to the nearest whole number (decimal place accuracy removed) for clarity. 10. PLL_CFG[0:4] settings not listed (01011, 01101, 01111, 10001, 10011, 10101, 11001, and 11011) are reserved. 11. Multiplier ratios for this PLL_CFG[0:4] setting are different from the MPC8240 and are not backwards compatible. 12. PCI_SYNC_IN range for this PLL_CFG[0:4] setting is different from the MPC8240 and may not be fully backwards compatible. 13. Bits 7- 4 of register offset <0xE2> contain the PLL_CFG[0:4] setting value. 14. In PLL Bypass mode, the PCI_SYNC_IN input signal clocks the internal processor directly, the peripheral logic PLL is disabled, and the bus mode is set for 1:1 (PCI:Mem) mode operation. This mode is intended for hardware modeling support. The AC timing specifications given in this document do not apply in PLL Bypass mode. 15. In Dual PLL Bypass mode, the PCI_SYNC_IN input signal clocks the internal peripheral logic directly, the peripheral logic PLL is disabled, and the bus mode is set for 1:1 (PCI_SYNC_IN:Mem) mode operation. In this mode, the OSC_IN input signal clocks the internal processor directly in 1:1 (OSC_IN:CPU) mode operation, and the processor PLL is disabled. The PCI_SYNC_IN and OSC_IN input clocks must be externally synchronized. This mode is intended for hardware modeling support. The AC timing specifications given in this document do not apply in Dual PLL Bypass mode. 16. Limited by minimum CPU operating frequency.(100 MHz) 17. Limited by minimum memory bus frequency. (50 MHz)
MOTOROLA
MPC825 Part Number Specification for the XPC8245RZUnnnPx Series PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE
5
18. PCI_SYNC_IN range for this PLL_CFG[0:4] setting does not exist on the MPC8240 and may not be fully backwards compatible.
1.9
Ordering Information
This section provides the part numbering nomenclature for the MPC8245. Note that the individual part numbers correspond to a maximum processor core frequency. For available frequencies, contact your local Motorola sales office. Figure provides the Motorola part numbering nomenclature for the MPC8245. In addition to the processor frequency, the part numbering scheme also consists of an application modifier. The application modifier may specify special application conditions such as specific temperature or voltage ranges. Each part number also contains a revision code. This refers to the die mask revision number and is specified in the part numbering scheme for identification purposes only.
.
MPC 8245 X ZU XXX X
Revision Level (Contact Local Motorola Sales Office) Product Code Part Identifier Processor Frequency (400 MHz) Package (ZU = TBGA) Application Modifier (R = Partial Spec., 0 to 85C Tj)
Figure 33. Motorola Part Number Key
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MPC825 Part Number Specification for the XPC8245RZUnnnPx Series PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE
MOTOROLA
MOTOROLA
MPC825 Part Number Specification for the XPC8245RZUnnnPx Series PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE
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