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SEMICONDUCTOR TECHNICAL DATA
Order Number: MPC9772/D Rev 2, 02/2003
3.3V 1:12 LVCMOS PLL Clock Generator
The MPC9772 is a 3.3V compatible, 1:12 PLL based clock generator targeted for high performance low-skew clock distribution in mid-range to high-performance networking, computing and telecom applications. With output frequencies up to 240 MHz and output skews less than 250 ps the device meets the needs of the most demanding clock applications.
MPC9772
3.3V 1:12 LVCMOS PLL CLOCK GENERATOR
* 1:12 PLL based low-voltage clock generator * 3.3V power supply * Internal power-on reset * Generates clock signals up to 240 MHz * Maximum output skew of 250 ps * On-chip crystal oscillator clock reference * Two LVCMOS PLL reference clock inputs * External PLL feedback supports zero-delay capability * Various feedback and output dividers (see application section) * Supports up to three individual generated output clock frequencies * Synchronous output clock stop circuitry for each individual output for
power down support
FA SUFFIX 52 LEAD LQFP PACKAGE CASE 848D
Features
* Drives up to 24 clock lines * Ambient temperature range 0C to +70C * Pin and function compatible to the MPC972
Functional Description The MPC9772 utilizes PLL technology to frequency lock its outputs onto an input reference clock. Normal operation of the MPC9772 requires the connection of the PLL feedback output QFB to feedback input FB_IN to close the PLL feedback path. The reference clock frequency and the divider for the feedback path determine the VCO frequency. Both must be selected to match the VCO frequency range. The MPC9772 features an extensive level of frequency programmability between the 12 outputs as well as the output to input relationships, for instance 1:1, 2:1, 3:1, 3:2, 4:1, 4:3, 5:1, 5:2, 5:3, 5:4, 5:6, 6:1, 8:1 and 8:3. The QSYNC output will indicate when the coincident rising edges of the above relationships will occur. The selectability of the feedback frequency is independent of the output frequencies. This allows for very flexible programming of the input reference versus output frequency relationship. The output frequencies can be either odd or even multiples of the input reference. In addition the output frequency can be less than the input frequency for applications where a frequency needs to be reduced by a non-binary factor. The MPC9772 also supports the 180 phase shift of one of its output banks with respect to the other output banks. The QSYNC outputs reflects the phase relationship between the QA and QC outputs and can be used for the generation of system baseline timing signals. The REF_SEL pin selects the internal crystal oscillator or the LVCMOS compatible inputs as the reference clock signal. Two alternative LVCMOS compatible clock inputs are provided for clock redundancy support. The PLL_EN control selects the PLL bypass configuration for test and diagnosis. In this configuration, the selected input reference clock is routed directly to the output dividers bypassing the PLL. The PLL bypass is fully static and the minimum clock frequency specification and all other PLL characteristics do not apply. The outputs can be individually disabled (stopped in logic low state) by programming the serial CLOCK_STOP interface of the MPC9772. The MPC9772 has an internal power-on reset. The MPC9772 is fully 3.3V compatible and requires no external loop filter components. All inputs (except XTAL) accept LVCMOS signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50 transmission lines. For series terminated transmission lines, each of the MPC9772 outputs can drive one or two traces giving the devices an effective fanout of 1:24. The device is pin and function compatible to the MPC972 and is packaged in a 52-lead LQFP package.
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(c) Motorola, Inc. 2003
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MPC9772
All input resistors have a value of 25k Bank A XTAL_IN XTAL_OUT XTAL VCC CCLK0 CCLK1 CCLK_SEL REF_SEL FB_IN VCO_SEL PLL_EN VCC FSEL_A[0:1] FSEL_B[0:1] FSEL_C[0:1] FSEL_FB[0:2] VCC INV_CLK STOP_DATA STOP_CLK MR/OE
12 2 2 2 3
QA0 /4, /6, /8, /12 /4, /6, /8, /10 /2, /4, /6, /8 /4, /6, /8, /10 /12, /16, /20 Sync Pulse Bank B CLK STOP QB1 QB2 QB3 Bank C QC0 CLK STOP 0 1 CLK STOP QC1 QC2 QC3 QFB CLK STOP QSYNC CLK STOP QA1 QA2 QA3 QB0
0 Ref 1 VCO /2 /1 0
0 1 1
0 1 VCC
PLL
200-480 MHz
FB
POWER-ON RESET
CLOCK STOP
Figure 1. MPC9772 Logic Diagram
FSEL_FB0 26 25 24 23 22 21 FB_IN
GND
GND
GND
VCC
VCC
39 38 37 36 35 34 33 32 31 30 29 28 27 FSEL_B1 FSEL_B0 FSEL_A1 FSEL_A0 QA3 VCC QA2 GND QA1 VCC QA0 GND VCO_SEL 40 41 42 43 44 45 46 47 48 49 50 51 52 1 2 3 4 5 6 7 8 9 10 11 12 13 FSEL_FB1 QSYNC GND QC0 VCC QC1 FSEL_C0 FSEL_C1 QC2 VCC QC3 GND INV_CLK
MPC9772
VCC XTAL_OUT
QFB
QB0
QB1
QB2
QB3
20 19 18 17 16 15 14
CCLK_SEL
STOP_CLK
Figure 2. MPC9772 52-Lead Package Pinout (Top View)
MOTOROLA
STOP_DATA
FSEL_FB2
REF_SEL
2
VCC_PLL
PLL_EN
CCLK0
CCLK1
XTAL_IN
MR/OE
GND
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MPC9772
Table 1. PIN CONFIGURATION
Pin CCLK0 CCLK1 XTAL_IN, XTAL_OUT FB_IN CCLK_SEL REF_SEL VCO_SEL PLL_EN MR/OE FSEL_A[0:1] FSEL_B[0:1] FSEL_C[0:1] FSEL_FB[0:2] INV_CLK STOP_CLK STOP_DATA QA[0-3] QB[0-3] QC[0-3] QFB QSYNC GND VCC_PLL Input Input Input Input Input Input Input Input Input Input Input Input Input Output Output Output Output Output Supply Supply I/O Input Input Type LVCMOS LVCMOS Analog LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS Ground VCC PLL reference clock Alternative PLL reference clock Crystal oscillator interface PLL feedback signal input, connect to an QFB LVCMOS clock reference select LVCMOS/PECL reference clock select VCO operating frequency select PLL enable/PLL bypass mode select Output enable/disable (high-impedance tristate) and device reset Frequency divider select for bank A outputs Frequency divider select for bank B outputs Frequency divider select for bank C outputs Frequency divider select for the QFB output Clock phase selection for outputs QC2 and QC3 Clock input for clock stop circuitry Configuration data input for clock stop circuitry Clock outputs (Bank A) Clock outputs (Bank B) Clock outputs (Bank C) PLL feedback output. Connect to FB_IN. Synchronization pulse output Negative power supply PLL positive power supply (analog power supply). It is recommended to use an external RC filter for the analog power supply pin VCC_PLL. Please see applications section for details. Positive power supply for I/O and core. All VCC pins must be connected to the positive power supply for correct operation Function
VCC
Supply
VCC
Table 2. FUNCTION TABLE (Configuration Controls)
Control REF_SEL CCLK_SEL VCO_SEL PLL_EN Default 1 1 1 1 Selects CCLK0 Selects VCO/2. The VCO frequency is scaled by a factor of 2 (low VCO frequency range). Test mode with the PLL bypassed. The reference clock is substituted for the internal VCO output. MPC9772 is fully static and no minimum frequency limit applies. All PLL related AC characteristics are not applicable. QC2 and QC3 are in phase with QC0 and QC1 Outputs disabled (high-impedance state) and device is reset. During reset/output disable the PLL feedback loop is open and the internal VCO is tied to its lowest frequency. The MPC9772 requires reset after any loss of PLL lock. Loss of PLL lock may occur when the external feedback path is interrupted. The length of the reset pulse should be greater than one reference clock cycle (CCLKx). The device is reset by the internal power-on reset (POR) circuitry during power-up. 0 Selects CCLKx as the PLL reference clock Selects CCLK1 Selects VCO/1. (high VCO frequency range) Normal operation mode with PLL enabled. 1 Selects the crystal oscillator as the PLL reference clock
INV_CLK MR/OE
1 1
QC2 and QC3 are inverted (180 phase shift) with respect to QC0 and QC1 Outputs enabled (active)
VCO_SEL, FSEL_A[0:1], FSEL_B[0:1], FSEL_C[0:1], FSEL_FB[0:2] control the operating PLL frequency range and input/output frequency ratios. See Table 3 to Table 6 and the applications section for supported frequency ranges and output to input frequency ratios.
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Table 3. Output Divider Bank A (NA)
VCO_SEL 0 0 0 0 1 1 1 1 FSEL_A1 0 0 1 1 0 0 1 1 FSEL_A0 0 1 0 1 0 1 0 1 QA[0:3] VCO/8 VCO/12 VCO/16 VCO/24 VCO/4 VCO/6 VCO/8 VCO/12
Table 5. Output Divider Bank C (NC)
VCO_SEL 0 0 0 0 1 1 1 1 FSEL_C1 0 0 1 1 0 0 1 1 FSEL_C0 0 1 0 1 0 1 0 1 QC[0:3] VCO/4 VCO/8 VCO/12 VCO/16 VCO/2 VCO/4 VCO/6 VCO/8
Table 4. Output Divider Bank B (NB)
VCO_SEL 0 0 0 0 1 1 1 1 FSEL_B1 0 0 1 1 0 0 1 1 FSEL_B0 0 1 0 1 0 1 0 1 QB[0:3] VCO/8 VCO/12 VCO/16 VCO/20 VCO/4 VCO/6 VCO/8 VCO/10
Table 6. Output Divider PLL Feedback (M)
VCO_SEL 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 FSEL_FB2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 FSEL_FB1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 FSEL_FB0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 QFB VCO/8 VCO/12 VCO/16 VCO/20 VCO/16 VCO/24 VCO/32 VCO/40 VCO/4 VCO/6 VCO/8 VCO/10 VCO/8 VCO/12 VCO/16 VCO/20
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Table 7. GENERAL SPECIFICATIONS
Symbol VTT MM HBM LU CPD CIN Characteristics Output Termination Voltage ESD Protection (Machine Model) ESD Protection (Human Body Model) Latch-Up Immunity Power Dissipation Capacitance Input Capacitance 200 2000 200 12 4.0 Min Typ VCC
B2
Max
Unit V V V mA pF pF
Condition
Per output Inputs
Table 8. ABSOLUTE MAXIMUM RATINGSa
Symbol VCC VIN VOUT IIN IOUT Supply Voltage DC Input Voltage DC Output Voltage DC Input Current DC Output Current Characteristics Min -0.3 -0.3 -0.3 Max 3.9 VCC+0.3 VCC+0.3 20 50 Unit V V V mA mA Condition
TS Storage Temperature -65 125 C a. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not implied.
Table 9. DC CHARACTERISTICS (VCC = 3.3V 5%, TA = 0 to 70C)
Symbol VCC_PLL VIH VIL VOH VOL ZOUT IIN ICC_PLL ICCQ a. b. Characteristics PLL Supply Voltage Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Output Impedance Input Currentb Maximum PLL Supply Current 14 - 17 200 8.0 13.5 2.4 0.55 0.30 Min 3.0 2.0 Typ Max VCC VCC + 0.3 0.8 Unit V V V V V V Condition LVCMOS LVCMOS LVCMOS IOH=-24 mAa IOL= 24 mA IOL= 12 mA VIN = VCC or GND VCC_PLL Pin
W
A mA
Maximum Quiescent Supply Current 35 mA All VCC Pins The MPC9772 is capable of driving 50 transmission lines on the incident edge. Each output drives one 50 parallel terminated transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50 series terminated transmission lines. Inputs have pull-down resistors affecting the input current.
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MPC9772
Table 10. AC CHARACTERISTICS (VCC = 3.3V 5%, TA = 0 to 70C)a b
Symbol fREF Characteristics Input reference frequency /4 feedback /6 feedback /8 feedback /10 feedback /12 feedback /16 feedback /20 feedback /24 feedback /32 feedback /40 feedback Min 50.0 33.3 25.0 20.0 16.6 12.5 10.0 8.33 6.25 5.00 Typ Max 120.0 80.0 60.0 48.0 40.0 30.0 24.0 20.0 15.0 12.0 250 200 10 /2 output /4 output /6 output /8 output /10 output /12 output /16 output /20 output /24 output 100.0 50.0 33.3 25.0 20.0 16.6 12.5 10.0 8.33 480 25 240.0 120.0 80.0 60.0 48.0 40.0 30.0 24.0 20.0 20 2.0 1.0 -3 -4 -166 +3 +4 +166 100 100 100 250 (T/2) - 200 0.1 T/2 (T/2) +200 1.0 8.0 8.0 150 /4 feedback /6 feedback /8 feedback /10 feedback /12 feedback /16 feedback /20 feedback /24 feedback /32 feedback /40 feedback 200 150 11 86 13 88 16 19 21 22 27 30 Unit MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz ns ns ps ps ps ps ps ps ns ns ns ps ps ps ps ps ps ps ps ps ps ps ps (VCO=400 MHz) 0.55 to 2.4V 0.8 to 2.0V PLL locked PLL locked Condition PLL locked
Input reference frequency in PLL bypass modec fVCO fXTAL fMAX VCO frequency ranged Crystal interface frequency ranged Output Frequency
PLL bypass
fSTOP_CLK tPW,MIN tR, tF t()
Serial interface clock frequency Input Reference Pulse Widthe CCLKx Input Rise/Fall Timef Propagation Delay (static phase offset)g CCLK to FB_IN 6.25 MHz < fREF < 65.0 MHz 65.0 MHz < fREF < 125 MHz fREF=50 MHz and feedback=/8 Output-to-output Skewh within QA outputs within QB outputs within QC outputs all outputs
tSK(O)
DC tR, tF tPLZ, HZ tPZL, LZ tJIT(CC) tJIT(PER) tJIT()
Output Duty Cyclei Output Rise/Fall Time Output Disable Time Output Enable Time Cycle-to-cycle jitterj Period Jitterk I/O Phase Jitter RMS (1 )l
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MPC9772
Table 10. AC CHARACTERISTICS (VCC = 3.3V 5%, TA = 0 to 70C)a b
Symbol BW Characteristics PLL closed loop bandwidthm /4 feedback /6 feedback /8 feedback /10 feedback /12 feedback /16 feedback /20 feedback /24 feedback /32 feedback /40 feedback Min Typ 1.20 - 3.50 0.70 - 2.50 0.50 - 1.80 0.45 - 1.20 0.30 - 1.00 0.25 - 0.70 0.20 - 0.55 0.17 - 0.40 0.12 - 0.30 0.11 - 0.28 Max Unit MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz Condition
tLOCK Maximum PLL Lock Time 10 ms a AC characteristics apply for parallel output termination of 50 to VTT. b In bypass mode, the MPC9772 divides the input reference clock. c The input reference frequency must match the VCO lock range divided by the total feedback divider ratio: fREF= fVCO / (M VCO_SEL). d The crystal frequency range must both meet the interface frequency range and VCO lock range divided by the feedback divider ratio: fXTAL(min, max) = fVCO(min, max) / (M VCO_SEL) and 10 MHz fXTAL 25 MHz. e Calculation of reference duty cycle limits: DCREF,MIN = tPW,MIN fREF 100% and DCREF,MAX = 100% - DCREF, MIN. f The MPC9772 will operate with input rise/fall times up to 3.0 ns, but the A.C. characteristics, specifically t(), tPW,MIN, DC and fMAX can only be guaranteed if tR, tF are within the specified range. g Static phase offset depends on the reference frequency. t() [s] = t() [] / (fREF 360). h Excluding QSYNC output. See application section for part-to-part skew calculation. i Output duty cycle is DC = (0.5 200 ps fOUT) 100%. E.g. the DC range at fOUT=100MHz is 48%TIMING SOLUTIONS
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MPC9772
APPLICATIONS INFORMATION
MPC9772 Configurations Configuring the MPC9772 amounts to properly configuring the internal dividers to produce the desired output frequencies. The output frequency can be represented by this formula:
fOUT = fREF M / N fREF PLL /VCO_SEL /N fOUT
the specified frequency range. This divider is controlled by the VCO_SEL pin. VCO_SEL effectively extends the usable input frequency range while it has no effect on the output to reference frequency ratio. The output frequency for each bank can be derived from the VCO frequency and output divider: fQA[0:3] = fVCO / (VCO_SEL NA) fQB[0:3] = fVCO / (VCO_SEL NB) fQC[0:3] = fVCO / (VCO_SEL NC) Table 11. MPC9772 Divider
Divider M Function PLL feedback FSEL_FB[0:3] FSEL FB[0 3] VCO_SEL /1 /2 /1 /2 /1 /2 /1 /2 Values 4, 6, 8, 10, 12, 16 8, 12, 16, 20, 24, 32, 40 4, 6, 8, 12 8, 12, 16, 24 4, 6, 8, 10 8, 12, 16, 20 2, 4, 6, 8 4, 8, 12, 16
/M
where fREF is the reference frequency of the selected input clock source (CCLKO, CCLK1 or XTAL interface), M is the PLL feedback divider and N is a output divider. The PLL feedback divider is configured by the FSEL_FB[2:0] and the output dividers are individually configured for each output bank by the FSEL_A[1:0], FSEL_B[1:0] and FSEL_C[1:0] inputs. The reference frequency fREF and the selection of the feedback-divider M is limited by the specified VCO frequency range. fREF and M must be configured to match the VCO frequency range of 200 to 480 MHz in order to achieve stable PLL operation: fVCO,MIN (fREF VCO_SEL M) fVCO,MAX The PLL post-divider VCO_SEL is either a divide-by-one or a divide-by-two and can be used to situate the VCO into Figure 3. Example Configuration
CCLK0 CCLK1 CCLK_SEL 1 11 00 00 101 VCO_SEL FB_IN QA[3:0] QB[3:0] 33.3 MHz 100 MHz
NA NB NC
Bank A Output Divider FSEL A[0 1] id FSEL_A[0:1] Bank B Output Diid FSEL_B[0:1] vider FSEL B[0 1] Bank C Output Divider FSEL_C[0:1] id FSEL C[0 1]
Table 11 shows the various PLL feedback and output dividers and Figure 3. and Figure 4. display example configurations for the MPC9772: Figure 4. Example Configuration
CCLK0 CCLK1 CCLK_SEL 1 00 00 00 011 VCO_SEL FB_IN QA[3:0] QB[3:0] 62.5 MHz 62.5 MHz
fref = 33.3 MHz
fref = 25 MHz
FSEL_A[1:0] QC[3:0] FSEL_B[1:0] FSEL_C[1:0] QFB FSEL_FB[2:0]
MPC9772
200 MHz
FSEL_A[1:0] QC[3:0] FSEL_B[1:0] FSEL_C[1:0] QFB FSEL_FB[2:0]
MPC9772
125 MHz
33.3 MHz (Feedback)
25 MHz (Feedback)
MPC9772 example configuration (feedback of QFB = 33.3 MHz, fVCO=400 MHz, VCO_SEL=/1, M=12, NA=12, NB=4, NC=2).
Frequency range Input QA outputs QB outputs QC outputs Min 16.6 MHz 16.6 MHz 50 MHz 100 MHz Max 40 MHz 40 MHz 120 MHz 240 MHz
MPC9772 example configuration (feedback of QFB = 25 MHz, fVCO=250 MHz, VCO_SEL=/1, M=10, NA=4, NB=4, NC=2).
Frequency range Input QA outputs QB outputs QC outputs Min 20 MHz 50 MHz 50 MHz 100 MHz Max 48 MHz 120 MHz 120 MHz 240 MHz
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MPC9772
MPC9772 Individual Output Disable (Clock Stop) Circuitry The individual clock stop (output enable) control of the MPC9772 allows designers, under software control, to implement power management into the clock distribution design. A simple serial interface and a clock stop control logic provides a mechanism through which the MPC9772 clock outputs can be individually stopped in the logic `0' state: The clock stop mechanism allows serial loading of a 12-bit serial input register. This register contains one programmable clock stop bit for 12 of the 14 output clocks. The QC0 and QFB outputs cannot be stopped (disabled) with the serial port. The user can program an output clock to stop (disable) by
STOP_CLK STOP_DATA START QA0 QA1 QA2 QA3 QB0 QB1 QB2 QB3 QC1 QC2 QC3 QSYNC
writing logic `0' to the respective stop enable bit. Likewise, the user may programmably enable an output clock by writing logic `1' to the respective enable bit. The clock stop logic enables or disables clock outputs during the time when the output would be in normally in logic low state, eliminating the possibility of short or `runt' clock pulses. The user can write to the serial input register through the STOP_DATA input by supplying a logic `0' start bit followed serially by 12 NRZ disable/enable bits. The period of each STOP_DATA bit equals the period of the free-running STOP_CLK signal. The STOP_DATA serial transmission should be timed so the MPC9772 can sample each STOP_DATA bit with the rising edge of the free-running STOP_CLK signal. (see Figure 5. )
Figure 5. Clock Stop Circuit Programming
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MPC9772
SYNC Output Description The MPC9772 has a system synchronization pulse output QSYNC. In configurations with the output frequency relationships are not integer multiples of each other QSYNC provides a signal for system synchronization purposes. The MPC9772 monitors the relationship between the A bank and the B bank of outputs. The QSYNC output is asserted (logic low) one period in duration and one period prior to the coincident rising edges of the QA and QC outputs. The duration and the placement of the pulse is dependent QA and QC output frequencies: the QSYNC pulse width is equal to the period of the higher of the QA and QC output frequencies. Figure 6. shows various waveforms for the QSYNC output. The QSYNC output is defined for all possible combinations of the bank A and bank C outputs.
fVCO 1:1 Mode QA QC QSYNC 2:1 Mode QA QC QSYNC 3:1 Mode QC(/2) QA(/6) QSYNC 3:2 Mode QA(/4) QC(/6) QSYNC 4:1 Mode QC(/2) QA(/8) QSYNC 4:3 Mode QA(/6) QC(/8) QSYNC 6:1 Mode QA(/12) QC(/2) QSYNC
Figure 6. QSYNC Timing Diagram
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MPC9772
Power Supply Filtering The MPC9772 is a mixed analog/digital product. Its analog circuitry is naturally susceptible to random noise, especially if this noise is seen on the power supply pins. Random noise on the V CC_PLL power supply impacts the device characteristics, for instance I/O jitter. The MPC9772 provides separate power supplies for the output buffers (VCC) and the phase-locked loop (VCC_PLL) of the device. The purpose of this design technique is to isolate the high switching noise digital outputs from the relatively sensitive internal analog phase-locked loop. In a digital system environment where it is more difficult to minimize noise on the power supplies a second level of isolation may be required. The simple but effective form of isolation is a power supply filter on the VCCA_PLL pin for the MPC9772. Figure 7. illustrates a typical power supply filter scheme. The MPC9772 frequency and phase stability is most susceptible to noise with spectral content in the 100kHz to 20MHz range. Therefore the filter should be designed to target this range. The key parameter that needs to be met in the final filter design is the DC voltage drop across the series filter resistor RF. From the data sheet the ICC_PLL current (the current sourced through the VCC_PLL pin) is typically 8 mA (13.5 mA maximum), assuming that a minimum of 3.0V must be maintained on the VCC_PLL pin. The resistor RF shown in Figure 7. "VCC_PLL Power Supply Filter" must have a resistance of 5-10W to meet the voltage drop criteria.
RF = 5-10 RF VCC CF 10 nF CF = 22 F VCC_PLL MPC9772 VCC 33...100 nF CCLKCommon tPD,LINE(FB)
Using the MPC9772 in zero-delay applications Nested clock trees are typical applications for the MPC9772. Designs using the MPC9772 as LVCMOS PLL fanout buffer with zero insertion delay will show significantly lower clock skew than clock distributions developed from CMOS fanout buffers. The external feedback option of the MPC9772 clock driver allows for its use as a zero delay buffer. The PLL aligns the feedback clock output edge with the clock input reference edge resulting a near zero delay through the device (the propagation delay through the device is virtually eliminated). The maximum insertion delay of the device in zero-delay applications is measured between the reference clock input and any output. This effective delay consists of the static phase offset, I/O jitter (phase or long-term jitter), feedback path delay and the output-to-output skew error relative to the feedback output.
Calculation of part-to-part skew The MPC9772 zero delay buffer supports applications where critical clock signal timing can be maintained across several devices. If the reference clock inputs of two or more MPC9772 are connected together, the maximum overall timing uncertainty from the common CCLKx input to any output is:
tSK(PP) = t() + tSK(O) + tPD, LINE(FB) + tJIT()
CF
This maximum timing uncertainty consist of 4 components: static phase offset, output skew, feedback board trace delay and I/O (phase) jitter:
-t()
Figure 7. VCC_PLL Power Supply Filter The minimum values for RF and the filter capacitor CF are defined by the required filter characteristics: the RC filter should provide an attenuation greater than 40 dB for noise whose spectral content is above 100 kHz. In the example RC filter shown in Figure 7. "VCC_PLL Power Supply Filter", the filter cut-off frequency is around 4.5 kHz and the noise attenuation at 100 kHz is better than 42 dB. As the noise frequency crosses the series resonant point of an individual capacitor its overall impedance begins to look inductive and thus increases with increasing frequency. The parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the bandwidth of the PLL. Although the MPC9772 has several design features to minimize the susceptibility to power supply noise (isolated power and grounds and fully differential PLL) there still may be applications in which overall performance is being degraded due to system power supply noise. The power supply filter schemes discussed in this section should be adequate to eliminate power supply noise related problems in most designs.
QFBDevice 1
tJIT()
Any QDevice 1
+tSK(O) +t()
QFBDevice2
tJIT()
Any QDevice 2 Max. skew
+tSK(O) tSK(PP)
Figure 8. MPC9772 max. device-to-device skew
Due to the statistical nature of I/O jitter a RMS value (1 is specified. I/O jitter numbers for other confidence factors (CF) can be derived from Table 12.
s)
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MPC9772
Table 12. Confidence Facter CF
CF 1s 2s 3s 4s 5s 6s Probability of clock edge within the distribution 0.68268948 0.95449988 tjit( ) [ps] RMS 0.99730007 0.99993663 0.99999943 0.99999999 120 100 80 60 40 20 FB=/12 FB=/6 FB=/24 Max. I/O Phase Jitter versus Frequency Parameter: PLL Feedback Divider FB
The feedback trace delay is determined by the board layout and can be used to fine-tune the effective delay through each device. Due to the frequency dependence of the static phase offset and I/O jitter, using Figure 9. to Figure 11. to predict a maximum I/O jitter and the specified t() parameter relative to the input reference frequency results in a precise timing performance analysis. In the following example calculation an I/O jitter confidence factor of 99.7% ( 3s) is assumed, resulting in a worst case timing uncertainty from the common input reference clock to any output of -455 ps to +455 ps relative to CCLK (PLL feedback = /8, reference frequency = 50 MHz, VCO frequency = 400 MHz, I/O jitter = 13 ps rms max., static phase offset t() = 166 ps):
tjit( ) [ps] RMS
0 200
250
300 350 400 VCO frequency [MHz]
450
480
Figure 10. MPC9772 I/O Jitter
Max. I/O Phase Jitter versus Frequency Parameter: PLL Feedback Divider FB 140 120 100 80 60 40 20 0 200
FB=/10 FB=/40 FB=/20
250
tSK(PP) =
[-166ps...166ps] + [-250ps...250ps] + [(13ps @ -3)...(13ps @ 3)] + tPD, LINE(FB) [-455ps...455ps] + tPD, LINE(FB)
300 350 400 VCO frequency [MHz]
450
480
Figure 11. MPC9772 I/O Jitter Driving Transmission Lines The MPC9772 clock driver was designed to drive high speed signals in a terminated transmission line environment. To provide the optimum flexibility to the user the output drivers were designed to exhibit the lowest impedance possible. With an output impedance of less than 20 the drivers can drive either parallel or series terminated transmission lines. For more information on transmission lines the reader is referred to Motorola application note AN1091. In most high performance clock networks point-to-point distribution of signals is the method of choice. In a point-to-point scheme either series terminated or parallel terminated transmission lines can be used. The parallel technique terminates the signal at the end of the line with a 50 resistance to VCC/2. This technique draws a fairly high level of DC current and thus only a single terminated line can be driven by each output of the MPC9772 clock driver. For the series terminated case however there is no DC current draw, thus the outputs can drive multiple series terminated lines. Figure 12. "Single
tSK(PP) =
Max. I/O Phase Jitter versus Frequency Parameter: PLL Feedback Divider FB 160 140 FB=/32 120 100 FB=/16 80 FB=/8 60 40 20 FB=/4 0 200 250 300 350 400 VCO frequency [MHz]
tjit( ) [ps] RMS
450
480
Figure 9. MPC9772 I/O Jitter
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TIMING SOLUTIONS
MPC9772
versus Dual Transmission Lines" illustrates an output driving a single series terminated line versus two series terminated lines in parallel. When taken to its extreme the fanout of the MPC9772 clock driver is effectively doubled due to its capability to drive multiple lines.
MPC9772 OUTPUT BUFFER VOLTAGE (V) IN
14
towards the quiescent 3.0V in steps separated by one round trip delay (in this case 4.0ns).
3.0 OutA tD = 3.8956 OutB tD = 3.9386
2.5
2.0 In 1.5
RS = 36
ZO = 50 OutA
MPC9772 OUTPUT BUFFER IN
14
1.0 RS = 36 ZO = 50 OutB0 0.5
RS = 36
ZO = 50 OutB1
0 2 4 6 8 TIME (nS) 10 12 14
Figure 12. Single versus Dual Transmission Lines The waveform plots in Figure 13. "Single versus Dual Line Termination Waveforms" show the simulation results of an output driving a single line versus two lines. In both cases the drive capability of the MPC9772 output buffer is more than sufficient to drive 50 transmission lines on the incident edge. Note from the delay measurements in the simulations a delta of only 43ps exists between the two differently loaded outputs. This suggests that the dual line driving need not be used exclusively to maintain the tight output-to-output skew of the MPC9772. The output waveform in Figure 13. "Single versus Dual Line Termination Waveforms" shows a step in the waveform, this step is caused by the impedance mismatch seen looking into the driver. The parallel combination of the 36 series resistor plus the output impedance does not match the parallel combination of the line impedances. The voltage wave launched down the two lines will equal: VL Z0 RS R0 VL = VS ( Z0 / (RS+R0 +Z0)) = 50 || 50 = 36 || 36 = 14 = 3.0 ( 25 / (18+17+25) = 1.31V
Figure 13. Single versus Dual Waveforms Since this step is well above the threshold region it will not cause any false clock triggering, however designers may be uncomfortable with unwanted reflections on the line. To better match the impedances when driving multiple lines the situation in Figure 14. "Optimized Dual Line Termination" should be used. In this case the series terminating resistors are reduced such that when the parallel combination is added to the output buffer impedance the line impedance is perfectly matched.
MPC9772 OUTPUT BUFFER
14
RS = 22
ZO = 50
RS = 22
ZO = 50
14 + 22 k 22 = 50 k 50 25 = 25 Figure 14. Optimized Dual Line Termination
At the load end the voltage will double, due to the near unity reflection coefficient, to 2.6V. It will then increment
MPC9772 DUT Pulse Generator Z = 50W ZO = 50 ZO = 50
RT = 50 VTT
RT = 50 VTT
Figure 15. CCLK MPC9772 AC test reference
TIMING SOLUTIONS
13
MOTOROLA
MPC9772
VCC VCC VCC VCC
B2
CCLKx
GND
B2
FB_IN
VCC VCC VCC VCC
B2 B2
GND
GND tSK(O) The pin-to-pin skew is defined as the worst case difference in propagation delay between any similar delay path within a single device
GND t()
Figure 16. Output-to-output Skew tSK(O)
VCC VCC tP T0 DC = tP /T0 x 100% The time from the PLL controlled edge to the non controlled edge, divided by the time between PLL controlled edges, expressed as a percentage
Figure 17. Propagation delay (t(), static phase offset) test reference
CCLKx
B2
GND FB_IN
TJIT() = |T0 -T1 mean| The deviation in t0 for a controlled edge with respect to a t0 mean in a random sample of cycles
Figure 18. Output Duty Cycle (DC)
Figure 19. I/O Jitter
TN
TN+1
TJIT(CC) = |TN -TN+1 |
T0
TJIT(PER) = |TN -1/f0 |
The variation in cycle time of a signal between adjacent cycles, over a random sample of adjacent cycle pairs
The deviation in cycle time of a signal with respect to the ideal period over a random sample of cycles
Figure 20. Cycle-to-cycle Jitter
Figure 21. Period Jitter
VCC=3.3V 2.4 0.55 tF tR
Figure 22. Output Transition Time Test Reference
MOTOROLA
14
TIMING SOLUTIONS
MPC9772
OUTLINE DIMENSIONS
FA SUFFIX 52 LEAD LQFP PACKAGE CASE 848D-03 ISSUE D
4X 4X 13 TIPS
0.20 (0.008) H L-M N
0.20 (0.008) T L-M N
52 1
40 39
-X- X=L, M, N C L -M- B V AB B1 VIEW Y V1
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE -H- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS -L-, -M- AND -N- TO BE DETERMINED AT DATUM PLANE -H-. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE -T-. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -H-. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED 0.46 (0.018). MINIMUM SPACE BETWEEN PROTRUSION AND ADJACENT LEAD OR PROTRUSION 0.07 (0.003). MILLIMETERS MIN MAX 10.00 BSC 5.00 BSC 10.00 BSC 5.00 BSC --- 1.70 0.05 0.20 1.30 1.50 0.20 0.40 0.45 0.75 0.22 0.35 0.65 BSC 0.07 0.20 0.50 REF 0.08 0.20 12.00 BSC 6.00 BSC 0.09 0.16 12.00 BSC 6.00 BSC 0.20 REF 1.00 REF 0_ 7_ --- 0_ 12 _ REF 12 _ REF INCHES MIN MAX 0.394 BSC 0.197 BSC 0.394 BSC 0.197 BSC --- 0.067 0.002 0.008 0.051 0.059 0.008 0.016 0.018 0.030 0.009 0.014 0.026 BSC 0.003 0.008 0.020 REF 0.003 0.008 0.472 BSC 0.236 BSC 0.004 0.006 0.472 BSC 0.236 BSC 0.008 REF 0.039 REF 0_ 7_ --- 0_ 12 _ REF 12 _ REF
3X
VIEW Y
-L-
AB
G
13 14 26
27
A1 S1 A S
-N-
C -H- -T-
SEATING PLANE
4X
q2
0.10 (0.004) T
4X
q3
VIEW AA
0.05 (0.002)
S
W
q1
C2
2X R
R1
0.25 (0.010)
q
GAGE PLANE
K C1 E VIEW AA Z J
PLATING
F
BASE METAL
U
DIM A A1 B B1 C C1 C2 D E F G J K R1 S S1 U V V1 W Z 1 2 3
0.13 (0.005)
SECTION AB-AB
ROTATED 90_ CLOCKWISE
TIMING SOLUTIONS
CCCC EEEE CCCC EEEE
M
D T L-M
S
N
S
15
MOTOROLA
MPC9772
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E Motorola Inc. 2003
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MOTOROLA
16
MPC9772/D TIMING SOLUTIONS

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