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| NJU6825 162COMMON x 128RGB LCD DRIVER FOR 4,096-COLOR STN DISPLAY ! GENERAL DESCRIPTION The NJU6825 is a 162COMMON x 128RGB LCD driver for 4,096-color STN display. It contains common drivers, RGB drivers, a serial and a parallel MPU interface circuit, an internal LCD power supply, grayscale palettes and 248,832-bit display data RAM. The segment drivers for RGB (Red, Green, Blue) independently produce optimum 16 grayscales from a built-in 32-grayscale palette, and the LSI achieves 4,096 colors (16x16x16). In addition, the NJU6825 operates with a low voltage of 1.7V and a low operating current, therefore it is ideally suited for battery-powered handheld applications. PACKAGE BUMP CHIP ! FEATURES # # # # # # # # # # # # # # # # # 4,096-color STN LCD driver Built-in LCD Drivers : 162-common Drivers x 128RGB Drivers (384-segment Drivers in B&W) Built-in Display Data RAM (DDRAM) : 248,832 bits for Graphic Display Programmable Display Mode - Variable 16-grayscale Mode : 4,096 Colors - Variable 8-grayscale Mode : 256 Colors - Fixed 8-grayscale Mode : 256 Colors - B&W Mode : Black & White 8-/16-bit Parallel Interface Selectable 8-/16-bit Bus Length for Display Data Selectable 3-/4-line Serial Interface Selectable Programmable Duty Ratio and Bias Ratio Programmable Internal Voltage Booster : Maximum 7 times Programmable Contrast Control : 128-step Electrical Variable Resistor (EVR) Various Useful Instructions Low Operating Current : 450uA Typical at VDD=3V, 4-time Boost, Checker Flag Display Low Logic Voltage : 1.7V to 3.3V Wide LCD Voltage Range : 5.0V to 18.0V C-MOS Technology Slim Chip for COG Package : Bump Chip / TCP Ver.2003-10-14 -1- NJU6825 TABLE OF CONTENTS ! GENERAL DESCRIPTION PACKAGE .............................................................................................. 1 ! FEATURES ................................................................................................................................................... 1 ! PAD LOCATION............................................................................................................................................ 5 ! PAD COORDINATES 1................................................................................................................................. 8 ! PAD COORDINATES 2................................................................................................................................. 9 ! PAD COORDINATES 3............................................................................................................................... 10 ! PAD COORDINATES 4............................................................................................................................... 11 ! PAD COORDINATES 5............................................................................................................................... 12 ! PAD COORDINATES 6............................................................................................................................... 13 ! BLOCK DIAGRAM ..................................................................................................................................... 14 ! LCD POWER SUPPLY BLOCK DIAGRAM ............................................................................................... 15 ! TERMINAL DESCRIPTION 1 ..................................................................................................................... 16 ! TERMINAL DESCRIPTION 2 ..................................................................................................................... 17 ! TERMINAL DESCRIPTION 3 ..................................................................................................................... 18 ! FUNCTIONAL DESCRIPTION ................................................................................................................... 19 (1) MPU INTERFACE......................................................................................................................................... 19 (1-1) Selection of Parallel/Serial Interface Mode .....................................................................................................19 (1-2) Selection of MPU Mode...................................................................................................................................19 (1-3) Data Recognition.............................................................................................................................................19 (1-4) Selection of 3-/4-line Serial Interface Mode ....................................................................................................19 (1-5) 4-line Serial Interface Mode ............................................................................................................................19 (1-6) 3-line Serial Interface Mode ............................................................................................................................20 (1-7) Accessing DDRAM ..........................................................................................................................................21 (1-8) Accessing Instruction Register ........................................................................................................................22 (1-9) Selection of 8-/16-bit Bus Length (Parallel Interface Mode) ...........................................................................22 (2) INITIAL DISPLAY LINE REGISTER ............................................................................................................. 22 (3) COLUMN AND ROW ADDRESS COUNTERS ............................................................................................ 22 (4) DDRAM ......................................................................................................................................................... 23 (4-1) DDRAM Address Range..................................................................................................................................23 (4-2) Window Area for DDRAM Access ...................................................................................................................24 (4-3) Segment Direction...........................................................................................................................................24 (4-4) Bit Assignment of Display Data .......................................................................................................................25 (4-4-1) (4-4-2) (4-4-3) (4-4-4) (4-4-5) (4-5) Write Bit Assignment Overview ......................................................................................................................................25 Bit Assignment in Variable 16-grayscale Mode .....................................................................................................26 Bit Assignment in Variable 8-level Gradation Mode ..............................................................................................29 Bit Assignment in Fixed 8-level Gradation Mode...................................................................................................30 Bit Assignment in B&W Mode ...............................................................................................................................34 Data and Read Data ..............................................................................................................................38 (5) GRAYSCALE CONTROL CIRCUIT .............................................................................................................. 39 (5-1) Display Mode Selection...................................................................................................................................39 (5-1-1) (5-1-2) (5-1-3) (5-1-4) Variable 16-grayscale Mode..................................................................................................................................39 Variable 8-grayscale Mode....................................................................................................................................39 Fixed 8-grayscale Mode........................................................................................................................................39 B&W Mode............................................................................................................................................................39 (6) GRAYSCALE PALETTE................................................................................................................................ 40 (6-1) Grayscale Selection in Variable 16-grayscale Mode.......................................................................................40 (6-2) Grayscale Selection in Variable 8-grayscale Mode.........................................................................................41 (6-3) Grayscale Selection in Fixed 8-grayscale Mode .............................................................................................42 (6-4) Grayscale Selection in B&W Mode .................................................................................................................42 -2Ver.2003-10-14 NJU6825 (7) DISPLAY TIMING GENERATOR.................................................................................................................. 43 (8) DATA LATCH CIRCUIT ................................................................................................................................. 43 (9) COMMON DRIVERS AND SEGMENT DRIVERS........................................................................................ 43 (10) OSCILLATOR.............................................................................................................................................. 44 (10-1) Using Internal Resistor (CKS=0) ...................................................................................................................44 (10-2) Using External Resistor (CKS=1) ..................................................................................................................44 (10-3) Using External Clock (CKS=1) ......................................................................................................................44 (11) LCD POWER SUPPLY................................................................................................................................ 44 (11-1) Voltage Booster .............................................................................................................................................45 (11-2) Voltage Converter ..........................................................................................................................................46 (11-2-1) Reference Voltage Generator ...........................................................................................................................46 (11-2-2) Voltage Regulator..............................................................................................................................................46 (11-2-3) Electrical Variable Resistor (EVR).....................................................................................................................46 (11-2-4) LCD Bias Voltage Generator.............................................................................................................................46 (11-3) External Components for LCD Power Supply ...............................................................................................47 (11-4) Discharge Circuit ...........................................................................................................................................50 (11-5) Power ON/OFF ..............................................................................................................................................50 (11-5-1) Power ON/OFF in Using Internal LCD Power Supply .......................................................................................50 (11-5-2) Power ON/OFF in Using External LCD Power Supply ......................................................................................50 (12) RESET FUNCTION..................................................................................................................................... 51 (13) INSTRUCTION TABLES ............................................................................................................................. 52 (13-1) Instruction Table and Register Address.........................................................................................................52 (13-2) Instruction Table 0 (RE2, RE1, RE0)=(0, 0, 0)............................................................................................53 (13-3) Instruction Table 1 (RE2, RE1, RE0)=(0, 0, 1)............................................................................................54 (13-4) Instruction Table 2 (RE2, RE1, RE0)=(0, 1, 0)............................................................................................55 (13-5) Instruction Table 3 (RE2, RE1, RE0)=(0, 1, 1)............................................................................................56 (13-6) Instruction Table 4 (RE2, RE1, RE0)=(1, 0, 0)............................................................................................57 (13-7) Instruction Table 5 (RE2, RE1, RE0)=(1, 0, 1)............................................................................................58 (14) INSTRUCTION DESCRIPTIONS ............................................................................................................... 59 (14-1) Display Data Write.........................................................................................................................................59 (14-2) Display Data Read.........................................................................................................................................59 (14-3) Column Address ............................................................................................................................................59 (14-4) Row Address .................................................................................................................................................59 (14-5) Initial Display Line..........................................................................................................................................59 (14-6) N-line Inversion..............................................................................................................................................60 (14-7) Display Control (1).........................................................................................................................................61 (14-8) Display Control (2).........................................................................................................................................62 (14-9) Increment Control ..........................................................................................................................................63 (14-10) Power Control ..............................................................................................................................................64 (14-11) Duty Cycle Ratio ..........................................................................................................................................65 (14-12) Boost Level ................................................................................................................................................65 (14-13) LCD Bias Ratio ............................................................................................................................................66 (14-14) Instruction Table Select................................................................................................................................66 (14-15) Palette A / B / C............................................................................................................................................67 (14-16) Initial COM ...................................................................................................................................................73 (14-17) Duty-1 /Display Clock ON/OFF....................................................................................................................73 (14-18) Display Mode Control ..................................................................................................................................73 (14-19) Bus Length...................................................................................................................................................74 (14-20) EVR Control.................................................................................................................................................74 (14-21) Frequency Control .......................................................................................................................................75 (14-22) Discharge ON/OFF ......................................................................................................................................75 (14-23) Register Address .........................................................................................................................................76 (14-24) Register Read ............................................................................................................................................76 (14-25) Window End Column Address .....................................................................................................................76 (14-26) Window End Row Address ..........................................................................................................................76 (14-27) Initial Line-reverse Address .........................................................................................................................76 (14-28) Last Line-reverse Address ...........................................................................................................................77 (14-29) Line Reverse ON/OFF .................................................................................................................................77 Ver.2003-10-14 -3- NJU6825 (14-30) Upper/Lower Palette Select .........................................................................................................................78 (14-31) PWM Control ...............................................................................................................................................78 (15) PARTIAL DISPLAY FUNCTION.................................................................................................................. 79 (16) SWAP FUNCTION ...................................................................................................................................... 80 (16-1) Swap Function in Variable 16-grayscale Mode .............................................................................................81 (16-2) Swap Function in Variable 8-grayscale Mode ...............................................................................................83 (16-3) Swap Function in Fixed 8-grayscale Mode ...................................................................................................84 (16-4) Swap Function in B&W Mode........................................................................................................................86 (17) RELATION BETWEEN ROW ADDRESS AND COMMON DRIVER.......................................................... 87 (17-1) SHIFT=0, Initial Display Line "0", Duty Cycle Ratio "1/163" ..........................................................................88 (17-2) SHIFT=1, Initial Display Line "0", Duty Cycle Ratio "1/163" ..........................................................................89 (17-3) SHIFT=0, Initial Display Line "0", Duty Cycle Ratio "1/16" ............................................................................90 (17-4) SHIFT=0, Initial Display Line "5", Duty Cycle Ratio "1/163" ..........................................................................91 (17-5) SHIFT=0, Initial Display Line "0", Duty Cycle Ratio "1/162" ..........................................................................92 (18) TYPICAL INSTRUCTION SEQUENCES.................................................................................................... 93 (18-1) Initialization Sequence in Using Internal LCD Power Supply........................................................................93 (18-2) Initialization Sequence in Using External LCD Power Supply.......................................................................94 (18-3) Display Data Write Sequence........................................................................................................................95 (18-4) Partial Display Sequence ..............................................................................................................................96 (18-5) Power OFF Sequence ...................................................................................................................................97 ! ABSOLUTE MAXIMUM RATINGS............................................................................................................. 98 ! RECOMMENDED OPERATING CONDITIONS ......................................................................................... 98 ! DC CHARACTERISTICS............................................................................................................................ 99 ! OSCILLATION FREQUENCY AND FRAME FREQUENCY.................................................................... 100 ! AC CHARACTERISTICS.......................................................................................................................... 102 (1) Write Operation (Parallel Interface / 80-series MPU) ................................................................................. 102 (2) Read Operation (Parallel Interface / 80-series MPU)................................................................................. 103 (3) Write Operation (Parallel Interface / 68-series MPU) ................................................................................. 104 (4) Read Operation (Parallel Interface / 68-series MPU)................................................................................. 105 (5) Write Operation (Serial Interface) ............................................................................................................... 106 (6) Display Control Timing ................................................................................................................................ 107 (7) Input Clock Timing ...................................................................................................................................... 108 (8) Reset Input Timing ...................................................................................................................................... 108 (9) Delay Time of Gate ..................................................................................................................................... 108 ! INPUT/OUTPUT BLOCK DIAGRAMS ..................................................................................................... 109 ! MPU CONNECTIONS............................................................................................................................... 110 -4- Ver.2003-10-14 NJU6825 ! PAD LOCATION SEGA126 SEGB126 SEGC126 SEGA127 SEGB127 SEGC127 COM81 COM100 DMY113 DMY114 COM101 COM149 DMY115 1 DMY40 WRb DMY39 DMY38 VSSA(R) VSSA(C) VSSA(L) DMY37 DMY36 SEL68 DMY35 DMY34 DMY33 P/S DMY32 DMY31 VDDA(R) VDDA(C) VDDA(L) DMY30 DMY29 TEST2 DMY28 DMY27 VSS(R) VSS(C) VSS(L) DMY26 DMY25 RS DMY24 DMY23 DMY22 CSb DMY21 DMY20 DMY19 RESb DMY18 DMY1r7 DMY16 DMY15 DMY14 DMY13 VDD(R) VDD(C) VDD(L) DMY12 DMY11 DMY10 DMY9 DMY8 TEST1 DMY7 DMY6 DMY5 DMY4 DMY3 VSSA(R) VSSA(C) VSSA(L) DMY2 DMY1 COM161 NOTE1) Multiple PADs with successive numbers are internally connected. NOTE2) Dummy PADs, symbolized with DUMMY, are electrically open. NOTE3) The purpose of this drawing is to show the order of PADs. Use "PAD CORDINATE TABLE 1 to 6" for design. Chip Center Chip Size Chip Thickness Bump Pitch Bump Space Bump Size Bump Height Bump Material Alignment marks a a: 30m b: 6m c: 120m d: 27m b Alignment mark coordinates X=-9831m, Y=-1396m X= 9831m, Y=-1396m b c a c d Ver.2003-10-14 COM150 DMY0 :X=0um, Y=0um :X=20.00mm, Y= 3.13mm :625um + 25um :45um(Min) :15um :32um x 68um (COM/SEG), 47um x 68um (Interface) :68um x 68um (DMY0, 109, 110, 111, 112, 113, 114, 115) :17.5um+ 3.5um :Au d -5- NJU6825 -6- DMY67 FLM DMY66 DMY65 CL DMY64 VSS (R) VSS (C) VSS (L) DMY63 D15 DMY62 D14 DMY61 D13 DMY60 D12 DMY59 D11 DMY58 D10 DMY57 D9 DMY56 D8 DMY55 D7 DMY54 D6 DMY53 D5 DMY52 D4/SPOL DMY51 D3/SMODE DMY50 D2 DMY49 D1/SDA DMY48 D0/SCL DMY47 DMY46 VDD(R) VDD(C) VDD(L) DMY45 DMY44 DMY43 RDb DMY42 DMY41 VEE(C) VEE(L) DMY87 DMY86 DMY85 VBA(R) VBA(C) VBA(L) DMY84 VREF(R) VREF(C) VREF(L) DMY83 DMY82 VREG(R) VREG(C) VREG(L) V4(R) V4(C) V4(L) DMY81 V3(R) V3(C) V3(L) V2(R) V2(C) V2(L) DMY80 V1(R) V1(C) V1(L) VLCD(R) VLCD(C) VLCD(L) DMY79 DMY78 VSSH(R) VSSH(C) VSSH(L) DMY77 DMY76 OSC2 DMY75 DMY74 OSC1 DMY73 DMY72 DMY71 CLK DMY70 DMY69 FR DMY68 Y X Ver.2003-10-14 NJU6825 DMY112 COM19 COM80 DMY108 VOUT(R) VOUT(C) VOUT(L) DMY107 DMY106 DMY105 DMY104 DMY103 C6-(R) C6-(C) C6-(L) DMY102 C6+(R) C6+(C) C6+(L) DMY101 C5-(R) C5-(C) C5-(L) DMY100 C5+(R) C5+(C) C5+(L) DMY99 C4-(R) C4-(C) C4-(L) DMY98 C4+(R) C4+(C) C4+(L) DMY97 C3-(R) C3-(C) C3-(L) DMY96 C3+(R) C3+(C) C3+(L) DMY95 C2-(R) C2-(C) C2-(L) DMY94 C2+(R) C2+(C) C2+(L) DMY93 C1-(R) C1-(C) C1-(L) DMY92 C1+(R) C1+(C) C1+(L) DMY91 DMY90 VSSH(R) VSSH(C) VSSH(L) DMY89 DMY88 VEE(R) COM0 SEGA0 SEGB0 SEGC0 SEGA1 SEGB1 SEGC1 DMY111 COM20 COM68 DMY110 DMY109 COM69 X Ver.2003-10-14 Y -7- NJU6825 ! PAD COORDINATES 1 Chip Size 20000m x 3130m (Chip Center 0m x 0m ) No. PAD NAME X (um) Y (um) No. PAD NAME X (um) Y (um) No. PAD NAME X (um) Y (um) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 DMY0 COM150 COM151 COM152 COM153 COM154 COM155 COM156 COM157 COM158 COM159 COM160 COM161 DMY1 DMY2 VSSA(L) VSSA(C) VSSA(R) DMY3 DMY4 DMY5 DMY6 DMY7 TEST1 DMY8 DMY9 DMY10 DMY11 DMY12 VDD(L) VDD(C) VDD(R) DMY13 DMY14 DMY15 DMY16 DMY17 DMY18 RESb DMY19 DMY20 DMY21 CSb DMY22 DMY23 DMY24 RS DMY25 DMY26 VSS(L) VSS(C) -9581 -9518 -9473 -9428 -9383 -9338 -9293 -9248 -9203 -9158 -9113 -9068 -9023 -8910 -8850 -8790 -8730 -8670 -8610 -8550 -8490 -8430 -8370 -8310 -8250 -8190 -8130 -8070 -8010 -7950 -7890 -7830 -7650 -7590 -7530 -7470 -7410 -7350 -7290 -7230 -7170 -7110 -7050 -6990 -6930 -6870 -6810 -6750 -6690 -6630 -6570 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 VSS(R) DMY27 DMY28 TEST2 DMY29 DMY30 VDDA(L) VDDA(C) VDDA(R) DMY31 DMY32 P/S DMY33 DMY34 DMY35 SEL68 DMY36 DMY37 VSSA(L) VSSA(C) VSSA(R) DMY38 DMY39 WRb DMY40 DMY41 DMY42 RDb DMY43 DMY44 DMY45 VDD(L) VDD(C) VDD(R) DMY46 DMY47 D0 DMY48 D1 DMY49 D2 DMY50 D3 DMY51 D4 DMY52 D5 DMY53 D6 DMY54 D7 -6510 -6330 -6270 -6210 -6150 -6090 -6030 -5970 -5910 -5850 -5790 -5730 -5670 -5610 -5550 -5490 -5430 -5370 -5310 -5250 -5190 -5130 -5070 -5010 -4950 -4890 -4830 -4770 -4710 -4650 -4590 -4530 -4470 -4410 -4230 -4170 -4050 -3930 -3810 -3690 -3570 -3450 -3330 -3210 -3090 -2970 -2850 -2730 -2610 -2490 -2370 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 DMY55 D8 DMY56 D9 DMY57 D10 DMY58 D11 DMY59 D12 DMY60 D13 DMY61 D14 DMY62 D15 DMY63 VSS(L) VSS(C) VSS(R) DMY64 CL DMY65 DMY66 FLM DMY67 DMY68 FR DMY69 DMY70 CLK DMY71 DMY72 DMY73 OSC1 DMY74 DMY75 OSC2 DMY76 DMY77 VSSH(L) VSSH(C) VSSH(R) DMY78 DMY79 VLCD(L) VLCD(C) VLCD(R) V1(L) V1(C) V1(R) -2250 -2130 -2010 -1890 -1770 -1650 -1530 -1410 -1290 -1170 -1050 -930 -810 -690 -570 -450 -330 -270 -210 -150 30 150 270 330 450 570 630 750 870 930 1050 1170 1230 1290 1350 1410 1470 1650 1830 1890 1950 2010 2070 2250 2310 2370 2430 2490 2670 2730 2790 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -8- Ver.2003-10-14 NJU6825 ! PAD COORDINATES 2 Chip Size 20000m x 3130m (Chip Center 0m x 0m ) No. PAD NAME X (um) Y (um) No. PAD NAME X (um) Y (um) No. PAD NAME X (um) Y (um) 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 DMY80 V2(L) V2(C) V2(R) V3(L) V3(C) V3(R) DMY81 V4(L) V4(C) V4(R) VREG(L) VREG(C) VREG(R) DMY82 DMY83 VREF(L) VREF(C) VREF(R) DMY84 VBA(L) VBA(C) VBA(R) DMY85 DMY86 DMY87 VEE(L) VEE(C) VEE(R) DMY88 DMY89 VSSH(L) VSSH(C) VSSH(R) DMY90 DMY91 C1+(L) C1+(C) C1+(R) DMY92 C1-(L) C1-(C) C1-(R) DMY93 C2+(L) C2+(C) C2+(R) DMY94 C2-(L) C2-(C) C2-(R) 2850 2910 2970 3030 3210 3270 3330 3390 3450 3510 3570 3750 3810 3870 3930 3990 4050 4110 4170 4230 4290 4350 4410 4470 4530 4590 4650 4710 4770 4950 5010 5190 5250 5310 5370 5430 5490 5550 5610 5670 5730 5790 5850 5910 5970 6030 6090 6150 6210 6270 6330 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 DMY95 C3+(L) C3+(C) C3+(R) DMY96 C3-(L) C3-(C) C3-(R) DMY97 C4+(L) C4+(C) C4+(R) DMY98 C4-(L) C4-(C) C4-(R) DMY99 C5+(L) C5+(C) C5+(R) DMY100 C5-(L) C5-(C) C5-(R) DMY101 C6+(L) C6+(C) C6+(R) DMY102 C6-(L) C6-(C) C6-(R) DMY103 DMY104 DMY105 DMY106 DMY107 VOUT(L) VOUT(C) VOUT(R) DMY108 COM80 COM79 COM78 COM77 COM76 COM75 COM74 COM73 COM72 COM71 6390 6450 6510 6570 6630 6690 6750 6810 6870 6930 6990 7050 7110 7170 7230 7290 7350 7410 7470 7530 7590 7650 7710 7770 7830 7890 7950 8010 8070 8130 8190 8250 8310 8370 8430 8490 8550 8610 8670 8730 8910 9023 9068 9113 9158 9203 9248 9293 9338 9383 9428 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 COM70 COM69 DMY109 DMY110 COM68 COM67 COM66 COM65 COM64 COM63 COM62 COM61 COM60 COM59 COM58 COM57 COM56 COM55 COM54 COM53 COM52 COM51 COM50 COM49 COM48 COM47 COM46 COM45 COM44 COM43 COM42 COM41 COM40 COM39 COM38 COM37 COM36 COM35 COM34 COM33 COM32 COM31 COM30 COM29 COM28 COM27 COM26 COM25 COM24 COM23 COM22 9473 9518 9581 9831 9831 9831 9831 9831 9831 9831 9831 9831 9831 9831 9831 9831 9831 9831 9831 9831 9831 9831 9831 9831 9831 9831 9831 9831 9831 9831 9831 9831 9831 9831 9831 9831 9831 9831 9831 9831 9831 9831 9831 9831 9831 9831 9831 9831 9831 9831 9831 -1396 -1396 -1396 -1143 -1080 -1035 -990 -945 -900 -855 -810 -765 -720 -675 -630 -585 -540 -495 -450 -405 -360 -315 -270 -225 -180 -135 -90 -45 0 45 90 135 180 225 270 315 360 405 450 495 540 585 630 675 720 765 810 855 900 945 990 Ver.2003-10-14 -9- NJU6825 ! PAD COORDINATES 3 Chip Size 20000m x 3130m (Chip Center 0m x 0m ) No. PAD NAME X (um) Y (um) No. PAD NAME X (um) Y (um) No. PAD NAME X (um) Y (um) 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 COM21 COM20 DMY111 DMY112 COM19 COM18 COM17 COM16 COM15 COM14 COM13 COM12 COM11 COM10 COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM0 SEGA0 SEGB0 SEGC0 SEGA1 SEGB1 SEGC1 SEGA2 SEGB2 SEGC2 SEGA2 SEGB3 SEGC3 SEGA4 SEGB4 SEGC4 SEGA5 SEGB5 SEGC5 SEGA6 SEGB6 SEGC6 SEGA7 SEGB7 SEGC7 SEGA8 SEGB8 SEGC8 9831 9831 9831 9581 9518 9473 9428 9383 9338 9293 9248 9203 9158 9113 9068 9023 8978 8933 8888 8843 8798 8753 8708 8663 8618 8573 8528 8483 8438 8393 8348 8303 8258 8213 8168 8123 8078 8033 7988 7943 7898 7853 7808 7763 7718 7673 7628 7583 7538 7493 7448 1035 1080 1144 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 SEGA9 SEGB9 SEGC9 SEGA10 SEGB10 SEGC10 SEGA11 SEGB11 SEGC11 SEGA12 SEGB12 SEGC12 SEGA13 SEGB13 SEGC13 SEGA14 SEGB14 SEGC14 SEGA15 SEGB15 SEGC15 SEGA16 SEGB16 SEGC16 SEGA17 SEGB17 SEGC17 SEGA18 SEGB18 SEGC18 SEGA19 SEGB19 SEGC19 SEGA20 SEGB20 SEGC20 SEGA21 SEGB21 SEGC21 SEGA22 SEGB22 SEGC22 SEGA23 SEGB23 SEGC23 SEGA24 SEGB24 SEGC24 SEGA25 SEGB25 SEGC25 7403 7358 7313 7268 7223 7178 7133 7088 7043 6998 6953 6908 6863 6818 6773 6728 6683 6638 6593 6548 6503 6458 6413 6368 6323 6278 6233 6188 6143 6098 6053 6008 5963 5918 5873 5828 5783 5738 5693 5648 5603 5558 5513 5468 5423 5378 5333 5288 5243 5198 5153 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 SEGA26 SEGB26 SEGC26 SEGA27 SEGB27 SEGC27 SEGA28 SEGB28 SEGC28 SEGA29 SEGB29 SEGC29 SEGA30 SEGB30 SEGC30 SEGA31 SEGB31 SEGC31 SEGA32 SEGB32 SEGC32 SEGA33 SEGB33 SEGC33 SEGA34 SEGB34 SEGC34 SEGA35 SEGB35 SEGC35 SEGA36 SEGB36 SEGC36 SEGA37 SEGB37 SEGC37 SEGA38 SEGB38 SEGC38 SEGA39 SEGB39 SEGC39 SEGA40 SEGB40 SEGC40 SEGA41 SEGB41 SEGC41 SEGA42 SEGB42 SEGC42 5108 5063 5018 4973 4928 4883 4838 4793 4748 4703 4658 4613 4568 4523 4478 4433 4388 4343 4298 4253 4208 4163 4118 4073 4028 3983 3938 3893 3848 3803 3758 3713 3668 3623 3578 3533 3488 3443 3398 3353 3308 3263 3218 3173 3128 3083 3038 2993 2948 2903 2858 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 - 10 - Ver.2003-10-14 NJU6825 ! PAD COORDINATES 4 Chip Size 20000m x 3130m (Chip Center 0m x 0m ) No. PAD NAME X (um) Y (um) No. PAD NAME X (um) Y (um) No. PAD NAME X (um) Y (um) 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 SEGA43 SEGB43 SEGC43 SEGA44 SEGB44 SEGC44 SEGA45 SEGB45 SEGC45 SEGA46 SEGB46 SEGC46 SEGA47 SEGB47 SEGC47 SEGA48 SEGB48 SEGC48 SEGA49 SEGB49 SEGC49 SEGA50 SEGB50 SEGC50 SEGA51 SEGB51 SEGC51 SEGA52 SEGB52 SEGC52 SEGA53 SEGB53 SEGC53 SEGA54 SEGB54 SEGC54 SEGA55 SEGB55 SEGC55 SEGA56 SEGB56 SEGC56 SEGA57 SEGB57 SEGC57 SEGA58 SEGB58 SEGC58 SEGA59 SEGB59 SEGC59 2813 2768 2723 2678 2633 2588 2543 2498 2453 2408 2363 2318 2273 2228 2183 2138 2093 2048 2003 1958 1913 1868 1823 1778 1733 1688 1643 1598 1553 1508 1463 1418 1373 1328 1283 1238 1193 1148 1103 1058 1013 968 923 878 833 788 743 698 653 608 563 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 SEGA60 SEGB60 SEGC60 SEGA61 SEGB61 SEGC61 SEGA62 SEGB62 SEGC62 SEGA63 SEGB63 SEGC63 SEGA64 SEGB64 SEGC64 SEGA65 SEGB65 SEGC65 SEGA66 SEGB66 SEGC66 SEGA67 SEGB67 SEGC67 SEGA68 SEGB68 SEGC68 SEGA69 SEGB69 SEGC69 SEGA70 SEGB70 SEGC70 SEGA71 SEGB71 SEGC71 SEGA72 SEGB72 SEGC72 SEGA73 SEGB73 SEGC73 SEGA74 SEGB74 SEGC74 SEGA75 SEGB75 SEGC75 SEGA76 SEGB76 SEGC76 518 473 428 383 338 293 248 203 158 113 68 23 -23 -68 -113 -158 -203 -248 -293 -338 -383 -428 -473 -518 -563 -608 -653 -698 -743 -788 -833 -878 -923 -968 -1013 -1058 -1103 -1148 -1193 -1238 -1283 -1328 -1373 -1418 -1463 -1508 -1553 -1598 -1643 -1688 -1733 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 SEGA77 SEGB77 SEGC77 SEGA78 SEGB78 SEGC78 SEGA79 SEGB79 SEGC79 SEGA80 SEGB80 SEGC80 SEGA81 SEGB81 SEGC81 SEGA82 SEGB82 SEGC82 SEGA83 SEGB83 SEGC83 SEGA84 SEGB84 SEGC84 SEGA85 SEGB85 SEGC85 SEGA86 SEGB86 SEGC86 SEGA87 SEGB87 SEGC87 SEGA88 SEGB88 SEGC88 SEGA89 SEGB89 SEGC89 SEGA90 SEGB90 SEGC90 SEGA91 SEGB91 SEGC91 SEGA92 SEGB92 SEGC92 SEGA93 SEGB93 SEGC93 -1778 -1823 -1868 -1913 -1958 -2003 -2048 -2093 -2138 -2183 -2228 -2273 -2318 -2363 -2408 -2453 -2498 -2543 -2588 -2633 -2678 -2723 -2768 -2813 -2858 -2903 -2948 -2993 -3038 -3083 -3128 -3173 -3218 -3263 -3308 -3353 -3398 -3443 -3488 -3533 -3578 -3623 -3668 -3713 -3758 -3803 -3848 -3893 -3938 -3983 -4028 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 Ver.2003-10-14 - 11 - NJU6825 ! PAD COORDINATES 5 Chip Size 20000m x 3130m (Chip Center 0m x 0m ) No. PAD NAME X (um) Y (um) No. PAD NAME X (um) Y (um) No. PAD NAME X (um) Y (um) 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 SEGA94 SEGB94 SEGC94 SEGA95 SEGB95 SEGC95 SEGA96 SEGB96 SEGC96 SEGA97 SEGB97 SEGC97 SEGA98 SEGB98 SEGC98 SEGA99 SEGB99 SEGC99 SEGA100 SEGB100 SEGC100 SEGA101 SEGB101 SEGC101 SEGA102 SEGB102 SEGC102 SEGA103 SEGB103 SEGC103 SEGA104 SEGB104 SEGC104 SEGA105 SEGB105 SEGC105 SEGA106 SEGB106 SEGC106 SEGA107 SEGB107 SEGC107 SEGA108 SEGB108 SEGC108 SEGA109 SEGB109 SEGC109 SEGA110 SEGB110 SEGC110 -4073 -4118 -4163 -4208 -4253 -4298 -4343 -4388 -4433 -4478 -4523 -4568 -4613 -4658 -4703 -4748 -4793 -4838 -4883 -4928 -4973 -5018 -5063 -5108 -5153 -5198 -5243 -5288 -5333 -5378 -5423 -5468 -5513 -5558 -5603 -5648 -5693 -5738 -5783 -5828 -5873 -5918 -5963 -6008 -6053 -6098 -6143 -6188 -6233 -6278 -6323 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 SEGA111 SEGB111 SEGC111 SEGA112 SEGB112 SEGC112 SEGA113 SEGB113 SEGC113 SEGA114 SEGB114 SEGC114 SEGA115 SEGB115 SEGC115 SEGA116 SEGB116 SEGC116 SEGA117 SEGB117 SEGC117 SEGA118 SEGB118 SEGC118 SEGA119 SEGB119 SEGC119 SEGA120 SEGB120 SEGC120 SEGA121 SEGB121 SEGC121 SEGA122 SEGB122 SEGC122 SEGA123 SEGB123 SEGC123 SEGA124 SEGB124 SEGC124 SEGA125 SEGB125 SEGC125 SEGA126 SEGB126 SEGC126 SEGA127 SEGB127 SEGC127 -6368 -6413 -6458 -6503 -6548 -6593 -6638 -6683 -6728 -6773 -6818 -6863 -6908 -6953 -6998 -7043 -7088 -7133 -7178 -7223 -7268 -7313 -7358 -7403 -7448 -7493 -7538 -7583 -7628 -7673 -7718 -7763 -7808 -7853 -7898 -7943 -7988 -8033 -8078 -8123 -8168 -8213 -8258 -8303 -8348 -8393 -8438 -8483 -8528 -8573 -8618 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 COM81 COM82 COM83 COM84 COM85 COM86 COM87 COM88 COM89 COM90 COM91 COM92 COM93 COM94 COM95 COM96 COM97 COM98 COM99 COM100 DMY113 DMY114 COM101 COM102 COM103 COM104 COM105 COM106 COM107 COM108 COM109 COM110 COM111 COM112 COM113 COM114 COM115 COM116 COM117 COM118 COM119 COM120 COM121 COM122 COM123 COM124 COM125 COM126 COM127 COM128 COM129 -8663 -8708 -8753 -8798 -8843 -8888 -8933 -8978 -9023 -9068 -9113 -9158 -9203 -9248 -9293 -9338 -9383 -9428 -9473 -9518 -9581 -9831 -9831 -9831 -9831 -9831 -9831 -9831 -9831 -9831 -9831 -9831 -9831 -9831 -9831 -9831 -9831 -9831 -9831 -9831 -9831 -9831 -9831 -9831 -9831 -9831 -9831 -9831 -9831 -9831 -9831 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1143 1080 1035 990 945 900 855 810 765 720 675 630 585 540 495 450 405 360 315 270 225 180 135 90 45 0 -45 -90 -135 -180 - 12 - Ver.2003-10-14 NJU6825 ! PAD COORDINATES 6 Chip Size 20000m x 3130m (Chip Center 0m x 0m ) No. PAD NAME X (um) Y (um) 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 COM130 COM131 COM132 COM133 COM134 COM135 COM136 COM137 COM138 COM139 COM140 COM141 COM142 COM143 COM144 COM145 COM146 COM147 COM148 COM149 DMY115 -9831 -9831 -9831 -9831 -9831 -9831 -9831 -9831 -9831 -9831 -9831 -9831 -9831 -9831 -9831 -9831 -9831 -9831 -9831 -9831 -9831 -225 -270 -315 -360 -405 -450 -495 -540 -585 -630 -675 -720 -765 -810 -855 -900 -945 -990 -1035 -1080 -1144 Ver.2003-10-14 - 13 - NJU6825 ! BLOCK DIAGRAM SEGA127 SEGB127 SEGC127 SEGA0 SEGB0 SEGC0 VSSA VDDA VDD VLCD, V1 -V4 5 Segment Driver Common Driver Shift Register VREF VBA VREG Voltage Converter Grayscale Palette (A/B/C) Grayscale Control Circuit Data Latch Circuit Initial Display Line Register VEE C1+/C1C2+/C2C3+/C3C4+/C4C5+/C5C6+/C6VOUT Row Address Register Row Address Decoder Row Address Counter Display Data RAM (DD RAM) 128x162x(4+4+4)bits D15 D14 D13 D12 D11 D10 I/O Buffer D9 D8 D7 D6 D5 D4/SPOL D3/SMODE D2 D1/SDA D0/SCL N-line Control RAM Interface Column Address Decoder Display Timing Generator FR FLM CL Column Address Counter Column Address Register CLK Oscillator OSC2 OSC1 Bus Holder Instruction Decoder Register Read Control Internal bus MPU Interface CSb RS RDb WRb P/S SEL68 RESb Line Counter Voltage Booster Line Address Decoder COM0 VSSH VSS - 14 - COM161 Ver.2003-10-14 NJU6825 ! LCD POWER SUPPLY BLOCK DIAGRAM Voltage Converter VBA LCD Bias Voltage Generator Reference Voltage Generator + + + + EVR 1/2 VREG + + VLCD VREG VREF Voltage Regulator V1 V2 + - Gain Control (1x-x) V3 V4 EVR Register Booster Level Register C1+ C1C2+ C2C3+ C3C4+ C4C5+ C5C6+ C6VEE VOUT Voltage Booster Ver.2003-10-14 - 15 - NJU6825 ! TERMINAL DESCRIPTION 1 No. 30~32, 83-85 50-52, 120-122 143~145 185~187 58~60 16~18, 70~72 148-150, 151-153, 155-157, 158-160, 162-164 190-192, 194-196 198-200, 202-204 206-208, 210-212 214-216, 218-220 222-224, 226-228 230-232, 234-236 174-176 170-172 180-182 242-244 165-167 39 Terminal VDD VSS VSSH VDDA VSSA VLCD V1 V2 V3 V4 C1+ C1C2+ C2C3+ C3C4+ C4C5+ C5C6+ C6VBA VREF VEE VOUT VREG RESb I/O Power Power Power Power Power Power Supply for Logic Circuits GND for Logic Circuits GND for High Voltage Circuits VDDA is internally connected to VDD to fix SEL68 or P/S to "H" if necessary, and cannot be used as main power supply. * VDDA should be open if not used. VSSA is internally connected to VSS to fix SEL68 or P/S to "L" if necessary, and cannot be used as main GND. * VSSA should be open if not used. LCD Bias Voltages * When the internal LCD power supply is used, internal LCD bias voltages (VLCD and V1-V4) are activated by the "Power Control" instruction. Stabilizing capacitors are required between each bias voltage and VSS. * When the external LCD power supply is used, LCD bias voltages are externally supplied on VLCD, V1, V2, V3 and V4 individually, with the following relation maintained: VSSH Power Power Power Power Power Power Power Power Power Power Power I - 16 - Ver.2003-10-14 NJU6825 ! TERMINAL DESCRIPTION 2 No. 88 Terminal D0 /SCL D1 /SDA D3 /SMODE D4 /SPOL D2 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 CSb I/O I/O D7 to D0 : 8-bit Bi-directional Bus * In the parallel interface mode (P/S="H"), D7-D0 are connected to 8-bit bi-directional MPU bus. Serial Interface SDA : Serial Data SCL : Serial Clock SMODE : 3-/4-line Serial Mode Select SPOL : RS Polarity Select (3-line Serial Interface Mode) * In the 3 or 4-line serial interface mode (P/S="L"), D0 is assigned to SCL, and D1 to SDA. * In the 3-line serial interface mode, D4 is assigned to SPOL. * Serial data on SDA is latched at the rising edge of SCL signal in order of D7, D6,... and D0, and then converted into 8-bit parallel data at the timing of the internal th signal produced from the 8 SCL. * SCL should be set to "L" right after data transmission or during non-access. 8-bit Bi-directional Bus * In the 16-bit bus length mode, D15-D8 are assigned to upper 8-bit data bus. * In the serial interface mode or the 8-bit parallel interface mode, D15-D8 should be fixed to "H" or "L". Chip Select * Active "L" Register Select * This signal interprets transferred data as display data or instruction. RS Data H Instruction L Display Data Function 1. Parallel Interface 90 I/O 94 I/O 96 I/O 92, 98, 100,102 I/O 104,106,108, 110,112,114, 116,118 I/O 43 I 47 RS I 79 RDb (E) I 75 WRb (R/W) I 80-series MPU Interface (P/S="H", SEL68="L") Data Read (RDb) Signal * Active "L" 68-series MPU Interface (P/S="H", SEL68="H") Enable Signal * Active "H" 80-series MPU Interface (P/S="H", SEL68="L") Data Write (WRb) Signal * Active "L" 68-series MPU Interface (P/S="H", SEL68="H") Data Read or Write (R/W) Signal R/W Status H Read L Write 24 55 TEST1 TEST2 I I Maker test terminal This terminal must be fixed to "L" in the user's application. Maker test terminal This terminal must be fixed to "H" in the user's application. Ver.2003-10-14 - 17 - NJU6825 ! TERMINAL DESCRIPTION 3 No. Terminal I/O MPU Mode Select 67 SEL68 I SEL86 MPU H 68-series L 80-series Function Parallel/Serial Interface Mode Select Chip Display / Read Serial Data Select Instruction /Write Clock H CSb RS D0 ~ D7 RDb, WRb L CSb RS SDA (D1) Write Only SCL (D0) * In the serial interface mode (P/S="L"), RDb, WRb, D2 and D5-D15 should be fixed to "H" or "L",. Line Clock * CL is normally open. First Line Maker * FLM is normally open. Frame Rate * FR is normally open. Clock Output * CLK is normally open. OSC * When the internal oscillator is used, fix OSC1 to "H" or "L" and leave OSC2 open. To attain more accurate frequency, connect OSC1 and OSC2 with an external resistor. * When the internal oscillator is not used, input external clock to OSC1 and leave OSC2 open. Segment Drivers P/S REV Register Normal Reverse SEGA0 ~SEGA127 331-714 SEGB0 ~SEGB127 SEGC0 ~SEGC127 O OFF 0 1 ON 1 0 63 P/S I 124 127 130 133 CL FLM FR CLK O O O O 137, 140 OSC1 OSC2 I O * Segment drivers output the following voltage levels. B/W Mode (Example) FR Signal Display Data Reverse Display OFF (Normal) Reverse Display ON V2 VLCD VLCD V2 V3 VSSH VSSH V3 311-330, 260-308, 246-257, 715-734, 737-785, 2-13 Common Drivers * Common drivers output the following voltage levels. COM0 ~ COM161 Data H L H L FR H H L L Output Levels VSSH V1 VLCD V4 O NOTE) DUMMY PADs: No. 14, 15, 20-23, 25-29, 33-38, 40-42, 44-46, 48, 49, 53, 54, 56, 57, 61, 62, 64-66, 68, 69, 73, 74, 76-78, 80-82, 86, 87, 89, 91, 93, 95, 97, 99, 101, 103, 105, 107, 109, 111, 113, 115, 117, 119, 123, 125, 126, 128, 129, 131, 132, 134-136, 138, 139, 141, 142, 146, 147, 154, 161, 168, 169, 173, 177-179, 183, 184, 188, 189, 193, 197, 201, 205, 209, 213, 217, 221, 225, 229, 233, 237-241, 245, 258, 259, 309, 310, 735, 736, and 786. - 18 - Ver.2003-10-14 NJU6825 ! FUNCTIONAL DESCRIPTION (1) MPU INTERFACE (1-1) Selection of Parallel/Serial Interface Mode The P/S selects a parallel or a serial interface mode, as shown in Table 1. In the serial interface mode, neither display data in the DDRAM nor instruction data in the registers can be read out. Table 1 Selection of Parallel/Serial Interface Mode P/S I/F Mode CSb RS RDb H Parallel I/F CSb RS RDb L Serial I/F CSb RS NOTE) " -" : Fix to "H" or "L". (1-2) Selection of MPU Mode WRb WRb - SEL68 SEL68 - SDA SDA SCL SCL Data D7-D0 (D15-D0) - In the parallel interface mode, the SEL68 selects 68 or 80-series MPU mode, as shown in Table 2. Table 2 Selection of MPU Mode SEL68 MPU Mode H 68-series MPU L 80-series MPU CSb CSb CSb RS RS RS RDb E RDb WRb R/W WRb Data D7-D0 (D15-D0) D7-D0 (D15-D0) (1-3) Data Recognition In the parallel interface mode, the data from MPU is interpreted as display data or instruction according to the combination of the RS, RDb and WRb (R/W) signals, as shown in Table 3. Table 3 RS H H L L Data Recognition (Parallel Interface Mode) 68-series 80-series R/W RDb WRb H L H L H L H L H L H L Function Read Instruction Write Instruction Read Display Data Write Display Data (1-4) Selection of 3-/4-line Serial Interface Mode In the serial interface mode, the SMODE selects 3- or 4-line serial interface mode, as shown in Table 4. Table 4 Selection of 3-/4-line Serial Interface Mode SMODE Serial Interface Mode H 3-line L 4-line (1-5) 4-line Serial Interface Mode While the chip select is active (CSb="L"), the SDA and SCL are enabled. While the chip select is inactive (CSb="H"), the SDA and SCL are disabled, and the internal shift register and the internal counter are being initialized. 8-bit serial data on the SDA is latched at the rising edge of the SCL signal in order of D7, D6,..., and D0, and converted into 8-bit parallel data at the timing of the internal signal produced from the 8th SCL signal. The data on the SDA is interpreted as display data or instruction according to the RS. Table 5 RS H L Data Recognition (4-line Serial Interface) Data Recognition Instruction Display Data Ver.2003-10-14 - 19 - NJU6825 Note that the SCL should be set to "L" right after data transmission or during non-access because the serial interface is susceptible to external noises which may cause malfunctions. For added safety, inactivate the chip-select (CSb="H") temporary whenever 8-bit data transmission is completed. Fig 1 illustrates the interface timing of the 4-line serial interface mode. CSb RS SDA SCL 1 2 3 Fig 1 VALID D7 D6 D5 D4 D3 D2 D1 D0 4 5 6 7 8 4-line Serial Interface Timing (1-6) 3-line Serial Interface Mode While the chip select is active (CSb="L"), the SDA and SCL are enabled. While the chip select is not active (CSb="H"), the SDA and SCL are disabled, and the internal shift register and the internal counter are being initialized. 9-bit serial data on the SDA is latched at the rising edge of the SCL signal in order of RS, D7, D6,..., and D0, and then converted into 9-bit parallel data at the timing of the internal signal produced from the 9th SCL signal. The data on the SDA is interpreted as display data or instruction according to the combination of the RS bit and the SPOL status, as follows. Table 6 RS 0 1 Data Recognition (3-line Serial Interface) SPOL=L SPOL=H Data Recognition RS Data Recognition Display Data 0 Instruction Instruction 1 Display Data Note that the SCL should be set to "L" right after data transmission or during non-access because the serial interface is susceptible to external noises which may cause malfunctions. For added safety, inactivate the chip-select (CSb="H") temporary whenever 9-bit data transmission is completed. Fig 2 illustrates the interface timing of the 3-line serial interface mode. CSb SDA SCL 1 2 3 Fig 2 RS D7 D6 D5 D4 D3 D2 D1 D0 4 5 6 7 8 9 3-line Serial Interface Timing - 20 - Ver.2003-10-14 NJU6825 (1-7) Accessing DDRAM While the chip select is active (CSb="L"), the data from MPU can be written into the DDRAM or the instruction register. When the RS is "L", the data is interpreted as display data which is stored in the DDRAM. The display data is latched at the rising edge of the WRb signal in the 80-series MPU mode, or at the falling edge of the E signal in the 68-series MPU mode. Table 7 RS L H Data Recognition Data Recognition Display Data Instruction In the DDRAM read sequence, be sure to execute a dummy read right after setting an address or right after writing display data or instruction. The data from MPU is temporarily held in the internal bus-holder, then released on the internal data-bus, therefore a dummy data is read out by the 1st "Display Data Read" instruction. After that, the display data is read out from a specified address by the 2nd instruction. Note that the "Display Data Read" instruction cannot be used in the serial interface mode. Display Data Write Operation D0 to D15 WRb Bus Holder WRb n n+1 n+2 n+3 n+4 n n+1 n+2 n+3 n+4 Display Data Read Operation WRb D0 to D7 (D0 to D15) n Address Set n RDb Dummy Read n Data Read n Address n+1 Data Read n+1 Address n+2 Data Read n+2 Address Internal Fig 3 Internal-signal Timing of Display Data Read/Write Operations NOTE) In 16-bit bus length mode, instruction is transmitted to/from instruction register in 16 bits, as well as display data. Ver.2003-10-14 - 21 - NJU6825 (1-8) Accessing Instruction Register Each instruction register has a specific address in between (0H) and (FH), and instruction data is read out from the register by the "Register Address" and "Register Read" instructions. For more information, refer to "(14-23) Register Address" and "(14-24) Register Read". WRb M Register Address D0 to D7 m Register Read N Register Address n Register Read RDb Fig 4 Access Timing of Instruction Register (1-9) Selection of 8-/16-bit Bus Length (Parallel Interface Mode) Either 8- or 16-bit bus length is selected by the D0 (WLS) bit of the "Bus Length" instruction. In the 16-bit bus length mode, instruction as well as display data is transmitted to/from the instruction registers in 16 bits (D15 to D0). However, only lower 8 bits (D7 to D0) are valid for instruction register access. And only 12 bits are actually stored in the DDRAM, even though entire 16 bits (D15 to D0) are transmitted for DDRAM access. For more information, refer to "(4-4) Bit Assignment of Display Data". Table 8 WLS L H Selection of 8-/16-bit Bus Length Mode Bus Length Mode 8-bit Bus Length 16-bit Bus Length (2) INITIAL DISPLAY LINE REGISTER The address data in the initial display line register specifies the row address, which corresponds to an initial COM and is normally positioned on top of a screen in full display. The initial COM is the start position of common scanning, which is specified by the "Initial COM" instruction. The row address, which is established in the initial display line register, is preset into the line counter whenever the FLM becomes "H". At the rising edge of the CL signal, the line counter is counted-up, then 384-bit display data is latched into the data latch circuit. At the falling edge of the CL signal, the latch data is released to the grayscale control circuit to decide a grayscale level, then the segment drivers Ai, Bi and Ci (i=0 to 127) generate LCD waveforms. (3) COLUMN AND ROW ADDRESS COUNTERS The column and row address counters designate a column address and a row address respectively for DDRAM access, but they are completely independent from the line counter. The line counter provides a line address which is synchronized with display control timings such as the FLM and the CL. - 22 - Ver.2003-10-14 NJU6825 (4) DDRAM (4-1) DDRAM Address Range The DDRAM is capable of 162 bits for row address and 1,536 bits (12-bit x 128-segment) for column address. The range of the column address is varied depending on the settings as follows, and the row address is from (00H) to (A1H). Setting outside these ranges is not allowed, otherwise it may cause malfunctions. For DDRAM access, two data transmissions are needed for 1 RGB-pixel in the 8-bit bus length mode, and one transmission in the 16-bit bus length mode. 8-bit Bus Length 00H 7 bits 01H 5 bits Column Address -------------------------------------------------FEH 7 bits FFH 5 bits Row Address 00H : : : : A1H 7 bits 00H 4 bits 5 bits 01H 8 bits Column Address -------------------------------------------------- 7 bits FEH 4 bits 5 bits FFH 8 bits ABS="1" Row Address 00H : : : : A1H 4 bits 8 bits Column Address -------------------------------------------------- 4 bits 8 bits HSW="1" 00H : : : : A1H 00H 8 bits 01H 8 bits BEH 8 bits BFH 8 bits Row Address 8 bits 00H 8 bits 8 bits 01H 8 bits Column Address -------------------------------------------------- 8 bits 7EH 8 bits 8 bits 7FH 8 bits C256="1" 00H : : : : A1H Row Address 8 bits Fig 5 8 bits Range of Column Address in 8-bit Bus Length Column Address -------------------------------------------------- 8 bits 8 bits 16-bit Bus Length 00H 12 bits 7FH 12 bits Row Address 00H : : : : A1H 12 bits Fig 6 Range of Column Address in 16-bit Bus Length 12 bits Ver.2003-10-14 - 23 - NJU6825 (4-2) Window Area for DDRAM Access In addition to the normal DDRAM access discussed previously, the window area access can be used. This area is set by the "Increment Control" instruction and the designation of the start point and the end point. By the "Increment Control", auto-increment is set for column address and row address individually. Once this mode is set up, the column address, row address or both are automatically counted up , whenever the DDRAM is accessed. And, the start point is specified by the "Column Address" and "Row Address" instructions, and the end point by the "Window End Column Address" and "Window End Row Address" instructions. For more information, refer to "(14-9) Increment Control", "(14-25) Window End Column Address" and "(14-26)Window End Row Address". The typical sequence of the window area setting is listed below. 1. Set "1" at D3 (WIN), D1 (AYI) and D0 (AXI) of "Increment Control" instruction. 2. Set start point by "Column Address" and "Row Address" instructions. 3. Set end point by "Window End Column Address" and "Window End Row Address" instructions. 4. Window area is set up, and DDRAM can be accessed. NOTE) The order of address setting is column address first, then row address. Column Address Start Point (AX, AY) Row Address Window Area End Point (EX, EY) Whole DDRAM Area Fig 7 NOTE1) Window Area The following relation should be maintained to avoid malfunctions. - AX (Window Start Column Address) < EX (Window End Column Address) < Maximum Column Address - AY (Window Start Row Address) < EY (Window End Row Address) < Maximum Row Address Auto-increment in the window area Start Address End Address Start Address End Address NOTE3) Column Address Row Address NOTE2) A read-modify-write operation is enabled by setting "1" at the D2 (AIM) of the "Increment Control" instruction. Refer to the description about "AIM" bit in "(14-9) Increment Control". (4-3) Segment Direction The DDRAM access direction is controlled by the D0 (REF) bit of the "Display Control (2)" instruction. This function is used to reverse the segment direction for reducing the restrictions on the IC position of an LCD module. - 24 - Ver.2003-10-14 Table 9-1 SEG1 SEG126 Palette C Palette A A3 A2 A1 A0 B3 B2 B1 B0 C3 C2 C1 C0 A3 A2 A1 A0 B3 B2 B1 B0 C3 C2 C1 C0 X=7EH D15 D14 D13 D12 D10 D9 D8 D7 D4 D3 D2 D1 D15 D14 D13 D12 D10 D9 D8 D7 D4 D3 D2 D1 X=01H D15 D14 D13 D12 D10 D9 D8 D7 D4 D3 D2 D1 D15 D14 D13 D12 D10 D9 D8 D7 D4 D3 D2 D1 X=7EH X=01H X=03H X=FCH X=02H X=FCH X=02H X=BDH X=01H(L) X=02H X=BEH X=00H X=03H X=00H X=FDH X=FEH X=03H X=00H X=FDH X=FEH X=FDH X=03H X=FDH X=02H X=BDH X=BEH(H) X=00H X=FFH X=01H X=FFH X=01H X=BFH X=01H(H) X=7FH D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D2 D1 D0 D7 D4 D3 D2 D1 D7 D6 D5 D4 D2 D1 D0 D7 D4 D3 D2 D1 D7 D6 D5 D4 D2 D1 D0 D7 D4 D3 D2 D1 D7 D6 D5 D4 D2 D1 D0 D7 D4 D3 D2 D1 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 X=00H X=7FH Palette B Palette A Palette B Palette C Palette C SEG127 Palette A X=01H X=7EH X=01H X=7EH X=02H X=FCH X=02H X=FCH X=01H Palette B RAM MAP 1 (Variable 16-grayscale Mode, Fixed 8-grayscale Mode or B&W Mode) SEG0 REF ABS C256 HSW WLS Mode Palette A Palette B Palette C A3 A2 A1 A0 B3 B2 B1 B0 C3 C2 C1 C0 A3 A2 A1 A0 B3 B2 B1 B0 C3 C2 C1 C0 (4-4-1) Bit Assignment Overview (4-4) Bit Assignment of Display Data Ver.2003-10-14 SEG1 Palette A Palette B Palette C Palette A Palette B SEG126 Palette C Palette A SEG127 Palette B Palette C A3 A2 A1 A0 B3 B2 B1 B0 C3 C2 C1 C0 A3 A2 A1 A0 B3 B2 B1 B0 C3 C2 C1 C0 X=01H X=7EH D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 X=7EH D7 D6 D5 D4 D3 D2 D1 D0 X=01H D7 D6 D5 D4 D3 D2 D1 D0 X=7FH D7 D6 D5 D4 D3 D2 D1 D0 X=00H D7 D6 D5 D4 D3 D2 D1 D0 1 0 x 0 0 X=00H D15 D14 D13 D12 D10 D9 D8 D7 D4 D3 D2 D1 D15 D14 D13 D12 D10 D9 D8 D7 D4 D3 D2 D1 1 0 x 1 0 X=7FH D15 D14 D13 D12 D10 D9 D8 D7 D4 D3 D2 D1 D15 D14 D13 D12 D10 D9 D8 D7 D4 D3 D2 D1 These maps is used for grasping general outlines of the variations in the bit assignment of display data. 16bit 1 1 x 0 0 X=00H D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 1 1 x 1 0 X=7FH D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 X=00H X=01H D7 D6 D5 D4 D2 D1 D0 D7 D4 D3 D2 D1 D7 D6 D5 D4 D2 D1 D0 D7 D4 D3 D2 D1 0 0 0 1 0 X=FEH X=FFH D7 D6 D5 D4 D2 D1 D0 D7 D4 D3 D2 D1 D7 D6 D5 D4 D2 D1 D0 D7 D4 D3 D2 D1 0 1 0 0 0 X=00H X=01H D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 8bit 0 1 0 1 0 X=FEH X=FFH D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 0 x 1 0 0 X=00H D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 0 x 1 1 0 X=BEH(L) X=BFH D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 Table 9-2 RAM MAP 2 (Variable 8-grayscale Mode, Fixed 8-grayscale Mode or B&W Mode) SEG0 REF ABS C256 WLS M ode HSW Palette A Palette B Palette C A3 A2 A1 A0 B3 B2 B1 B0 C3 C2 C1 C0 A3 A2 A1 A0 B3 B2 B1 B0 C3 C2 C1 C0 0 x x 0 1 X=00H - - - - D7 D6 D5 D4 D3 D2 D1 D0 8 bit 0 x x 1 1 X=7FH - - - - D7 D6 D5 D4 D3 D2 D1 D0 Table 10 SWAP Palette A Palette B Palette C SWAP SWAP A3 A2 A1 A0 B3 B2 B1 B0 C3 C2 C1 C0 0 0 1 1 SEGAx SEGBx SEGCx 0 1 1 0 SEGCx SEGBx SEGAx NJU6825 NOTE1) On the RAM MAP 2, A0, B0, C1 and C0 bits are fixed to "1". NOTE2) The functions of the variable 8-grayscale mode are different from those of the fixed 8-grayscale mode. NOTE3) The contents of the DDRAM at "C256=0" are not compatible with the contents at "C256=1". NOTE4) "C256=1" can be used in the 8-bit bus length mode, but not in the 16-bit bus length mode. - 25 - NJU6825 (4-4-2) Bit Assignment in Variable 16-grayscale Mode 16-bit Bus Length HSW * * ABS 0 0 (MON=0, PWM=0, C256=0, WLS=1) SWAP 0 1 D15 D14 D13 D12 D10 Column Address / Display Data / Segment Driver X=7FH X=00H REF 0 1 X=00H X=7FH D15 D14 D13 D12 D10 D9 D8 D7 D4 D3 D2 D1 D9 D8 D7 D4 D3 D3 D2 D2 D2 D2 D1 D1 Grayscale Palette Segment Driver Palette A SEGA0 Palette B SEGB0 Palette C SEGC0 Palette A SEGA127 Palette B SEGB127 Palette C SEGC127 HSW * * ABS 0 0 REF 0 1 SWAP 1 0 D15 D14 D13 D12 D10 X=00H X=7FH Column Address / Display Data / Segment Driver X=7FH X=00H D15 D14 D13 D12 D10 D9 D8 D7 D4 D3 D2 D1 D9 D8 D7 D4 Grayscale Palette Segment Driver Palette A SEGC0 Palette B SEGB0 Palette C SEGA0 Palette A SEGC127 Palette B SEGB127 Palette C SEGA127 HSW * * ABS 1 1 REF 0 1 SWAP 0 1 D10 D11 D9 D8 D7 X=00H X=7FH Column Address / Display Data / Segment Driver X=7FH X=00H D11 D10 D6 D5 D4 D3 D2 D1 D0 D9 D8 D7 D6 D5 D4 D3 Grayscale Palette Segment Driver Palette A SEGA0 Palette B SEGB0 Palette C SEGC0 Palette A SEGA127 Palette B SEGB127 Palette C SEGC127 HSW * * ABS 1 1 REF 0 1 SWAP 1 0 D10 D11 D9 D8 D7 X=00H X=7FH Column Address / Display Data / Segment Driver X=7FH X=00H D11 D10 D6 D5 D4 D3 D2 D1 D0 D9 D8 D7 D6 D5 D4 D3 Grayscale Palette Segment Driver Palette A SEGC0 Palette B SEGB0 Palette C SEGA0 Palette A SEGC127 Palette B SEGB127 Palette C SEGA127 - 26 - Ver.2003-10-14 D0 Display Data in DDRAM D0 Display Data in DDRAM D1 Display Data in DDRAM D1 Display Data in DDRAM NJU6825 8-bit Bus Length HSW 0 0 ABS 0 0 (MON=0, PWM=0, C256=0, WLS=0) SWAP 0 1 D7 D6 Column Address / Display Data / Segment Driver X=01H X=FEH X=FFH X=00H REF 0 1 X=00H X=FEH X=FFH X=01H D5 D4 D2 D1 D0 D7 D4 D3 D2 D1 D7 D6 D5 D4 D2 D1 D0 D7 D4 D3 D3 D2 D2 D2 D2 D1 D1 Grayscale Palette Segment Driver Palette A SEGA0 Palette B SEGB0 Palette C SEGC0 Palette A SEGA127 Palette B SEGB127 Palette C SEGC127 HSW 0 0 ABS 0 0 REF 0 1 SWAP 1 0 D7 D6 X=00H X=FEH Column Address / Display Data / Segment Driver X=01H X=FEH X=FFH X=00H X=FFH X=01H D5 D4 D2 D1 D0 D7 D4 D3 D2 D1 D7 D6 D5 D4 D2 D1 D0 D7 D4 Grayscale Palette Segment Driver Palette A SEGC0 Palette B SEGB0 Palette C SEGA0 Palette A SEGC127 Palette B SEGB127 Palette C SEGA127 HSW 0 0 ABS 1 1 REF 0 1 SWAP 0 1 D3 X=00H X=FEH Column Address / Display Data / Segment Driver X=01H X=FEH X=FFH X=00H X=FFH X=01H D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D3 D2 D1 D0 D7 D6 D5 D4 D3 Grayscale Palette Segment Driver Palette A SEGA0 Palette B SEGB0 Palette C SEGC0 Palette A SEGA127 Palette B SEGB127 Palette C SEGC127 HSW 0 0 ABS 1 1 REF 0 1 SWAP 1 0 D3 X=00H X=FEH Column Address / Display Data / Segment Driver X=01H X=FEH X=FFH X=00H X=FFH X=01H D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D3 D2 D1 D0 D7 D6 D5 D4 D3 Grayscale Palette Segment Driver Palette A SEGC0 Palette B SEGB0 Palette C SEGA0 Palette A SEGC127 Palette B SEGB127 Palette C SEGA127 Ver.2003-10-14 - 27 - D0 Display Data in DDRAM D0 Display Data in DDRAM D1 Display Data in DDRAM D1 Display Data in DDRAM NJU6825 HSW 1 ABS * REF 0 SWAP 0 D7 D6 D5 X=00H Column Address / Display Data / Segment Driver X=01H X=02H ... ... ... ... Display Data in DDRAM Grayscale Palette Segment Driver D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D1 Palette A SEGA0 Palette B SEGB0 Palette C SEGC0 Palette A SEGA1 Palette B SEGB1 Palette C SEGC1 ... ... ... ... X=BDH Column Address / Display Data / Segment Driver X=BEH X=BFH D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 Palette A SEGA126 Palette B SEGB126 Palette C SEGC126 Palette A SEGA127 Palette B SEGB127 Palette C SEGC127 HSW 1 ABS * REF 0 SWAP 1 D7 D6 D5 X=00H Column Address / Display Data / Segment Driver X=01H X=02H D0 ... ... ... ... Display Data in DDRAM Grayscale Palette Segment Driver D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D1 Palette A SEGC0 Palette B SEGB0 Palette C SEGA0 Palette A SEGC1 Palette B SEGB1 Palette C SEGA1 ... ... ... ... X=BDH Column Address / Display Data / Segment Driver X=BEH X=BFH D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 Palette A SEGC126 Palette B SEGB126 Palette C SEGA126 Palette A SEGC127 Palette B SEGB127 Palette C SEGA127 HSW 1 ABS * REF 1 SWAP 0 D3 X=BEH Column Address / Display Data / Segment Driver X=BFH X=BDH X=BEH D0 ... ... ... ... Display Data in DDRAM Grayscale Palette Segment Driver D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D5 Palette A SEGC0 Palette B SEGB0 Palette C SEGA0 Palette A SEGC1 Palette B SEGB1 Palette C SEGA1 ... ... ... ... X=01H Column Address / Display Data / Segment Driver X=02H X=00H X=01H D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 Palette A SEGC126 Palette B SEGB126 Palette C SEGA126 Palette A SEGC127 Palette B SEGB127 Palette C SEGA127 HSW 1 ABS * REF 1 SWAP 1 D3 X=BEH Column Address / Display Data / Segment Driver X=BFH X=BDH X=BEH D4 ... ... ... ... Display Data in DDRAM Grayscale Palette Segment Driver D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D5 Palette A SEGA0 Palette B SEGB0 Palette C SEGC0 Palette A SEGA1 Palette B SEGB1 Palette C SEGC1 ... ... ... ... X=01H Column Address / Display Data / Segment Driver X=02H X=00H X=01H D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 Palette A SEGA126 Palette B SEGB126 Palette C SEGC126 Palette A SEGA127 Palette B SEGB127 Palette C SEGC127 - 28 - Ver.2003-10-14 D4 D4 D4 D0 D0 NJU6825 (4-4-3) Bit Assignment in Variable 8-level Gradation Mode 8-bit Bus Length HSW * * ABS * * (MON=0, PWM=0, C256=1, WLS=0) SWAP 0 1 D7 D6 D5 D4 Column Address / Display Data / Segment Driver X=7FH X=00H REF 0 1 X=00H X=7FH D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 Grayscale Palette Segment Driver Palette A SEGA0 Palette B SEGB0 Palette C SEGC0 Palette A SEGA127 Palette B SEGB127 Palette C SEGC127 HSW * * ABS * * REF 0 1 SWAP 1 0 D7 D6 D5 D4 X=00H X=7FH Column Address / Display Data / Segment Driver X=7FH X=00H D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 Grayscale Palette Segment Driver Palette A SEGC0 Palette B SEGB0 Palette C SEGA0 Palette A SEGC127 Palette B SEGB127 Palette C SEGA127 Ver.2003-10-14 - 29 - D0 Display Data in DDRAM D0 Display Data in DDRAM NJU6825 (4-4-4) Bit Assignment in Fixed 8-level Gradation Mode 16-bit Bus Length HSW * * ABS 0 0 (MON=0, PWM=1, C256=0, WLS=1) SWAP 0 1 D15 D14 D13 D12 D10 Column Address / Display Data / Segment Driver X=7FH X=00H REF 0 1 X=00H X=7FH D15 D14 D13 D12 D10 D9 D8 D7 D4 D3 D2 D1 D9 D8 D7 D4 D3 D3 D2 D2 D2 D2 D1 D1 Grayscale Palette Segment Driver Palette A SEGA0 Palette B SEGB0 Palette C SEGC0 Palette A SEGA127 Palette B SEGB127 Palette C SEGC127 HSW * * ABS 0 0 REF 0 1 SWAP 1 0 D15 D14 D13 D12 D10 X=00H X=7FH Column Address / Display Data / Segment Driver X=7FH X=00H D15 D14 D13 D12 D10 D9 D8 D7 D4 D3 D2 D1 D9 D8 D7 D4 Grayscale Palette Segment Driver Palette A SEGC0 Palette B SEGB0 Palette C SEGA0 Palette A SEGC127 Palette B SEGB127 Palette C SEGA127 NOTE) The data indicated with a slash mark ( / ) is invalid. HSW * * ABS 1 1 REF 0 1 SWAP 0 1 D10 D11 D9 D8 D7 Column Address / Display Data / Segment Driver X=7FH X=00H X=00H X=7FH D11 D10 D6 D5 D4 D3 D2 D1 D0 D9 D8 D7 D6 D5 D4 D3 Grayscale Palette Segment Driver Palette A SEGA0 Palette B SEGB0 Palette C SEGC0 Palette A SEGA127 Palette B SEGB127 Palette C SEGC127 HSW * * ABS 1 1 REF 0 1 SWAP 1 0 D10 D11 D9 D8 D7 X=00H X=7FH Column Address / Display Data / Segment Driver X=7FH X=00H D11 D10 D6 D5 D4 D3 D2 D1 D0 D9 D8 D7 D6 D5 D4 D3 Grayscale Palette Segment Driver Palette A SEGC0 Palette B SEGB0 Palette C SEGA0 Palette A SEGC127 Palette B SEGB127 Palette C SEGA127 NOTE) The data indicated with a slash mark ( / ) is invalid. - 30 - Ver.2003-10-14 D0 Display Data in DDRAM D0 Display Data in DDRAM D1 Display Data in DDRAM D1 Display Data in DDRAM NJU6825 8-bit Bus Length HSW 0 0 ABS 0 0 (MON=0, PWM=1, C256=0, WLS=0) SWAP 0 1 D7 D6 Column Address / Display Data / Segment Driver X=01H X=FEH X=FFH X=00H REF 0 1 X=00H X=FEH X=FFH X=01H D5 D4 D2 D1 D0 D7 D4 D3 D2 D1 D7 D6 D5 D4 D2 D1 D0 D7 D4 D3 D3 D2 D2 D2 D2 D1 D1 Grayscale Palette Segment Driver Palette A SEGA0 Palette B SEGB0 Palette C SEGC0 Palette A SEGA127 Palette B SEGB127 Palette C SEGC127 HSW 0 0 ABS 0 0 REF 0 1 SWAP 1 0 D7 D6 X=00H X=FEH Column Address / Display Data / Segment Driver X=01H X=FEH X=FFH X=00H X=FFH X=01H D5 D4 D2 D1 D0 D7 D4 D3 D2 D1 D7 D6 D5 D4 D2 D1 D0 D7 D4 Grayscale Palette Segment Driver Palette A SEGC0 Palette B SEGB0 Palette C SEGA0 Palette A SEGC127 Palette B SEGB127 Palette C SEGA127 NOTE) The data indicated with a slash mark ( / ) is invalid. HSW 0 0 ABS 1 1 REF 0 1 SWAP 0 1 D3 Column Address / Display Data / Segment Driver X=01H X=FEH X=FFH X=00H X=00H X=FEH X=FFH X=01H D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D3 D2 D1 D0 D7 D6 D5 D4 D3 Grayscale Palette Segment Driver Palette A SEGA0 Palette B SEGB0 Palette C SEGC0 Palette A SEGA127 Palette B SEGB127 Palette C SEGC127 HSW 0 0 ABS 1 1 REF 0 1 SWAP 1 0 D3 X=00H X=FEH Column Address / Display Data / Segment Driver X=01H X=FEH X=FFH X=00H X=FFH X=01H D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D3 D2 D1 D0 D7 D6 D5 D4 D3 Grayscale Palette Segment Driver Palette A SEGC0 Palette B SEGB0 Palette C SEGA0 Palette A SEGC127 Palette B SEGB127 Palette C SEGA127 NOTE) The data indicated with a slash mark ( / ) is invalid. Ver.2003-10-14 - 31 - D0 Display Data in DDRAM D0 Display Data in DDRAM D1 Display Data in DDRAM D1 Display Data in DDRAM NJU6825 HSW 1 ABS * REF 0 SWAP 0 D7 D6 D5 X=00H Column Address / Display Data / Segment Driver X=01H X=02H ... ... ... ... Display Data in DDRAM Grayscale Palette Segment Driver D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D1 Palette A SEGA0 Palette B SEGB0 Palette C SEGC0 Palette A SEGA1 Palette B SEGB1 Palette C SEGC1 ... ... ... ... X=BDH Column Address / Display Data / Segment Driver X=BEH X=BFH D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 Palette A SEGA126 Palette B SEGB126 Palette C SEGC126 Palette A SEGA127 Palette B SEGB127 Palette C SEGC127 HSW 1 ABS * REF 0 SWAP 1 D7 D6 D5 X=00H Column Address / Display Data / Segment Driver X=01H X=02H D0 ... ... ... ... Display Data in DDRAM Grayscale Palette Segment Driver D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D1 Palette A SEGC0 Palette B SEGB0 Palette C SEGA0 Palette A SEGC1 Palette B SEGB1 Palette C SEGA1 ... ... ... ... X=BDH Column Address / Display Data / Segment Driver X=BEH X=BFH D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 Palette A SEGC126 Palette B SEGB126 Palette C SEGA126 Palette A SEGC127 Palette B SEGB127 Palette C SEGA127 HSW 1 ABS * REF 1 SWAP 0 D3 X=BEH Column Address / Display Data / Segment Driver X=BFH X=BDH X=BEH D0 ... ... ... ... Display Data in DDRAM Grayscale Palette Segment Driver D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D5 Palette A SEGC0 Palette B SEGB0 Palette C SEGA0 Palette A SEGC1 Palette B SEGB1 Palette C SEGA1 ... ... ... ... X=01H Column Address / Display Data / Segment Driver X=02H X=00H X=01H D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 Palette A SEGC126 Palette B SEGB126 Palette C SEGA126 Palette A SEGC127 Palette B SEGB127 Palette C SEGA127 HSW 1 ABS * REF 1 SWAP 1 D3 X=BEH Column Address / Display Data / Segment Driver X=BFH X=BDH X=BEH D4 ... ... ... ... Display Data in DDRAM Grayscale Palette Segment Driver D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D5 Palette A SEGA0 Palette B SEGB0 Palette C SEGC0 Palette A SEGA1 Palette B SEGB1 Palette C SEGC1 ... ... ... ... X=01H Column Address / Display Data / Segment Driver X=02H X=00H X=01H D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 Palette A SEGA126 Palette B SEGB126 Palette C SEGC126 Palette A SEGA127 Palette B SEGB127 Palette C SEGC127 - 32 - Ver.2003-10-14 D4 D4 D4 D0 D0 NJU6825 8-bit Bus Length HSW * * ABS * * (MON=0, PWM=1, C256=1, WLS=0) SWAP 0 1 D7 D6 D5 D4 Column Address / Display Data / Segment Driver X=7FH X=00H REF 0 1 X=00H X=7FH D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 Grayscale Palette Segment Driver Palette A SEGA0 Palette B SEGB0 Palette C SEGC0 Palette A SEGA127 Palette B SEGB127 Palette C SEGC127 HSW * * ABS * * REF 0 1 SWAP 1 0 D7 D6 D5 D4 X=00H X=7FH Column Address / Display Data / Segment Driver X=7FH X=00H D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 Grayscale Palette Segment Driver Palette A SEGC0 Palette B SEGB0 Palette C SEGA0 Palette A SEGC127 Palette B SEGB127 Palette C SEGA127 Ver.2003-10-14 - 33 - D0 Display Data in DDRAM D0 Display Data in DDRAM NJU6825 (4-4-5) Bit Assignment in B&W Mode 16-bit Bus Length HSW * * ABS 0 0 (MON=1, PWM=*, C256=0, WLS=1) SWAP 0 1 D15 D14 D13 D12 D10 Column Address / Display Data / Segment Driver X=7FH X=00H REF 0 1 X=00H X=7FH D15 D14 D13 D12 D10 D9 D8 D7 D4 D3 D2 D1 D9 D8 D7 D4 D3 D3 D2 D2 D2 D2 D1 D1 Grayscale Palette Segment Driver Palette A SEGA0 Palette B SEGB0 Palette C SEGC0 Palette A SEGA127 Palette B SEGB127 Palette C SEGC127 HSW * * ABS 0 0 REF 0 1 SWAP 1 0 D15 D14 D13 D12 D10 X=00H X=7FH Column Address / Display Data / Segment Driver X=7FH X=00H D15 D14 D13 D12 D10 D9 D8 D7 D4 D3 D2 D1 D9 D8 D7 D4 Grayscale Palette Segment Driver Palette A SEGC0 Palette B SEGB0 Palette C SEGA0 Palette A SEGC127 Palette B SEGB127 Palette C SEGA127 HSW * * ABS 1 1 REF 0 1 SWAP 0 1 D10 D11 D9 D8 D7 X=00H X=7FH Column Address / Display Data / Segment Driver X=7FH X=00H D11 D10 D6 D5 D4 D3 D2 D1 D0 D9 D8 D7 D6 D5 D4 D3 Grayscale Palette Segment Driver Palette A SEGA0 Palette B SEGB0 Palette C SEGC0 Palette A SEGA127 Palette B SEGB127 Palette C SEGC127 HSW * * ABS 1 1 REF 0 1 SWAP 1 0 D10 D11 D9 D8 D7 X=00H X=7FH Column Address / Display Data / Segment Driver X=7FH X=00H D11 D10 D6 D5 D4 D3 D2 D1 D0 D9 D8 D7 D6 D5 D4 D3 Grayscale Palette Segment Driver Palette A SEGC0 Palette B SEGB0 Palette C SEGA0 Palette A SEGC127 Palette B SEGB127 Palette C SEGA127 NOTE) The data indicated with a slash mark ( / ) is invalid, and only MSB bits are effective. - 34 - Ver.2003-10-14 D0 Display Data in DDRAM D0 Display Data in DDRAM D1 Display Data in DDRAM D1 Display Data in DDRAM NJU6825 8-bit Bus Length HSW 0 0 ABS 0 0 (MON=1, PWM=*, C256=0, WLS=0) SWAP 0 1 D7 D6 Column Address / Display Data / Segment Driver X=01H X=FEH X=FFH X=00H REF 0 1 X=00H X=FEH X=FFH X=01H D5 D4 D2 D1 D0 D7 D4 D3 D2 D1 D7 D6 D5 D4 D2 D1 D0 D7 D4 D3 D3 D2 D2 D2 D2 D1 D1 Grayscale Palette Segment Driver Palette A SEGA0 Palette B SEGB0 Palette C SEGC0 Palette A SEGA127 Palette B SEGB127 Palette C SEGC127 HSW 0 0 ABS 0 0 REF 0 1 SWAP 1 0 D7 D6 X=00H X=FEH Column Address / Display Data / Segment Driver X=01H X=FEH X=FFH X=00H X=FFH X=01H D5 D4 D2 D1 D0 D7 D4 D3 D2 D1 D7 D6 D5 D4 D2 D1 D0 D7 D4 Grayscale Palette Segment Driver Palette A SEGC0 Palette B SEGB0 Palette C SEGA0 Palette A SEGC127 Palette B SEGB127 Palette C SEGA127 HSW 0 0 ABS 1 1 REF 0 1 SWAP 0 1 D3 X=00H X=FEH Column Address / Display Data / Segment Driver X=01H X=FEH X=FFH X=00H X=FFH X=01H D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D3 D2 D1 D0 D7 D6 D5 D4 D3 Grayscale Palette Segment Driver Palette A SEGA0 Palette B SEGB0 Palette C SEGC0 Palette A SEGA127 Palette B SEGB127 Palette C SEGC127 HSW 0 0 ABS 1 1 REF 0 1 SWAP 1 0 D3 X=00H X=FEH Column Address / Display Data / Segment Driver X=01H X=FEH X=FFH X=00H X=FFH X=01H D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D3 D2 D1 D0 D7 D6 D5 D4 D3 Grayscale Palette Segment Driver Palette A SEGC0 Palette B SEGB0 Palette C SEGA0 Palette A SEGC127 Palette B SEGB127 Palette C SEGA127 NOTE) The data indicated with a slash mark ( / ) is invalid, and only MSB bits are effective. Ver.2003-10-14 - 35 - D0 Display Data in DDRAM D0 Display Data in DDRAM D1 Display Data in DDRAM D1 Display Data in DDRAM NJU6825 HSW 1 ABS * REF 0 SWAP 0 D7 D6 D5 X=00H Column Address / Display Data / Segment Driver X=01H X=02H ... ... ... ... Display Data in DDRAM Grayscale Palette Segment Driver D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D1 Palette A SEGA0 Palette B SEGB0 Palette C SEGC0 Palette A SEGA1 Palette B SEGB1 Palette C SEGC1 ... ... ... ... X=BDH Column Address / Display Data / Segment Driver X=BEH X=BFH D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 Palette A SEGA126 Palette B SEGB126 Palette C SEGC126 Palette A SEGA127 Palette B SEGB127 Palette C SEGC127 HSW 1 ABS * REF 0 SWAP 1 D7 D6 D5 X=00H Column Address / Display Data / Segment Driver X=01H X=02H D0 ... ... ... ... Display Data in DDRAM Grayscale Palette Segment Driver D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D1 Palette A SEGC0 Palette B SEGB0 Palette C SEGA0 Palette A SEGC1 Palette B SEGB1 Palette C SEGA1 ... ... ... ... X=BDH Column Address / Display Data / Segment Driver X=BEH X=BFH D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 Palette A SEGC126 Palette B SEGB126 Palette C SEGA126 Palette A SEGC127 Palette B SEGB127 Palette C SEGA127 HSW 1 ABS * REF 1 SWAP 0 D3 X=BEH Column Address / Display Data / Segment Driver X=BFH X=BDH X=BEH D0 ... ... ... ... Display Data in DDRAM Grayscale Palette Segment Driver D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D5 Palette A SEGC0 Palette B SEGB0 Palette C SEGA0 Palette A SEGC1 Palette B SEGB1 Palette C SEGA1 ... ... ... ... X=01H Column Address / Display Data / Segment Driver X=02H X=00H X=01H D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 Palette A SEGC126 Palette B SEGB126 Palette C SEGA126 Palette A SEGC127 Palette B SEGB127 Palette C SEGA127 HSW 1 ABS * REF 1 SWAP 1 D3 X=BEH Column Address / Display Data / Segment Driver X=BFH X=BDH X=BEH D4 ... ... ... ... Display Data in DDRAM Grayscale Palette Segment Driver D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D5 Palette A SEGA0 Palette B SEGB0 Palette C SEGC0 Palette A SEGA1 Palette B SEGB1 Palette C SEGC1 ... ... ... ... X=01H Column Address / Display Data / Segment Driver X=02H X=00H X=01H D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 Palette A SEGA126 Palette B SEGB126 Palette C SEGC126 Palette A SEGA127 Palette B SEGB127 Palette C SEGC127 NOTE) The data indicated with a slash mark ( / ) is invalid, and only MSB bits are effective. - 36 - Ver.2003-10-14 D4 D4 D4 D0 D0 NJU6825 8-bit Bus Length HSW * * ABS * * (MON=1, PWM=*, C256=1, WLS=0) SWAP 0 1 D7 D6 D5 D4 Column Address / Display Data / Segment Driver X=7FH X=00H REF 0 1 X=00H X=7FH D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D1 Grayscale Palette Segment Driver Palette A SEGA0 Palette B SEGB0 Palette C SEGC0 Palette A SEGA127 Palette B SEGB127 Palette C SEGC127 HSW * * ABS * * REF 0 1 SWAP 1 0 D7 D6 D5 D4 X=00H X=7FH Column Address / Display Data / Segment Driver X=7FH X=00H D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 Grayscale Palette Segment Driver Palette A SEGC0 Palette B SEGB0 Palette C SEGA0 Palette A SEGC127 Palette B SEGB127 Palette C SEGA127 NOTE) The data indicated with a slash mark ( / ) is invalid, and only MSB bits are effective. Ver.2003-10-14 - 37 - D0 Display Data in DDRAM D0 Display Data in DDRAM NJU6825 (4-5) Write Data and Read Data 16-bit Bus Length ABS=0 Write Data Read Data D15 D15 D14 D14 D13 D13 D12 D12 D11 * D10 D10 D9 D9 D8 D8 D7 D7 D6 * D5 * D4 D4 D3 D3 D2 D2 D1 D1 D0 * ABS=1 Write Data Read Data D15 * D14 * D13 * D12 * D11 D11 D10 D10 D9 D9 D8 D8 D7 D7 D6 D6 D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0 D0 8-bit Bus Length ABS=0, HSW=0, C256=0 Write Data Read Data D7 D7 D6 D6 D5 D5 D4 D4 (Column Address: 00H, 02H, ...FCH, FEH) D3 * D2 D2 D1 D1 D0 D0 ABS=0, HSW=0, C256=0 Write Data Read Data D7 D7 D6 * D5 * D4 D4 (Column Address: 01H, 03H, ...FDH, FFH) D3 D3 D2 D2 D1 D1 D0 * ABS=1, HSW=0, C256=0 Write Data Read Data D7 * D6 * D5 * D4 * (Column Address: 00H, 02H, ...FCH, FEH) D3 D3 D2 D2 D1 D1 D0 D0 ABS=1, HSW=0, C256=0 Write Data Read Data D7 D7 D6 D6 D5 D5 D4 D4 (Column Address: 01H, 03H, ...FDH, FFH) D3 D3 D2 D2 D1 D1 D0 D0 ABS=0, HSW=1, C256=0 Write Data Read Data D7 D7 D6 D6 D5 D5 D4 D4 (Column Address: 00H, 01H, ...BEH, BFH) D3 D3 D2 D2 D1 D1 D0 D0 ABS=0, HSW=0, C256=1 Write Data Read Data D7 D7 D6 D6 D5 D5 D4 D4 (Column Address: 00H, 01H, ...7EH, 7FH) D3 D3 D2 D2 D1 D1 D0 D0 NOTE) * : Invalid Data - 38 - Ver.2003-10-14 NJU6825 (5) GRAYSCALE CONTROL CIRCUIT (5-1) Display Mode Selection A display mode is selected by the combination of the D2 (MON) bit of the "Display Control (1)" instruction and the D3 (PWM) and D2 (C256) bits of the "Display Mode Control" instruction, as shown below. Table 11 MON 0 Display Mode Selection C256 PWM Display Mode (NOTE1) 0 Variable 16-grayscale Mode 0 1 Variable 8-grayscale Mode 0 1 Fixed 8-grayscale Mode 1 0 * B&W Mode 1 Oscillation (NOTE2) fOSC1 fOSC2 fOSC3 Bus Length 4096 Colors 256 Colors 256 Colors Black & White 8-/16-bit 8-bit 8-/16-bit 8-bit 8-/16-bit 8-bit (WLS=0/1) (WLS=0) (WLS=0/1) (WLS=0) (WLS=0/1) (WLS=0) 1 NOTE1) In the variable grayscale mode, "C256" bit selects either 16-grayscale (4K colors) or 8-grayscale (256 colors). When C256="0" (16-grayscale), all 12 bits are assigned to 1 RGB-pixel. When C256="1" (8-grayscale), only 8 bits are assigned and the 8-bit bus length should be used. In the fixed 8-grayscale mode or the B&W mode, the "C256" bit is usually "1". For more information how the display data is assigned, refer to "(4-4) Bit Assignment of Display Data". NOTE2)Oscillation frequency is decided according to the display mode, and is fine-tuned by the "Frequency Control" Instruction. Refer to "(10) OSCILLATOR" and "OSCILLATION FREQUENCY AND FRAME FREQUENCY". (5-1-1) Variable 16-grayscale Mode In this mode, each of the palettes Aj, Bj and Cj (j=0-15) is capable of selecting 16 from 32 grayscales (0/31-31/31) by setting palette data in the grayscale palette. Then, each of the segment drivers SEGAi, SEGBi and SEGCi (i=0 to 127) generates 16 grayscales to achieve 4,096 colors. Refer to Table 12-1 and Table 12-2. (5-1-2) Variable 8-grayscale Mode Each of the palettes Aj, Bj and Cj (j=0-15) is capable of selecting 8 from 32 grayscales (0/31-31/31). 2 segment drivers of 1 RGB-group (SEGAi, SEGBi and SEGCi (i=0 to 127)) generate 8 grayscales, and the other driver does 4 grayscales to achieve 256 colors. Refer to Table 13-1 through Table 13-4. The 8-bit bus length is usually used in this mode. (5-1-3) Fixed 8-grayscale Mode The palette setting is not necessary, because the palettes Aj, Bj and Cj (j=0-15) are always fixed at 4 or 8 grayscales between 0/7 and 7/7. 2 segment drivers of 1 RGB-group (SEGAi, SEGBi and SEGCi (i=0 to 127)) are fixed at 8 grayscales, and the other driver is 4 grayscales, then results in 256 colors. Refer to Table 14-1 and Table 14-2. (5-1-4) B&W Mode The palette setting is not necessary, where the only MSB bits of display data are valid. Refer to Table 15. Ver.2003-10-14 - 39 - NJU6825 (6) GRAYSCALE PALETTE (6-1) Grayscale Selection in Variable 16-grayscale Mode Table 12-1 Grayscale selection ( Palette Aj, Bj, and Cj ) Display Data MSB----LSB Palette Name Table 12-2 Grayscale Palette ( Palette Aj, Bj, and Cj ) Palette Data MSB---LSB Grayscale Default Setting Palette Data MSB---LSB Grayscale Default Setting 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Palette A0/B0/C0 Palette A1/B1/C1 Palette A2/B2/C2 Palette A3/B3/C3 Palette A4/B4/C4 Palette A5/B5/C5 Palette A6/B6/C6 Palette A7/B7/C7 Palette A8/B8/C8 Palette A9/B9/C9 Palette A10/B10/C10 Palette A11/B11/C11 Palette A12/B12/C12 Palette A13/B13/C13 Palette A14/B14/C14 Palette A15/B15/C15 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 0 1/31 2/31 3/31 4/31 5/31 6/31 7/31 8/31 9/31 10/31 11/31 12/31 13/31 14/31 15/31 Palette A0/B0/C0 Palette A1/B1/C1 Palette A2/B2/C2 Palette A3/B3/C3 Palette A4/B4/C4 Palette A5/B5/C5 Palette A6/B6/C6 Palette A7/B7/C7 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 16/31 17/31 18/31 19/31 20/31 21/31 22/31 23/31 24/31 25/31 26/31 27/31 28/31 29/31 30/31 31/31 Palette A8/B8/C8 Palette A9/B9/C9 Palette A10/B10/C10 Palette A11/B11/C11 Palette A12/B12/C12 Palette A13/B13/C13 Palette A14/B14/C14 Palette A15/B15/C15 NOTE1) "MON=0", "PWM=0", "C256=0" NOTE2) Applied to palette Aj, Bj and Cj (j=0 to 15) - 40 - Ver.2003-10-14 NJU6825 (6-2) Grayscale Selection in Variable 8-grayscale Mode Table 13-1 Grayscale selection ( Palette Aj and Bj ) Display Data MSB----LSB Palette Name Table 13-2 Palette Data MSB---LSB Grayscale Palette Palette Data MSB---LSB ( Palette Aj and Bj ) Grayscale Default Setting Grayscale Default Setting 000* 001* 010* 011* 100* 101* 110* 111* Palette A1/B1/C1 Palette A3/B3/C3 Palette A5/B5/C5 Palette A7/B7/C7 Palette A9/B9/C9 Palette A11/B11/C11 Palette A13/B13/C13 Palette A15/B15/C15 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 0 1/31 2/31 3/31 4/31 5/31 6/31 7/31 8/31 9/31 10/31 11/31 12/31 13/31 14/31 15/31 Palette A1/B1/C1 Palette A3/B3/C3 Palette A5/B5/C5 Palette A7/B7/C7 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 16/31 17/31 18/31 19/31 20/31 21/31 22/31 23/31 24/31 25/31 26/31 27/31 28/31 29/31 30/31 31/31 Palette A9/B9/C9 Palette A11/B11/C11 Palette A13/B13/C13 Palette A15/B15/C15 NOTE1) "MON=0", "PWM=0", "C256=1". NOTE2) Applied to palette Aj and Bj (j=0 to 15) NOTE3) Palette 0, 2, 4, 6, 8, 10, 12 and 14 are disabled. Table 13-3 Grayscale selection ( Palette Cj ) Display Data MSB----LSB Palette Name Table 13-4 ( Palette Cj ) Palette Data MSB---LSB Grayscale Palette Palette Data MSB---LSB Grayscale Default Setting Grayscale Default Setting 00** Palette A3/B3/C3 01** Palette A7/B7/C7 10** Palette A11/B11/C11 11** Palette A15/B15/C15 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 0 1/31 2/31 3/31 4/31 5/31 6/31 7/31 8/31 9/31 10/31 11/31 12/31 13/31 14/31 15/31 Palette A3/B3/C3 Palette A7/B7/C7 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 16/31 17/31 18/31 19/31 20/31 21/31 22/31 23/31 24/31 25/31 26/31 27/31 28/31 29/31 30/31 31/31 Palette A11/B11/C11 Palette A15/B15/C15 NOTE1) "MON=0", "PWM=0", "C256=1" NOTE2) Applied to palette Cj (j=0 to 15) NOTE3) Palette 0, 1, 2, 4, 5, 6, 8, 9, 10, 12, 13 and 14 are disabled. Ver.2003-10-14 - 41 - NJU6825 (6-3) Grayscale Selection in Fixed 8-grayscale Mode Table 14-1 Grayscale Selection Table 14-2 Grayscale Palette ( Palette Aj and Bj ) Display Data MSB- - - -LSB 000* 001* 010* 011* 100* 101* 110* 111* Grayscale 0/7 1/7 2/7 3/7 4/7 5/7 6/7 7/7 ( Palette Cj ) Display Data MSB- - - -LSB 00** 01** 10** 11** Grayscale 0/7 3/7 5/7 7/7 NOTE1) "MON=0", "PWM=1", "C256=0 or 1" (6-4) Grayscale Selection in B&W Mode Table 15 Grayscale Selection Grayscale 0 1 Display Data MSB- - - -LSB 0*** 1*** NOTE1) "MON=1", "PWM=0 or 1" and "C256=0 or 1" - 42 - Ver.2003-10-14 NJU6825 (7) DISPLAY TIMING GENERATOR The display timing generator generates timing clocks such as the CL (Line Clock), FR (Frame Rate) and FLM (First Line Maker) by dividing an oscillation frequency. These clocks are used inside the LSI, and are activated by setting "1" at the D0 (SON) bit of the "Duty-1 /Display Clock ON/OFF" instruction. The CL is used for the line counter and the data latch circuit. At the rising edge of the CL signal, the line counter is counted up, then 384-bit display data is latched into the data latch circuit. At the falling edge of the CL signal, the latch data is released to the grayscale control circuit, then segment drivers Ai, Bi and Ci (i=0 to 127) produce LCD driving waveforms. The internal data-transmission timing between the DDRAM and segment drivers is completely independent of external data-transmission timing, so that MPU makes access to the LSI without concern for the LSI's internal operation. The FR and FLM are generated by the CL. The FR toggles once every frame in the default status, and is programmed to toggle once every N lines. And the FLM is used to specify an initial display line, which is preset whenever the FLM becomes "H". (8) DATA LATCH CIRCUIT The data latch circuit is used to temporarily store display data which is released to the grayscale control circuit. The display data in this circuit is updated in synchronization with the CL. The "All Pixels ON/OFF", "Display ON/OFF" and "Reverse Display ON/OFF" instructions control the data in this circuit, but does not change the data in the DDRAM. (9) COMMON DRIVERS AND SEGMENT DRIVERS The LSI includes 162-common drivers and 384-segment drivers. The common drivers generate LCD driving waveforms formed on the VLCD, V1, V4 and VSSH levels. The segment drivers generate waveforms formed on the VLCD, V2, V3 and VSSH levels. COM 0 COM 1 163 1 CL SEG0 SEG2 FLM 234 5 163 1 2 34 5 163 1 SEG1 FR VLCD V1 V2 V3 V4 VSSH VLCD V1 V2 V3 V4 VSSH VLCD V1 V2 V3 V4 VSSH VLCD V1 V2 V3 V4 VSSH COM 0 COM 1 SEG0 SEG1 Fig 8 LCD Driving Waveforms (B&W Mode, Color Reverse OFF, 1/163 Duty) Ver.2003-10-14 - 43 - NJU6825 (10) OSCILLATOR The oscillator is equipped with a resistor and a capacitor, and generates internal clocks used for the display timing generator and the voltage booster. The internal resistor is enabled by setting "0" at the D1 (CKS) bit of the "Bus Length" instruction. For more accurate frequency, using an external resistor or external clock is recommended. When using the internal resistor, the resistance is controlled to optimize frame frequency for different LCD panels, by setting the D2-D0 (RF2-RF0) bits of the "Frequency Control" instruction. For more safety, make sure what is the best frequency in the particular application. (10-1) Using Internal Resistor (CKS=0) In this case, the OSC1 should be fixed at "H" or "L" and the OSC2 is open. The oscillation frequency is varied according to the display mode, as follows. Table 16 Symbol fOSC1 fOSC2 fOSC3 Oscillation Frequency vs. Display Mode MON PWM Display Mode 0 0 Variable 8-/16-grayscale Mode 0 1 Fixed 8-grayscale Mode 1 * B&W Mode *: Don't care (10-2) Using External Resistor (CKS=1) Be sure to connect the OSC1 and OSC2 with an external resistor. The frequency of the oscillator should be adjusted to the same value generated by the internal resistor. (10-3) Using External Clock (CKS=1) Input external clock to the OSC1 and leave the OSC2 open. The external clock with 50% duty is recommended. The frequency of the external clock should be the same value generated by the internal resistor. (11) LCD POWER SUPPLY The internal LCD power supply is organized into the voltage converter and the voltage booster. The voltage converter consists of the reference voltage generator, the voltage regulator with EVR and the LCD bias voltage generator. The configuration of the LCD power supply is arranged by setting the D3 (AMPON) and D1 (DCON) bits of the "Power Control" instruction. For this configuration, the internal LCD power supply can be partially used in combination with an external supply voltage, as shown in Table 17. Table 17 DCON 0 0 1 Configuration of LCD Power Supply AMPON Voltage Booster Voltage Converter 0 Inactive Inactive 1 Inactive Active 1 Active Active External Supply Voltage VOUT, VLCD, V1, V2, V3, V4 VOUT - NOTE 1, 3, 4 2, 3, 4 - NOTE1) No internal LCD power supply is used. The LCD bias voltages are externally supplied, and the C1+, C1-, C2+, C2-, C3+, C3-, C4+, C4-, C5+, C5-, C6+, C6-, VREF, VREG and VEE are open. NOTE2) Only the voltage converter is used. The VOUT is externally supplied, and the C1+, C1-, C2+, C2-, C3+, C3-, C4+, C4-, C5+, C5-, C6+, C6-, and VEE are open. The reference voltage is supplied on the VREF. NOTE3) The following relation among each LCD bias voltages must be maintained. VOUT VLCD V1 V2 V3 V4 VSSH NOTE4) If the internal LCD power supply doesn't have enough capability to drive the particular LCD panel, use the external LCD power supply. Otherwise, it may affect display quality. - 44 - Ver.2003-10-14 NJU6825 (11-1) Voltage Booster The internal voltage booster generates up to 7xVEE voltage. The boost level is selected from 2x, 3x, 4x, 5x, 6xor7x by setting the D2-D0 (VU2-VU0) bits of the "Boost Level" instruction. The boost voltage VOUT must not exceed 18.0V, otherwise the voltage stress may cause a permanent damage to the LSI. VOUT=17.5V VOUT=9V VEE=3V VSSH=0V 3-time Boost Fig 9 VEE=2.5V VSSH=0V 7-time Boost Boost Voltage 7-time Boost C1+ C1C2+ C2C3+ C3C4+ C4C5+ C5C6+ C6VOUT 6-time Boost 5-time Boost + + + + + + + C1+ C1C2+ C2C3+ C3C4+ C4C5+ C5C6+ C6VOUT + + + + + + C1+ C1C2+ C2C3+ C3C4+ C4C5+ C5C6+ C6VOUT + + + + + 4-time Boost C1+ C1C2+ C2C3+ C3C4+ C4C5+ C5C6+ C6VOUT 3-time Boost 2-time Boost + + + + C1+ C1C2+ C2C3+ C3C4+ C4C5+ C5C6+ C6VOUT + + + C1+ C1C2+ C2C3+ C3C4+ C4C5+ C5C6+ C6VOUT + Fig 10 External Capacitor Connection of Voltage Booster Ver.2003-10-14 - 45 - NJU6825 (11-2) Voltage Converter (11-2-1) Reference Voltage Generator The reference voltage generator produces the reference voltage (VBA=0.9xVEE). When using the internal LCD power supply, connect the VBA and the VREF, or supply 0.9xVEE or lower voltage on the VREF. When using an external LCD power supply, the VBA should be open. (11-2-2) Voltage Regulator The voltage regulator consists of an operational amplifier with gain control and EVR. The VREF voltage is multiplied to obtain the VREG voltage, and its multiple (boost level) is set by the D2-D0 (VU2-VU0) bits of the "Boost Level" instruction. The formula is shown below. VREG = VREF x N (N: Boost Level) (11-2-3) Electrical Variable Resistor (EVR) The EVR is used to fine-tune the VLCD voltage to optimize display contrast. The EVR value is controlled in 128 steps by setting the D2-D0 (DV2-DV0) bits of the "EVR Control" instruction. The formula is shown below. VLCD = 0.5 x VREG + M (VREG - 0.5 x VREG) / 127 (11-2-4) LCD Bias Voltage Generator (M: EVR Value) The LCD bias voltage generator consists of buffer amplifiers and bleeder resistors to generate the LCD bias voltages such as the VLCD, V1, V2, V3 and V4, and its bias ratio is selected from1/5, 1/6, 1/7, 1/8, 1/9, 1/10, 1/11 or 1/12. As shown in Fig 11, when using only the internal LCD power supply, the capacitors CA2 are connected to the VLCD, V1, V2, V3 and V4 respectively. As shown in Fig 12, when using no internal LCD power supply, the LCD bias voltages are externally supplied on the VLCD, V1, V2, V3 and V4, and the internal LCD power supply should be turned off by setting "0" at the "DCON" and "AMPON" bits. And the C1+, C1-, C2+, C2-, C3+, C3-, C4+, C4-, C5+, C5-, C6+, C6-, VEE, VREF and VREG are open. Fig 13 and 14 show typical peripheral circuits when partially using the LCD power supply without the reference voltage generator. Fig 15 shows the circuit when partially using the LCD power supply without the voltage booster. - 46 - Ver.2003-10-14 NJU6825 (11-3) External Components for LCD Power Supply Using Only Internal LCD Power Supply (7x boost) Using Only External LCD Power Supply VDD VDD CA1 VEE VBA CA3 CA3 VREF VREG VDD CA1 VDD VEE VBA VREF VREG CA1 CA1 CA1 CA1 CA1 CA1 CA1 CA2 CA2 CA2 CA2 CA2 C1C1+ C2C2+ C3C3+ C4C4+ C5C5+ CC+ VOUT VLCD V1 V2 V3 V4 External Power Circuit CA1 VLCD V1 V2 V3 V4 C1C1+ C2C2+ C3C3+ C4C4+ C5C5+ C6C6+ VOUT VLCD V1 V2 V3 V4 CA2 CA2 CA2 CA2 Fig 11 Reference Values CA1 CA2 CA3 1.0 to 4.7F 1.0 to 2.2F 0.1F Fig 12 NOTE1) B grade capacitor is recommended for CA1-CA3. Make sure what is the best capacitor value in the particular application. NOTE2) Parasitic resistance on the power supply lines (VDD, VSS, VEE, VSSH, VOUT, VLCD, V1, V2, V3 and V4) reduces step-up efficiency of the voltage booster, and may have an impact on the LSI's operation and display quality. To minimize this impact, be sure to lay out the shortest wires and place capacitors as close to the LSI as possible. Ver.2003-10-14 - 47 - NJU6825 Using Internal LCD Power Supply Without Reference Voltage generator (1) (7x boost) VDD VDD CA1 VEE VBA VREG C1C1+ C2C2+ C3C3+ C4C4+ C5C5+ C6C6+ VOUT CA1 CA1 Thermistor VREF CA3 Using Internal LCD Power Supply Without Reference Voltage generator (2) (7x boost) VDD CA1 VDD VEE VBA VREF CA3 VREG C1C1+ C2C2+ C3C3+ C4C4+ C5C5+ C6C6+ VOUT CA1 CA1 CA1 CA1 CA1 CA1 CA1 CA1 CA1 CA1 CA1 CA1 CA2 CA2 CA2 CA2 CA2 VLCD V1 V2 V3 V4 CA2 CA2 CA2 CA2 CA2 VLCD V1 V2 V3 V4 Fig 13 Reference Values CA1 CA2 CA3 1.0 to 4.7F 1.0 to 2.2F 0.1F Fig 14 NOTE1) B grade capacitor is recommended for CA1-CA3. Make sure what is the best capacitor value in the particular application. NOTE2) Parasitic resistance on the power supply lines (VDD, VSS, VEE, VSSH, VOUT, VLCD, V1, V2, V3 and V4) reduces step-up efficiency of the voltage booster, and may have an impact on the LSI's operation and display quality. To minimize this impact, be sure to lay out the shortest wires and place capacitors as close to the LSI as possible. - 48 - Ver.2003-10-14 NJU6825 Using Internal LCD Power Supply Without Voltage Booster VDD VDD CA1 VEE VBA CA3 CA3 VREF VREG C1C1+ C2C2+ C3C3+ C4C4+ C5C5+ C6External Power Circuit C6+ VOUT CA1 CA2 CA2 CA2 CA2 CA2 VLCD V1 V2 V3 V4 Fig 15 Reference Values CA1 CA2 CA3 1.0 to 4.7F 1.0 to 2.2F 0.1F NOTE1) B grade capacitor is recommended for CA1-CA3. Make sure what is the best capacitor value in the particular application. NOTE2) Parasitic resistance on the power supply lines (VDD, VSS, VEE, VSSH, VOUT, VLCD, V1, V2, V3 and V4) reduces step-up efficiency of the voltage booster, and may have an impact on the LSI's operation and display quality. To minimize this impact, be sure to lay out the shortest wires and place capacitors as close to the LSI as possible. Ver.2003-10-14 - 49 - NJU6825 (11-4) Discharge Circuit The LSI incorporates two discharge circuits which are independently controlled for the VLCD and V1-V4 and for the VOUT. The VLCD and V1-V4 are discharged by setting "1" at the D0 (DIS) bit of the "Discharge ON/OFF" instruction or the reset by the RESb. Be sure to turned off the internal or external LCD power supply when this instruction is executed, otherwise it may function as a current load and affect an operating current. Refer to "(14-22) Discharge ON/OFF". (11-5) Power ON/OFF To protect the LSI from overcurrent, the following sequences must be maintained to turn on and off the power supply. In addition to the following discussions, refer to "(18) TYPICAL INSTRUCTION SEQUENCES". (11-5-1) Power ON/OFF in Using Internal LCD Power Supply Power ON First "VDD and VEE ON", next "Reset by RESb", then "Internal LCD power supply ON". Be sure to execute the "Display ON" instruction later than the completion of this power ON sequence. Otherwise, unexpected pixels may be turned on instantly. Power OFF First "Reset by RESb or "HALT" instruction", next "VDD and VEE OFF". If using different power sources for the VDD and the VEE individually, the VEE must be turned off after the reset or the "HALT". After that, the VDD can be turned off, waiting until the LCD bias voltages (VLCD, V1, V2, V3 and V4) drop below the threshold level of LCD pixels. (11-5-2) Power ON/OFF in Using External LCD Power Supply Power ON First "VDD and VEE ON", next "Reset by RESb", then "External LCD power supply ON". When using only external VOUT, first "VDD ON", next "Reset by RESb", then "External VOUT ON", as well. Power OFF First "Reset by RESb or "HALT" instruction" to isolate external LCD bias voltages, next "VDD OFF". For more safety, placing a resistor in series on the VLCD line (or the VOUT line in using only the external VOUT) is recommended. That resistance is usually between 50 and 100. - 50 - Ver.2003-10-14 NJU6825 (12) RESET FUNCTION The reset function initializes the LSI to the following default status by setting the RESb to "L". Connecting the RESb with MPU's reset is recommended so that the LSI and MPU is initialized at a time. Default Status 1. Display Data in DDRAM 2. Column Address 3. Row Address 4. Initial Display Line 5. Display ON/OFF 6. Reverse Display ON/OFF 7. Duty Cycle Ratio 8. N-line Inversion ON/OFF 9. COM Scan Direction 10. Increment Control 11. REF 12. Swap 13. EVR Value 14. Internal LCD Power Supply 15. Display Mode 16. LCD Bias Ratio 17. Palette 0 18. Palette 1 19. Palette 2 20. Palette 3 21. Palette 4 22. Palette 5 23. Palette 6 24. Palette 7 25. Palette 8 26. Palette 9 27. Palette 10 28. Palette 11 29. Palette 12 30. Palette 13 31. Palette 14 32. Palette 15 33. Display Mode Control 34. Bus Length 35. Discharge ON/OFF :Undefined :(00)H :(00)H :(0)H (1st line) :OFF :OFF (Normal) :1/163 Duty (DSE=0) :OFF :COM0 COM161 :Auto-increment OFF (AIM, AXI, AYI)=(0, 0, 0) :REF=0 (Normal) :OFF (Normal) :(0, 0, 0, 0, 0, 0, 0) :OFF :Grayscale Mode :1/9 Bias :(0, 0, 0, 0, 0) :(0, 0, 0, 1, 1) :(0, 0, 1, 0, 1) :(0, 0, 1, 1, 1) :(0, 1, 0, 0, 1) :(0, 1, 0, 1, 1) :(0, 1, 1, 0, 1) :(0, 1, 1, 1, 1) :(1, 0, 0, 0, 1) :(1, 0, 0, 1, 1) :(1, 0, 1, 0, 1) :(1, 0, 1, 1, 1) :(1, 1, 0, 0, 1) :(1, 1, 0, 1, 1) :(1, 1, 1, 0, 1) :(1, 1, 1, 1, 1) :Variable 16-grayscale Mode (4,096 Colors) :8-bit Bus Length :OFF (DIS)=(0) Ver.2003-10-14 - 51 - NJU6825 (13) INSTRUCTION TABLES (13-1) Instruction Table and Register Address The LSI incorporates 6 instruction tables as shown in Fig 16, and each instruction table has a specific address in between "0" and "5". And each instruction register has a specific address in between (0H) and (FH), and instruction is read out from the register by the "Register Address" and "Register Read" instructions. Fig 17 shows part of the instruction sequence, where the instruction table should be specified prior to other instructions. However, when some instructions of the same table are sequentially executed, the table selection may be omitted. In addition, the "Display Data Write", "Display Data Read" and "Register Read" instructions can be performed in any table. Table "0" (RE2,RE1,RE0)=(0,0,0) Table "1" (RE2,RE1,RE0)=(0,0,1) Table "2" (RE2,RE1,RE0)=(0,1,0) Table "3" (RE2,RE1,RE0)=(0,1,1) Table "4" (RE2,RE1,RE0)=(1,0,0) Table "5" (RE2,RE1,RE0)=(1,0,1) Instruction (0H) Instruction (0H) Instruction (0H) Instruction (0H) Instruction (0H) Instruction (0H) Instruction (FH) Instruction (FH) Instruction (FH) Instruction (FH) Instruction (FH) Instruction (FH) NOTE) Address (FH) is assigned to "Instruction Table Select" in any table. Fig 16 Instruction Table Overview Optional Status Instruction Table "0" Select Instruction 1 Instruction 2 Instruction 3 Instruction Table "4" Select Instruction 4 Instructions in Table "4" Instruction 5 Instruction Table "5" Select Instruction 6 Optional Status Fig 17 Outline of Instruction Sequence [RE2:RE0]=[1,0,1] Instruction in Table "5" [RE2:RE0]=[1,0,0] Instructions in Table "0" [RE2:RE0]=[0,0,0] - 52 - Ver.2003-10-14 NJU6825 (13-2) Instruction Table 0 Instructions/ Register Address [NH] 1 Display Data Write 2 Display Data Read Column Address (RE2, RE1, RE0)=(0, 0, 0) Code (80 Series MPU I/F) Code D7 D6 D5 D4 D3 D2 D1 D0 Functions Writing Display Data Reading Display Data AX2 AX1 AX0 Setting Column Address for start point Setting Column Address for start point Setting Row Address for start point Setting Row Address for start point Setting Row Address for Initial COM Setting Row Address for Initial COM Setting the Number of N-line Inversion Setting the Number of N-line Inversion : Common Scan Direction : Grayscale/B/W Mode : All Pixels ON/OFF : Display ON/OFF : Reverse Display ON/OFF : N-line Inversion ON/OFF : SWAP ON/OFF : Segment Direction : Window Area ON/OFF : Read-Modify-Write ON/OFF : Row Increment : Column Increment : Voltage Converter ON/OFF : Power Save ON/OFF : Voltage Booster ON/OFF : Reset CSb 0 0 0 RS 0 0 1 RDb WRb RE2 RE1 RE0 1 0 1 0 1 0 0/1 0/1 0 0/1 0/1 0 0/1 0/1 0 Write Data Read Data 0 0 0 0 AX3 (Lower) [0H] 3 Column Address (Upper) [1H] Row Address 0 1 1 0 0 0 0 0 0 0 1 AX7 AX6 AX5 AX4 (Lower) [2H] 4 Row Address 0 1 1 0 0 0 0 0 0 1 0 AY3 AY2 AY1 AY0 (Upper) [3H] Initial Display Line (Lower) [4H] 5 Initial Display Line (Upper) [5H] N-line Inversion (Lower) [6H] 6 N-line Inversion (Upper) [7H] 7 Display Control (1) [8H] Display Control (2) [9H] Increment Control [AH] Power Control [BH] Duty Cycle Ratio [CH] Boost Level [DH] LCD Bias Ratio [EH] Instruction Table Select [FH] 0 1 1 0 0 0 0 0 0 1 1 AY7 AY6 AY5 AY4 0 1 1 0 0 0 0 0 1 0 0 LA3 LA2 LA1 LA0 0 1 1 0 0 0 0 0 1 0 1 LA7 LA6 LA5 LA4 0 1 1 0 0 0 0 0 1 1 0 N3 N2 N1 N0 0 1 1 0 0 0 0 0 1 1 1 N7 N6 N5 N4 0 1 1 0 0 0 0 1 0 0 0 8 0 1 1 0 0 0 0 1 0 0 1 9 0 1 1 0 0 0 0 1 0 1 0 10 0 1 1 0 0 0 0 1 0 1 1 SHIFT ALL ON/ MON SHIFT MON ON OFF ALLON ON/OFF REV NLIN REV NLIN SWAP REF SWAP REF WIN AIM WIN AIM AYI AXI AYI AXI AMPON HALT DC AMP ACL HALT ON DCON ON ACL DS3 DS2 11 0 1 1 0 0 0 0 1 1 0 0 DS1 DS0 Setting LCD Duty Cycle Ratio 12 0 1 1 0 0 0 0 1 1 0 1 * VU2 VU1 VU0 VU2-0 : Setting Boost Level 13 0 1 1 0 0 0 0 1 1 1 0 * B2 B1 B0 Setting LCD Bias Ratio 14 0 1 1 0 0/1 0/1 0/1 1 1 1 1 TST0 RE2 RE1 RE0 Setting Instruction Table NOTE1) * : Don't care. NOTE2) [NH] (N=0-F) : Register Address NOTE3) Any nonexistent instruction code is prohibited. NOTE4) Dual instructions except for "EVR Control" are already effective when either upper byte or lower byte is set. NOTE5) "EVR Control" instruction is finally effective when both upper and lower bytes are set. Send upper byte first, next lower byte. Ver.2003-10-14 - 53 - NJU6825 (13-3) Instruction Table 1 Instructions/ Register Address [NH] Palette A0/A8 (Lower) [0H] Palette A0/A8 (Upper) [1H] Palette A1/A9 (Lower) [2H] Palette A1/A9 (Upper) [3H] Palette A2/A10 (Lower) [4H] Palette A2/A10 (Upper) [5H] Palette A3/A11 (Lower) [6H] 15 Palette A3/A11 (Upper) [7H] Palette A4/A12 (Lower) [8H] Palette A4/A12 (Upper) [9H] Palette A5/A13 (Lower) [AH] Palette A5/A13 (Upper) [BH] Palette A6/A14 (Lower) [CH] Palette A6/A14 (Upper) [DH] 14 Instruction Table Select [FH] 0 1 1 0 0 0 1 0 1 1 1 * * * PA34/ Setting Palette Data : PA114 A3(PS=0) /A11(PS=1) (RE2, RE1, RE0)=(0, 0, 1) Code (80 series MPU I/F) Code D7 0 D6 0 D5 0 D4 0 D3 D2 D1 D0 Functions CSb 0 RS 1 RDb WRb RE2 RE1 RE0 1 0 0 0 1 PA03/ PA02/ PA01/ PA00/ Setting Palette Data : PA83 PA82 PA81 PA80 A0(PS=0) /A8(PS=1) * * * PA04/ Setting Palette Data : PA84 A0(PS=0) /A8(PS=1) 0 1 1 0 0 0 1 0 0 0 1 0 1 1 0 0 0 1 0 0 1 0 PA13/ PA12/ PA93 PA92 PA11/ PA10/ Setting Palette Data : PA91 PA90 A1(PS=0) /A9(PS=1) * PA14/ Setting Palette Data : PA94 A1(PS=0) /A9(PS=1) 0 1 1 0 0 0 1 0 0 1 1 * * 0 1 1 0 0 0 1 0 1 0 0 PA23/ PA22/ PA21/ PA20/ Setting Palette Data : PA103 PA102 PA101 PA100 A2(PS=0) /A10(PS=1) * * * PA24/ Setting Palette Data : PA104 A2(PS=0) /A10(PS=1) 0 1 1 0 0 0 1 0 1 0 1 0 1 1 0 0 0 1 0 1 1 0 PA33/ PA32/P PA31/ PA30/ Setting Palette Data : PA113 A112 PA111 PA110 A3(PS=0) /A11(PS=1) 0 1 1 0 0 0 1 1 0 0 0 PA43/ PA42/P PA41/ PA40/ Setting Palette Data : PA123 A122 PA121 PA120 A4(PS=0) /A12(PS=1) * * * PA44/ Setting Palette Data : PA124 A4(PS=0) /A12(PS=1) 0 1 1 0 0 0 1 1 0 0 1 0 1 1 0 0 0 1 1 0 1 0 PA53/ PA52/P PA51/ PA50/ Setting Palette Data : PA133 A132 PA131 PA130 A5(PS=0) /A13(PS=1) * * * PA54/ Setting Palette Data : PA134 A5(PS=0) /A13(PS=1) 0 1 1 0 0 0 1 1 0 1 1 0 1 1 0 0 0 1 1 1 0 0 PA63/ PA62/P PA61/ PA60/ Setting Palette Data : PA143 A142 PA141 PA140 A6(PS=0) /A14(PS=1) * * * PA64/ Setting Palette Data : PA144 A6(PS=0) /A14(PS=1) RE0 Setting Instruction Table 0 1 1 0 0 0 1 1 1 0 1 0 1 1 0 0/1 0/1 0/1 1 1 1 1 TST0 RE2 RE1 NOTE1) * : Don't care. NOTE2) [NH] (N=0-F) : Register Address NOTE3) Any nonexistent instruction code is prohibited. NOTE4) Dual instructions except for "EVR Control" are already effective when either upper byte or lower byte is set. NOTE5) "EVR Control" instruction is finally effective when both upper and lower bytes are set. Send upper byte first, next lower byte. - 54 - Ver.2003-10-14 NJU6825 (13-4) Instruction Table 2 Instructions/ Register Address [NH] Palette A7/A15 (Lower) [0H] Palette A7/A15 (Upper) [1H] Palette B0/B8 (Lower) [2H] Palette B0/B8 (Upper) [3H] Palette B1/B9 (Lower) [4H] Palette B1/B9 (Upper) [5H] Palette B2/B10 (Lower) [6H] 15 Palette B2/B10 (Upper) [7H] Palette B3/B11 (Lower) [8H] Palette B3/B11 (Upper) [9H] Palette B4/B12 (Lower) [AH] Palette B4/B12 (Upper) [BH] Palette B5/B13 (Lower) [CH] Palette B5/B13 (Upper) [DH] 14 Instruction Table Select [FH] 0 1 1 0 0 1 0 0 1 1 1 * * * PB24/ Setting Palette Data : PB104 B2(PS=0) /B10(PS=1) (RE2, RE1, RE0)=(0, 1, 0) Code (80 series MPU I/F) Code D7 0 D6 0 D5 0 D4 0 D3 D2 D1 D0 Functions CSb 0 RS 1 RDb WRb RE2 RE1 RE0 1 0 0 1 0 PA73/ PA72/P PA71/ PA70/ Setting Palette Data : PA153 A152 PA151 PA150 A7(PS=0) /A15(PS=1) * * * PA74/ Setting Palette Data : PA154 A7(PS=0) /A15(PS=1) 0 1 1 0 0 1 0 0 0 0 1 0 1 1 0 0 1 0 0 0 1 0 PB03/ PB02/ PB01/ PB00/ Setting Palette Data : PB83 PB82 PB81 PB80 B0(PS=0) /B8(PS=1) * * * PB04/ Setting Palette Data : PG84 B0(PS=0) /B8(PS=1) 0 1 1 0 0 1 0 0 0 1 1 0 1 1 0 0 1 0 0 1 0 0 PB13/ PB12/ PB11/ PB10/ Setting Palette Data : PB93 PB92 PB91 PB90 B1(PS=0) /B9(PS=1) * * * PB14/ Setting Palette Data : PB94 B1(PS=0) /B9(PS=1) 0 1 1 0 0 1 0 0 1 0 1 0 1 1 0 0 1 0 0 1 1 0 PB23/ PB22/ PB21/ PB20/ Setting Palette Data : PB103 PB102 PB101 PB100 B2(PS=0) /B10(PS=1) 0 1 1 0 0 1 0 1 0 0 0 PB33/ PB32/ PB31/ PB30/ Setting Palette Data : PB113 PB112 PB111 PB110 B3(PS=0) /B11(PS=1) * * * PB34/ Setting Palette Data : PB114 B3(PS=0) /B11(PS=1) 0 1 1 0 0 1 0 1 0 0 1 0 1 1 0 0 1 0 1 0 1 0 PB43/ PB42/ PB41/ PB40/ Setting Palette Data : PB123 PB122 PB121 PB120 B4(PS=0) /B12(PS=1) * * * PB44/ Setting Palette Data : PB124 B4(PS=0) /B12(PS=1) 0 1 1 0 0 1 0 1 0 1 1 0 1 1 0 0 1 0 1 1 0 0 PB53/ PB52/ PB51/ PB50/ Setting Palette Data : PB133 PB132 PB131 PB130 B5(PS=0) /B13(PS=1) * * * PB54/ Setting Palette Data : PB134 B5(PS=0) /B13(PS=1) RE0 Setting Instruction Tablet 0 1 1 0 0 1 0 1 1 0 1 0 1 1 0 0/1 0/1 0/1 1 1 1 1 TST0 RE2 RE1 NOTE1) * : Don't care. NOTE2) [NH] (N=0-F) : Register Address NOTE3) Any nonexistent instruction code is prohibited. NOTE4) Dual instructions except for "EVR Control" are already effective when either upper byte or lower byte is set. NOTE5) "EVR Control" instruction is finally effective when both upper and lower bytes are set. Send upper byte first, next lower byte. Ver.2003-10-14 - 55 - NJU6825 (13-5) Instruction Table 3 Instructions/ Register Address [NH] Palette B6/B14 (Lower) [0H] Palette B6/B14 (Upper) [1H] Palette B7/B15 (Lower) [2H] Palette B7/B15 (Upper) [3H] Palette C0/C8 (Lower) [4H] Palette C0/C8 (Upper) [5H] Palette C1/C9 (Lower) [6H] 15 Palette C1/C9 (Upper) [7H] Palette C2/C10 (Lower) [8H] Palette C2/C10 (Upper) [9H] Palette C3/C11 (Lower) [AH] Palette C3/C11 (Upper) [BH] Palette C4/C12 (Lower) [CH] Palette C4/C12 (Upper) [DH] 14 Instruction Table Select [FH] 0 1 1 0 0 1 1 0 1 1 1 * * * PC14/ Setting Palette Data : PC94 C1(PS=0) /C9(PS=1) (RE2, RE1, RE0)=(0, 1, 1) Code (80 series MPU I/F) Code D7 0 D6 0 D5 0 D4 0 D3 D2 D1 D0 Functions CSb 0 RS 1 RDb WRb RE2 RE1 RE0 1 0 0 1 1 PB63/ PB62/ PB61/ PB60/ Setting Palette Data : PB143 PB142 PB141 PB140 B6(PS=0) /B14(PS=1) * * * PB64/ Setting Palette Data : PB144 B6(PS=0) /B14(PS=1) 0 1 1 0 0 1 1 0 0 0 1 0 1 1 0 0 1 1 0 0 1 0 PB73/ PB72/ PB71/ PB70/ Setting Palette Data : PB153 PB152 PB151 PB150 B7(PS=0) /B15(PS=1) * * * PB74/ Setting Palette Data : PB154 B7(PS=0) /B15(PS=1) 0 1 1 0 0 1 1 0 0 1 1 0 1 1 0 0 1 1 0 1 0 0 PC03/ PC02/ PC01/ PC00/ Setting Palette Data : PC83 PC82 PC81 PC80 C0(PS=0) /C8(PS=1) * * * PC04/ Setting Palette Data : PC84 C0(PS=0) /C8(PS=1) 0 1 1 0 0 1 1 0 1 0 1 0 1 1 0 0 1 1 0 1 1 0 PC13/ PC12/ PC11/ PC10/ Setting Palette Data : PC93 PC92 PC91 PC90 C1(PS=0) /C9(PS=1) 0 1 1 0 0 1 1 1 0 0 0 PC23/ PC22/ PC21/ PC20/ Setting Palette Data : PC103 PC102 PC101 PC100 C2(PS=0) /C10(PS=1) * * * PC24/ Setting Palette Data : PC104 C2(PS=0) /C10(PS=1) 0 1 1 0 0 1 1 1 0 0 1 0 1 1 0 0 1 1 1 0 1 0 PC33P PC32/ PC31/ PC30/ Setting Palette Data : C113 PC112 PC111 PC110 C3(PS=0) /C11(PS=1) * * * PC34/ Setting Palette Data : PC114 C3(PS=0) /C11(PS=1) 0 1 1 0 0 1 1 1 0 1 1 0 1 1 0 0 1 1 1 1 0 0 PC43/ PC42/ PC41/ PC40/ Setting Palette Data : PC123 PC122 PC121 PC120 C4(PS=0) /C12(PS=1) * * * PC44/ Setting Palette Data : PC124 C4(PS=0) /C12(PS=1) RE0 Setting Instruction Table 0 1 1 0 0 1 1 1 1 0 1 0 1 1 0 0/1 0/1 0/1 1 1 1 1 TST0 RE2 RE1 NOTE1) * : Don't care. NOTE2) [NH] (N=0-F) : Register Address NOTE3) Any nonexistent instruction code is prohibited. NOTE4) Dual instructions except for "EVR Control" are already effective when either upper byte or lower byte is set. NOTE5) "EVR Control" instruction is finally effective when both upper and lower bytes are set. Send upper byte first, next lower byte. - 56 - Ver.2003-10-14 NJU6825 (13-6) Instruction Table 4 Instructions/ Register Address [NH] Palette C5/C13 (Lower) [0H] Palette C5/C13 (Upper) [1H] Palette C6/C14 (Lower) [2H] 15 Palette C6/C14 (Upper) [3H] Palette C7/C15 (Lower) [4H] Palette C7/C15 (Upper) [5H] 16 Initial COM [6H] Duty-1 /Display Clock ON/OFF [7H] Display Mode Control [8H] Bus Length [9H] EVR Control (Lower) [AH] 20 EVR Control (Upper) [BH] 21 Frequency Control [DH] Discharge ON/OFF [EH] Register Address [CH] 0 1 1 0 1 0 0 1 0 1 1 * DV6 DV5 DV4 Setting EVR Value (Upper Bit) (RE2, RE1, RE0)=(1, 0, 0) Code (80 series MPU I/F) Code D7 0 D6 0 D5 0 D4 0 D3 D2 D1 D0 Functions CSb 0 RS 1 RDb WRb RE2 RE1 RE0 1 0 1 0 0 PC53/ PC52/ PC51/ PC50/ Setting Palette Data : PC133 PC132 PC131 PC130 C5(PS=0) /C13(PS=1) * * * PC54/ Setting Palette Data : PC134 C5(PS=0) /C13(PS=1) 0 1 1 0 1 0 0 0 0 0 1 0 1 1 0 1 0 0 0 0 1 0 PC63/P PC62/ PC61/ PC60/ Setting Palette Data : C143 PC142 PC141 PC140 C6(PS=0) /C14(PS=1) * * * PC64/ Setting Palette Data : PC144 C6(PS=0) /C14(PS=1) 0 1 1 0 1 0 0 0 0 1 1 0 1 1 0 1 0 0 0 1 0 0 PC73/ PC72/ PC71/ PC70/ Setting Palette Data : PC153 PC152 PC151 PC150 C7(PS=0) /C15(PS=1) * * * PC74/ Setting Palette Data : PC154 C7(PS=0) /C15(PS=1) SC0 Setting start COM for scanning 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 1 0 0 0 1 1 0 SC3 SC2 SC1 17 18 0 0 1 1 1 1 0 0 1 1 0 0 0 0 0 1 1 0 1 0 1 0 * * DSE SON SON : Display Clock ON/OFF DSE : Duty-1 ON/OFF PWM : Variable/Fixed Grayscale Mode PWM C256 FDC1 FDC2 C256 : 256-color Mode ON/OFF. 19 0 1 1 0 1 0 0 1 0 0 1 HSW ABS CKS FDC HSW ABS WLS CKS WLS : Boost clock : High Speed Writing : Bit Assignment : Oscillator Set : 8-/16-bit Bus Length 0 1 1 0 1 0 0 1 0 1 0 DV3 DV2 DV1 DV0 Setting EVR Value (Lower Bit) 0 1 1 0 1 0 0 1 1 0 1 * RF2 RF1 RF0 Adjusting Oscillation Frequency 22 0 1 1 0 1 0 0 1 1 1 0 * * * DIS Discharge ON/OFF Setting Register Address Reading Instruction 23 0 1 1 0 1 0 0 1 1 0 0 Register Address 24 Register Read 14 Instruction Table Select [FH] 0 0 1 1 0 1 1 0 0/1 0/1 0/1 0/1 0/1 0/1 1 1 1 1 Read Data TST0 RE2 RE1 RE0 Setting Instruction Table Select NOTE1) * : Don't care. NOTE2) [NH] (N=0-F) : Register Address NOTE3) Any nonexistent instruction code is prohibited. NOTE4) Dual instructions except for "EVR Control" are already effective when either upper byte or lower byte is set. NOTE5) "EVR Control" instruction is finally effective when both upper and lower bytes are set. Send upper byte first, next lower byte. Ver.2003-10-14 - 57 - NJU6825 (13-7) Instruction Table 5 Instructions/ Register Address [NH] Window End Column Address (Lower) [0H] 25 Window End Column Address (Upper) [1H] Window End Row Address (Lower) [2H] 26 Window End Row Address (Upper) [3H] Initial Line-reverse Address (Lower) [4H] 27 Initial Line-reverse Address (Upper) [5H] Last Line-reverse Address (Lower) [6H] 28 Last Line-reverse Address (Upper) [7H] 29 Line Reverse ON/OFF [8H] 0 [9H] 31 PWM Control [AH] Instruction Table Select [FH] 0 1 1 0 1 0 1 1 0 1 0 PWM PWM PWM PWM Setting PWM Mode S A B C TST0 RE2 RE1 RE0 Setting Instruction Table 0 1 1 0 1 0 1 0 1 1 1 LE7 LE6 LE5 LE4 Setting End Line for Line-reverse Display BT : Blink Set LREV : Line-reverse ON/OFF 0 1 1 0 1 0 1 0 1 0 1 LS7 LS6 LS5 LS4 Setting Start Line for Line-reverse Display Setting End Line for Line-reverse Display 0 1 1 0 1 0 1 0 0 1 1 EY7 EY6 EY5 EY4 Setting Row Address for end point Setting Start Line for Line-reverse Display 0 1 1 0 1 0 1 0 0 0 1 EX7 EX6 EX5 EX4 Setting Column Address for end point Setting Row Address for end point (RE2, RE1, RE0)=(1, 0, 1) Code (80 series MPU I/F) CSb 0 RS 1 RDb WRb RE2 RE1 RE0 1 0 1 0 1 D7 0 D6 0 D5 0 Code D4 0 D3 D2 D1 D0 Functions Setting Column Address for end point EX3 EX2 EX1 EX0 0 1 1 0 1 0 1 0 0 1 0 EY3 EY2 EY1 EY0 0 1 1 0 1 0 1 0 1 0 0 LS3 LS2 LS1 LS0 0 1 1 0 1 0 1 0 1 1 0 LE3 LE2 LE1 LE0 0 1 1 0 1 0 1 1 0 0 0 * * BT LREV Upper/Lower 30 Palette Select 1 1 0 1 0 1 1 0 0 1 * * * PS PS : Upper/Lower Palette Register 14 0 1 1 0 0/1 0/1 0/1 1 1 1 1 NOTE1) * : Don't care. NOTE2) [NH] (N=0-F) : Register Address NOTE3) Any nonexistent instruction code is prohibited. NOTE4) Dual instructions except for "EVR Control" are already effective when either upper byte or lower byte is set. NOTE5) "EVR Control" instruction is finally effective when both upper and lower bytes are set. Send upper byte first, next lower byte. - 58 - Ver.2003-10-14 NJU6825 (14) INSTRUCTION DESCRIPTIONS This chapter provides detailed descriptions about each instruction. These descriptions are written with the assumption that 80-series MPU is used. When using 68-series MPU, the polarities of the E and R/W signals differ from those of the RDb and WRb signals. (14-1) Display Data Write The "Display Data Write" instruction writes display data on a specified DDRAM address. CSb 0 RS 0 RDb 1 WRb 0 RE2 0/1 RE1 0/1 RE0 0/1 D7 D6 D5 D4 D3 Display Data D2 D1 D0 (14-2) Display Data Read The "Display Data Read" instruction reads out display data from a specified DDRAM address. One dummy read is necessary right after DDRAM address setting. CSb 0 RS 0 RDb 0 WRb 1 RE2 0/1 RE1 0/1 RE0 0/1 D7 D6 D5 D4 D3 Display Data D2 D1 D0 (14-3) Column Address The "Column Address" instruction specifies the column address of the start point. The setting order is lower byte first, then upper byte. CSb 0 RS 1 RDb 1 WRb 0 RE2 0 RE1 0 RE0 0 D7 0 D6 0 D5 D4 D3 D2 D1 D0 0 0 AX3 AX2 AX1 AX0 (Default: AX3-AX0=0H / Register Address: 0H) D5 D4 D3 D2 D1 D0 0 1 AX7 AX6 AX5 AX4 (Default: AX7-AX4=0H / Register Address: 1H) CSb 0 RS 1 RDb 1 WRb 0 RE2 0 RE1 0 RE0 0 D7 0 D6 0 (14-4) Row Address The "Row Address" instruction specifies the row address of the start point. Available setting range is from (00H) to (A1H), and outside this range is not allowed. The setting order is lower byte first, then upper byte. CSb 0 RS 1 RDb 1 WRb 0 RE2 0 RE1 0 RE0 0 D7 0 D6 0 D5 D4 D3 D2 D1 D0 1 0 AY3 AY2 AY1 AY0 (Default: AY3-AY0=0H / Register Address: 2H) D5 D4 D3 D2 D1 D0 1 1 AY7 AY6 AY5 AY4 (Default: AY7-AY4=0H / Register Address: 3H) CSb 0 RS 1 RDb 1 WRb 0 RE2 0 RE1 0 RE0 0 D7 0 D6 0 (14-5) Initial Display Line This instruction sets the row address, which corresponds to an initial COM and is normally positioned on top of a screen in full display. For more information, refer to "(14-16) Initial COM". The setting order is lower byte first, then upper byte. CSb 0 RS 1 RDb 1 WRb 0 RE2 0 RE1 0 RE0 0 D7 0 D6 1 D5 D4 D3 D2 D1 D0 0 0 LA3 LA2 LA1 LA0 (Default: LA3-LA0=0H / Register Address: 4H) D5 D4 D3 D2 D1 D0 0 1 LA7 LA6 LA5 LA4 (Default: LA7-LA4=0H / Register Address: 5H) CSb 0 RS 1 RDb 1 WRb 0 RE2 0 RE1 0 RE0 0 D7 0 D6 1 Ver.2003-10-14 - 59 - NJU6825 Table 18 Initial Display Line Address LA7 LA6 LA5 LA4 LA3 0 0 0 0 0 0 0 0 0 0 : 1 0 1 0 0 0 0 1 LA2 0 0 LA1 0 0 LA0 0 1 Row Address 0 1 : 161 (14-6) N-line Inversion The number of N line is selected in between "2" and "162". When the N-line inversion is enabled by setting "1" at the D2 (NLIN) bit of the "Display Control (2)" instruction, the FR toggles once every N lines. When the N-line inversion is disabled by setting "0" at this bit, the FR toggles by the frame. CSb 0 RS 1 RDb 1 WRb 0 RE2 0 RE1 0 RE0 0 D7 0 D6 1 D5 D4 D3 D2 D1 D0 1 0 N3 N2 N1 N0 (Default: N3-N0=0H / Register Address: 6H) D5 D4 D3 D2 D1 D0 1 1 N7 N6 N5 N4 (Default: N7-N4=0H / Register Address: 7H) CSb 0 RS 1 RDb 1 WRb 0 RE2 0 RE1 0 RE0 0 D7 0 D6 1 Table 19 N-line Inversion N7 N6 N5 0 0 0 0 0 0 N4 0 0 : : : N3 0 0 N2 0 0 N1 0 0 N0 0 1 1 NOTE1) N Line=(N Value)+1 0 1 0 0 0 0 1 N Line Inhibited 2 : : : 162 N-line inversion OFF 1st line 2nd line 3rd line 162nd line rd 1st line 163 line CL FLM FR N-line inversion ON N-line Inversion 1 line st 2nd line 3 line rd N line 1st line 2nd line CL FR Fig 18 N-line Inversion Timing (1/163 Duty) - 60 - Ver.2003-10-14 NJU6825 (14-7) Display Control (1) The "Display Control (1)" instruction controls display conditions. CSb 0 RS 1 RDb 1 WRb 0 RE2 0 RE1 0 RE0 0 D1 D0 ALL ON 1 0 0 0 SHIFT MON ON /OFF (Default: [SHIFT,MON,ALLON,ON/OFF]=0H / Register Address: 8H) D7 D6 D5 D4 D3 D2 D0 (ON/OFF) ON/OFF=0 ON/OFF=1 : Display OFF (All COM/SEG fixed at VSSH level) : Display ON D1 (ALLON) This bit forcibly turns on all pixels regardless of display data. This bit has a priority over the "REV" bit of the "Display Control (2)" instruction. ALLON=0 ALLON=1 D2 (MON) MON=0 MON=1 D3 (SHIFT) SHIFT=0 SHIFT=1 : Normal : All pixels ON : Grayscale Mode (Variable 16-grayscale, Variable 8-grayscale or Fixed 8-grayscale Mode) : B&W Mode : COM0 COM161 : COM0 COM161 Ver.2003-10-14 - 61 - NJU6825 (14-8) Display Control (2) The "Display Control (2)" instruction controls display conditions. CSb 0 RS 1 RDb 1 WRb 0 RE2 0 RE1 0 RE0 0 D7 D6 D5 D4 D3 D2 D1 D0 1 0 0 1 REV NLIN SWAP REF (Default: [REV,NLIN,SWAP,REF]=0H / Register Address: 9H) D0 (REF) This bit controls the DDRAM access direction which reverses the segment direction for reducing the restrictions on the IC position of an LCD module. For more information, refer to "(17) SWAP FUNCTION". D1 (SWAP) This bit swaps palettes Aj and palettes Cj (j=0-15). This function reduces the restrictions on the IC position of an LCD module. Refer to "(16) SWAP FUNCTION". SWAP=0 SWAP=1 : SWAP OFF : SWAP ON D2 (NLIN) This bit enables the N-line inversion. NLIN=0 NLIN=1 : N-line Inversion OFF : N-line Inversion ON (FR toggles by the frame.) (FR toggles once every N lines.) D3 (REV) This bit enables the reverse display function that reverses the polarities of all display data without changing the DDRAM. REV=0 REV=1 : Reverse Display OFF : Reverse Display ON (Normal) Table 20 Reverse Display ON/OFF REV Display DDRAM Data Display Data 0 0 0 Normal 1 1 0 1 1 Reverse 1 0 - 62 - Ver.2003-10-14 NJU6825 (14-9) Increment Control The "AIM", "AYI" and "AXI" bits set an auto-increment operation to the column address and row address individually. Once this mode is set up, the column address, row address or both are automatically counted up, whenever the DDRAM is accessed. The "WIN" bits enables/disables the window area access. CSb 0 RS 1 RDb 1 WRb 0 RE2 0 RE1 0 RE0 0 D7 D6 D5 D4 D3 D2 D1 D0 1 0 1 0 WIN AIM AYI AXI (Default: [WIN,AIM,AYI,AXI]=0H / Register Address: AH) D2 (AIM) Table 21 Read-modify-write ON/OFF AIM Increment Mode 0 1 Read-modify-write OFF Read-modify-write ON NOTE 1 2 NOTE1) Increment in writing and reading display data NOTE2) Increment in writing display data only D1, D0 (AYI, AXI) Table 22 AYI 0 0 1 1 Column/Row Increment AXI Column/Row Increment 0 Non Increment 1 Column Address Increment 0 Row Address Increment 1 Column & Row Addresses Increment NOTE 1 2 3 4 NOTE1) Non increment. The "AIM" bit is disabled. NOTE2) Increment operation of column address. The "AIM" bit is enabled. 00H MAX NOTE3) Row address increment. The "AIM" bit is enabled. 00H MAX NOTE4) Column & row addresses increment. The "AIM" bit is enabled. 00H MAX 00H Row Address MAX Column Address D3 (WIN) The window access should be enabled (WIN=1) in combination with the auto-increment operation (AXI=1, AYI=1). The typical sequence of the window area setting is discussed in "(4-2) Window Area for DDRAM Access". WIN=0 WIN=1 : Window Area Access OFF (Normal DDRAM Access) : Window Area Access ON Start Address End Address Start Address End Address Column Address Row Address Ver.2003-10-14 - 63 - NJU6825 (14-10) Power Control CSb 0 RS 1 RDb WRb RE2 RE1 RE0 1 0 0 0 0 D7 1 D6 0 D5 1 D4 1 D3 AMPON D2 HALT D1 DCON D0 ACL (Default: [AMPON,HALT,DCON,ACL]=0H / Register Address: BH) D0 (ACL) This bit initializes the internal LCD power supply. ACL=0 ACL=1 : Initialization OFF (Normal) : Initialization ON NOTE) During the initialization, "1" is read out as the status of the "ACL" bit by the "Register Read" instruction. After the initialization, it is "0". As the CLK triggers the initialization, the "wait time" at least equivalent to 2 cycles of the CLK is required for the next instruction. D1 (DCON) The "DCON" bit activates the voltage booster. DCON=0 DCON=1 : Voltage Booster OFF : Voltage Booster ON D2 (HALT) The "HALT" bit enables the power save mode. During the power save, operating current is down to the stand-by level. The internal state of the LSI in the power save mode is listed below. HALT=0 HALT=1 : Power Save OFF (Normal) : Power Save ON Internal State in Power Save Mode (HALT="1") - Internal oscillator and internal LCD power supply are halted. - All segment and common drivers are fixed at VSSH level. - External clock to the OSC1 cannot be accepted. - Display data in the DDRAM is being maintained. - Data in the instruction registers are being maintained. - VLCD, V1, V2, V3 and V4 are in high impedance. NOTE) In the power save ON sequence, execute the "Display OFF" prior to the "Power Save ON". In the power save OFF sequence, execute the "Power save OFF" prior to the "Display ON". If the "Power Save ON/OFF" instruction is executed during the "Display ON", unexpected pixels may be turned on instantly. D3 (AMPON) The "AMPON" bit activates the voltage converter which includes the reference voltage generator, the voltage regulator and the LCD bias generator. AMPON=0 AMPON=1 : Voltage Converter OFF : Voltage Converter ON - 64 - Ver.2003-10-14 NJU6825 (14-11) Duty Cycle Ratio The "Duty Cycle Ratio" instruction selects LCD duty cycle ratio, and is used to carry out the partial display in combination with other instructions such as the "Boost Level", the "LCD Bias Ratio" and the "EVR Control". CSb 0 RS 1 RDb 1 WRb 0 RE2 0 RE1 0 RE0 0 D7 1 D6 1 D5 D4 D3 D2 D1 D0 0 0 DS3 DS2 DS1 DS0 (Default: DS3-DS0=0H / Register Address: CH) # of Commons 162 commons 160 commons 144 commons 132 commons 128 commons 112 commons 96 commons 80 commons 72 commons 64 commons 56 commons 48 commons 40 commons 32 commons 24 commons 16 commons Table 23 DS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Duty Cycle Ratio DS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 DS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 DS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Duty Cycle Ratio DSE=0 DES=1 1/163 1/162 1/161 1/160 1/145 1/144 1/133 1/132 1/129 1/128 1/113 1/112 1/97 1/96 1/81 1/80 1/73 1/72 1/65 1/64 1/57 1/56 1/49 1/48 1/41 1/40 1/33 1/32 1/25 1/24 1/17 1/16 NOTE) Duty cycle ratio is subtracted by 1 (Duty-1) from the original duty cycle ratio by setting "1" at the D1 (DSE) bit of the "Duty-1 ON/OFF" instruction. Refer to "(14-17) Duty-1 /Display Clock ON/OFF". (14-12) Boost Level The "Boost Level" selects the multiple of the voltage booster. CSb 0 RS 1 RDb 1 WRb 0 RE2 0 RE1 0 RE0 0 D7 1 D6 1 D5 D4 D3 D2 D1 D0 0 1 * VU2 VU1 VU0 (Default:VU2-VU0=0H / Register Address: DH) D2, D1, D0 (VU2, VU1, VU0) Table 24 Boost Level VU2 VU1 VU0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Boost Level 1 time (No boost) 2 times 3 times 4 times 5 times 6 times 7 times Inhibited . Ver.2003-10-14 - 65 - NJU6825 (14-13) LCD Bias Ratio The "LCD bias ratio" selects LCD bias ratio. CSb 0 RS 1 RDb 1 WRb 0 RE2 0 RE1 0 RE0 0 D7 1 D6 1 D5 D4 D3 D2 D1 D0 1 0 * B2 B1 B0 (Default: B2-B0=0H / Register Address: EH) Table 25 LCD Bias Ratio B2 B1 B0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 LCD Bias Ratio 1/9 1/8 1/7 1/6 1/5 1/10 1/11 1/12 (14-14) Instruction Table Select This instruction specifies an instruction table, and should be executed prior to other instructions. CSb 0 RS 1 RDb 1 WRb 0 RE2 0/1 RE1 0/1 RE0 0/1 D7 1 D6 D5 D4 D3 D2 D1 D0 1 1 1 TST0 RE2 RE1 RE0 (Default: TST0, RE2-RE0=0H / Register Address: FH) Table 26 Instruction Table Select RE2 RE1 RE0 Instructions 0 0 0 Instruction Table (0) 0 0 1 Instruction Table (1) 0 1 0 Instruction Table (2) 0 1 1 Instruction Table (3) 1 0 0 Instruction Table (4) 1 0 1 Instruction Table (5) NOTE) "TST0" bit must be "0". This is used for maker tests only. - 66 - Ver.2003-10-14 NJU6825 (14-15) Palette A / B / C Palette A0 (PS=0) / Palette A8 (PS=1) CSb RS RDb WRb RE2 RE1 0 1 1 0 0 0 RE0 1 D7 0 D6 0 D5 0 D4 0 D3 D2 D1 D0 PA03/ PA02/ PA01/ PA00/ PA83 PA82 PA81 PA80 (Register Address: 0H) CSb 0 RS 1 RDb 1 WRb 0 RE2 0 RE1 0 RE0 1 D7 0 D6 0 D5 0 D4 1 D3 * D0 PA04/ * * PA84 (Register Address: 1H) D2 D1 Palette A1 (PS=0) / Palette A9 (PS=1) CSb RS RDb WRb RE2 RE1 0 1 1 0 0 0 RE0 1 D7 0 D6 0 D5 1 D4 0 D3 D2 D1 D0 PA13/ PA12/ PA11/ PA10/ PA93 PA92 PA91 PA90 (Register Address: 2H) D3 * D0 PA14/ * * PA94 (Register Address: 3H) D2 D1 CSb 0 RS 1 RDb 1 WRb 0 RE2 0 RE1 0 RE0 1 D7 0 D6 0 D5 1 D4 1 Palette A2 (PS=0) / Palette A10 (PS=1) CSb RS RDb WRb RE2 RE1 0 1 1 0 0 0 RE0 1 D7 0 D6 1 D5 0 D4 0 D3 D2 D1 D0 PA23/ PA22/ PA21/ PA20/ PA103 PA102 PA101 PA100 (Register Address: 4H) D3 * D0 PA24/ * * PA104 (Register Address: 5H) D2 D1 CSb 0 RS 1 RDb 1 WRb 0 RE2 0 RE1 0 RE0 1 D7 0 D6 1 D5 0 D4 1 Palette A3 (PS=0) / Palette A11 (PS=1) CSb RS RDb WRb RE2 RE1 0 1 1 0 0 0 RE0 1 D7 0 D6 1 D5 1 D4 0 D3 D2 D1 D0 PA33/ PA32/ PA31/ PA30/ PA113 PA112 PA111 PA110 (Register Address: 6H) D3 * D0 PA34/ * * PA114 (Register Address: 7H) D2 D1 CSb 0 RS 1 RDb 1 WRb 0 RE2 0 RE1 0 RE0 1 D7 0 D6 1 D5 1 D4 1 Palette A4 (PS=0) / Palette A12 (PS=1) CSb RS RDb WRb RE2 RE1 0 1 1 0 0 0 RE0 1 D7 1 D6 0 D5 0 D4 0 D3 D2 D1 D0 PA43/ PA42/ PA41/ PA40/ PA123 PA122 PA121 PA120 (Register Address: 8H) D3 * D0 PA44/ * * PA124 (Register Address: 9H) D2 D1 CSb 0 RS 1 RDb 1 WRb 0 RE2 0 RE1 0 RE0 1 D7 1 D6 0 D5 0 D4 1 NOTE) Refer to the tables in "(6) GRAYSCALE PALETTE" for default setting. Ver.2003-10-14 - 67 - NJU6825 Palette A5 (PS=0) / Palette A13 (PS=1) CSb RS RDb WRb RE2 RE1 0 1 1 0 0 0 RE0 1 D7 1 D6 0 D5 1 D4 0 D3 D2 D1 D0 PA53/ PA52/ PA51/ PA50/ PA133 PA132 PA131 PA130 (Register Address: AH) D3 * D0 PA54/ * * PA134 (Register Address: BH) D2 D1 CSb 0 RS 1 RDb 1 WRb 0 RE2 0 RE1 0 RE0 1 D7 1 D6 0 D5 1 D4 1 Palette A6 (PS=0) / Palette A14 (PS=1) CSb RS RDb WRb RE2 RE1 0 1 1 0 0 0 RE0 1 D7 1 D6 1 D5 0 D4 0 D3 D2 D1 D0 PA63/ PA62/ PA61/ PA60/ PA143 PA142 PA141 PA140 (Register Address: CH) D3 * D0 PA64/ * * PA144 (Register Address: DH) D2 D1 CSb 0 RS 1 RDb 1 WRb 0 RE2 0 RE1 0 RE0 1 D7 1 D6 1 D5 0 D4 1 Palette A7 (PS=0) / Palette A15 (PS=1) CSb RS RDb WRb RE2 RE1 0 1 1 0 0 1 RE0 0 D7 0 D6 0 D5 0 D4 0 D3 D2 D1 D0 PA73/ PA72/ PA71/ PA70/ PA153 PA152 PA151 PA150 (Register Address: 0H) D3 * D0 PA74/ * * PA154 (Register Address: 1H) D2 D1 CSb 0 RS 1 RDb 1 WRb 0 RE2 0 RE1 1 RE0 0 D7 0 D6 0 D5 0 D4 1 NOTE) Refer to the tables in "(6) GRAYSCALE PALETTE" for default setting. - 68 - Ver.2003-10-14 NJU6825 Palette B0 (PS=0) / Palette B8 (PS=1) CSb RS RDb WRb RE2 RE1 0 1 1 0 0 1 RE0 0 D7 0 D6 0 D5 1 D4 0 D3 D2 D1 D0 PB03/ PB02/ PB01/ PB00/ PB83 PB82 PB81 PB80 (Register Address: 2H) D3 * D0 PB04/ * * PB84 (Register Address: 3H) D2 D1 CSb 0 RS 1 RDb 1 WRb 0 RE2 0 RE1 1 RE0 0 D7 0 D6 0 D5 1 D4 1 Palette B1 (PS=0) / Palette B9 (PS=1) CSb RS RDb WRb RE2 RE1 0 1 1 0 0 1 RE0 0 D7 0 D6 1 D5 0 D4 0 D3 D2 D1 D0 PB13/ PB12/ PB11/ PB10/ PB93 PB92 PB91 PB90 (Register Address: 4H) D3 * D0 PB14/ * * PB94 (Register Address: 5H) D2 D1 CSb 0 RS 1 RDb 1 WRb 0 RE2 0 RE1 1 RE0 0 D7 0 D6 1 D5 0 D4 1 Palette B2 (PS=0) / Palette B10 (PS=1) CSb RS RDb WRb RE2 RE1 0 1 1 0 0 1 RE0 0 D7 0 D6 1 D5 1 D4 0 D3 D2 D1 D0 PB23/ PB22/ PB21/ PB20/ PB103 PB102 PB101 PB100 (Register Address: 6H) D3 * D0 PB24/ * * PB104 (Register Address: 7H) D2 D1 CSb 0 RS 1 RDb 1 WRb 0 RE2 0 RE1 1 RE0 0 D7 0 D6 1 D5 1 D4 1 Palette B3 (PS=0) / Palette B11 (PS=1) CSb RS RDb WRb RE2 RE1 0 1 1 0 0 1 RE0 0 D7 1 D6 0 D5 0 D4 0 D3 D2 D1 D0 PB33/ PB32/ PB31/ PB30/ PB113 PB112 PB111 PB110 (Register Address: 8H) D3 * D0 PB34/ * * PB114 (Register Address: 9H) D2 D1 CSb 0 RS 1 RDb 1 WRb 0 RE2 0 RE1 1 RE0 0 D7 1 D6 0 D5 0 D4 1 Palette B4 (PS=0) / Palette B12 (PS=1) CSb RS RDb WRb RE2 RE1 0 1 1 0 0 1 RE0 0 D7 1 D6 0 D5 1 D4 0 D3 D2 D1 D0 PB43/ PB42/ PB41/ PB40/ PB123 PB122 PB121 PB120 (Register Address: AH) D3 * D0 PB44/ * * PB124 (Register Address: BH) D2 D1 CSb 0 NOTE) RS 1 RDb 1 WRb 0 RE2 0 RE1 1 RE0 0 D7 1 D6 0 D5 1 D4 1 Refer to the tables in "(6) GRAYSCALE PALETTE" for default setting. Ver.2003-10-14 - 69 - NJU6825 Palette B5 (PS=0) / Palette B13 (PS=1) CSb RS RDb WRb RE2 RE1 0 1 1 0 0 1 RE0 0 D7 1 D6 1 D5 0 D4 0 D3 D2 D1 D0 PB53/ PB52/ PB51/ PB50/ PB133 PB132 PB131 PB130 (Register Address: CH) D3 * D0 PB54/ * * PB134 (Register Address: DH) D2 D1 CSb 0 RS 1 RDb 1 WRb 0 RE2 0 RE1 1 RE0 0 D7 1 D6 1 D5 0 D4 1 Palette B6 (PS=0) / Palette B14 (PS=1) CSb RS RDb WRb RE2 RE1 0 1 1 0 0 1 RE0 1 D7 0 D6 0 D5 0 D4 0 D3 D2 D1 D0 PB63/ PB62/ PB61/ PB60/ PB143 PB142 PB141 PB140 (Register Address: 0H) D3 * D0 PB64/ * * PB144 (Register Address: 1H) D2 D1 CSb 0 RS 1 RDb 1 WRb 0 RE2 0 RE1 1 RE0 1 D7 0 D6 0 D5 0 D4 1 Palette B7 (PS=0) / Palette B15 (PS=1) CSb RS RDb WRb RE2 RE1 0 1 1 0 0 1 RE0 1 D7 0 D6 0 D5 1 D4 0 D3 D2 D1 D0 PB73/ PB72/ PB71/ PB70/ PB153 PB152 PB151 PB150 (Register Address: 2H) D3 * D0 PB74/ * * PB154 (Register Address: 3H) D2 D1 CSb 0 RS 1 RDb 1 WRb 0 RE2 0 RE1 1 RE0 1 D7 0 D6 0 D5 1 D4 1 NOTE) Refer to the tables in "(6) GRAYSCALE PALETTE" for default setting. - 70 - Ver.2003-10-14 NJU6825 Palette C0 (PS=0) / Palette C8 (PS=1) CSb RS RDb WRb RE2 RE1 0 1 1 0 0 1 RE0 1 D7 0 D6 1 D5 0 D4 0 D3 D2 D1 D0 PC03/ PC02/ PC01/ PC00/ PC83 PC82 PC81 PC80 (Register Address: 4H) D3 * D0 PC04/ * * PC84 (Register Address: 5H) D2 D1 CSb 0 RS 1 RDb 1 WRb 0 RE2 0 RE1 1 RE0 1 D7 0 D6 1 D5 0 D4 1 Palette C1 (PS=0) / Palette C9 (PS=1) CSb RS RDb WRb RE2 RE1 0 1 1 0 0 1 RE0 1 D7 0 D6 1 D5 1 D4 0 D3 D2 D1 D0 PC13/ PC12/ PC11/ PC10/ PC93 PC92 PC91 PC90 (Register Address: 6H) D3 * D0 PC14/ * * PC94 (Register Address: 7H) D2 D1 CSb 0 RS 1 RDb 1 WRb 0 RE2 0 RE1 1 RE0 1 D7 0 D6 1 D5 1 D4 1 Palette C2 (PS=0) / Palette C10 (PS=1) CSb RS RDb WRb RE2 RE1 0 1 1 0 0 1 RE0 1 D7 1 D6 0 D5 0 D4 0 D3 D2 D1 D0 PC23/ PC22/ PC21/ PC20/ PC103 PC102 PC101 PC100 (Register Address: 8H) D3 * D0 PC24/ * * PC104 (Register Address: 9H) D2 D1 CSb 0 RS 1 RDb 1 WRb 0 RE2 0 RE1 1 RE0 1 D7 1 D6 0 D5 0 D4 1 Palette C3 (PS=0) / Palette C11 (PS=1) CSb RS RDb WRb RE2 RE1 0 1 1 0 0 1 RE0 1 D7 1 D6 0 D5 1 D4 0 D3 D2 D1 D0 PC33/ PC32/ PC31/ PC30/ PC113 PC112 PC111 PC110 (Register Address: AH) D3 * D0 PC34/ * * PC114 (Register Address: BH) D2 D1 CSb 0 RS 1 RDb 1 WRb 0 RE2 0 RE1 1 RE0 1 D7 1 D6 0 D5 1 D4 1 Palette C4 (PS=0) / Palette C12 (PS=1) CSb RS RDb WRb RE2 RE1 0 1 1 0 0 1 RE0 1 D7 1 D6 1 D5 0 D4 0 D3 D2 D1 D0 PC43/ PC42/ PC41/ PC40/ PC123 PC122 PC121 PC120 (Register Address: CH) D3 * D0 PC44/ * * PC124 (Register Address: DH) D2 D1 CSb 0 RS 1 RDb 1 WRb 0 RE2 0 RE1 1 RE0 1 D7 1 D6 1 D5 0 D4 1 NOTE) Refer to the tables in "(6) GRAYSCALE PALETTE" for default setting. Ver.2003-10-14 - 71 - NJU6825 Palette C5 (PS=0) / Palette C13 (PS=1) CSb 0 RS 1 RDb 1 WRb 0 RE2 1 RE1 0 RE0 0 D7 0 D6 0 D5 0 D4 0 D3 D2 D1 D0 PC53/ PC52/ PC51/ PC50/ PC133 PC132 PC131 PC130 (Register Address: 0H) D3 * D0 PC54/ * * PC134 (Register Address: 1H) D2 D1 CSb 0 RS 1 RDb 1 WRb 0 RE2 1 RE1 0 RE0 0 D7 0 D6 0 D5 0 D4 1 Palette C6 (PS=0) / Palette C14 (PS=1) CSb RS RDb WRb RE2 RE1 0 1 1 0 1 0 RE0 0 D7 0 D6 0 D5 1 D4 0 D3 D2 D1 D0 PC63/ PC62/ PC61/ PC60/ PC143 PC142 PB141 PB140 (Register Address: 2H) D3 * D0 PC64/ * * PC144 (Register Address: 3H) D2 D1 CSb 0 RS 1 RDb 1 WRb 0 RE2 1 RE1 0 RE0 0 D7 0 D6 0 D5 1 D4 1 Palette C7 (PS=0) / Palette C15 (PS=1) CSb RS RDb WRb RE2 RE1 0 1 1 0 1 0 RE0 0 D7 0 D6 1 D5 0 D4 0 D3 D2 D1 D0 PC73/ PC72/ PC71/ PC70/ PC153 PC152 PC151 PC150 (Register Address: 4H) D3 * D0 PC74/ * * PC154 (Register Address: 5H) D2 D1 CSb 0 RS 1 RDb 1 WRb 0 RE2 1 RE1 0 RE0 0 D7 0 D6 1 D5 0 D4 1 NOTE) Refer to the tables in "(6) GRAYSCALE PALETTE" for default setting. - 72 - Ver.2003-10-14 NJU6825 (14-16) Initial COM The "Initial COM" instruction specifies the common driver for a scan start common. CSb 0 RS 1 Table 27 SC3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 RDb 1 WRb 0 RE2 1 RE1 0 RE0 0 D7 0 D6 1 D5 D4 D3 D2 D1 D0 1 0 SC3 SC2 SC1 SC0 (Default: SC3-SC0=0H / Register Address: 6H) Initial COM (SHIFT=1) COM161 COM160 COM152 COM146 COM144 COM136 COM128 COM120 COM112 COM104 COM96 COM88 COM39 COM31 COM23 COM15 Initial COM SC2 SC1 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 SC0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Initial COM (SHIFT=0) COM0 COM1 COM9 COM14 COM17 COM25 COM33 COM41 COM49 COM57 COM65 COM73 COM122 COM130 COM138 COM146 (14-17) Duty-1 /Display Clock ON/OFF This instruction controls ON (Duty-1) /OFF (Duty-0) and Display Clock ON/OFF. CSb 0 RS 1 RDb 1 WRb 0 RE2 1 RE1 0 RE0 0 D7 0 D6 1 D5 D4 D3 D2 D1 D0 1 1 * * DSE SON (Default: SON,DSE=0H / Register Address: 7H) D0 (SON) SON=0 SON=1 : CL, FLM, FR, and CLK are fixed at "L" level. : CL, FLM, FR, and CLK are enabled. D1 (DSE) The duty cycle ratio is subtracted by 1 (Duty-1) from the original duty cycle ratio by setting "1" at the "DSE" bit. DSE=0 DSE=1 : OFF : ON (Duty-0) (Duty-1) NOTE) For the last common timing at "DSE=0", all common drivers generate non-selective waveforms, and segment drivers generate the same waveforms as for the previous common timing. For instance, in 1/163 duty cycle, the segment rd nd waveforms for 163 common timing are the same as for 162 common timing (last line). (14-18) Display Mode Control The "Display Mode Control" instruction sets up display modes such as the variable or fixed grayscale mode and the variable 8- or 16-grayscale mode. The D2 (MON) bit of the "Display Control (1)" is used in combination. Refer to "(5) GRAY SCALE CONTROL CIRCUIT" and "(14-7) Display Control (1)." CSb 0 RS 1 RDb 1 WRb 0 RE2 1 RE1 0 RE0 0 D7 1 D6 D5 D4 D3 D2 D1 D0 0 0 0 PWM C256 FDC1 FDC2 (Default: PWM,C256=0H / Register Address: 8H) D3 (PWM) PWM=0 PWM=1 : Variable grayscale Mode (Variable 8-/16-grayscale Mode) : Fixed 8-grayscale Mode Ver.2003-10-14 - 73 - NJU6825 D2 (C256) C256=0 C256=1 : Variable 16-grayscale Mode at "PWM=0" (4096 colors) : Variable 8-grayscale Mode at "PWM=0" (256 colors) D1(FDC1), D0(FDC2) These bits are used to select clock multiply for voltage booster. FDC1 0 0 1 1 (14-19) Bus Length FDC2 0 1 0 1 Boost Clock x1 x2 x4 x1/2 This instruction selects 8- or 16-bit bus length, and sets oscillator configuration, ABS mode ON/OFF and high speed writing ON/OFF as well. CSb 0 RS 1 RDb 1 WRb 0 RE2 1 RE1 0 RE0 0 D7 D6 D5 D4 D3 D2 D1 D0 1 0 0 1 HSW ABS CKS WLS (Default: HSW,ABS,CKS,WLS=0H / Register Address: 9H) D0 (WLS) WLS=0: 8-bit Bus Length WLS=1: 16-bit Bus Length D1 (CKS) CKS =0: Internal Oscillator using an internal resistor CKS =1: External Clock, or Internal Oscillator using an external resistor NOTE) Refer to "(10) OSCILLATOR". D2 (ABS) ABS=0: ABS Mode OFF (Normal) ABS=1: ABS Mode ON D3 (HSW) HSW=0: High Speed Writing OFF (Normal) HSW=1: High Speed Writing ON (14-20) EVR Control The "EVR Control" instruction adjusts VLCD to optimize display contrast. This instruction is finally effective when both upper and lower bytes are transmitted in order to prevent high VLCD. The setting order is upper byte first, then lower byte. Refer to "(11-2-3) Electrical Variable Resistor (EVR)". CSb 0 RS 1 RDb 1 WRb 0 RE2 1 RE1 0 RE0 0 D7 1 D6 0 D5 D4 D3 D2 D1 D0 1 0 DV3 DV2 DV1 DV0 (Default: DV3-DV0=0H / Register Address: AH) D5 D4 D3 D2 D1 D0 1 1 * DV6 DV5 DV4 (Default: DV6-DV4=0H / Register Address: BH) CSb 0 RS 1 RDb 1 WRb 0 RE2 1 RE1 0 RE0 0 D7 1 D6 0 Table 28 EVR Control DV6 DV5 DV4 DV3 0 0 0 0 0 0 0 0 : : 1 1 1 1 DV2 0 0 DV1 0 0 DV0 0 1 1 1 1 VLCD Low : : : High - 74 - Ver.2003-10-14 NJU6825 Formula of VLCD VLCD [V] = 0.5x VREG + M (VREG - 0.5x VREG) / 127 VBA = VEE x 0.9 VREG = VREF x N VBA VREF VREG N M : Output of the reference voltage generator : Input of the voltage regulator : Output of the voltage regulator : Boost level : EVR Value (14-21) Frequency Control The "Frequency Control" instruction adjusts the frame frequency. CSb 0 RS 1 RDb 1 WRb 0 RE2 1 RE1 0 RE0 0 D7 1 D6 1 D5 D4 D3 D2 D1 D0 0 1 * Rf2 Rf1 Rf0 (Default: DV3-DV0=0H / Register Address: DH) Table 29 Rf 2 0 0 0 0 1 1 1 1 Frequency Control Rf 1 Rf 0 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 Feedback Resistor Value Reference Value 0.8 x Reference Value 0.9 x Reference Value 1.1 x Reference Value 1.2 x Reference Value Inhibited Inhibited Inhibited (14-22) Discharge ON/OFF Discharge circuit is used to discharge out of the stabilizing capacitors placed on the VLCD, V1, V2, V3,V4 and VOUT. Refer to "(11-4) Discharge Circuit". CSb 0 RS 1 RDb 1 WRb 0 RE2 1 RE1 0 RE0 0 D7 1 D6 D5 D4 D3 D2 D1 D0 1 1 0 * * * DIS (Default: DIS2,DIS1=0H / Register Address: EH) D0 (DIS) DIS=0 DIS=1 : Discharge OFF : Discharge ON (Discharge from VLCD, V1, V2, V3 and V4) NOTE) Resistance is 100K typical. Ver.2003-10-14 - 75 - NJU6825 (14-23) Register Address The "Register Address" instruction specifies a register address. CSb 0 RS 1 RDb 1 WRb 0 RE2 1 RE1 0 RE0 0 D7 1 D6 1 D5 D4 D3 D2 D1 D0 0 0 RA3 RA2 RA1 RA0 (Default: RA3-RA0=BH / Register Address: CH) (14-24) Register Read The "Register Read" instruction reads out instruction data from the register which address is specified by the "Register Address" instruction. CSb 0 RS 1 RDb 0 WRb 1 RE2 0/1 RE1 0/1 RE0 0/1 D7 * D6 * D5 * D4 * D3 D2 D1 D0 Internal register data (14-25) Window End Column Address The "Window End Column Address" instruction specifies the column address of the end point. Refer to "(4-2) Window Area for DDRAM Access". The setting order is lower byte first, then upper byte. CSb 0 RS 1 RDb 1 WRb 0 RE2 1 RE1 0 RE0 1 D7 0 D6 0 D5 D4 D3 D2 D1 D0 0 0 EX3 EX2 EX1 EX0 (Default: EX3-EX0=0H / Register Address: 0H) D5 D4 D3 D2 D1 D0 0 1 EX7 EX6 EX5 EX4 (Default: EX7-EX4=0H / Register Address: 1H) CSb 0 RS 1 RDb 1 WRb 0 RE2 1 RE1 0 RE0 1 D7 0 D6 0 (14-26) Window End Row Address The "Window End Row Address" instruction specifies the row address of the end point. Refer to "(4-2) Window Area for DDRAM Access". The setting order is lower byte first, then upper byte. CSb 0 RS 1 RDb 1 WRb 0 RE2 1 RE1 0 RE0 1 D7 0 D6 0 D5 D4 D3 D2 D1 D0 1 0 EY3 EY2 EY1 EY0 (Default: EY3-EY0=0H / Register Address: 2H) D5 D4 D3 D2 D1 D0 1 1 EY7 EY6 EY5 EY4 (Default: EY7-EY4=0H / Register Address: 3H) CSb 0 RS 1 RDb 1 WRb 0 RE2 1 RE1 0 RE0 1 D7 0 D6 0 (14-27) Initial Line-reverse Address The "Initial Line-reverse Address" instruction specifies the start line of the line-reverse display area. The setting order is lower byte first, then upper byte. CSb 0 RS 1 RDb 1 WRb 0 RE2 1 RE1 0 RE0 1 D7 0 D6 1 D5 D4 D3 D2 D1 D0 0 0 LS3 LS2 LS1 LS0 (Default: LS3-LS0=0H / Register Address: 4H) D5 D4 D3 D2 D1 D0 0 1 LS7 LS6 LS5 LS4 (Default: LS7-LS4=0H / Register Address: 5H) CSb 0 RS 1 RDb 1 WRb 0 RE2 1 RE1 0 RE0 1 D7 0 D6 1 - 76 - Ver.2003-10-14 NJU6825 (14-28) Last Line-reverse Address The "Last Line-reverse Address" instruction specifies the end line of the line-reverse display area. The setting order is lower byte first, then upper byte. CSb 0 RS 1 RDb 1 WRb 0 RE2 1 RE1 0 RE0 1 D7 0 D6 1 D5 D4 D3 D2 D1 D0 1 0 LE3 LE2 LE1 LE0 (Default: LE3-LE0=0H / Register Address: 6H) D5 D4 D3 D2 D1 D0 1 1 LE7 LE6 LE5 LE4 (Default: LE7-LE4=0H / Register Address: 7H) CSb 0 RS 1 RDb 1 WRb 0 RE2 1 RE1 0 RE0 1 D7 0 D6 1 (14-29) Line Reverse ON/OFF The "Line Reverse ON/OFF" instruction enables the line-reverse display, and blink function as well. Note that the line reverse display cannot be used for entire display area. In this case, use the reverse display function by the D3 (REV) bit of the "Display Control (2)" instruction. CSb 0 RS 1 RDb 1 WRb 0 RE2 1 RE1 0 RE0 1 D7 1 D6 0 D5 D4 D3 D2 D1 D0 0 0 * * BT LREV (Default: BT,LREV=0H / Register Address: 8H) D0 (LREV) LREV =0 LREV =1 D1 (BT) BT =0 BT =1 : Line Reverse OFF (Normal) : Line Reverse ON : No Blink : Blink once every 32 frames Fig 19 On-screen Image in Using Line-reverse Display and Blink Function Ver.2003-10-14 - 77 - NJU6825 (14-30) Upper/Lower Palette Select The "Upper/Lower Palette Select" instruction selects either upper or lower palette register. CSb 0 RS 1 RDb 1 WRb 0 RE2 1 RE1 0 RE0 1 D7 1 D6 0 D5 0 D4 D3 D2 D1 D0 1 * * * PS (Default: PS=0 / Register Address: 9H) D0 (PS) PS=0 PS=1 : Lower Palettes (PA00, PA01, PA02, PA03, ..., PC74) : Upper Palettes (PA80, PA81, PA82, PA83, ..., PC154) (14-31) PWM Control The "PWM control" instruction selects PWM type, as shown in Fig 20. CSb 0 RS 1 RDb 1 WRb 0 RE2 1 RE1 0 RE0 D3 D2 D1 D0 PWM PWM PWM PWM 1 1 0 1 0 S A B C (Default: PWMS,PWMA,PWMB,PWMC=0H / Register Address: AH) D7 D6 D5 D4 D3 (PWMS) PWMS=0 PWMS=1 : Type 1 : Type 2 D2 (PWMA), D1 (PWMB), D0 (PWMC) PWMZ=0 (Z=A, B and C): Type 1-O PWMZ=1 (Z=A, B and C): Type 1-E PWM Type 1 (PWMS=0) Odd Line CL VLCD V2 SEG VLCD V2 Even Line Type-0 Type-E PWM Type 2 (PWMS=1) CL SEG VLCD V2 Fig 20 PWM Control - 78 - Ver.2003-10-14 NJU6825 (15) PARTIAL DISPLAY FUNCTION The partial display function activates specified area on an LCD screen, or equivalently, common drivers are simply scanning this specified area. This function allows LCD modules to work in a minimum duty cycle ratio to minimize power consumption. The partial display function is carried out by the combination of the "Duty Cycle Ratio", "LCD Bias Ratio", "Boost Level" and "EVR Control" instructions. For more information, refer to "(14-11) Duty Cycle Ratio", "(14-12) Boost Level", "(14-13) LCD Bias Ratio" and "(14-20) EVR Control". Typical setting sequence is shown in "(18-4) Partial Display Sequence". NJRC LCD DRIVER Low Power and Low Voltage Normal Fig 21 LCD DRIVER Partial Display On-screen Image in Using Partial Display Function Ver.2003-10-14 - 79 - NJU6825 (16) SWAP FUNCTION The swap function switches the palettes Aj and the palettes Cj (j=0-15), and is controlled by the D1 (SWAP) bit of the "Display Control (2)" instruction. This function reduces the restrictions on the IC position of an LCD module. Fig 22 "Overview of Swap Function" illustrates general outlines of internal operations, and (16-1-1) through (16-1-4) show each configuration on a mode-by-mode basis. (SWAP, REF)=(0,0) - Default state LCD Panel 1RGB 1RGB 1RGB (SWAP, REF)=(0,1) - Swapping Palette A and Palette C - Reversing Column Address LCD Panel 1RGB SEGB127 SEGC127 SEGB0 SEGC0 (00H) (7FH) Grayscale Control Circuits MSB ABC Data Selected Palette LSB MSB ABC Data LSB Grayscale Control Circuits (7FH) MSB SEGB0 SEGC0 SEGA0 SEGA0 Segment Driver Segment Driver (00H) ABC Data (7FH) Selected Palette LSB MSB ABC Data (00H) SEGB127 SEGC127 LSB LSB LSB SEGA127 (00H) (7FH) LSB MSB Display Data in DDRAM MSB Data Data LSB Display Data in DDRAM MSB Data LSB MSB Display Data from MPU LSB MSB Data (00H) LSB MSB Data (7FH) Display Data from MPU MSB Data (00H) LSB MSB (SWAP, REF)=(1,0) - Swapping Palette A and Palette C LCD Panel 1RGB 1RGB (SWAP, REF)=(1,1) - Reversing Column Address LCD Panel 1RGB 1RGB SEGC127 SEGA127 Selected Palette LSB MSB Data Data (7FH) SEGA127 SEGB127 SEGC0 SEGA0 SEGB0 SEGA0 SEGB0 Grayscale Control Circuits (00H) (7FH) (7FH) SEGC0 Segment Driver Segment Driver ABC MSB Selected Palette LSB MSB ABC Data LSB Data Grayscale Control Circuits ABC MSB Data SEGA127 SEGB127 (00H) ABC Data LSB (00H) (7FH) LSB MSB (7FH) LSB (00H) LSB MSB Display Data in DDRAM MSB Data Data Display Data in DDRAM MSB Data Data SEGC127 LSB LSB Display Data from MPU MSB Data (00H) LSB MSB Data (7FH) LSB Display Data from MPU MSB Data (00H) LSB MSB Data (7FH) Fig 22 Overview of SWAP Function - 80 - Ver.2003-10-14 NJU6825 (16-1) Swap Function in Variable 16-grayscale Mode 16-bit Bus Length (REF, SWAP)=(0,0) or (1,1) SEGAi SEGBi SEGCi (i=0-127) 0/31 (Default) 7/31 (Default) 31/31 (Default) Grayscale Level Palette A0 Palette B3 Palette C15 Grayscale Palette 0 MSB 0 0 0 LSB 0 MSB 0 1 1 LSB 1 MSB 1 1 1 LSB Display Data in Grayscale Control Circuit 0 D15 ABS=1 D11 0 D14 D10 0 D13 D9 0 D12 D8 0 D10 D7 0 D9 D6 1 D8 D5 1 D7 D4 1 D4 D3 1 D3 D2 1 D2 D1 1 D1 D0 Display Data from MPU to LSI (REF, SWAP)=(0,1) or (1,0) SEGAi SEGBi SEGCi (i=0-127) 31/31 (Default) 7/31 (Default) 0/31 (Default) Grayscale Level Palette C15 Palette B3 Palette A0 Grayscale Palette 1 LSB 1 1 1 MSB 1 LSB 1 0 0 MSB 0 LSB 0 0 0 MSB Display Data in Grayscale Control Circuit | | 0 D15 ABS=1 D11 0 D14 D10 0 D13 D9 0 D12 D8 0 D10 D7 0 D9 D6 1 D8 D5 1 D7 D4 1 D4 D3 1 D3 D2 1 D2 D1 1 D1 D0 Display Data from MPU to LSI NOTE1) Without a special note on the left, the setting bit such as the ABS, HSW, and C256 are regarded as "0". Ver.2003-10-14 - 81 - NJU6825 8-bit Bus Length (REF, SWAP)=(0,0) or (1,1) SEGAi SEGBi SEGCi (i=0-127) 0/31 (Default) 7/31 (Default) 31/31 (Default) Grayscale Level Palette A0 Palette B3 Palette C15 Grayscale Palette 0 MSB 0 0 0 LSB 0 MSB 0 1 1 LSB 1 MSB 1 1 1 LSB Display Data in Grayscale Control Circuit 0 D7 ABS=1 HSW=1 D3 D7 0 D6 D2 D6 0 D5 D1 D5 0 D4 D0 D4 0 D2 D7 D3 0 D1 D6 D2 1 D0 D5 D1 1 D7 D4 D0 1 D4 D3 D7 1 D3 D2 D6 1 D2 D1 D5 1 D1 D0 D4 Display Data from MPU to LSI (REF, SWAP)=(0,1) or (1,0) SEGAi SEGBi SEGCi (i=0-127) 31/31 (Default) 7/31 (Default) 0/31 (Default) Grayscale Level Palette C15 Palette B3 Palette A0 Grayscale Palette 1 LSB 1 1 1 MSB 1 LSB 1 0 0 MSB 0 LSB 0 0 0 MSB Display Data in Grayscale Control Circuit | | 0 D7 ABS=1 HSW=1 D3 D7 0 D6 D2 D6 0 D5 D1 D5 0 D4 D0 D4 0 D2 D7 D3 0 D1 D6 D2 1 D0 D5 D1 1 D7 D4 D0 1 D4 D3 D7 1 D3 D2 D6 1 D2 D1 D5 1 D1 D0 D4 Display Data from MPU to LSI NOTE1) Without a special note on the left, the setting bit such as the ABS, HSW, and C256 are regarded as "0". - 82 - Ver.2003-10-14 NJU6825 (16-2) Swap Function in Variable 8-grayscale Mode 8-bit Bus Length (REF, SWAP)=(0,0) or (1,1) SEGAi SEGBi SEGCi (i=0-127) 3/31 (Default) 7/31 (Default) 31/31 (Default) Grayscale Level Palette A0 Palette B3 Palette C15 Grayscale Palette 0 MSB 0 0 * LSB 0 MSB 0 1 * LSB 1 MSB 1 * * LSB Display Data in Grayscale Control Circuit 0 D7 0 D6 0 D5 * * 0 D4 0 D3 1 D2 * * 1 D1 1 D0 * * * * Display Data from MPU to LSI (REF, SWAP)=(0,1) or (1,0) SEGAi SEGBi SEGCi (i=0-127) 31/31 (Default) 7/31 (Default) 3/31 (Default) Grayscale Level Palette C15 Palette B3 Palette A0 Grayscale Palette * LSB * 1 1 MSB * LSB 1 0 0 MSB * LSB 0 0 0 MSB Display Data in Grayscale Control Circuit | | 0 D7 0 D6 0 D5 * * 0 D4 0 D3 1 D2 * * 1 D1 1 D0 * * * * Display Data from MPU to LSI NOTE1) Without a special note on the left, the setting bit such as the ABS, HSW, and C256 are regarded as "0". Ver.2003-10-14 - 83 - NJU6825 (16-3) Swap Function in Fixed 8-grayscale Mode 16-bit Bus Length (REF, SWAP)=(0,0) or (1,1) SEGAi SEGBi SEGCi (i=0-127) 0/7 1/7 7/7 Grayscale Level - - - 0 MSB 0 0 0 LSB 0 MSB 0 1 1 LSB 1 MSB 1 1 1 LSB Display Data in Grayscale Control Circuit 0 D15 ABS=1 D11 0 D14 D10 0 D13 D9 0 D12 D8 0 D10 D7 0 D9 D6 1 D8 D5 1 D7 D4 1 D4 D3 1 D3 D2 1 D2 D1 1 D1 D0 Display Data from MPU to LSI (REF, SWAP)=(0,1) or (1,0) SEGAi SEGBi SEGCi (i=0-127) 7/7 1/7 0/7 Grayscale Level - - - 1 LSB 1 1 1 MSB 1 LSB 1 0 0 MSB 0 LSB 0 0 0 MSB Display Data in Grayscale Control Circuit | | 0 D15 ABS=1 D11 0 D14 D10 0 D13 D9 0 D12 D8 0 D10 D7 0 D9 D6 1 D8 D5 1 D7 D4 1 D4 D3 1 D3 D2 1 D2 D1 1 D1 D0 Display Data from MPU to LSI NOTE1) Without a special note on the left, the setting bit such as the ABS, HSW, and C256 are regarded as "0". NOTE2) The data indicated with a slash mark ( / ) is invalid. - 84 - Ver.2003-10-14 NJU6825 8-bit Bus Length (REF, SWAP)=(0,0) or (1,1) SEGAi SEGBi SEGCi (i=0-127) 0/7 1/7 7/7 Grayscale Level - - - 0 MSB 0 0 0 LSB 0 MSB 0 1 1 LSB 1 MSB 1 1 1 LSB Display Data in Grayscale Control Circuit 0 D7 ABS=1 HSW=1 C256=1 D3 D7 D7 0 D6 D2 D6 D6 0 D5 D1 D5 D5 0 D4 D0 D4 * 0 D2 D7 D3 D4 0 D1 D6 D2 D3 1 D0 D5 D1 D2 1 D7 D4 D0 * 1 D4 D3 D7 D1 1 D3 D2 D6 D0 1 D2 D1 D5 * 1 D1 D0 D4 * Display Data from MPU to LSI (REF, SWAP)=(0,1) or (1,0) SEGAi SEGBi SEGCi (i=0-127) 7/7 1/7 0/7 Grayscale Level - - - 1 LSB 1 1 1 MSB 1 LSB 1 0 0 MSB 0 LSB 0 0 0 MSB Display Data in Grayscale Control Circuit | | 0 D7 ABS=1 HSW=1 C256=1 D3 D7 D7 0 D6 D2 D6 D6 0 D5 D1 D5 D5 0 D4 D0 D4 * 0 D2 D7 D3 D4 0 D1 D6 D2 D3 1 D0 D5 D1 D2 1 D7 D4 D0 * 1 D4 D3 D7 D1 1 D3 D2 D6 D0 1 D2 D1 D5 * 1 D1 D0 D4 * Display Data from MPU to LSI NOTE1) Without a special note on the left, the setting bit such as the ABS, HSW, and C256 are regarded as "0". NOTE2) The data indicated with a slash mark ( / ) is invalid. Ver.2003-10-14 - 85 - NJU6825 (16-4) Swap Function in B&W Mode 16-bit Bus Length (REF, SWAP)=(0,0) or (1,1) SEGAi SEGBi SEGCi (i=0-127) 0/1 (OFF) 0/1 (OFF) 1/1 (ON) Grayscale Level - - - 0 MSB 0 0 0 LSB 0 MSB 0 1 1 LSB 1 MSB 1 1 1 LSB Display Data in Grayscale Control Circuit 0 D15 ABS=1 D11 0 D14 D10 0 D13 D9 0 D12 D8 0 D10 D7 0 D9 D6 1 D8 D5 1 D7 D4 1 D4 D3 1 D3 D2 1 D2 D1 1 D1 D0 Display Data from MPU to LSI (REF, SWAP)=(0,1) or (1,0) SEGAi SEGBi SEGCi (i=0-127) 1/1 (ON) 0/1 (OFF) 0/1 (OFF) Grayscale Level - - - 1 LSB 1 1 1 MSB 1 LSB 1 0 0 MSB 0 LSB 0 0 0 MSB Display Data in Grayscale Control Circuit | | 0 D15 ABS=1 D11 0 D14 D10 0 D13 D9 0 D12 D8 0 D10 D7 0 D9 D6 1 D8 D5 1 D7 D4 1 D4 D3 1 D3 D2 1 D2 D1 1 D1 D0 Display Data from MPU to LSI NOTE1) Without a special note on the left, the setting bit such as the ABS, HSW, and C256 are regarded as "0". NOTE2) The data indicated with a slash mark ( / ) is invalid. - 86 - Ver.2003-10-14 NJU6825 8-bit Bus Length SWAP=0 SEGAi SEGBi SEGCi (i=0-127) 0/1 (OFF) 0/1 (OFF) 1/1 (ON) Grayscale Level - - - 0 MSB 0 0 0 LSB 0 MSB 0 1 1 LSB 1 MSB 1 1 1 LSB Display Data in Grayscale Control Circuit 0 D7 ABS=1 HSW=1 C256=1 D3 D7 D7 0 D6 D2 D6 D6 0 D5 D1 D5 D5 0 D4 D0 D4 * 0 D2 D7 D3 D4 0 D1 D6 D2 D3 1 D0 D5 D1 D2 1 D7 D4 D0 * 1 D4 D3 D7 D1 1 D3 D2 D6 D0 1 D2 D1 D5 * 1 D1 D0 D4 * Display Data from MPU to LSI SWAP=1 SEGAi SEGBi SEGCi (i=0-127) 1/1 (ON) 0/1 (OFF) 0/1 (OFF) Grayscale Level - - - 1 LSB 1 1 1 MSB 1 LSB 1 0 0 MSB 0 LSB 0 0 0 MSB Display Data in Grayscale Control Circuit | | 0 D7 ABS=1 HSW=1 C256=1 D3 D7 D7 0 D6 D2 D6 D6 0 D5 D1 D5 D5 0 D4 D0 D4 * 0 D2 D7 D3 D4 0 D1 D6 D2 D3 1 D0 D5 D1 D2 1 D7 D4 D0 * 1 D4 D3 D7 D1 1 D3 D2 D6 D0 1 D2 D1 D5 * 1 D1 D0 D4 * Display Data from MPU to LSI NOTE1) Without a special note on the left, the setting bit such as the ABS, HSW, and C256 are regarded as "0". NOTE2) The data indicated with a slash mark ( / ) is invalid. (17) RELATION BETWEEN ROW ADDRESS AND COMMON DRIVER The relation between row address and common driver is changed by the D3 (SHIFT) bit of the "Display Control (1)" and the "Duty Cycle Ratio", "Initial Display Line" and "Initial COM" instructions. When the "Initial Display Line" is set to (LA7:LA0=00H: Address "0"), the row address corresponding to an initial COM is "0". However, if the "Initial Display Line" is other than "0", the row address is shifted from "0" by just that address. For instance, when the initial display line address is (LA7:LA0=05H: Address "5") and the initial COM is (SC3:SC0=1H), the row address on the initial COM is "5" and the initial COM is "COM1". (17-1) through (17-5) illustrate the examples of the relation between row address and common driver. Ver.2003-10-14 - 87 - NJU6825 (17-1) SHIFT=0, Initial Display Line "0", Duty Cycle Ratio "1/163" SC3 SC2 SC1 SC0 0000 0 SHIFT="0"(Common forward scan), DS3, 2, 1, 0="0000", LA7....LA0="00000000"(Initial display line 0) DSE="0" 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 161 0 153 148 145 137 129 121 113 105 97 89 1100 40 1101 32 1110 24 1111 16 COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 : COM23 COM24 COM25 COM26 COM27 COM28 COM29 COM30 COM31 COM32 COM33 COM34 COM35 COM36 COM37 COM38 COM39 COM40 COM41 COM42 COM43 COM44 COM45 COM46 COM47 COM48 COM49 COM50 COM51 COM52 COM53 COM54 COM55 COM56 COM57 COM58 COM59 COM60 COM61 COM62 COM63 COM64 COM65 COM66 COM67 COM68 COM69 COM70 COM71 COM72 COM73 COM74 COM75 COM76 COM77 COM78 : COM120 COM121 COM122 : COM128 COM129 COM130 : COM136 COM137 COM138 COM139 COM140 COM141 COM142 COM143 COM144 COM145 COM146 COM147 COM148 COM149 COM150 COM151 COM152 COM153 COM154 COM155 COM156 COM157 COM158 COM159 COM160 COM161 (163rd COM period) *2 161 0 161 0 161 0 161 0 161 0 161 0 161 0 161 0 161 0 161 0 161 0 161 0 161 0 161 0 161 161 160 161 152 161 147 161 144 161 136 161 128 161 120 161 112 161 104 161 96 161 88 161 39 161 31 161 23 161 15 161 Fig 23 Relation between Row address and Common Driver (1) NOTE1) DS: Duty Cycle Ratio / SC: Initial COM / LA: Initial Display Line Address rd nd NOTE2) Segment waveforms for 163 COM timing are the same as for 162 COM timing (Row address "A1H"). - 88 - Ver.2003-10-14 NJU6825 (17-2) SHIFT=1, Initial Display Line "0", Duty Cycle Ratio "1/163" SC3 SC2 SC1 SC0 0000 161 SHIFT="1"(Common backward scan), DS3, 2, 1, 0="0000", LA7....LA0="00000000"(Initial display line 0) DSE="0" 0011 0100 0001 0010 0101 0110 0111 1000 1001 1010 1011 160 152 146 144 136 128 120 112 104 96 88 1100 39 1101 31 1110 23 1111 15 COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23 COM24 COM25 : COM31 COM32 : COM39 COM40 : COM88 COM89 COM90 COM91 COM92 COM93 COM94 COM95 COM96 COM97 COM98 COM99 COM100 COM101 COM102 COM103 COM104 COM105 COM106 COM107 COM108 COM109 COM110 COM111 COM112 COM113 COM114 COM115 COM116 COM117 COM118 COM119 COM120 COM121 COM122 COM123 COM124 COM125 COM126 COM127 COM128 COM129 COM130 COM131 COM132 COM133 COM134 COM135 COM136 COM137 COM138 COM139 COM140 COM141 COM142 COM143 COM144 COM145 COM146 COM147 COM148 COM149 COM150 COM151 COM152 COM153 COM154 COM155 COM156 COM157 COM158 COM159 COM160 COM161 (163rd COM period) *2 0 161 0 161 0 161 0 161 0 161 0 161 0 161 0 161 0 161 0 161 0 161 0 161 0 161 0 161 0 161 0 161 161 153 161 147 161 145 161 137 161 129 161 121 161 113 161 105 161 97 161 89 161 40 161 32 161 24 161 16 161 Fig 24 Relation between Row address and Common Driver (2) NOTE1) DS: Duty Cycle Ratio / SC: Initial COM / LA: Initial Display Line Address rd nd NOTE2) Segment waveforms for 163 COM timing are the same as for 162 COM timing (Row address "A1H"). Ver.2003-10-14 - 89 - NJU6825 (17-3) SHIFT=0, Initial Display Line "0", Duty Cycle Ratio "1/16" SC3 COM0 COM1 COM2 : COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23 COM24 COM25 COM26 COM27 COM28 COM29 COM30 COM31 COM32 COM33 COM34 COM35 COM36 COM37 COM38 COM39 COM40 COM41 COM42 COM43 COM44 COM45 COM46 COM47 COM48 COM49 COM50 COM51 COM52 COM53 COM54 COM55 COM56 COM57 COM58 COM59 COM60 COM61 COM62 COM63 COM64 COM65 COM66 COM67 COM68 COM69 COM70 COM71 COM72 COM73 COM74 COM75 COM76 COM77 COM78 COM79 COM80 COM81 : COM88 : COM121 COM122 : COM130 COM131 COM132 COM133 COM134 COM135 COM136 COM137 COM138 : COM145 COM146 : COM153 : COM160 COM161 SC2 SC1 SC0 0000 0 SHIFT="0"(Common forward scan), DS3, 2, 1, 0="1111", LA7....LA0="00000000"(Initial display line 0) DSE="1" 0011 0100 0001 0010 0101 0110 0111 1000 1001 1010 0 1011 1100 1101 1110 1111 0 0 15 15 0 15 0 15 15 0 15 0 15 0 15 0 15 0 15 0 15 15 0 0 15 0 15 0 15 15 Fig 25 Relation between Row address and Common Driver (3) NOTE1) DS: Duty Cycle Ratio / SC: Initial COM / LA: Initial Display Line Address - 90 - Ver.2003-10-14 NJU6825 (17-4) SHIFT=0, Initial Display Line "5", Duty Cycle Ratio "1/163" SC3 SC2 SC1 SC0 0000 5 SHIFT="0"(Common forward scan), DS3, 2, 1, 0="0000", LA7....LA0="00000101"(Initial display line 5) DSE="0" 0011 0100 0001 0010 0101 0110 0111 1000 1001 1010 1011 4 5 158 153 150 142 134 126 118 110 102 94 1100 45 1101 37 1110 29 1111 21 COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23 COM24 COM25 COM26 COM27 COM28 : COM33 COM34 COM35 COM36 : COM41 COM42 COM43 COM44 : COM49 COM50 COM51 COM52 COM53 COM54 COM55 COM56 COM57 COM58 COM59 COM60 : COM65 COM66 COM67 COM68 COM69 COM70 COM71 COM72 COM73 : COM116 COM117 : COM122 COM123 COM124 COM125 COM126 COM127 COM128 COM129 COM130 COM131 COM132 COM133 COM134 COM135 COM136 COM137 COM138 COM139 COM140 COM141 COM142 COM143 COM144 COM145 COM146 : COM156 COM157 COM158 COM159 COM160 COM161 (163rd COM period) *1 161 0 5 161 0 161 0 5 5 161 0 5 161 0 5 161 0 5 161 0 5 161 0 5 1161 0 5 161 0 5 161 0 5 161 0 5 161 0 5 161 0 5 161 0 161 0 4 161 3 161 157 161 152 161 149 161 141 161 133 161 125 161 117 161 109 161 101 161 93 161 44 161 36 161 28 161 20 161 Fig 26 Relation between Row address and Common Driver (4) NOTE1) DS: Duty Cycle Ratio / SC: Initial COM / LA: Initial Display Line Address Ver.2003-10-14 - 91 - NJU6825 (17-5) SHIFT=0, Initial Display Line "0", Duty Cycle Ratio "1/162" SC3 COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 : COM23 COM24 COM25 COM26 COM27 COM28 COM29 COM30 COM31 COM32 COM33 COM34 COM35 COM36 COM37 COM38 COM39 COM40 COM41 COM42 COM43 COM44 COM45 COM46 COM47 COM48 COM49 COM50 COM51 COM52 COM53 COM54 COM55 COM56 COM57 COM58 COM59 COM60 COM61 COM62 COM63 COM64 COM65 COM66 COM67 COM68 COM69 COM70 COM71 COM72 COM73 COM74 COM75 COM76 COM77 COM78 : COM120 COM121 COM122 : COM128 COM129 COM130 : COM136 COM137 COM138 COM139 COM140 COM141 COM142 COM143 COM144 COM145 COM146 COM147 COM148 COM149 COM150 COM151 COM152 COM153 COM154 COM155 COM156 COM157 COM158 COM159 COM160 COM161 SC2 SC1 SC0 0000 0 SHIFT="0"(Common forward scan), DS3, 2, 1, 0="0000", LA7....LA0="00000000"(Initial display line 0) DSE="1" 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 161 0 153 148 145 137 129 121 113 105 97 1011 89 1100 40 1101 32 1110 24 1111 16 161 0 161 0 161 0 161 0 161 0 161 0 161 0 161 0 161 0 161 0 161 0 161 0 161 0 161 0 161 160 152 147 144 136 128 120 112 104 96 88 39 31 23 15 Fig 27 Relation between Row address and Common Driver (5) NOTE1) DS: Duty Cycle Ratio / SC: Initial COM / LA: Initial Display Line Address - 92 - Ver.2003-10-14 NJU6825 (18) TYPICAL INSTRUCTION SEQUENCES (18-1) Initialization Sequence in Using Internal LCD Power Supply Power ON (VDD, VEE) with RESb "L" WAIT (NOTE2) RESET WAIT (NOTE3) Display Setting INSTRUCTION TABLE SELECT Duty Cycle Ratio N-line Inversion (Lower) N-line Inversion (Upper) INSTRUCTION TABLE SELECT Display Mode Control Power Setting EVR Control (Upper) EVR Control (Lower) INSTRUCTION TABLE SELECT Boost Level LCD Bias Ratio Power Control WAIT (NOTE4) Power Control WAIT (NOTE5) END (NOTE1) -------------- Instruction Code -------------D7 1 1 0 0 1 1 D6 1 1 1 1 1 0 D5 1 0 1 1 1 0 D4 1 0 0 1 1 0 D3 0 1 0 * 0 1 D2 0 0 1 0 1 1 D1 0 0 1 0 0 * D0 0 1 0 --------- Setting (Example) --------- - Instruction Table Select (0,0,0) - 1/65 Duty - N=7 0 0 * - Instruction Table Select (1,0,0) - Fixed 8-grayscale Mode - 256-color Mode ON 1 1 1 1 1 1 0 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 0 1 * 1 0 0 * 0 1 1 0 1 0 0 0 1 0 0 1 1 1 - M=95 1 0 0 0 0 - Instruction Table Select (0,0,0) - 5-times Booster - 1/7 Bias - Voltage Booster ON 1 0 1 1 1 0 1 0 - Voltage Converter ON NOTE1) If different power sources are applied to the VDD and the VEE, turn on the VDD first. NOTE2) Wait until the VDD and VEE are stabilized. NOTE3) Wait 10 [us] or more. NOTE4) Wait until the VOUT is stabilized. NOTE5) Wait until the VLCD and V1-V4 are stabilized. Ver.2003-10-14 - 93 - NJU6825 (18-2) Initialization Sequence in Using External LCD Power Supply Power ON (VDD) with RESb "L" WAIT (NOTE1) RESET WAIT (NOTE2) External LCD Power Supply ON WAIT (NOTE3) Display Setting INSTRUCTION TABLE SELECT Duty Cycle Ratio N-line Inversion (Lower) N-line Inversion (Upper) INSTRUCTION TABLE SELECT Display Mode Control END -------------- Instruction Code -------------D7 1 1 0 0 1 1 D6 1 1 1 1 1 0 D5 1 0 1 1 1 0 D4 1 0 0 1 1 0 D3 0 1 0 * 0 1 D2 0 0 1 0 1 1 D1 0 0 1 0 0 * D0 0 1 0 --------- Setting (Example) --------- - Instruction Table Select (0,0,0) - 1/65 Duty - N=7 0 0 * - Instruction Table Select (1,0,0) - Fixed 8-grayscale Mode - 256-color Mode ON NOTE1) Wait until the VDD is stabilized. NOTE2) Wait 10 [us] or more. NOTE3) Wait until the external LCD power supply (VOUT, VLCD, V1-V4) are stabilized. - 94 - Ver.2003-10-14 NJU6825 (18-3) Display Data Write Sequence Optional Status INSTRUCTION TABLE SELECT Initial Display Line (Lower) Initial Display Line (Upper) Increment Control Column Address (Lower) Column Address (Upper) Row Address (Lower) Row Address (Upper) INSTRUCTION TABLE SELECT Window End Column Address (Lower) Window End Column Address (Upper) Window End Row Address (Lower) Window End Row Address (Upper) Display Data Write : : : : : : : Display Data Write INSTRUCTION TABLE SELECT Display Control (1) END -------------- Instruction Code -------------D7 1 0 0 1 0 0 0 0 1 0 0 0 0 0 D6 1 1 1 0 0 0 0 0 1 0 0 0 0 0 D5 1 0 0 1 0 0 1 1 1 0 0 1 1 0 D4 1 0 1 0 0 1 0 1 1 0 1 0 1 0 D3 0 0 * 1 0 0 0 0 0 0 0 0 0 0 D2 0 0 0 1 0 0 0 0 1 1 0 1 0 0 D1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 D0 0 0 -Initial Display Line (00)H 0 1 0 - Window Start Column Address (00)H 0 0 - Window Start Row Address (00)H 0 1 0 -Window End Column Address (04)H 0 0 - Window End Row Address (04)H 0 0 - Writing Display Data on the DDRAM for Checker Flag in B&W Mode (Example) 00H 00H Y 04H X 04H --------- Setting (Example) --------- - Instruction Table Select (0,0,0) - Window Area Access ON - Read-modify-write ON - Column & Row Increment - Instruction Table Select (1,0,1) 1 1 1 1 1 1 1 1 : : : : : : : : : : : : : : : : Repeating All "0" and All "1" Alternately : : : : : : : : : : : : : : : : 1 1 1 1 1 1 1 1 0 1 1 0 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 - Instruction Table Select (0,0,0) - Display ON Ver.2003-10-14 - 95 - NJU6825 (18-4) Partial Display Sequence Optional Status INSTRUCTION TABLE SELECT Display Control (1) Power Control Power Control WAIT (NOTE1) Display Setting Duty Cycle Ratio Initial Display Line (Lower) Initial Display Line (Upper) INSTRUCTION TABLE SELECT Initial COM Power Setting EVR Control (Upper) EVR Control (Lower) INSTRUCTION TABLE SELECT Boost Level LCD Bias Ratio Power Control WAIT (NOTE2) Power Control WAIT (NOTE3) Display Control (1) END -------------- Instruction Code -------------D7 1 1 1 1 D6 1 0 0 0 D5 1 0 1 1 D4 1 0 1 1 D3 0 0 0 0 D2 0 0 0 0 D1 0 0 1 0 D0 0 0 0 0 --------- Setting (Example) --------- - Instruction Table Select (0,0,0) - Display OFF - Voltage Converter OFF - Voltage Booster OFF 1 0 0 1 0 1 1 1 1 1 0 0 0 1 1 0 0 1 1 0 1 0 * 0 0 1 0 0 1 0 0 0 0 0 0 1 0 - 1/33 Duty - Initial Display Line (00)H 0 0 0 - Instruction Table Select (1,0,0) - Initial COM: COM0 1 1 1 1 1 1 0 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 0 1 * 1 0 * * 0 0 1 0 0 1 0 1 0 0 1 0 1 1 - M=60 0 0 0 0 0 - Instruction Table Select (0,0,0) - 3-times Booster - 1/5 Bias - Voltage Booster ON 1 0 1 1 1 0 1 0 - Voltage Converter ON 1 0 0 0 0 0 0 1 - Display ON NOTE1) Wait until the voltage booster is completely turned off. Make sure what is the wait time in the particular application. NOTE2) Wait until the VOUT is stabilized. NOTE3) Wait until the VLCD and V1-V4 are stabilized. - 96 - Ver.2003-10-14 NJU6825 (18-5) Power OFF Sequence Optional Status INSTRUCTION TABLE SELECT Display Control (1) Power Control Power Control Power Control INSTRUCTION TABLE SELECT Discharge ON/OFF WAIT (NOTE) Power OFF (VDD-VSS, VEE-VSSH) END NOTE) Wait until the Discharge is completed. -------------- Instruction Code -------------D7 1 1 1 1 1 1 1 D6 1 0 0 0 0 1 1 D5 1 0 1 1 1 1 1 D4 1 0 1 1 1 1 0 D3 0 0 0 0 0 0 * D2 0 0 0 0 1 1 * D1 0 0 1 0 0 0 1 D0 0 0 0 0 0 0 1 --------- Setting (Example) --------- - Instruction Table Select (0,0,0) - Display OFF - Voltage Converter OFF - Voltage Booster OFF - Power Save ON - Instruction Table Select (1,0,0) - Discharge ON Ver.2003-10-14 - 97 - NJU6825 ! ABSOLUTE MAXIMUM RATINGS PARAMETER Supply Voltage (1) Supply Voltage (2) Supply Voltage (3) Supply Voltage (4) Supply Voltage (5) Supply Voltage (6) Input Voltage Storage Temperature SYMBOL VDD VEE VOUT VREG VLCD V1, V2, V3, V4 VI Tstg CONDITION TERMINAL VDD VEE VOUT VREG VLCD V1, V2, V3, V4 *1 RATING -0.3 to +4.0 -0.3 to +4.0 -0.3 to +19.0 -0.3 to +19.0 -0.3 to +19.0 -0.3 to VLCD + 0.3 -0.3 to VDD + 0.3 -45 to +125 UNIT V V V V V V V C VSS=0V Ta = +25C NOTE1) D0 to D15, CSb, RS, RDb, WRb, OSC1, RESb, TEST1, and TEST2 NOTE2) To stabilize the LSI operation, place decoupling capacitors between VDD and VSS and between VEE and VSSH. ! RECOMMENDED OPERATING CONDITIONS PARAMETER Supply Voltage SYMBOL VDD1 VDD2 VEE VLCD VOUT VREG VREF Topr TERMINAL VDD VEE VLCD VOUT VREG VREF MIN 1.7 2.4 2.4 5 TYP MAX 3.3 3.3 3.3 18.0 18.0 VOUT x 0.9 3.3 85 UNIT V V V V V V V C NOTE 1 2 3 4 Operating Voltage Operating Temperature 2.1 -30 5 NOTE1) Applied to the condition when the reference voltage generator is not used. NOTE2) Applied to the condition when the reference voltage generator is used. NOTE3) Applied to the condition when the voltage booster is used. NOTE4) The following relation among the LCD bias voltages must be maintained. VSSH Ver.2003-10-14 NJU6825 ! DC CHARACTERISTICS VSS = 0V, VDD = +1.7 to +3.3V, Ta = -30 to +85C PARAMETER High level input voltage Low level input voltage High level output voltage Low level output voltage High level output voltage Low level output voltage Input leakage current Output leakage current Driver ON-resistance Stand-by current Internal oscillation Frequency External oscillation Frequency Voltage converter output voltage Supply current (1) Supply current (2) Supply current (3) Supply current (4) Supply current (5) Supply current (6) Supply current (7) Supply current (8) VBA Operating voltage VREG Operating voltage SYM BOL VIH VIL VOH1 VOL1 VOH2 VOL2 ILI ILO RON1 ISTB fOSC1 fOSC2 fOSC3 fr1 fr2 fr3 VOUT IDD1 IDD2 IDD3 IDD4 IDD5 IDD6 IDD7 IDD8 VBA VREG V2 V3 VD12 VD34 VD24 CONDITION MIN 0.8 VDD 0 VDD - 0.4 VDD - 0.4 -10 -10 TYP MAX VDD 0.2VDD 0.4 0.4 10 10 2 4 15 900 203 29.5 UNIT NOTE V V V V V V A A k A kHz *1 *1 *2 *2 *3 *3 *4 *5 *6 *7 *8 *9 *10 *11 *12 IOH = -0.4mA IOL = 0.4mA IOH = -0.1mA IOL = 0.1mA VI = VSS or VDD VI = VSS or VDD |VON| = 0.5V VLCD = 10V VLCD = 6V 1 2 625 141 20.5 763 172 25 750 185 27.2 CSb=VDD, Ta=25C VDD = 3V VDD = 3V Ta = 25C Rf=10k Rf=51k Rf=390k N-time booster (N=2 to 7) RL = 500k (VOUT - VSS) VDD = 2.5V, 7-time booster Whole ON pattern VDD = 2.5V, 7-time booster Checker pattern VDD = 3V, 6-time booster Whole ON pattern VDD = 3V, 6-time booster Checker pattern VDD = 3V, 5-time booster Whole ON pattern VDD = 3V, 5-time booster Checker pattern VDD = 3V, 4-time booster Whole ON pattern VDD = 3V, 4-time booster Checker pattern VEE = 2.4 to 3.3V VEE = 2.4 to 3.3V VREF = 0.9 x VEE N-time booster (N=2 to 7) kHz V (N x VEE) x 0.95 870 1060 760 930 520 650 360 450 (0.9 VEE) x 0.98 (VREF x N) 1300 1590 1140 1400 780 980 540 680 (0.9 VEE) x 1.02 (VREF x N) A *13 0.9 VEE (VREF x N) V V *14 *15 x 0.97 -100 -100 -30 -30 -30 x 1.03 +100 +100 +30 +30 +30 Output Voltage 0 0 0 0 0 mV *16 Ver.2003-10-14 - 99 - NJU6825 ! OSCILLATION FREQUENCY AND FRAME FREQUENCY PARAMETER SYMBOL Display mode Variable 8-/16-level Grayscale Mode Display duty cycle ratio (1/D) 1/163 to 1/97 1/81 to 1/57 1/49 to 1/33 1/25 to 1/17 NOTE fOSC / (62xD) fOSC / (14xD) fOSC / (2xD) fCK / (62xD) fCK / (14xD) fCK / (2xD) fOSC / (62xDx2) fOSC / (14xDx2) fOSC / (2xDx2) fCK / (62xDx2) fCK / (14xDx2) fCK / (2xDx2) fOSC / (62xDx4) fOSC / (62xDx8) fOSC / (14xDx4) fOSC / (14xDx8) fOSC / (2xDx4) fCK / (62xDx4) fCK / (14xDx4) fCK / (2xDx4) fOSC / (2xDx8) FLM fCK / (62xDx8) fCK / (14xDx8) fCK / (2xDx8) Internal clock fOSC Fixed 8-level Grayscale Mode B&W Mode Variable 8-/16-level Grayscale Mode External clock fCK Fixed 8-level Grayscale Mode B&W Mode - 100 - Ver.2003-10-14 NJU6825 NOTE1) NOTE2) NOTE3) NOTE4) NOTE5) NOTE6) D0-D15, CSb, RS, RDb, WRb, P/S, SEL68 and RESb D0-D15 CL, FLM, FR and CLK CSb, RS, SEL68, RDb, WRb, P/S, RESb and OSC1 D0-D15 in high impedance SEGA0-SEGA127, SEGB0-SEGB127, SEGC0-SEGC127 and COM0-COM161 This parameter defines the resistance between each COM/SEG and each LCD bias (VLCD, V1, V2, V3 and V4). - 0.5V Difference / 1/9 LCD Bias VDD Oscillator is halted. - CSb=1 (Disabled) / No-load on COM/SEG CLK This parameter defines the oscillation frequency by using the internal resistor, in the Variable grayscale mode. - (Rf2, Rf1, Rf0)=(0,0,0) CLK This parameter defines the oscillation frequency by using the internal resistor, in the 8-level fixed grayscale mode. - (Rf2, Rf1, Rf0)=(0,0,0) NOTE7) NOTE8) NOTE9) NOTE10) CLK This parameter defines the oscillation frequency by using the internal resistor, in the B&W mode. - (Rf2, Rf1, Rf0)=(0,0,0) NOTE11) OSC2 - VDD=3V / Ta=25C NOTE12) VOUT This parameter is applied to the condition that the internal LCD power supply and the internal oscillator are used. - VEE=2.4V to 3.3V / EVR= (1,1,1,1,1,1,1) / 1/5 to 1/12 LCD Bias / 1/163 Duty Cycle / No-load on COM/SEG / RL=500k between VOUT and VSSH / CA1=CA2=1.0uF / CA3=0.1uF / DCON="1" / AMPON="1" NOTE13) VSS This parameter is applied to the condition that the internal LCD power supply and the internal oscillator are used. - EVR= (1,1,1,1,1,1,1) / All Pixels ON or Checker Flag Display / No-load on COM/SEG / No-access from MPU / VDD=VEE / VREF=0.9VEE / CA1=CA2=1.0uF / CA3=0.1uF / DCON="1" / AMPON="1" / NLIN="0" / 1/163 Duty cycle / Ta=25C NOTE14) VBA - VBA=VREF / Boost Level (N)="1",/ DCON="0" / VOUT=13.5V NOTE15) VREG - VEE=2.4V to 3.3V / VREF=0.9VEE / VOUT=18V / 1/5 to 1/12 LCD bias ratio / 1/163 duty cycle / EVR=(1,1,1,1,1,1,1) / Checker flag display / No-load on COM/SEG / Boost Level (N)="2" to "7" / CA1=CA2=1.0uF / CA3=0.1uF / DCON="0" / AMPON="1" / NLIN="0" NOTE16) VLCD, V1, V2, V3 and V4 - VEE=3.0V / VREF=0.9VEE / VOUT=15V/ 1/5 to 1/12 LCD Bias / EVR= (1,1,1,1,1,1,1) / Display OFF / No-load on COM/SEG / Boost Level (N)="5" / CA1=CA2=1.0uF / CA3=0.1uF / DCON="0" / AMPON="1" (1) (2) (3) (4) VLCD V1 V2 V3 V4 VSSH VD12: (1)-(2) VD34: (3)-(4) VD24: (2)-(4) Ver.2003-10-14 - 101 - NJU6825 ! AC CHARACTERISTICS (1) Write Operation (Parallel Interface / 80-series MPU) tAS8 CSb RS tAH8 WRb tWRLW8 tWRHW8 tDS8 tDH8 D0 to D15 tCYC8 PARAMETER Address hold time Address setup time System cycle time Enable "L" level pulse width Enable "H" level pulse width Data setup time Data hold time SYMBOL tAH8 tAS8 tCYC8 tWRLW8 tWRHW8 tDS8 tDH8 CONDITION MIN. 0 0 90 35 35 30 5 MAX. (VDD=2.5 to 3.3V, Ta=-30 to +85C) UNIT TERMINAL ns ns ns ns ns ns ns CSb RS WRb D0 to D15 PARAMETER Address hold time Address setup time System cycle time Enable "L" level pulse width Enable "H" level pulse width Data setup time Data hold time SYMBOL tAH8 tAS8 tCYC8 tWRLW8 tWRHW8 tDS8 tDH8 CONDITION MIN. 0 0 160 70 70 40 5 MAX. (VDD=2.2 to 2.5V, Ta=-30 to +85C) UNIT TERMINAL ns ns ns ns ns ns ns CSb RS WRb D0 to D15 (VDD=1.7 to 2.2V, Ta=-30 to +85C) PARAMETER Address hold time Address setup time System cycle time Enable "L" level pulse width Enable "H" level pulse width Data setup time Data hold time SYMBOL tAH8 tAS8 tCYC8 tWRLW8 tWRHW8 tDS8 tDH8 CONDITION MIN. 0 0 180 80 80 70 10 MAX. UNIT ns ns ns ns ns ns ns TERMINAL CSb RS WRb D0 to D15 NOTE) Each timing is specified based on 20% and 80% of VDD. - 102 - Ver.2003-10-14 NJU6825 (2) Read Operation (Parallel Interface / 80-series MPU) tAS8 CSb RS tAH8 RDb tWRLR8 tWRHR8 tRDH8 D0 to D15 tRDD8 tCYC8 (VDD=2.5 to 3.3V, Ta=-30 to +85C) UNIT TERMINAL ns ns ns ns ns 60 0 ns ns CSb RS RDb PARAMETER Address hold time Address setup time System cycle time Enable "L" level pulse width Enable "H" level pulse width Read Data delay time Read Data hold time SYMBOL tAH8 tAS8 tCYC8 tWRLR8 tWRHR8 tRDD8 tRDH8 CONDITION MIN. 0 0 180 80 80 MAX. CL=15pF D0 to D15 PARAMETER Address hold time Address setup time System cycle time Enable "L" level pulse width Enable "H" level pulse width Read Data delay time Read Data hold time SYMBOL tAH8 tAS8 tCYC8 tWRLR8 tWRHR8 tRDD8 tRDH8 CONDITION MIN. 0 0 180 80 80 MAX. (VDD=2.2 to 2.5V, Ta=-30 to +85C) UNIT TERMINAL ns ns ns ns ns CSb RS RDb CL=15pF 60 0 ns ns D0 to D15 (VDD=1.7 to 2.2V, Ta=-30 to +85C) PARAMETER Address hold time Address setup time System cycle time Enable "L" level pulse width Enable "H" level pulse width Read Data delay time Read Data hold time SYMBOL tAH8 tAS8 tCYC8 tWRLR8 tWRHR8 tRDD8 tRDH8 CL=15pF CONDITION MIN. 0 0 250 120 120 110 0 MAX. UNIT ns ns ns ns ns ns ns TERMINAL CSb RS RDb D0 to D15 NOTE) Each timing is specified based on 20% and 80% of VDD. Ver.2003-10-14 - 103 - NJU6825 (3) Write Operation (Parallel Interface / 68-series MPU) tAS6 CSb RS R/W (WRb) tAH6 E (RDb) tEHW6 tDS6 tDH6 tELW6 D0 to D15 tCYC6 (VDD=2.5 to 3.3V, Ta=-30 to +85C) UNIT TERMINAL ns ns ns ns ns ns ns CSb RS E PARAMETER Address hold time Address setup time System cycle time Enable "L" level pulse width Enable "H" level pulse width Data setup time Data hold time SYMBOL tAH6 tAS6 tCYC6 tELW6 tEHW6 tDS6 tDH6 CONDITION MIN. 0 0 90 35 35 40 5 MAX. D0 to D15 PARAMETER Address hold time Address setup time System cycle time Enable "L" level pulse width Enable "H" level pulse width Data setup time Data hold time SYMBOL tAH6 tAS6 tCYC6 tELW6 tEHW6 tDS6 tDH6 CONDITION MIN. 0 0 160 70 70 50 5 MAX. (VDD=2.2 to 2.5V, Ta=-30 to +85C) UNIT TERMINAL ns ns ns ns ns ns ns CSb RS E D0 to D15 (VDD=1.7 to 2.2V, Ta=-30 to +85C) PARAMETER Address hold time Address setup time System cycle time Enable "L" level pulse width Enable "H" level pulse width Data setup time Data hold time SYMBOL tAH6 tAS6 tCYC6 tELW6 tEHW6 tDS6 tDH6 CONDITION MIN. 0 0 180 80 80 70 10 MAX. UNIT ns ns ns ns ns ns ns TERMINAL CSb RS E D0 to D15 NOTE) Each timing is specified based on 20% and 80% of VDD. - 104 - Ver.2003-10-14 NJU6825 (4) Read Operation (Parallel Interface / 68-series MPU) tAS6 CSb RS tAH6 R/W (WRb) tELR6 E (RDb) tRDH6 tEHR6 D0 to D15 tRDD6 tCYC6 (VDD=2.5 to 3.3V, Ta=-30 to +85C) MAX. UNIT TERMINAL ns ns ns ns ns 70 ns ns CSb RS E PARAMETER Address hold time Address setup time System cycle time Enable "L" level pulse width Enable "H" level pulse width Read Data delay time Read Data hold time SYMBOL tAH6 tAS6 tCYC6 tELR6 tEHR6 tRDD6 tRDH6 CONDITION MIN. 0 0 180 80 80 CL=15pF 0 D0 to D15 PARAMETER Address hold time Address setup time System cycle time Enable "L" level pulse width Enable "H" level pulse width Read Data delay time Read Data hold time SYMBOL tAH6 tAS6 tCYC6 tELR6 tEHR6 tRDD6 tRDH6 CONDITION MIN. 0 0 180 80 80 (VDD=2.2 to 2.5V, Ta=-30 to +85C) MAX. UNIT TERMINAL ns ns ns ns ns 70 ns ns CSb RS E CL=15pF 0 D0 to D15 PARAMETER Address hold time Address setup time System cycle time Enable "L" level pulse width Enable "H" level pulse width Read Data delay time Read Data hold time SYMBOL tAH6 tAS6 tCYC6 tELR6 tEHR6 tRDD6 tRDH6 CONDITION MIN. 0 0 250 120 120 (VDD=1.7 to 2.2V, Ta=-30 to +85C) MAX. UNIT TERMINAL ns ns ns ns ns 110 ns ns CSb RS E CL=15pF 0 D0 to D15 NOTE) Each timing is specified based on 20% and 80% of VDD. Ver.2003-10-14 - 105 - NJU6825 (5) Write Operation (Serial Interface) CSb tCSS tCSH RS tASS SCL tSHW tCYCS tSLW tAHS tDSS tDHS SDA (VDD=2.5 to 3.3V, Ta=-30 to +85C) PARAMETER Serial clock cycle SCL "H" level pulse width SCL "L" level pulse width Address setup time Address hold time Data setup time Data hold time CSb - SCL time CSb hold time SYMBOL tCYCS tSHW tSLW tASS tAHS tDSS tDHS tCSS tCSH CONDITION MIN. 50 20 20 20 20 20 20 20 20 MAX. UNIT ns ns ns ns ns ns ns ns ns TERMINAL SCL RS SDA CSb (VDD=2.2 to 2.5V, Ta=-30 to +85C) PARAMETER Serial clock cycle SCL "H" level pulse width SCL "L" level pulse width Address setup time Address hold time Data setup time Data hold time CSb - SCL time CSb hold time SYMBOL tCYCS tSHW tSLW tASS tAHS tDSS tDHS tCSS tCSH CONDITION MIN. 50 20 20 20 20 20 20 20 20 MAX. UNIT ns ns ns ns ns ns ns ns ns TERMINAL SCL RS SDA CSb (VDD=1.7 to 2.2V, Ta=-30 to +85C) PARAMETER Serial clock cycle SCL "H" level pulse width SCL "L" level pulse width Address setup time Address hold time Data setup time Data hold time CSb - SCL time CSb hold time SYMBOL tCYCS tSHW tSLW tASS tAHS tDSS tDHS tCSS tCSH CONDITION MIN. 80 35 35 35 35 35 35 35 35 MAX. UNIT ns ns ns ns ns ns ns ns ns TERMINAL SCL RS SDA CSb NOTE) Each timing is specified based on 20% and 80% of VDD. - 106 - Ver.2003-10-14 NJU6825 (6) Display Control Timing CLK tDCL CL tDFLM tDFLM FLM tFR FR Output timing PARAMETER FLM delay time FR delay time CL delay time SYMBOL tDFLM tFR tDCL CONDITION CL=15pF MIN. 0 0 0 MAX. 500 500 200 (VDD=2.4 to 3.3V, Ta=-30 to +85C) UNIT ns ns ns TERMINAL FLM FR CL Output timing PARAMETER FLM delay time FR delay time CL delay time SYMBOL tDFLM tFR tDCL CONDITION CL=15pF MIN. 0 0 0 MAX. 1000 1000 200 (VDD=1.7 to 2.4V, Ta=-30 to +85C) UNIT ns ns ns TERMINAL FLM FR CL NOTE) Each timing is specified based on 20% and 80% of VDD. Ver.2003-10-14 - 107 - NJU6825 (7) Input Clock Timing tCKLW OSC1 tCKHW (VDD=1.7 to 3.3V, Ta=-30 to +85C) PARAMETER OSC1 "H" level pulse width (1) OSC1 "L" level pulse width (1) OSC1 "H" level pulse width (2) OSC1 "L" level pulse width (2) OSC1 "H" level pulse width (3) OSC1 "L" level pulse width (3) SYMBOL tCKHW1 tCKLW1 tCKHW2 tCKLW2 tCKHW3 tCKLW3 CONDITION MIN. 0.555 0.555 2.46 2.46 16.9 16.9 MAX. 0.800 0.800 3.54 3.54 24.4 24.4 UNIT s s s s s s TERMINAL OSC1 (NOTE2) OSC1 (NOTE3) OSC1 (NOTE4) NOTE1) Each timing is specified based on 20% and 80% of VDD. NOTE2) Applied to Variable 8-/16-level grayscale mode (MON="0",PWM="0") NOTE3) Applied to fixed 8-level grayscale mode (MON="0",PWM="1") NOTE4) Applied to B&W mode (MON="1") (8) Reset Input Timing tRW RESb tR Internal circuit status During reset End of reset (VDD=2.4 to 3.3V, Ta=-30 to +85C) PARAMETER Reset time RESb "L" level pulse width SYMBOL tR tRW 10.0 CONDITION MIN. MAX. 1.0 UNIT s s RESb Terminal (VDD=1.7 to 2.4V, Ta=-30 to +85C) PARAMETER Reset time RESb "L" level pulse width SYMBOL tR tRW 10.0 CONDITION MIN. MAX. 1.5 UNIT s s RESb Terminal NOTE) Each timing is specified based on 20% and 80% of VDD. (9) Delay Time of Gate PARAMETER Delay time of gate SYMBOL Ta=+25C, VSS=0V, VDD=3.0V MIN TYP 10 MAX UNIT ns - 108 - Ver.2003-10-14 NJU6825 ! INPUT/OUTPUT BLOCK DIAGRAMS Input Block Diagram Terminals CSb, RS, RDb, WRb, SEL68, P/S, RESb VDD Output Block Diagram Terminals : FLM, CL, FR, CLK VDD Input signal Output control signal I VSS(0V) O Output signal VSS(0V Input/Output Block Diagram Terminals : D0 - D15 VDD I/O Input signal VSS(0V) VSS(0V) Input control signal VDD Output control signal Output signal VSS(0V) COM/SEG Driver Block Diagram Terminals : SEGA0/B0/C0 - SEGA127/B127/C127, COM0 - COM161 VLCD VLCD VLCD V1/V2 Output control signal 1 O Output control signal 3 VSSH(0V) V3/V4 VSSH(0V) VSSH(0V) Output control signal 2 Output control signal 4 Ver.2003-10-14 - 109 - NJU6825 ! MPU CONNECTIONS Parallel Interface / 80-series MPU 1.7V - 3.3V VCC A0 A1 -A7 IORQb D0 - D7 RDb WRb RESb 8 7 Decoder RS CSb D0 -D7 RDb WRb RESb RESET VDD (80-MPU) (NJU6825) GND VSS Parallel Interface / 68-series MPU 1.7V - 3.3V VCC A0 A1 -A15 15 Decoder RS CSb D0 -D7 VDD (68 -MPU) VMA D0 - D7 E R/W RESb (NJU6825) 8 RDb (E) WRb (R/W) RESb RESET VSS GND Serial Interface 1.7V - 3.3V VCC A0 A1 -A7 7 Decoder RS CSb VDD ( MPU) (NJU6825) PORT1 PORT2 RESb GND RESET SDA SCL RESb VSS - 110 - Ver.2003-10-14 NJU6825 [CAUTION] The specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. The application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights. Ver.2003-10-14 - 111 - |
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