View NSC04645_993647.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

DS3884A BTL Handshake Transceiver
July 1998
DS3884A BTL Handshake Transceiver
General Description
The DS3884A is pin to pin and functionally compatible with the DS3884. The DS3884A is a speed and power enhanced version of the DS3884. There are two minor differences between the DS3884 and DS3884A. The external resistor used in the DS3884A is different from that used in the DS3884. REXT for the DS3884 is 6.2k while REXT for the DS3884A is 13k. The available filter settings for the DS3884A are 5 ns, 10 ns, 14 ns, 24 ns, while the settings for the DS3884 are 5 ns, 7.5 ns, 15 ns, and 25 ns. The DS3884A is one in a series of transceivers designed specifically for the implementation of high performance Futurebus+ and proprietary bus interfaces. The DS3884A is a BTL 6-bit Handshake Transceiver designed to conform to IEEE 1194.1 (Backplane Transceiver Logic -- BTL) as specified in the IEEE 896.2 Futurebus+ specification. Utilization of the DS3884A simplifies the implementation of all handshake signals which require Wired-OR glitch filtering. Three of the six bits have an additional parallel Wired-OR filtered receive output giving a total of nine receiver outputs. In Wired-OR applications, the glitch generated as drivers are released from the bus, is dependent upon the backplane and parasitic wiring components causing the characteristics of the glitch to vary in pulse width and amplitude. To accommodate this variation the DS3884A features two pins defined as PS1 and PS2 which allow selection of a 5 ns, 10 ns, 14 ns and 24 ns filter setting to optimize glitch filtering for a given situation. The REXT pin is issued in conjunction with the filtering circuitry and requires a 13 k resistor to ground. For additional information on Wired-OR glitch, reference Application Note AN-774. The DS3884A driver output configuration is an NPN open collector which allows Wired-OR connection on the bus. Each driver output incorporates a Schottky diode in series with its collector to isolate the transistor output capacitance from the bus thus reducing the bus loading in the inactive state. The combined output capacitance of the driver and receiver input is typically less than 5 pF. The driver also has high sink current capability to comply with the bus loading requirements defined within IEEE 1194.1 BTL specification. Backplane Transceiver Logic (BTL) is a signaling standard that was invented and first introduced by National Semiconductor, then developed by the IEEE to enhance the performance of backplane buses. BTL compatible transceivers feature low output capacitance drivers to minimize bus loading, a 1V nominal signal swing for reduced power consumption and receivers with precision thresholds for maximum noise immunity. The BTL standard eliminates settling time delays that severely limit TTL bus performance, and thus provide significantly higher bus transfer rates. The backplane bus is intended to be operated with termination resistors (selected to match the bus impedance) connected to 2.1V at both ends. The low voltage is typically 1V. Separate ground pins are provided for each BTL output to minimize induced ground noise during simultaneous switching. The device's unique driver circuitry meets a maximum slew rate of 0.5V/ns which allows controlled rise and fall times to reduce noise coupling to adjacent lines. The transceiver's high impedance control and driver inputs are fully TTL compatible. The receiver is a high speed comparator that utilizes a bandgap reference for precision threshold control allowing maximum noise immunity to the BTL 1V signaling level. Separate QVCC and QGND pins are provided to minimize the effects of high current switching noise. Output pins FR1-FR3 are the filtered outputs and R1-R6 are the unfiltered outputs. All receiver outputs are fully TTL compatible. The DS3884A supports live insertion as defined for Futurebus+ through the LI (Live Insertion) pin. To implement live insertion the LI pin should be connected to the live insertion power connector. If this function is not supported the LI pin must be tied to the VCC pin. The DS3884A also provides power up/down glitch free protection during power sequencing. The DS3884A has two types of power connections in addition to the LI pin. They are the Logic VCC (VCC) and the Quiet VCC (QVCC). There are two VCC pins on the DS3884A that provide the supply voltage for the logic and control circuitry. Multiple connections are provided to reduce the effects of package inductance and thereby minimize switching noise. As these pins are common to the V CC bus internal to the device, a voltage difference should never exist between these pins and the voltage difference between V CC and QV CC should never exceed 0.5V because of ESD circuitry. Additionally, the ESD circuitry between the VCC pins and all other pins except for BTL I/O's and LI pins requires that any voltage on these pins should not exceed the voltage on VCC + 0.5V. There are three different types of ground pins on the DS3884A. They are the logic ground (GND), BTL grounds (B1GND-B6GND) and the Bandgap reference ground (QGND). All of these ground reference pins are isolated within the chip to minimize the effects of high current switching transients. For optimum performance the QGND should be returned to the connector through a quiet channel that does not carry transient switching current. The GND and B1GND-B6GND should be connected to the nearest backplane ground pin with the shortest possible path. Since many different grounding schemes could be implemented and ESD circuitry exist on the DS3884A, it is important to note that any voltage difference between ground pins, QGND, GND or B1GND-B6GND should not exceed 5V including power up/down sequencing. Additional transceivers included in the Futurebus+ / BTL family are; the DS3883A BTL 9-bit Transceiver, and the DS3886A BTL 9-bit Latching Data Transceiver featuring
TRI-STATE (R) is a registered trademark of National Semiconductor Corporation.
(c) 1999 National Semiconductor Corporation
DS011460
www.national.com
General Description
(Continued)
edge triggered latches in the driver which may be bypassed during a fall-through mode and a transparent latch in the receiver.
n n n n n n n n n n
Features
Fast propagation delay (3 ns typ) 6-bit BTL transceiver Selective receiver glitch filtering (FR1-FR3) Meets 1194.1 Standard on Backplane Transceiver Logic (BTL) n Supports live insertion n Glitch free power-up/down protection n n n n
Typically less than 5 pF bus-port capacitance Low Bus-port voltage swing (typically 1V) at 80 mA TTL compatible driver and control inputs Separate TTL I/O Open collector bus-port outputs allow Wired-OR connection Controlled rise and fall time to reduce noise coupling to adjacent lines Built in Bandgap reference with separate QV CC and QGND pins for precise receiver thresholds Exceeds 2 kV ESD testing (Human Body Model) Individual Bus-port ground pins Product offered in PLCC and PQFP package styles
Connection Diagrams
DS011460-1
DS011460-2
Order Number DS3884AV or DS3884AVF See NS Package V44A or VF44B
www.national.com
2
Logic Diagram
DS011460-3
3
www.national.com
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage Control Input Voltage Driver Input and Receiver Output Receiver Input Current Bus Termination Voltage Power Dissipation at 25C PLCC PQFP 6.5V 6.5V 5.5V 15 mA 2.4V 2.5W 1.3W
Derate PLCC Package Derate PQFP Package Storage Temperature Range Lead Temperature (Soldering, 4 seconds):
20 mW/C 11.1 mW/C -65C to +150C 260C
Recommended Operating Conditions
Supply Voltage, VCC Bus Termination Voltage (VT) Operating Free Air Temperature 4.5V-5.5V 2.06V-2.14V 0C to 70C
DC Electrical Characteristics (Notes 2, 3)
TA = 0 to +70C, V Symbol VIH VIL II IIH IIL VCL VOLB IOLBZ IOHBZ IOLB IOHB VTH VCLP VCLN VOH VOL IOS ICC ILI
CC
= 5V 10% Conditions Min 2.0 0.8 VIN = V CC = 5.5V VIN = 2.4V VIN = 0.5V ICLAMP = -12 mA Dn = 2.4V, DE* = 0V, IOL = 80 mA Dn = 0.5V, DE* = 2.4V, Bn = 0.75V Dn = 0.5V, DE* = 2.4V, Bn = 2.1V Dn = 0.5V, DE* = 0V, Bn = 0.75V Dn = 0.5V, DE* = 0V, Bn = 2.1V DE* = 2.4V VCC = Max or 0V, IBn = 1 mA VCC = Max or 0V, IBn = 10 mA ICLAMP = -12 mA Bn = 1.1V, DE* = 2.4V, IOH = -2 mA Bn = 2.1V, DE* = 2.4V, IOL = 24 mA Bn = 2.1V, DE* = 2.4V, IOL = 8 mA Bn = 1.1V, DE* = 2.4V (Note 4) DE* = 0.5V, All Dn DE* = 2.4V, All Bn DE* = 2.4V, All Dn DE* = 0.5V, All Dn = 2.4V = 2.1V = 0.5V = 2.4V 0.75 1.0 100 40 -100 -1.2 1.1 100 100 220 350 1.47 2.4 2.9 1.55 3.4 3.9 1.62 4.5 5.0 -1.2 2.4 3.2 0.35 0.35 -40 -70 50 50 1 2 0.5 0.4 -100 70 70 3 5 Typ Max Units V V A A A V V A A A A V V V V V V V mA mA mA mA mA
Parameter Minimum Input High Voltage Maximum Input Low Voltage Input Leakage Current Input High Current Input Low Current Input Diode Clamp Voltage Output Low Bus Voltage (Note 5) Output Low Bus Current Output High Bus Current Output Low Bus Current Output High Bus Current Receiver Input Threshold Positive Clamp Voltage Negative Clamp Voltage Voltage Output High Voltage Output Low Output Short Circuit Current Supply Current: Includes VCC, QVCC and LI Live Insertion Current
DRIVER AND CONTROL INPUT: (Dn, DE*, PS1 and PS2)
DRIVER OUTPUT/RECEIVER INPUT: (Bn)
RECEIVER OUTPUT: (FRn and Rn)
SUPPLY CURRENT
Note 1: "Absolute Maximum Ratings" are those beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device should be operated at these limits. The table of "Electrical Characteristics" provide conditions for actual device operation. Note 2: All input and/or output pins shall not exceed VCC plus 0.5V and shall not exceed the absolute maximum rating at anytime, including power-up and power-down. This prevents the ESD structure from being damaged due to excessive currents flowing from the input and/or output pins to QV CC and VCC. There is a diode between each input and/or output to VCC which is forward biased when incorrect sequencing is applied. Alternatively, a current limiting resistor can be used when pulling-up the inputs to prevent damage. The current into any input/output pin shall be no greater than 50 mA. Exception, LI and Bn pins do not have power sequencing requirements with respect to VCC and QVCC. Furthermore, the difference between VCC and QVCC should never be greater than 0.5V at any time including power-up. Note 3: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to device ground unless otherwise specified. All typical values are specified under these conditions.: VCC = 5V and TA = 25C unless otherwise stated. Note 4: Only one output should be shorted at a time, and duration of the short should not exceed one second. Note 5: Referenced to appropriate signal ground. Do not exceed maximum power dissipation of package.
www.national.com
4
AC Electrical Characteristics
TA = 0C to +70C, VCC = 5V 10% Symbol DRIVER tPHL tPLH tPHL tPLH tr tf SR tskew RECEIVER tPHL tPLH tskew Skew between Receivers in Same Package FILTERED RECEIVER tPHL Bn to FRn Prop. Delay Bn to Rn Prop. Delay 20% to 80% Skew Rate is Calculated from 1.3V to 1.8V Skew between Drivers in the Same Package DE* to Bn Enable Time Disable Time Transition Time -- Rise/Fall Dn to Bn Prop. Delay Parameter
(Note 6) Conditions DE* = 0V (Figure 1, Figure 2 ) Dn = 3V (Figure 1, Figure 3 ) (Figure 1, Figure 2 ) (Note 11) (Note 7) 1 Min 1 1 2 2 1 1 Typ 3 3 4 4 2 2 Max 5 5 6 6 3.5 3.5 0.5 3 Units ns ns ns ns ns ns V/ns ns
DE* = 3V (Figure 4, Figure 5 ) (Note 7)
2 2
4 4 1
5 6 3
ns ns ns
PS1 = 0V PS2 = 0V DE* (Figure 4, Figure 5 ), REXT = PS1 = 0V PS2 = 3V DE* (Figure 4, Figure 5 ), REXT =
= 3V 13 k = 3V
6 11 15 25
12 16 21 33
16 21 27 45
ns ns ns ns
13 k PS1 = 3V PS2 = 0V DE* = 3V (Figure 4, Figure 5 ), REXT = 13 k PS1 = 3V PS2 = 3V DE* = 3V (Figure 4, Figure 5 ), REXT = 13 k tPLH Bn to FRn Prop. Delay DE* = 3V (Figure 4, Figure 5 ) (Note 8) REXT = 13 k PS1 = 0V PS2 = 0V DE* (Figure 4, Figure 6 ), REXT = PS1 = 0V PS2 = 3V DE* (Figure 4, Figure 6 ), REXT = = 3V 13 k = 3V
2
5
7
ns
tGR
Glitch Rejection
5 10 14 24
9 13 18 31
16 18 24 42
ns ns ns ns
13 k PS1 = 3V PS2 = 0V DE* = 3V (Figure 4, Figure 6 ), REXT = 13 k PS1 = 3V PS2 = 3V DE* = 3V (Figure 4, Figure 6 ), REXT = 13 k FILTERED RECEIVER TIMING REQUIREMENTS ts Coutput tNR PSn to Bn Capacitance at Bn Noise Rejection Set-Up Time (Figure 7 ), REXT = 13 k (Note 9) (Note 10)
250 5 1
ns pF ns
PARAMETERS NOT TESTED
Note 6: Input waveforms shall have a rise/fall time of 3 ns. Note 7: tskew is an absolute value defined as differences seen in propagation delays between drivers in the same package with identical load conditions. Note 8: Filtered receiver tPLH is independent of filter setting. Note 9: The parameter is tested using TDR techniques described in P1194.0 BTL Backplane Design Guide. Note 10: This parameter is tested during device characterization. The measurements revealed that the part will reject 1 ns pulse width. Note 11: Futurebus+ transceivers are required to limit bus signal rise and fall times to no faster than 0.5V/ns, measured between 1.3V and 1.8V (approximately 20% to 80% of nominal voltage swing). The rise and fall times are measured with a transceiver loading equivalent to 12.5 tied to +2.1V DC.
5
www.national.com
Pin Descriptions
Pin Name B1-B6 B1GND-B6GND Number of Pins 6 6 Input/ Output I/O NA BTL receiver input and driver output Driver output ground reduces bounce due to high current switching of driver outputs (Note 12) DE* D1-D6 FR1-FR3 GND LI 1 6 3 3 1 I I O NA NA Driver Enable Low TTL Driver Input TTL Filtered Receiver Output Ground reference for switching circuits. (Note 12) Power supply for live insertion. Boards that require live insertion should connect LI to the live insertion pin on the connector. (Note 13) No Connect Pulse Width Selection pin determines glitch filter setting (Note 14) TTL Receiver Output External Resistor pin. External resistor is used for internal biasing of filter circuitry. The 13 k resistor shall be connected between REXT and GND. The resistor shall have a tolerance of 1% and a temperature coefficient of 100 ppm/C or better. Ground reference for receiver input bandgap reference and non-switching circuits (Note 12) VCC supply for bandgap reference and non-switching circuits (Note 13) VCC supply for switching circuits (Note 13) Description
NC PS1, PS2 R1-R6 REXT
4 2 6 1
NA I O NA
QGND QVCC VCC
2 1 2
NA NA NA
Note 12: the multiplicity of grounds reduces the effective inductance of bonding wires and leads, which then reduces the noise caused by transients on the ground path. The various ground pins can be tied together provided that the external ground has low inductance (i.e., ground plane with power pins and many signal pins connected to the backplane ground). If the external ground floats considerably during transients, precautionary steps should be taken to prevent QGND from moving with reference to the backplane ground. The receiver threshold should have the same ground reference as the signal coming from the backplane. A voltage offset between their grounds will degrade the noise margin. Note 13: The same considerations for ground are used for V CC in reducing lead inductance (see Note 12). QVCC and V CC should be tied together externally. If live insertion is not supported, the LI pin can be tied together with QVCC and VCC. Note 14: See AC characteristics for filter setting.
www.national.com
6
Pin Descriptions
DE* H H L L Dn X X H L
(Continued) FRn H L H L Rn H L H L Bn L H L H FIGURE 3. Driver: DE* to Bn
DS011460-7
X: High or low logic state L: Low state H: High state L-H: Low to high transition
Glitch Filter Table
PS1 L L H H PS2 L H L H Filter Setting 5 ns 10 ns 14 ns 24 ns S1 Switch Position tPLH open tPHL close
DS011460-8
FIGURE 4. Receiver Propagation Delay Set-Up
DS011460-5
FIGURE 1. Driver Propagation Delay Set-Up
DS011460-9
FIGURE 5. Receiver: Bn to FRn, Bn to Rn
DS011460-6
FIGURE 2. Driver: Dn to Bn
DS011460-10
FIGURE 6. Receiver: tGR, FRn(min) = 2V
DS011460-11
FIGURE 7. Receiver: PSn to Bn
7
www.national.com
Physical Dimensions
inches (millimeters) unless otherwise noted
44-Pin PLCC Order Number DS3884AV NS Package V44A
www.national.com
8
DS3884A BTL Handshake Transceiver
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
44-Pin PQFP Order Number DS3884AVF NS Package VF44B
LIFE SUPPORT POLICY NATIONAL'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
National Semiconductor Corporation Americas Tel: 1-800-272-9959 Fax: 1-800-737-7018 Email: support@nsc.com www.national.com National Semiconductor Europe Fax: +49 (0) 1 80-530 85 86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 1 80-530 85 85 English Tel: +49 (0) 1 80-532 78 32 Francais Tel: +49 (0) 1 80-532 93 58 Italiano Tel: +49 (0) 1 80-534 16 80
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
National Semiconductor Asia Pacific Customer Response Group Tel: 65-2544466 Fax: 65-2504466 Email: sea.support@nsc.com
National Semiconductor Japan Ltd. Tel: 81-3-5639-7560 Fax: 81-3-5639-7507
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.

▲Up To Search▲

Price & Availability of NSC04645

	To Download NSC04645 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .