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MICROCIRCUIT DATA SHEET MNCLC532A-X REV 0A0
HIGH-SPEED 2:1 ANALOG MULTIPLEXER
General Description
The CLC532 is a high-speed 2:1 multiplexer with active input and output stages. The CLC532 also employs a closed-loop design which dramatically improves accuracy. This accurate monolithic device is constructed using an advanced high-performance bipolar process. The CLC532 has been specifically designed to provide settling times of 17ns to 0.01%. This design, coupled with the adjustable noise bandwidth, makes the CLC532 an ideal choice for infrared and CCD imaging systems. Channel-to-channel isolation is better than 80dB @ 10MHz. Low distortion (80dBc) and spurious signal levels make the CLC532 a very suitable choice for both I/Q processors and receivers. Original Creation Date: 07/17/98 Last Update Date: 04/05/99 Last Major Revision Date: 09/24/98
Industry Part Number
CLC532A
NS Part Numbers
CLC532AE-QML** CLC532AJ-QML*
Prime Die
UB1451A
Controlling Document
5962-9203501MCA*, M2A**
Processing
MIL-STD-883, Method 5004
Subgrp Description
1 2 3 4 5 6 7 8A 8B 9 10 11 Static tests at Static tests at Static tests at Dynamic tests at Dynamic tests at Dynamic tests at Functional tests at Functional tests at Functional tests at Switching tests at Switching tests at Switching tests at
Temp ( oC)
+25 +125 -55 +25 +125 -55 +25 +125 -55 +25 +125 -55
Quality Conformance Inspection
MIL-STD-883, Method 5005
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MNCLC532A-X REV 0A0
MICROCIRCUIT DATA SHEET
Features
12-bit settling (0.01%) - 17ns Low noise - 32uVrms High isolation - 80dB @ 10MHz Low distortion - 80dB @ 5MHz Adjustable bandwidth - 190MHz (max)
Applications
Infrared system multiplexing CCD sensor signals Radar I/Q switching High definition video HDTV Test and calibration
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MNCLC532A-X REV 0A0
MICROCIRCUIT DATA SHEET
(Absolute Maximum Ratings)
(Note 1) Positive Supply Voltage (+Vcc) -0.5V to +7.0V Negative Supply Voltage (-Vee) +0.5V to -7.0V Differential Voltage Between Any Two Ground Pins 200mV Analog Input Voltage Range -Vee to +Vcc Digital Input Voltage Range -Vee to +Vcc Maximum Power Dissipation (Pd) (Note 2) Ceramic DIP LCC Output Current (Iout) Output Short Circuit Duration (output shorted to GND) Infinite Junction Temperature (Tj) +175 C Storage Temperature Range -65 C to +150 C Lead Temperature (soldering, 10 seconds) +300 C Thermal Resistance Junction -to-ambient (ThetaJA) Ceramic DIP (Still Air) (500 LFPM) LCC (Still Air) (500 LFPM) Junction -to-case (ThetaJC) Ceramic DIP LCC Package Weight (Typical) Ceramic DIP LCC ESD Tolerance (Note 3) ESD Rating Note 1:
1.76 W 3.0 W 36mA
TBD TBD TBD TBD TBD TBD
2190 mg TBD
500 V
Note 2:
Note 3:
Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. The maximum power dissipation must be derated at elevated temperatures and is dictated by Tjmax (maximum junction temperature), ThetaJA (package junction to ambient thermal resistance), and TA (ambient temperature). The maximum allowable power dissipation at any temperature is Pdmax = (Tjmax - TA) / ThetaJA or the number given in the Absolute Maximum Ratings, whichever is lower. Human body model, 100pF discharged through 1.5K Ohms.
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MNCLC532A-X REV 0A0
MICROCIRCUIT DATA SHEET
Recommended Operating Conditions
Positive Supply Voltage (+Vcc) +5.0V Negative Supply Voltage (-Vee) -5.2V or -5.0V Differential Voltage Between Any Two Ground Pins 10mV Analog Input Voltage Range +2V SELECT Input Voltage Range (TTL Mode) 0V to +3.0V SELECT Input Voltage Range (ECL Mode) -2.0V to 0V COMPENSATION Capacitance Range (Ccomp) 0pF to 100pF Ambient Operating Temperature Range (Ta) -55 C to +125 C
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MNCLC532A-X REV 0A0
MICROCIRCUIT DATA SHEET
Electrical Characteristics
DC PARAMETERS
(The following conditions apply to all the following parameters, unless otherwise specified.) DC: +Vs = +5.0V, -Vs = -5.2V, Rin = 50Ohms, Rl = 500Ohms, Ccomp = 10pF, and ECL mode, pin 6 = no connection. See figure 3. -55 C < Ta < +125 C (Note 3). SYMBOL IBN PARAMETER Input Bias Current Output Offset Voltage Supply Current Vcc = +5V, Vin = 0V, no load CONDITIONS NOTES PINNAME MIN -120 -250 Voo -3.5 -6.5 Icc 18 16 18 Iee Supply Current Vee = -5.2V, Vin = 0V, no load -30 -26 -31 PSRR Power Supply Rejection Ratio MAX +120 +250 +3.5 +6.5 28 25 30 -19 -16 -19 -63 -64 -60 GA SSBW Gain Accuracy Small Signal Bandwidth +2V -3 dB Bandwidth, Vout < 0.1 Vpp 2 2 GFP Gain Flatness Peaking Vout < 0.1 Vpp, at 0.1 MHz to 200 MHz 2 2 GFR Gain Flatness Rolloff Vout < 0.1 Vpp, at 0.1 MHz to 100 MHz 2 2 HD2 2nd Harmonic Distortion 3rd Harmonic Distortion Note 1: Note 2: Note 3: 2 Vpp at 5 MHz 2 HD3 2 Vpp at 5 MHz 2 -1.8 -2.6 -1.8 -67 -67 -68 -68 .988 140 110 140 0.7 0.8 0.7 1.000 UNIT uA uA mV mV mA mA mA mA mA mA dB dB dB V/V MHz MHz MHz dB dB dB dB dB dB dBc dBc dBc dBc SUBGROUPS 1, 2 3 1, 2 3 1 2 3 1 2 3 1 2 3 1, 2, 3 4 5 6 4 5 6 4 5 6 4 5, 6 4 5, 6
If not tested, shall be guaranteed to the limits specified in table I Group A testing only. The algebraic convention, whereby the most negative value is a minimum and most positive is a maximum, is used in this table. Negative current shall be defined as convential current flow out of a device terminal.
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MNCLC532A-X REV 0A0
MICROCIRCUIT DATA SHEET
Graphics and Diagrams
GRAPHICS# 07067HRA2 07074HRA2 E20ARE J14ARH P000398A P000399A CERDIP (J), 14 LEAD (B/I CKT) LCC (E), TYPE C, 20 TERMINAL (B/I CKT) LCC (E), TYPE C, 20 TERMINAL(P/P DWG) CERDIP (J), 14 LEAD (P/P DWG) CERDIP (J), 14 LEAD (PINOUT) LCC (E), TYPE C, 20 TERMINAL (PINOUT) DESCRIPTION
See attached graphics following this page.
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GND INA GND INB DGND DREF SELECT
1 2 3 4 5 6 7
14 13 12 11 10 9 8
+VCC +VCC COMP1 OUTPUT COMP2 VEE VEE
CLC532J 14 - LEAD DIP CONNECTION DIAGRAM TOP VIEW P000398A
N
MIL/AEROSPACE OPERATIONS 2900 SEMICONDUCTOR DRIVE SANTA CLARA, CA 95050
INA
GND
N/C
+VCC +VCC
GND N/C INB N/C DGND
4 5 6 7 8
3
2
1
20
19
18 17 16 15 14
COMP1 N/C OUTPUT N/C COMP2
9
10
11
12
13
DREF SELECT N/C
VEE
VEE
CLC532E 20 - LEAD LCC CONNECTION DIAGRAM TOP VIEW P000399A
N
MIL/AEROSPACE OPERATIONS 2900 SEMICONDUCTOR DRIVE SANTA CLARA, CA 95050
MNCLC532A-X REV 0A0
MICROCIRCUIT DATA SHEET
Revision History
Rev
0A0
ECN #
Rel Date
Originator
Shaw Mead
Changes
Initial MDS Release
M0003339 04/05/99
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