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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document by MC33253/D
Advance Information Full Bridge Driver
The MC33253 is a full bridge driver with integrated charge pump, two independent high and low side driver channels and a voltage supply unit. The high and low side drivers include a cross conduction suppression circuit, which, if enabled, prevents the external power FETs from being on at the same time. Therefore each output driver detects the gate to source voltage and masks the input signal of the opposite channel. The outputs are formed with 1 A pulse peak current Drivers. The low side channel is referenced to ground. A linear regulator provides 12 V for the low side gate driver stage independent of the supply voltage VCC2. This guarantees gate protection at VCC2 above 14 V. The high side driver stage is supplied with a voltage of 12 V above VCC provided by the charge pump. Both the high side and low side driver supply voltages are buffered with an external capacitor. A under- and over-voltage protection prevents erratic system operation at abnormal supply voltages. The under- and over-voltage protection forces the driver stage into an off state during a failure condition. The logic inputs are compatible with standard CMOS or LSTTL outputs. The input hysteresis makes the output switching time independent of the input transition time. Each channel can be driven with inverted or non-inverted logic. A circuit shut-down is achieved by driving the global enable signal with a logic low or tri-state. During shut-down, all BIAS circuits and the charge pump are disabled in order to reduce the quiescent current to a minimum. To wake up the circuit, 5 V has to be provided at G_EN in order to supply the logic circuits during wake-up. A ground referenced operational amplifier provides an analog feedback of the bridge current with the use of either Sense FETs or an external shunt resistor. Features:
MC33253
55 VOLT FULL BRIDGE DRIVER
28 1
DW SUFFIX PLASTIC PACKAGE CASE 751F-05 (SO-28) ORDERING INFORMATION MC33253DW SOIC Wide
PIN CONNECTIONS (TOP VIEW) CASE 751F-05 (28 SOIC) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 VCC C2 CP_OUT SRC_HS1 ISOUT 28 G_EN 27 /CCS 26 SRC_HS2 25
* * * * * *
Operating Voltage Range from 5.5 V up to 55 V Automotive Temperature Range -40C to 125C 1A Pulse Current Output Driver Fast PWM Capability up to 100 kHz Built-In Charge Pump Cross Conduction Supression Circuit
GATE_HS1 GATE_HS2 24 /IN_HS1 IN_HS1 /IN_LS1 IN_LS1 GATE_LS1 GND1 LR_OUT VCC2 GND_A /IN_HS2 23 IN_HS2 22 /IN_LS2 21 IN_LS2 20 GATE_LS2 19 GND2 18 IS-IN 17 IS+IN 16 C1 15
MC33253
This document contains information on a new product. Specifications and information herein are subject to change without notice.
12/98 (c) Motorola, Inc. 1998
MOTOROLA ANALOG IC DEVICE DATA
REV 0
1
MC33253
SIMPLIFIED BLOCK DIAGRAM
C1 VCC UV/OV Detect VCC G_EN VDD VCC VCC RDY EN GND VCC2 VCC2 EN GND Linear Reg +13.5 V +5.0 V +13.5 V VDD CP_OUT Charge Pump C1 C2 Vpos +13.5 V VCC2 VCC2 VCC VCC C2
VCC CCS
LR_OUT
BRG_EN BRG_EN IN_HS1 VCC VCC IN_HS1 VCC Input & CCS LOGIC VCC VCC IN_LS1 VCC
CCS CCS
HIGH AND LOW SIDE CONTROL WITH CHARGE PUMP
Vgs_ls Vgs_ls VCC
Vgs_hs
VDD/VPOS Level Shift
Pulse Generator G_LOW_HS G_LOW_LS
IN Output Driver
OUT
GATE_HS SRC_HS
IN_LS1
VDD/VCC Level Shift
Pulse Generator
IN
Output Driver
OUT
GATE_LS
HIGH AND LOW SIDE CHANNEL WITH CROSS CONDUCTION SUPPRESSION
Figure 1. Principal Building Blocks
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MOTOROLA ANALOG IC DEVICE DATA
MC33253
C1 G_EN
C2 VCC CP_OUT VCC2 Vgs_ls Vgs_hs LR_OUT 5.5 V... 28 V GATE_HS1 SRC_HS1 GATE_LS1 5.5 V... 55 V
HIGH AND LOW SIDE CONTROL WITH CHARGE PUMP CCS BRG_EN CCS IN_HS1 IN_HS1 IN_LS1 IN_LS1 VCC VDD
BRG_EN CCS
VCC VDD Vgs_ls HIGH AND LOW SIDE CHANNEL WITH CROSS CONDUCTION SUPPRESSION VCC VDD
Vgs_hs
IN_HS2 IN_HS2 IN_LS2 IN_LS2
BRG_EN CCS
VCC
VDD
Vgs_ls
Vgs_hs
GATE_HS2 SRC_HS2 GATE_LS2
HIGH AND LOW SIDE CHANNEL WITH CROSS CONDUCTION SUPPRESSION
SENSE CURRENT AMPLIFIER VDD
- + IS+IN IS-IN
GND
ISOUT
Figure 2. Block Diagram
MOTOROLA ANALOG IC DEVICE DATA
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MC33253
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to GND. Rating Supply Voltage 1 Supply Voltage 2 Linear Regulator Output Voltage High Side Floating Supply Absolute Voltage High Side Floating Supply Offset Voltage High Side Floating Output Voltage Low Side Output Voltage Logic Input Voltage Max VPOSHS Slew Rate Max VGATELS/HS Slew Rate Power Dissipation and Thermal Characteristics Maximum Power Dissipation Thermal Resistance Junction-to-Air Operating Junction Temperature Storage Temperature PD RqJA TJ Tstg W C/W C C Symbol VCC VCC2 VBST_out VLR_out VPOS_HS VCP_OUT VSRCHS VGATEHS VGATELS VIN dVPOSHS/dt dVGATE/dt Min -0.3 -0.3 -0.3 -0.3 -1.0 VSRCHS-0,3 -0.3 -0.3 -- -- Max 60 28 28 65 65 VSRCHS+14 (and <65 V) 14 10 50 50 V/ns Unit VDC
-40 -65
+150 +150
OPERATING CONDITIONS (Typical values for TA = 25C, Min/Max values for TA = -40C to +125C)
Rating Supply Voltage (Power Stage) Supply Voltage 2 (VBATT) (Note 2) High Side Floating Supply Absolute Voltage (Note 1) High Side Floating Supply Offset Voltage High Side Floating Output Voltage Low Side Output Voltage High Side Floating Output Voltage Low Side Output Voltage Logic Input Voltage Ambient Temperature Range Note 1: The minimum voltage is calculated for VCC2 = 6.0 V Note 2: VCC2 = 28 V can be withstand only at TA = 85C (Jump Start Condition!) ON (Note 1) ON OFF OFF Symbol VCC VCC2 VPOS_HS VCP_OUT VSRCHS VGATEHS VGATELS VGATEHS VGATELS VIN TA Min 5,5 5,5 VCC+4 -0.7 VSRCHS+4V VCC2 - 1 -- -- 0 -40 Max 55 28 VCC+14 but <65 VCC +0.7 VSRCHS+14 14 VSRCHS+0,5 0,5 5.0 +125 Unit V V V VDC V V V V V C
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MOTOROLA ANALOG IC DEVICE DATA
MC33253
STATIC ELECTRICAL CHARACTERISTICS VCC = 12 V, VCC2 = 12 V, CCP = 300 nF, G_EN = 4.5 V unless otherwise specified. The logic input parameters (VIN, IIN) are referenced to GND. The gate drive outputs are referenced to GND. (Typical values for TA = 25C, Min/Max values for TA = -40C to +125C, unless otherwise specified)
Characteristic LOGIC SECTION Logic "1" Input Voltage (IN_LS & IN_HS) Logic "0" Input Voltage (IN_LS & IN_HS) Wake Up Input Voltage (G_EN) Wake Up Current (G_EN) VG_EN = 14 V LINEAR REGULATOR SECTION VGS Linear Regulator VIrout @ VCC2 = 28 V VGS Linear Regulator VIrout @ VCC2 12 V CHARGE PUMP SECTION Charge Pump Output Voltage (Note 1) IPOS = 0 mA Charge Pump Output Voltage (Note 1) IPOS = 7 mA Charge Pump Output Average Current Half Bridge (Note 4) Charge Pump Output Average Current Full Bridge (Note 4) UNDER/OVERVOLTAGE SECTION Under Voltage Shutdown VCC2 Under Voltage Shutdown VCC Over Voltage Shutdown VCC Over Voltage Shutdown VCC2 OUTPUT SECTION Nom. Sink Current (turned off) VGS = 1.0 V Nom. Source Current (turned on) Vpos_hs, VG = 1.0 V Peak Current (turn off) VGS = 12 V (Note 4) Peak Current (turn on) VGS = 0 V (Note 4) SENSE CURRENT AMPLIFIER SECTION (Internal VCC supply @ 5V) Output Dynamic Range Open Loop Gain (at 25C) (Note 4) Input Bias Input Offset Voltage Input Common Mode Range Sink Capability Source Capability Gain Bandwidth Product SUPPLY SECTION Quiescent Supply Current VCC2 (G_EN = 0) (Note 2) Quiescent Supply Current VCC (G_EN = 0) (Note 2) Supply Current VCC Supply Current VCC2 13 1 1 13 IQSD IQSD IOP IOP - - - - - - - - 20 20 TBD TBD A A mA mA 28 28 16, 17 16, 17 28 VO A IIB Vio VICR Isink Isource GBW - - - - - - - - - 50 200 2.0 - 100 2.0 2.0 4.0 - 500 5.0 3.0 300 5.0 - V dB V mV V A mA mHz 5, 10 19, 19 24 IO- IO+ IOSK IOSS - - - - 100 100 1000 1000 - - - - mA mA mA mA 13 1 1 13 UV2 UV OV OV2 5.1 5.1 56 28 5.5 5.5 - - 5.9 5.9 60 32 V V V V 3 3 3 3 VCP_OUT VCP_OUT ICP_OUT ICP_OUT VCC + 10 - - - VCC + 12 VCC + 9 5.0 10 VCC + 14 - - - V V mA mA 12 12 VIrout 12 VCC2 - 1 - - 14 12 V 27 27 VIH VIL VG_EN IG_EN 2.0 - 4.5 ? - - 5.0 V - 10 0.8 VCC2 ? V V V A Pin # Symbol Min Typ Max Unit
DYNAMIC ELECTRICAL CHARACTERISTICS (Typical values for TA = 25C, Min/Max values for TA = -40C to +125C) Charge Pump Start Up Time (Note 4) 3 TON - TBD - Prop. Delay HS and LS between 50% input to 50% output, CI = 5.0 nF TPD - 200 - Skew Propagation Delay HS and LS HS/LS Rise Time @ CI = 5.0 nF, 10% to 90% HS/LS Fall Time @ CI = 5.0 nF, 90% to 10%
NOTE 1 NOTE 2 NOTE 3 NOTE 4
ns ns ns ns ns
TDPD TRISE TFALL
- - -
TBD 80 80
- 180 180
If G_EN is driven low or tri-state, then the charge pump is disabled. G_EN is driven low or tri-state. Rise time is given by time needed to charge the gate from 1.0 V to 10 V (vica versa for fall time) Characterization only
MOTOROLA ANALOG IC DEVICE DATA
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MC33253
Driver Characteristics Turn-On: For turn-on the current required to charge the gate source capacitor Ciss in the specified time can be calculated as follows: Peak Current for Rise/Fall Time (tr) and a typical PowerMosFET Gate Charge Qg IP = Qg/tr = 75 nC/80 ns 1.0 A
Flyback Spike charge LS-Gate via Crss Charge Current Irss up to 2.0 A! Uncontrolled Turn-On of Low Side FET Crss VBAT Flyback Spike pull down HS- Drain VGS Increase Delayed Turn-Off of High Side FET Crss VBAT OFF g_hs L1 g_hs ILOAD Ciss Crss L1 ILOAD Ciss Crss g_hs VGATE -VDRN L1 ILOAD Ciss Crss
Turn-Off: Basically, the peak current for turn-off can be obtained in the same way as for turn-on. In addition to the dynamically current, required to turn-off or turn-on the FET, various application related switching scenarios have to be considered:
Flyback Spike charge LS-Gate via Crss Charge Current Irss up to 2.0 A! Delayed Turn-Off of Low Side FET Crss VBAT
Flyback Spike pull down HS- Drain VGS Increase Uncontrolled Turn-On of High Side FET Crss OFF g_hs L1 ILOAD VBAT
Ciss Irss VGATE g_ls OFF Ciss Driver Requirement: Low Resistive Gate-Source Path during OFF-State Crss
g_ls OFF Ciss Driver Requirement: Low Resistive Gate Source Path during OFF-State. High Peak Sink Current Capab.
g_ls
g_ls
Ciss Driver Requirement: High Peak Sink Current Capab.
Ciss Driver Requirement: Low Resistive Gate-Source Path during OFF-State
The output driver sources a peak current of up to 1A for 200 ns to turn on the gate. After 200 ns 100 mA are provided continuously to maintain the gate charged. The output driver sinks a peak current of up to 1A for 200 ns to turn off the gate. After 200 ns 100 mA are sinked continuously to maintain the gate discharged. In order to withstand high dV/dt spikes (up to 10 V/ns) a low resistive path between gate and source is implemented during the off state. Driver Supply The High Side Driver is supplied from the internal charge pump buffered at CP_OUT. The low-drop regulator provides approx. 3.5 mA per gate. In case of the full bridge that means approx. 14 mA, 7.0 mA for the high side and 7.0 mA for the low side. (Note: The average current required to switch a gate with a frequency of 100 kHz is: Average Current (Charge Pump) for PWM Frq. (fPWM) ICP = Qg*fPWM = 75 nC*100 kHz = 7,5 mA A full bridge application switch only one high side and one low side at the same time.)
The Charge Pump and Linear Reg. output are buffered externally with a capacitor in order to supply high peak currents. The Low Side Driver is supplied from low drop regulator directly, buffered at LR_OUT in order to supply the high peak currents.
Gate Protection The low side gate is protected by the internal linear regulator, which guarantees that VGATE_LS does not exceed the maximum VGS. Especially when working with the charge pump the voltage at POS_HS can be up to 65 V! (VCC + 14 V). The high side gate is clamped internally, in order to avoid a VGS exceeding 14 V. The Gate protection does not include a Flyback Voltage Clamp that protects the driver and the external FET from a Flyback voltage that can appear when driving inductive load. This Flyback voltage can reach high negative voltage values and needs to be clamped externally.
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MOTOROLA ANALOG IC DEVICE DATA
MC33253
Vgs_ls Vgs_hs M1 IN Output Driver G_LOW OUT GATE_HS VGS < 14 V under all conditions L1 M2 IN Output Driver OUT GATE_LS Inductive Flyback Voltage Clamp VCC
SRC_HS Dcl
G_LOW
Figure 3. Gate Protection and Flyback Voltage Clamp
TMOS Failure Protection All output driver stages are protected against TMOS failure conditions. If one of the external power FETs is destroyed (Gate = VCC, or Gate = Gnd) the function of the remaining output driver stages is not affected. All output drivers are short circuit protected against short circuits to ground or VCC.
Cross Conduction Suppression The purpose of the cross conduction suppression is to avoid that high and low side FET are turned on at the same time, which prevents the half bridge power FETs of a shoot- through condition. The CCS can be disabled / enabled by an external signal (/CCS).
MOTOROLA ANALOG IC DEVICE DATA
7
MC33253
VCC G_EN AND AND EN_CP/LDO UV_OV VCC CCS VDD VCC IN_HS 10 k AND 10 k IN_HS VDD 10 k AND VCC AND OR en1_ls VCC IN_LS AND drv_ls en2_ls AND G_LOW_LS "1" FET is Turned-Off OUT_LS "1" Turn-On FET VCC en1_hs OR en2_hs drv_hs AND OUT_HS "1" Turn-On FET G_LOW_HS "1" FET is Turned-Off BRG_EN CCS ChP_RDY "0" Cross Conduction Suppression is Enabled en2hs = G_LOW_LS, en2ls = G_LOW_HS en1hs = drv_ls, en1ls = drv_hs "1" Cross Conduction Suppression is Disabled en2hs = "1", en2ls = "1" en1hs = "0", en1ls = "0" "1" Enable Charge Pump and LDO "1" Supply is ok "0" Under Voltage or Over Voltage Condition "1" Charge Pump is Ready
IN_LS
Figure 4. Input Logic and Cross Conduction Suppression
Logic Inputs Logic Input Voltage Range: (Max. Operating) -0.3 V ... 10 V Wake Up Function: (G_EN) 4.5 V ... VCC2 During Wake-Up the logic is supplied from the G_EN pin. Low Drop Linear Regulator The low drop linear regulator provides the 5.0 V for the logic section of the driver, the Vgs_ls buffered at LR_OUT and the +13.5 V for the charge pump, which generates the Vgs_hs. The low drop linear regulator provides 3.5 mA average current per driver stage. If VCC2 exceeds 14 V the output is limited to 14 V. Charge Pump The charge pump generates the high side driver supply voltage (Vgs_hs), buffered at CP_OUT. Vgs_hs = VCC + VCC2 - 1.2 V. The average output current is ICP = 3.5 mA per output driver.
The charge pump charges an external storage capacitor, which provides the peak switching current to the output drivers. Sense Current OP-Amp Typically shunt resistivity is dimensioned as low as possible (1.0 mOhm/10 A). The typical voltage generated by sensing the current is in the range of 10 mV. The A/D input of typical micro controller is in the range of 1.0 V. That requires a voltage gain of 100. Over / Under Voltage Shutdown The under voltage protection becomes active at VCC below 6.0 V and the overvoltage protection is activated at VCC above 55 V or at VCC2 above 28 V. If the OUV protection is activated the outputs are driven low, in order to switch off the FETs. Protection A protection against double battery and load dump spikes up to 55 V is given by VCC = 55 V. A protection against reverse polarity is given by the external power FET with the free wheeling diodes, forming a conducting pass from ground to VCC. An additional protection is not provided within the circuit.
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MOTOROLA ANALOG IC DEVICE DATA
MC33253
APPLICATION DIAGRAM
Both applications utilize the internal charge pump to provide the high side floating voltage. This voltage can be provided by an external source also.
VBAT VLOGIC VCC /G_EN /DLY_EN C1 C2 IN_HS1 IN_LS1 IN_HS2 IN_LS2 ISOUT R1 LR_OUT CP_OUT
C1
C3
M1
M3
C2 CAN PWM1 PWM2 PWM3 PWM4 HS_1 LS_1 HS_2 LS_2 CURRENT FDBK
GATE_HS1 SRC_HS1 FULL BRIDGE DRIVER GATE_LS1 DRN_LS1 GATE_HS2 SRC_HS2 GATE_LS2 ISIN ISIN GND G G Lm
M2
M4
mC
SS R2 Rsh
SL
SS
SL
Figure 5. DC Motor Control with Micro Controller
VBAT ON/OFF VCC /G_EN /DLY_EN C1 C2 IN_HS1 LEFT/RIGHT IN_LS1 IN_HS2 IN_LS2 LR_OUT CP_OUT
C1
C3
M1
M3
C2
GATE_HS1 SRC_HS1 FULL BRIDGE DRIVER GATE_LS1 DRN_LS1 GATE_HS2 SRC_HS2 GATE_LS2 ISIN ISIN GND Lm
M2
M4
Figure 6. DC Motor Control (low cost)
MOTOROLA ANALOG IC DEVICE DATA
9
MC33253
PIN DEFINITIONS
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Symbol VCC C2 CP_OUT SRC_HS1 GATE_HS1 /IN_HS1 IN_HS1 /IN_LS1 IN_LS1 GATE_LS1 GND1 LR_OUT VCC2 GND_A C1 IS+ IS- GND2 GATE_LS2 IN_LS2 /IN_LS2 IN_HS2 /IN_HS2 GATE_HS2 SRC_HS2 /CCS G_EN IS_OUT Supply 1 Charge Pump Capacitor Charge Pump Out Source 1 Output High Side Gate 1 Output High Side Neg. Input High Side 1 Pos. Input High Side 1 Neg. Input Low Side 1 Pos. Input Low Side 1 Gate 1 Output Low Side Ground Linear Regulator Output Supply 2 Analog Ground Charge Pump Capacitor Sense OpAmp Pos. Input Sense OpAmp Neg. Input Ground 2 Gate 2 Output Low Side Pos. Input Low Side 2 Neg. Input Low Side 2 Pos. Input High Side 2 Neg. Input High Side 2 Gate 2 Output High Side Source 2 Output High Side Enable Cross Conduction Supression Global Enable Sense Current OpAmp Output Pin Description
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MOTOROLA ANALOG IC DEVICE DATA
MC33253
PACKAGE DIMENSIONS
A
D
28 15 M
NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSIONS. 4. MAXIMUM MOLD PROTRUSION 0.015 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS MIN MAX 2.35 2.65 0.13 0.29 0.35 0.49 0.23 0.32 17.80 18.05 7.40 7.60 1.27 BSC 10.05 10.55 0.41 0.90 0_ 8_
E
H
1 14 PIN 1 IDENT
B
0.25
M
B
L 0.10
SEATING PLANE
e B 0.025
M
C
DIM A A1 B C D E e H L
A1
A
C CA
S
B
q
q
S
CASE 751F-05 ISSUE F
MOTOROLA ANALOG IC DEVICE DATA
11
MC33253
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. Mfax is a trademark of Motorola, Inc. How to reach us: USA / EUROPE / Locations Not Listed: Motorola Literature Distribution; P.O. Box 5405, Denver, Colorado 80217. 1-303-675-2140 or 1-800-441-2447 Customer Focus Center: 1-800-521-6274 MfaxTM: RMFAX0@email.sps.mot.com - TOUCHTONE 1-602-244-6609 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, Motorola Fax Back System - US & Canada ONLY 1-800-774-1848 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298 - http://sps.motorola.com/mfax/ HOME PAGE: http://motorola.com/sps/ JAPAN: Nippon Motorola Ltd.; SPD, Strategic Planning Office, 141, 4-32-1 Nishi-Gotanda, Shinagawa-ku, Tokyo, Japan. 81-3-5487-8488
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MC33253/D MOTOROLA ANALOG IC DEVICE DATA

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