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| SN74LS156 Dual 1-of-4 Decoder/ Demultiplexer The SN74LS156 is a high speed Dual 1-of-4 Decoder/ Demultiplexer. This device has two decoders with common 2-bit Address inputs and separate gated Enable inputs. Decoder "a" has an Enable gate with one active HIGH and one active LOW input. Decoder "b" has two active LOW Enable inputs. If the Enable functions are satisfied, one output of each decoder will be LOW as selected by the address inputs. The LS156 has open collector outputs for wired-OR (DOT-AND) decoding and function generator applications. The LS156 is fabricated with the Schottky barrier diode process for high speed and are completely compatible with all ON Semiconductor TTL families. http://onsemi.com LS156-OPEN-COLLECTOR LOW POWER SCHOTTKY * * * * * * Schottky Process for High Speed Multifunction Capability Common Address Inputs True or Complement Data Demultiplexing Input Clamp Diodes Limit High Speed Termination Effects ESD > 3500 Volts 16 1 PLASTIC N SUFFIX CASE 648 GUARANTEED OPERATING RANGES Symbol VCC TA VOH IOL Parameter Supply Voltage Operating Ambient Temperature Range Output Voltage - High Output Current - Low Min 4.75 0 Typ 5.0 25 Max 5.25 70 5.5 8.0 Unit V C V mA 16 1 SOIC D SUFFIX CASE 751B ORDERING INFORMATION Device SN74LS156N SN74LS156D Package 16 Pin DIP 16 Pin Shipping 2000 Units/Box 2500/Tape & Reel (c) Semiconductor Components Industries, LLC, 1999 1 December, 1999 - Rev. 0 Publication Order Number: SN74LS156/D SN74LS156 CONNECTION DIAGRAM DIP (TOP VIEW) VCC 16 Eb 15 Eb 14 A0 13 O3b 12 O2b 11 O1b 10 O0b 9 NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package. 1 Ea 2 Ea 3 A1 4 O3a 5 O2a 6 O1a 8 7 O0a GND LOADING (Note a) PIN NAMES A0, A1 Ea, Eb Ea O0 - O3 Address Inputs Enable (Active LOW) Inputs Enable (Active HIGH) Input Active LOW Outputs HIGH 0.5 U.L. 0.5 U.L. 0.5 U.L. 10 U.L. LOW 0.25 U.L. 0.25 U.L. 0.25 U.L. 5 U.L. NOTES: a) 1 TTL Unit Load (U.L.) = 40 mA HIGH/1.6 mA LOW. LOGIC SYMBOL 12 13 3 14 15 E DECODER a 0 1 2 3 A0 A1 A0 A1 0 1 E DECODER b 2 3 7 6 5 4 9 10 11 12 VCC = PIN 16 GND = PIN 8 http://onsemi.com 2 SN74LS156 LOGIC DIAGRAM Ea Ea 1 2 13 A0 A1 3 14 Eb Eb 15 7 6 5 4 9 10 11 12 O0a O1a O2a O3a O0b O1b O2b O3b VCC = PIN 16 GND = PIN 8 = PIN NUMBERS FUNCTIONAL DESCRIPTION The LS156 is a Dual 1-of-4 Decoder/Demultiplexer with common Address inputs and separate gated Enable inputs. When enabled, each decoder section accepts the binary weighted Address inputs (A0, A1) and provides four mutually exclusive active LOW outputs (O0 - O3). If the Enable requirements of each decoder are not met, all outputs of that decoder are HIGH. Each decoder section has a 2-input enable gate. The enable gate for Decoder "a" requires one active HIGH input and one active LOW input (Ea*Ea). In demultiplexing applications, Decoder "a" can accept either true or complemented data by using the Ea or Ea inputs respectively. The enable gate for Decoder "b" requires two active LOW inputs (Eb*Eb). The LS155 or LS156 can be used as a 1-of-8 Decoder/Demultiplexer by tying Ea to Eb and relabeling the common connection as (A2). The other Eb and Ea are connected together to form the common enable. The LS156 can be used to generate all four minterms of two variables. These four minterms are useful in some applications replacing multiple gate functions as shown in Fig. a. The LS156 has the further advantage of being able to AND the minterm functions by tying outputs together. Any number of terms can be wired-AND as shown below. f = (E + A0 + A1) (E + A0 + A1) (E + A0 + A1) (E + A0 + A1) where E = Ea + Ea; E = Eb + Eb E A0 A1 E A0 A1 E A0 A1 E A0 A1 E O0 A0 A1 E O1 A0 A1 E O2 A0 A1 E O3 A0 A1 O0 O1 O2 O3 Figure a TRUTH TABLE ADDRESS A0 X X L H L H A1 X X L L H H ENABLE "a" Ea L X H H H H Ea X H L L L L O0 H H L H H H OUTPUT "a" O1 H H H L H H O2 H H H H L H O3 H H H H H L ENABLE "b" Eb H X L L L L Eb X H L L L L O0 H H L H H H OUTPUT "b" O1 H H H L H H O2 H H H H L H O3 H H H H H L H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care http://onsemi.com 3 SN74LS156 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK IOH VOL Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Current 0.25 Output LOW Voltage 0.35 Input HIGH Current 0.1 Input LOW Current Power Supply Current - 0.4 10 0.5 20 IIH IIL ICC V A mA mA mA - 0.65 Min 2.0 0.8 - 1.5 100 0.4 Typ Max Unit V V V A V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for All Inputs VCC = MIN, IIN = - 18 mA VCC = MIN, VOH = MAX IOL = 4.0 mA IOL = 8.0 mA VCC = VCC MIN, VIN = VIL or VIH per Truth Table VCC = MAX, VIN = 2.7 V VCC = MAX, VIN = 7.0 V VCC = MAX, VIN = 0.4 V VCC = MAX AC CHARACTERISTICS (TA = 25C) Limits Symbol tPLH tPHL tPLH tPHL tPLH tPHL Parameter Propagation Delay Address, Ea or Eb to Output Propagation Delay Address to Output Propagation Delay Ea to Output Min Typ 25 34 31 34 32 32 Max 40 51 46 51 48 48 Unit ns ns ns Figure 1 Figure 2 Figure 1 VCC = 5.0 V CL = 15 pF RL = 2.0 k Test Conditions AC WAVEFORMS VIN 1.3 V tPHL 1.3 V tPLH 1.3 V VIN 1.3 V tPHL 1.3 V tPLH 1.3 V VOUT 1.3 V VOUT 1.3 V Figure 1. Figure 2. http://onsemi.com 4 SN74LS156 PACKAGE DIMENSIONS N SUFFIX PLASTIC PACKAGE CASE 648-08 ISSUE R -A- 16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M S INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01 B 1 8 F S C L -T- H G D 16 PL SEATING PLANE K J TA M M 0.25 (0.010) M http://onsemi.com 5 SN74LS156 PACKAGE DIMENSIONS D SUFFIX PLASTIC SOIC PACKAGE CASE 751B-05 ISSUE J -A- NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019 16 9 -B- 1 8 P 8 PL 0.25 (0.010) M B S G F K C -T- SEATING PLANE R X 45 _ M D 16 PL M J 0.25 (0.010) TB S A S DIM A B C D F G J K M P R http://onsemi.com 6 SN74LS156 Notes http://onsemi.com 7 SN74LS156 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. PUBLICATION ORDERING INFORMATION North America Literature Fulfillment: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: ONlit@hibbertco.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada EUROPE: LDC for ON Semiconductor - European Support German Phone: (+1) 303-308-7140 (M-F 2:30pm to 5:00pm Munich Time) Email: ONlit-german@hibbertco.com French Phone: (+1) 303-308-7141 (M-F 2:30pm to 5:00pm Toulouse Time) Email: ONlit-french@hibbertco.com English Phone: (+1) 303-308-7142 (M-F 1:30pm to 5:00pm UK Time) Email: ONlit@hibbertco.com ASIA/PACIFIC: LDC for ON Semiconductor - Asia Support Phone: 303-675-2121 (Tue-Fri 9:00am to 1:00pm, Hong Kong Time) Toll Free from Hong Kong 800-4422-3781 Email: ONlit-asia@hibbertco.com JAPAN: ON Semiconductor, Japan Customer Focus Center 4-32-1 Nishi-Gotanda, Shinagawa-ku, Tokyo, Japan 141-8549 Phone: 81-3-5487-8345 Email: r14153@onsemi.com Fax Response Line: 303-675-2167 800-344-3810 Toll Free USA/Canada ON Semiconductor Website: http://onsemi.com For additional information, please contact your local Sales Representative. http://onsemi.com 8 SN74LS156/D |
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