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SN54/74LS353 DUAL 4-INPUT MULTIPLEXER WITH 3-STATE OUTPUTS
The LSTTL / MSI SN54 / 74LS353 is a Dual 4-Input Multiplexer with 3-state outputs. It can select two bits of data from four sources using common select inputs. The outputs may be individually switched to a high impedance state with a HIGH on the respective Output Enable (E0) inputs, allowing the outputs to interface directly with bus oriented systems. It is fabricated with the Schottky barrier diode process for high speed and is completely compatible with all TTL families.
DUAL 4-INPUT MULTIPLEXER WITH 3-STATE OUTPUTS
LOW POWER SCHOTTKY
* * * *
Inverted Version of the SN54 / 74LS253 Schottky Process for High Speed Multifunction Capability Input Clamp Diodes Limit High Speed Termination Effects CONNECTION DIAGRAM DIP (TOP VIEW)
VCC 16 E0b 15 S0 14 I3b 13 I2b 12 I1b 11 I0b 10 Zb 9
NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package. 16 1
J SUFFIX CERAMIC CASE 620-09
16 1
N SUFFIX PLASTIC CASE 648-08
1 E0a
2 S1
3 I3a
4 I2a
5 I1a
6 I0a
7 Za
8 GND
16 1
D SUFFIX SOIC CASE 751B-03
PIN NAMES
LOADING (Note a) HIGH LOW 0.25 U.L.
ORDERING INFORMATION
SN54LSXXXJ SN74LSXXXN SN74LSXXXD Ceramic Plastic SOIC
S0, S1 Multiplexer A E0a I0A - I3a Za Multiplexer B E0b I0b - I3b Zb
Common Select Inputs
0.5 U.L.
Output Enable (Active LOW) Input Multiplexer Inputs Multiplexer Output (Note b)
0.5 U.L. 0.5 U.L. 65 (25) U.L.
0.25 U.L. 0.25 U.L. 15 (7.5) U.L.
LOGIC SYMBOL
Output Enable (Active LOW) Input Multiplexer Inputs Multiplexer Output (Note b) 0.5 U.L. 0.5 U.L. 65 (25) U.L. 0.25 U.L. 0.25 U.L. 15 (7.5) U.L.
1
6
54
3
10 11 12 13 15 I0b I1b I2b I3b E0b
NOTES: a) 1 TTL Unit Load (U.L.) = 40 A HIGH/1.6 mA LOW. b) The Output LOW drive factor is 7.5 U.L. for Military (54) and 15 U.L. for Commercial (74) Temperature Ranges. The Output HIGH drive factor is 25 U.L. for Military and 65 U.L. for Commercial Temperature Ranges.
14 2
E0a I0a I1a I2a I3a S0 S1 Za
Zb
7 VCC = PIN 16 GND = PIN 8
9
FAST AND LS TTL DATA 5-1
SN54/74LS353
LOGIC DIAGRAM
E0b
15
I3b
13
I2b
12
I1b
11
I0b
10
S0
14
S1
2
I3a
3
I2a
4
I1a
5
I0a
6
E0a
1
9
Zb
VCC = PIN 16 GND = PIN 8 = PIN NUMBERS
7
Za
FUNCTIONAL DESCRIPTION The SN54 / 74LS353 contains two identical 4-input Multiplexers with 3-state outputs. They select two bits from four sources selected by common select inputs (S0, S1). The 4-input multiplexers have individual Output Enable (E0a, E0b)
inputs which when HIGH, forces the outputs to a high impedance (high Z) state. The logic equations for the outputs are shown below:
Za = E0a * (I0a * S1 * S0 + I1a * S1 * S0 + I2a * S1 * S0 + I3a * S1 * S0) Zb = E0b * (I0b * S1 * S0 + I1b * S1 * S0 + I2b * S1 * S0 + I3b * S1 * S0) If the outputs of 3-state devices are tied together, all but one device must be in the high impedance state to avoid high currents that would exceed the maximum ratings. Designers should ensure that Output Enable signals to 3-state devices whose outputs are tied together are designed so that there is no overlap.
TRUTH TABLE
SELECT INPUTS S S0 X L L H H L L H H S1 X L L L L H H H H I0 X L H X X X X X X DATA INPUTS I1 X X X L H X X X X I2 X X X X X L H X X I3 X X X X X X X L H OUTPUT ENABLE E0 H L L L L L L L L OUTPUT Z (Z) H L H L H L H L
H = HIGH Level L = LOW Level X = Immaterial (Z) = High Impedance (off) Address inputs S0 and S1 are common to both sections.
FAST AND LS TTL DATA 5-2
SN54/74LS353
GUARANTEED OPERATING RANGES
Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current -- High Output Current -- Low Parameter 54 74 54 74 54 74 54 74 Min 4.5 4.75 -55 0 Typ 5.0 5.0 25 25 Max 5.5 5.25 125 70 - 1.0 -2.6 12 24 Unit V C mA mA
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits Symbol S bl VIH VIL VIK VOH Parameter P Input HIGH Voltage 54 Input LOW Voltage 74 Input Clamp Diode Voltage 54 Output HIGH Voltage 74 Output LOW Voltage p g QA - QH Output Off Current HIGH Output Off Current LOW Input HIGH Current 0.1 Input LOW Current Short Circuit Current (Note 1) Power Supply Current Total, Output 3-State Total, Output LOW - 20 - 0.4 - 130 14 12 54, 74 74 2.4 3.1 0.25 0.35 0.4 0.5 20 - 20 20 IIH IIL IOS ICC V V V A A A mA mA mA 2.4 - 0.65 3.4 0.8 - 1.5 V V Min 2.0 0.7 V Typ Max Unit Ui V Test C di i T Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for p g All Inputs VCC = MIN, IIN = - 18 mA VCC = MIN, IOH = MAX, VIN = VIH , , or VIL per Truth Table IOL = 12 mA IOL = 24 mA VCC = VCC MIN, VIN = VIL or VIH per Truth Table
VOL IOZH IOZL
VCC = MAX, VOUT = 2.7 V VCC = MAX, VOUT = 0.4 V VCC = MAX, VIN = 2.7 V VCC = MAX, VIN = 7.0 V VCC = MAX, VIN = 0.4 V VCC = MAX VCC = MAX
mA
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
AC CHARACTERISTICS (TA = 25C, VCC = 5.0 V)
Limits Symbol S bl tPLH tPHL tPLH tPHL tPZH tPZL tPLZ tPHZ Parameter P Propagation Delay, Data to Output Propagation Delay, Select to Output Output Enable Time to HIGH Level Output Enable Time to LOW Level Output Disable Time to LOW Level Output Disable Time to HIGH Level Min Typ 11 13 20 21 11 15 12 27 Max 25 20 45 32 23 23 27 41 Unit Ui ns ns ns ns ns ns Figure 1 Figure 1 or 2 CL = 15 pF F Figures 4, 5 Figures 3, 5 Figures 3, 5 CL = 5.0 pF 50 Figures 4, 5 Test C di i T Conditions
FAST AND LS TTL DATA 5-3
SN54/74LS353
3-STATE WAVEFORMS
VIN
1.3 V tPLH
1.3 V tPHL 1.3 V
VIN
1.3 V tPLH
1.3 V tPHL 1.3 V
VOUT
1.3 V
VOUT
1.3 V
Figure 1
Figure 2
VE 1.5 V VE VOUT tPZL 1.5 V 0.5 V 1.5 V tPLZ 1.5 V VOL
VE 1.5 V VE tPZH 1.5 V VOUT tPHZ 1.5 V VOH 1.5 V 0.5 V
Figure 3
Figure 4
AC LOAD CIRCUIT
VCC
SWITCH POSITIONS
RL SW1 SYMBOL tPZH tPZL TO OUTPUT UNDER TEST tPLZ tPHZ SW1 Open Closed Closed Closed SW2 Closed Open Closed Closed
5.0 k CL* SW2
* Includes Jig and Probe Capacitance.
Figure 5
FAST AND LS TTL DATA 5-4

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