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| QL58x0 Enhanced QuickPCI Target Family Data Sheet * * * * * * 33/66 MHz/32-bit PCI Target with Embedded Programmable Device Highlights High Performance PCI Controller * 33/66 MHz 32-bit PCI Target * Zero-wait state PCI Target provides up to 264 MBps transfer rates * Target interface supports retry, disconnect with/without data transfer, and target abort * Fully programmable back-end interface * Independent PCI bus (33/66 MHz) and local bus (up to 160 MHz) clocks * Fully customizable PCI Configuration Space * Configurable FIFOs with depths up to 256 words * Reference design with driver code (Win 95/98/2000/NT 4.0) available * PCI v2.3 compliant * Supports Type 0 configuration cycles * 3.3 V PCI signaling * 1.8 V supply voltage * 484-ball PBGA, 280-ball LFBGA, 208-pin PQFP, 196-ball TFBGA, and 144-pin TQFP packages * Unlimited/Continuous Burst Transfers supported Figure 1: QL58x0 Block Diagram PCI Bus 33/66 MHz/32 bits (data and address) Logic, Embedded Computational Units, and Dual Port SRAM Extendable PCI Functionality * Support for Configuration Space from 0 x 40 to 0 x 3FF * PCI v2.3 Power Management Spec. compatible * PCI v2.3 Vital Product Data (VPD) configuration support Flexible Programmable Logic * Up to 1,478 logic cells * Up to 50,688 RAM bits * Up to 264 I/O pins * All back-end interface and glue-logic can be implemented on chip * Two 32-bit busses interface between the PCI Controller and the Programmable Logic * Up to twenty-two 2,304 bit dual-port high performance SRAM blocks * Up to 3,748 flip-flops available High Speed Data Path Target Controller 32 bit Interface Programmable Logic 264 User I/O 160 MHz FIFOs PCI Bus High Speed Logic Cells Config. Space (c) 2005 QuickLogic Corporation www.quicklogic.com * * * * * * 1 QL58x0 Enhanced QuickPCI Target Family Data Sheet Rev. I Architecture Overview The QL58x0 device family of QuickPCI Embedded Standard Products (ESPs) provides a complete and customizable PCI interface solution combined with programmable logic. Since the QL58x0 devices provide optimized pre-verified PCI cores, the burden of PCI timing closure and PCI protocol compliance has been eliminated and allows for the maximum 32-bit PCI bus bandwidth (264 MBps). The programmable logic portion of this family contains up to 1,478 QuickLogic Logic Cells and up to 22 QuickLogic Dual-Port RAM Blocks. These configurable RAM blocks can be configured in many width/depth combinations. They can also be combined with logic cells to form FIFOs, or be initialized via Serial EEPROM on power-up and used as ROMs. The QL58x0 device meets PCI 2.3 electrical and timing specifications and has been fully hardware-tested. The QL58x0 device features 1.8 V operation with multi-volt compatible I/Os. The device can easily operate in 3.3 V embedded systems and is fully compatible with 3.3 V applications. PCI Controller The PCI Controller is a 33/66 MHz 32-bit PCI 2.3 compliant Target Controller capable of infinite length Target Write and Read transactions at zero wait states (264 MBps). The Target interface offers full PCI Configuration Space and flexible target addressing. It supports zero-waitstate target Write and Read operations. It also supports retry, disconnect with/without data transfer, and target abort requested by the back end. Any number of 32-bit BARs may be configured as either memory or I/O space. All required and optional PCI 2.3 Configuration Space registers can be implemented within the programmable region of the device. A reference design of a Target Configuration Space and Addressing module is available and is included in the QuickWorks design software. The interface ports are designed for target transactions. The Target Configuration Space and Address Decoding are done in the programmable logic region of the device. These functions are not timing critical, so leaving these elements in the programmable region allows the greatest degree of flexibility to the designer. Table 1 shows several commonly implemented IP cores in the programmable logic portion of the Target Controller device. Their respective logic cell utilization and performance information are shown for easy reference. Notice that the Configuration Space and Address Decoding core is labelled as an essential IP core. This IP block is necessary for the Target Controller to be fully functional. The optional IP cores are common interface IP cores made available so that designers may implement according to their design requirements. These optional IP cores do not affect the functionality of the Target Controller. 2 * www.quicklogic.com * * * * * (c) 2005 QuickLogic Corporation QL58x0 Enhanced QuickPCI Target Family Data Sheet Rev. I Table 1: IP Implemented in Programmable Logic Essential PCI IP Cores Configuration Space/Address Decoding Optional IP Cores Async 32x32 FIFO Async 128x32 FIFO SDRAM Controller DDR SDRAM Controller Pulse Width Modulation Logic Cells 110 Logic Cells 64 88 149 216 20 RAM N/A RAM 2 2 N/A N/A N/A Performance 33/66 MHz Performance 210 MHz 190 MHz 160 MHz 100 MHz 303 MHz Configuration Space and Address Decode The configuration space is completely customizable in the programmable region of the device. PCI address and command decoding is performed by logic in the programmable section of the device. This allows support for any size of memory or I/O space for back end logic. It also allows the user to implement any subset of the PCI commands supported by the QL58x0. QuickLogic provides a reference Address Register/Counter and Command Decode block. PCI Interface Symbol Figure 2 shows the graphical interface symbol numbers you have to use in your schematic design in order to attach the local interface programmable logic design to the Target PCI core. If you are designing with a toplevel Verilog or VHDL file, use a structural instantiation of this PCI32TV2 block instead of a graphical symbol. (c) 2005 QuickLogic Corporation www.quicklogic.com * * * * * * 3 QL58x0 Enhanced QuickPCI Target Family Data Sheet Rev. I Figure 2: PCI Interface Symbol 4 * www.quicklogic.com * * * * * (c) 2005 QuickLogic Corporation QL58x0 Enhanced QuickPCI Target Family Data Sheet Rev. I PCI Target Interface Table 2: PCI Target Interface Signal I/O Description Target address, and target Write data. During all target accesses, the address is presented on Usr_Addr_WrData[31:0]; at the same time, Usr_Adr_Valid is active. During O target Write transactions, this port also presents valid Write data to the PCI configuration space or user logic when Usr_Adr_Inc is active. PCI command and byte enables. During target accesses, the PCI command is O presented on Usr_CBE[3:0]; at the same time, Usr_Adr_Valid is active. This port also presents active-low byte enables to the PCI configuration space or user logic. Indicates the beginning of a PCI transaction, and that a target address is valid on Usr_Addr_WrData[31:0] and the PCI command is valid on Usr_CBE[3:0]. When this signal is active, the target address must be latched and decoded to determine if this O address belongs to the device's memory or I/O space. Also, the PCI command must be decoded to determine the type of PCI transaction. On subsequent clocks of a target access, this signal is low, indicating that address is NOT present on Usr_Addr_WrData[31:0]. Indicates that the target address should be incremented, because the previous data transfer has completed. During burst target accesses, the target address is only presented to the back-end logic at the beginning of the transaction (when Usr_Adr_Valid is active), and must therefore be latched and incremented by four for subsequent data O transfers. Note that during target Write transactions, Usr_Adr_Inc indicates valid data on Usr_Addr_WrData[31:0] that must be accepted by the backend logic (regardless of the state of Usr_Rdy). During Read transactions, Usr_Adr_Inc signals to the backend that the PCI core has presented the read data on the PCI bus (TRDYN asserted). This signal should be the combinatorial decode of the "user read" command from Usr_CBE[3:0]. This command may be mapped from any of the PCI Read commands, such as Memory Read, Memory Read Line, Memory Read Multiple, I/O Read, etc. It is internally gated with Usr_Adr_Valid. This signal should be the combinatorial decode of the "user write" command from Usr_CBE[3:0]. This command may be mapped from any of the PCI Write commands, such as Memory Write or I/O Write. It is internally gated with Usr_Adr_Valid. This signal should be driven active when the address on Usr_Addr_WrData[31:0] has been decoded and determined to be within the address space of the device. Usr_Addr_WrData[31:0] must be compared to each of the valid Base Address Registers in the PCI configuration space. Also, this signal must be gated by the Memory Access Enable or I/O Access Enable registers in the PCI configuration space (Command Register bits 1 or 0 at offset 04h). Internally gated with Usr_Adr_Valid. Usr_Addr_WrData[31:0] Usr_CBE[3:0] Usr_Adr_Valid Usr_Adr_Inc Usr_RdDecode I Usr_WrDecode I Usr_Select I Usr_Write This signal is active throughout a "user write" transaction, which has been decoded by Usr_WrDecode at the beginning of the transaction. The Write strobe for individual O DWORDs of data (on Usr_Addr_WrData[31:0]) during a user Write transaction should be generated by logically ANDing this signal with Usr_Adr_Inc. This signal is active throughout a "configuration write" transaction. The Write strobe for O individual DWORDs of data (on Usr_Addr_WrData[31:0]) during a configuration Write transaction should be generated by logically ANDing this signal with Usr_Adr_Inc. I I Data from the PCI configuration registers, required to be presented during PCI configuration reads. Data from the back-end user logic required to be presented during PCI user reads. Cfg_Write Cfg_RdData[31:0] Usr_RdData[31:0] (c) 2005 QuickLogic Corporation www.quicklogic.com * * * * * * 5 QL58x0 Enhanced QuickPCI Target Family Data Sheet Rev. I Table 2: PCI Target Interface (Continued) Signal Cfg_CmdReg6 I/O I Description Bit 6 from the Command Register in the PCI configuration space (offset 04h). Parity Error Response. If high, the core uses PERRN to report data parity errors. Otherwise it never drives it. Bit 8 from the Command Register in the PCI configuration space (offset 04h). SERRN Enable. If high, the cores uses SERRN to report address parity errors if Cfg_CmdReg6 is high. Parity error detected on the PCI bus. When this signal is active, bit 15 of the Status Register must be set in the PCI configuration space (offset 04h). Cfg_CmdReg8 I Cfg_PERR_Det O Cfg_SERR_Sig System error asserted on the PCI bus. When this signal is active, the Signalled System O Error bit, bit 14 of the Status Register, must be set in the PCI configuration space (offset 04h). O O O Inverted copy of the TRDYN signal as driven by the PCI target interface. Valid only within a target access. Inverted copy of the DEVSELN signal as driven by the PCI target interface. Valid only within a target access. Active one clock cycle after the last data phase (may not with data transfer) occurs on PCI and inactive one clock cycle afterwards. Used to delay (add wait states to) a target PCI transaction when the backend needs additional time to provide data (read) or accept data (write). Subject to PCI latency restrictions. Used to prematurely stop a PCI target access on the next PCI clock. Usr_TRDY Usr_DEVSEL Usr_Last_Cycle_D1 Usr_Rdy Usr_Stop Usr_STOPN I I O Copy of the STOPN signal as driven by the PCI target interface Indicates the number of dwords currently in the read pipeline ("00" = 0 elements, "01" = 1 element, "11" = 2 elements). This value is important at the end of a transaction (i.e., when Usr_Last_Cycle_D1 is active) if non-prefetchable memory is being read. NonO prefetchable memory is defined as registers or memory elements whose value changes when they are read. Examples are status registers which are cleared when they are read, or FIFO memories, since consecutive reads from the same address in these elements may not produce the same data values. Usr_RdPipe_Stat[1:0] 6 * www.quicklogic.com * * * * * (c) 2005 QuickLogic Corporation QL58x0 Enhanced QuickPCI Target Family Data Sheet Rev. I PCI Internal Signals Table 3: PCI Internal Signals Signal PCI_clock PCI_reset PCI_IRDYN_D1 PCI_FRAMEN_D1 PCI_DEVSELN_D1 PCI_TRDYN_D1 PCI_STOPN_D1 PCI_IDSEL_D1 I/O O O O O O O O O PCI clock. PCI reset signal. Copy of the IRDYN signal from the PCI bus, delayed by one clock. Copy of the FRAMEN signal from the PCI bus, delayed by one clock. Copy of the DEVSELN signal from the PCI bus, delayed by one clock. Copy of the TRDYN signal from the PCI bus, delayed by one clock. Copy of the STOPN signal from the PCI bus, delayed by one clock. Copy of the IDSEL signal from the PCI bus, delayed by one clock. Description Table 4: QL58x0 Target QuickPCI Family Members QL5810 Max Gates Logic Cells Max Flip-Flops Max I/O RAM Modules RAM Bits PLLs ECUs TQFP TFBGA (0.8 mm) Packages PQFP LFBGA (0.8 mm) PBGA (1.0 mm) 63,840 192 630 78 2 4,608 144 196 QL5820 188,946 575 1,455 97 14 32,256 144 196 208 280 QL5840 320,640 1,472 3,748 264 22 50,688 4 12 208 280 484 Table 5: Max I/O per Device/Package Combination Device QL5810 QL5820 QL5840 144 TQFP 54 54 196 TFBGA 78 78 208 PQFP 97 69 280 LFBGA 117 117 484 PBGA 264 NOTE: All devices support 33 MHz and 66 MHz PCI except QL5840-PQ208 which supports 33 MHz PCI only. (c) 2005 QuickLogic Corporation www.quicklogic.com * * * * * * 7 QL58x0 Enhanced QuickPCI Target Family Data Sheet Rev. I QuickWorks Design Software The QuickWorks package provides the most complete ESP and FPGA software solution from design entry to logic synthesis, to place and route, to power calculation, and simulation. The package provides a solution for designers who use third-party tools from Cadence, Mentor, OrCAD, Synopsys, Viewlogic, and other thirdparty tools for design entry, synthesis, or simulation. Process Data The QL58x0 device family is fabricated on a 0.18 , six layer metal CMOS process. The core voltage is 1.8 V and the I/Os are up to 3.3 V drive/tolerant. The QL58x0 device family product line is available in commercial, industrial, and military temperature grades. Programmable Logic Architectural Overview The QL58x0 device family logic cell structure is presented in Figure 3. This architectural feature addresses today's register-intensive designs. Table 6: Performance Standardsa Function Multiplexer Parity Tree Counter Description 16:1 24 36 16 bit 32 bit 128 x 32 Synchronous FIFO Clock-to-Out System clock 128 x 64 256 x 16 Slowest Speed Grade 2.8 ns 3.4 ns 4.6 ns 275 MHz 250 MHz 197 MHz 188 MHz 208 MHz 6.5 ns 200 MHz Fastest Speed Grade 2.4 ns 2.9 ns 3.9 ns 328 MHz 300 MHz 235 MHz 266 MHz 248 MHz 6 ns 300 MHz a. Performance standards for worst-case commercial conditions. The QL58x0 device family logic cell structure presented in Figure 3 is a dual register, multiplexer-based logic cell. It is designed for wide fan-in and multiple, simultaneous output functions. Both registers share CLK, SET, and RESET inputs. The second register has a two-to-one multiplexer controlling its input. The register can be loaded from the NZ output or directly from a dedicated input. NOTE: The input PP is not an "input" in the classical sense. It is a static input to the logic cell and selects which path (NZ or PS) is used as an input to the Q2Z register. All other inputs are dynamic and can be connected to multiple routing channels. The complete logic cell consists of two six-input AND gates, four two-input AND gates, seven two-to-one multiplexers, and two D flip-flops with asynchronous SET and RESET controls. The cell has a fan-in of 30 (including register control lines), fits a wide range of functions with up to 17 simultaneous inputs, and has six outputs (four combinatorial and two registered). The high logic capacity and fan-in of the logic cell accommodates many user functions with a single level of logic delay while other architectures require two or more levels of delay. 8 * www.quicklogic.com * * * * * (c) 2005 QuickLogic Corporation QL58x0 Enhanced QuickPCI Target Family Data Sheet Rev. I Figure 3: QL58x0 Device Family Logic Cell QS A1 A2 A3 A4 A5 A6 OS OP B1 B2 C1 C2 MP MS D1 D2 E1 E2 NP NS F1 F2 F3 F4 F5 F6 PS PP QC QR AZ OZ QZ NZ Q2Z FZ RAM Modules The QL58x0 device family includes up to 24 dual-port 2,304-bit RAM modules for implementing RAM, ROM, and FIFO functions. Each module is user-configurable into two different block organizations and can be cascaded horizontally to increase their effective width, or vertically to increase their effective depth as shown in Figure 5. Figure 4: 2,304-bit RAM Module MODE[1:0] WA[7:0] WD[17:0] WE WCLK ASYNCRD RA[7:0] RD[17:0] RE RCLK The number of RAM modules varies from 4 to 24 blocks for a total of 9.2 K to 55.3 K bits of RAM. Using the two "mode" pins, designers can configure each module into 128 x 18 and 256 x 9. The blocks are also easily cascadable to increase their effective width and/or depth (see Figure 5). (c) 2005 QuickLogic Corporation www.quicklogic.com * * * * * * 9 QL58x0 Enhanced QuickPCI Target Family Data Sheet Rev. I Figure 5: Cascaded RAM Modules WDATA WADDR RDATA RADDR RAM Module (2,304 bits) WDATA RAM Module (2,304 bits) RDATA The RAM modules are dual-port, with completely independent READ and WRITE ports and separate READ and WRITE clocks. The READ ports support asynchronous and synchronous operation, while the WRITE ports support synchronous operation. Each port has 18 data lines and 8 address lines, allowing word lengths of up to 18 bits and address spaces of up to 256 words. Depending on the mode selected, however, some higher order data or address lines may not be used. The Write Enable (WE) line acts as a clock enable for synchronous write operation. The Read Enable (RE) acts as a clock enable for synchronous READ operation (ASYNCRD input low), or as a flow-through enable for asynchronous READ operation (ASYNCRD input high). Designers can cascade multiple RAM modules to increase the depth or width allowed in single modules by connecting corresponding address lines together and dividing the words between modules. A similar technique can be used to create depths greater than 256 words. In this case address signals higher than the MSB are encoded onto the write enable (WE) input for WRITE operations. The READ data outputs are multiplexed together using encoded higher READ address bits for the multiplexer SELECT signals. The RAM blocks can be loaded with data generated internally (typically for RAM or FIFO functions) or with data from an external PROM (typically for ROM functions). 10 * www.quicklogic.com * * * * * (c) 2005 QuickLogic Corporation QL58x0 Enhanced QuickPCI Target Family Data Sheet Rev. I Embedded Computational Unit (ECU) Traditional Programmable Logic architectures do not implement arithmetic functions efficiently or effectively-- these functions require high logic cell usage while garnering only moderate performance results. The QL58x0 device family architecture allows for functionality above and beyond that achievable using programmable logic devices. By embedding a dynamically reconfigurable computational unit, the QL58x0 device family can address various arithmetic functions efficiently. This approach offers greater performance and utilization than traditional programmable logic implementations. The embedded block is implemented at the transistor level as shown in Figure 6. Figure 6: ECU Block Diagram RESET D S1 S2 S3 CIN SIGN1 SIGN2 00 01 3-1 mux 10 Q[16:0] 3-4 decoder C B A A[7:0] A[15:8] 8-bit Multiplier 2-1 mux 16-bit Adder D Q 17-bit Register A[0:15] CLK B[0:15] 2-1 mux The QL58x0 device family ECU blocks (Table 7) are placed next to the SRAM circuitry for efficient memory/instruction fetch and addressing for DSP algorithmic implementations. Table 7: QL58x0 Device Family ECU Blocks Device QL5840 QL5820 QL5810 ECUs 12 0 0 Up to twelve 8-bit MAC functions can be implemented per cycle for a total of 1 billion MACs/s when clocked at 100 MHz. Additional multiply-accumulate functions can be implemented in the programmable logic. The modes for the ECU block are dynamically re-programmable through the programmable logic. (c) 2005 QuickLogic Corporation www.quicklogic.com * * * * * * 11 QL58x0 Enhanced QuickPCI Target Family Data Sheet Rev. I Table 8: ECU Mode Select Criteria Instruction S1 0 0 0 0 1 1 1 1 S2 0 0 1 1 0 0 1 1 S3 0 1 0 1 0 1 0 1 Operation Multiply Multiply-Add Accumulate Add Multiply (registered)c Multiply- Add (registered) Multiply - Accumulate Add (registered) b ECU Performancea, tPD 6.6 ns max 8.8 ns max tSU -8 WCC tCO 3.9 ns min 3.1 ns max 9.6 ns min 9.6 ns min 9.6 ns min 3.9 ns min 1.2 ns max 1.2 ns max 1.2 ns max 1.2 ns max 1.2 ns max a. tPD, tSU and tCO do not include routing paths in/out of the ECU block. b. Internal feedback path in ECU restricts max clk frequency to 238 MHz. c. B [15:0] set to zero. NOTE: Timing numbers in Table 8 represent -8 Worst Case Commercial conditions. 12 * www.quicklogic.com * * * * * (c) 2005 QuickLogic Corporation QL58x0 Enhanced QuickPCI Target Family Data Sheet Rev. I Phase Locked Loop (PLL) Information Instead of requiring extra components, designers simply need to instantiate one of the pre-configured models (described in this section). The QuickLogic built-in PLLs support a wider range of frequencies than many other PLLs. These PLLs also have the ability to support different ranges of frequency multiplications or divisions, driving the device at a faster or slower rate than the incoming clock frequency. When PLLs are cascaded, the clock signal must be routed off-chip through the PLLPAD_OUT pin prior to routing into another PLL; internal routing cannot be used for cascading PLLs. Figure 7 illustrates a QuickLogic PLL. Figure 7: PLL Block Diagram 1st Quadrant 2nd Quadrant 3rd Quadrant FIN Frequency Divide _ .1 . . _2 . . _4 . + Filter vco PLL Bypass 4th Quadrant Clock Tree Frequency Multiply .1 _ . . _2 . . _4 . FOUT Fin represents a very stable high-frequency input clock and produces an accurate signal reference. This signal can either bypass the PLL entirely, thus entering the clock tree directly, or it can pass through the PLL itself. Within the PLL, a voltage-controlled oscillator (VCO) is added to the circuit. The external Fin signal and the local VCO form a control loop. The VCO is multiplied or divided down to the reference frequency, so that a phase detector (the crossed circle in Figure 7) can compare the two signals. If the phases of the external and local signals are not within the tolerance required, the phase detector sends a signal through the charge pump and loop filter (Figure 7). The charge pump generates an error voltage to bring the VCO back into alignment, and the loop filter removes any high frequency noise before the error voltage enters the VCO. This new VCO signal enters the clock tree to drive the chip's circuitry. Fout represents the clock signal emerging from the output pad (the output signal PLLPAD_OUT is explained in Table 10). The PLL always drives the PLLPAD_OUT signal, regardless of whether the PLL is configured for on-chip use. The PLLPAD_OUT will not oscillate if PLL_RESET is asserted, or if the PLL is powered down. Most QuickLogic products contain four PLLs. The PLL presented in Figure 7 controls the clock tree in the fourth quadrant of its FPGA. QuickLogic PLLs compensate for the additional delay created by the clock tree itself, as previously noted, by subtracting the clock tree delay through the feedback path. (c) 2005 QuickLogic Corporation www.quicklogic.com * * * * * * 13 QL58x0 Enhanced QuickPCI Target Family Data Sheet Rev. I PLL Modes of Operation QuickLogic PLLs have eight modes of operation, based on the input frequency and desired output frequency-- Table 9 indicates the features of each mode. NOTE: "HF" stands for "high frequency" and "LF" stands for "low frequency." Table 9: PLL Mode Frequencies PLL Model PLL_HF PLL_LF PLL_MULT2HF PLL_MULT2LF PLL_DIV2HF PLL_DIV2LF PLL_MULT4 PLL_DIV4 Output Frequency Same as input Same as input 2x 2x 1/2x 1/2x 4x 1/4x Input Frequency Range 66 MHz-220 MHz 25 MHz-66 MHz 33 MHz-110 MHz 12.5 MHz-33 MHz 220 MHz-440 MHz 50 MHz-220 MHz 12.5 MHz-50 MHz 100 MHz-440 MHz Output Frequency Range 66 MHz-220 MHz 25 MHz-66 MHz 66 MHz-220 MHz 25 MHz-66 MHz 110 MHz-220 MHz 25 MHz-110 MHz 50 MHz-200 MHz 25 MHz-110 MHz The input frequency can range from 12.5 MHz to 440 MHz, while output frequency ranges from 25 MHz to 220 MHz. When adding PLLs to the top-level design, be sure that the PLL mode matches the desired input and output frequencies. PLL Signals Table 10 summarizes the key signals in QuickLogic PLLs. Table 10: QuickLogic PLL Signals Signal Name PLLCLK_IN PLL_RESET ONn_OFFCHIP CLKNET_OUT PLLCLK_OUT Input clock signal Active High Reset If PLL_RESET is asserted, then CLKNET_OUT and PLLPAD_OUT are reset to 0. This signal must be asserted and then released in order for the LOCK_DETECT to work. This is a reserved signal. It can be connected to VCC or GND. Out to internal gates This signal bypasses the PLL logic before driving the internal gates. Note that this signal cannot be used in the same quadrant where the PLL signal is used (PLLCLK_OUT). Out from PLL to internal gates This signal can drive the internal gates after going through the PLL. Out to off-chip This outgoing signal is used off-chip. The PLLPAD_OUT is always active, driving the PLL-derived clock signal out through the pad. The PLLPAD_OUT will not oscillate if PLL_RESET is asserted, or if the PLL is powered down. Description PLLPAD_OUT Active High Lock detection signal LOCK_DETECT NOTE: For simulation purposes, this signal gets asserted after 10 clock cycles. However, it can take a maximum of 200 clock cycles to sync with the input clock upon release of the PLL_RESET signal. NOTE: Because PLLCLK_IN and PLL_RESET signals have PLL_INPAD, and PLLPAD_OUT has OUTPAD, you do not need to add additional pads to your design. 14 * www.quicklogic.com * * * * * (c) 2005 QuickLogic Corporation QL58x0 Enhanced QuickPCI Target Family Data Sheet Rev. I I/O Cell Structure The QL58x0 device family features a variety of distinct I/O pins to maximize performance, functionality, and flexibility with bi-directional I/O pins and input-only pins. All input and I/O pins are 1.8 V, 2.5 V, and 3.3 V tolerant and comply with the specific I/O standard selected. For single ended I/O standards, VCCIO specifies the input tolerance and the output drive. For voltage referenced I/O standards (e.g SSTL), the voltage supplied to the INREF pins in each bank specifies the input switch point. For example, the VCCIO pins must be tied to a 3.3 V supply to provide 3.3 V compliance. The QL58x0 device family can also support the LVDS and LVPECL I/O standards with the use of external resistors (see Table 11). Table 11: I/O Standards and Applications I/O Standard LVTTL LVCMOS25 LVCMOS18 PCI GTL+ SSTL3 SSTL2 Reference Voltage n/a n/a n/a n/a 1 1.5 1.25 Output Voltage 3.3 V 2.5 V 1.8 V 3.3 V n/a 3.3 V 2.5 V Application General Purpose General Purpose General Purpose PCI Bus Applications Backplane SDRAM SDRAM As designs become more complex and requirements more stringent, several application-specific I/O standards have emerged for specific applications. I/O standards for processors, memories, and a variety of bus applications have become commonplace and a requirement for many systems. In addition, I/O timing has become a greater issue with specific requirements for setup, hold, clock to out, and switching times. The QL58x0 device family has addressed these new system requirements and now includes a completely new I/O cell which consists of programmable I/Os as well as a new cell structure consisting of three registers--Input, Output, and OE. The QL58x0 device family offers banks of programmable I/Os that address many of the bus standards that are popular today. As shown in Figure 8 each bi-directional I/O pin is associated with an I/O cell which features an input register, an input buffer, an output register, a three-state output buffer, an output enable register, and 2 two-to-one output multiplexers. (c) 2005 QuickLogic Corporation www.quicklogic.com * * * * * * 15 QL58x0 Enhanced QuickPCI Target Family Data Sheet Rev. I Figure 8: QL58x0 Device Family I/O Cell + - INPUT REGISTER QE D R OUTPUT REGISTER D R Q PAD OUTPUT ENABLE REGISTER D E Q R The bi-directional I/O pin options can be programmed for input, output, or bi-directional operation. As shown in Figure 8, each bi-directional I/O pin is associated with an I/O cell which features an input register, an input buffer, an output register, a three-state output buffer, an output enable register, and 2 two-to-one multiplexers. The select lines of the two-to-one multiplexers are static and must be connected to either VCC or GND. For input functions, I/O pins can provide combinatorial, registered data, or both options simultaneously to the logic array. For combinatorial input operation, data is routed from I/O pins through the input buffer to the array logic. For registered input operation, I/O pins drive the D input of input cell registers, allowing data to be captured with fast, predictable set-up times without consuming internal logic cell resources. The comparator and multiplexer in the input path allows for native support of I/O standards with reference points offset from traditional ground. For output functions, I/O pins can receive combinatorial or registered data from the logic array. For combinatorial output operation, data is routed from the logic array through a multiplexer to the I/O pin. For registered output operation, the array logic drives the D input of the output cell register which in turn drives the I/O pin through a multiplexer. The multiplexer allows either a combinatorial or a registered signal to be driven to the I/O pin. The addition of an output register will also decrease the Tco. Since the output register does not need to drive the routing the length of the output path is also reduced, and static timing analysis becomes very predictable. The three-state output buffer controls the flow of data from the array logic to the I/O pin and allows the I/O pin to act as an input and/or output. The buffer's output enable can be individually controlled by the logic cell array or any pin (through the regular routing resources), or it can be bank-controlled through one of the global networks. The signal can also be either combinatorial or registered. This is identical to that of the flow for the output cell. For combinatorial control operation, data is routed from the logic array through a multiplexer to the three-state control. The IOCTRL pins can directly drive the OE and CLK signals for all I/O cells within the same bank. 16 * www.quicklogic.com * * * * * (c) 2005 QuickLogic Corporation QL58x0 Enhanced QuickPCI Target Family Data Sheet Rev. I For registered control operation, the array logic drives the D input of the OE cell register which in turn drives the three-state control through a multiplexer. The multiplexer allows either a combinatorial or a registered signal to be driven to the three-state control. When I/O pins are unused, the OE controls can be permanently disabled, allowing the output cell register to be used for registered feedback into the logic array. I/O cell registers are controlled by clock, clock enable, and reset signals, which can come from the regular routing resources, from one of the global networks, or from two IOCTRL input pins per bank of I/O's. The CLK and RESET signals share common lines, while the clock enables for each register can be independently controlled. I/O interface support is programmable on a per bank basis. The two larger QL58x0 devices contain eight I/O banks. Figure 9 illustrates the I/O bank configurations for QL5840. The two smaller QL58x0 devices contain two I/O banks per device. Figure 10 illustrates the I/O bank configurations for QL5820 and QL5810. Each I/O bank is independent of other I/O banks and each I/O bank has its own VCCIO and INREF supply inputs. A mixture of different I/O standards can be used on the device; however, there is a limitation as to which I/O standards can be supported within a given bank. Only standards that share a common VCCIO and INREF can be shared within the same bank (e.g., PCI and LVTTL). In the case of the QL5820 and QL5810, only one voltage-referenced standard can be used. The two I/O banks, A and B, share the INREF pin. Figure 9: Multiple I/O Banks on QL5840 VCCIO(F) INREF(F) VCCIO(E) INREF(E) VCCIO(G) PLL Embedded RAM Blocks Embeded Computational Units PLL VCCIO(D) INREF(G) INREF(D) Fabric VCCIO(H) VCCIO(C) INREF(H) PLL Embedded RAM Blocks PLL INREF (C) VCCIO(A) INREF(A) VCCIO(B) INREF(B) (c) 2005 QuickLogic Corporation www.quicklogic.com * * * * * * 17 QL58x0 Enhanced QuickPCI Target Family Data Sheet Rev. I Figure 10: Multiple I/O Banks on QL5820 and 5810 VDED Embedded RAM Blocks VCCIO(A) Fabric VCCIO(B) Embedded RAM Blocks INREF Programmable Slew Rate Each I/O has programmable slew rate capability--the slew rate can be either fast or slow. The slower rate can be used to reduce the switching times of each I/O. Programmable Weak Pull-Down A programmable Weak Pull-Down resistor is available on each I/O. The I/O Weak Pull-Down eliminates the need for external pull down resistors for used I/Os as shown in Figure 11. The spec for pull-down current is maximum of 150 A under worst case condition. Figure 11: Programmable I/O Weak Pull-Down I/O Output Logic PAD 18 * www.quicklogic.com * * * * * (c) 2005 QuickLogic Corporation QL58x0 Enhanced QuickPCI Target Family Data Sheet Rev. I Clock Networks Global Clocks There are a maximum of seven global clock networks in each QL58x0 device. Global clocks can drive logic cells and I/O registers, ECUs, and RAM blocks in the device. All global clocks have access to a Quad Net (local clock network) connection with a programmable connection to the logic cell's register clock input. Figure 12: Global Clock Architecture Quad Net Global Clock Net CLK Pin Quad-Net Network There are five Quad-Net local clock networks in each quadrant for a total of 20 in a device. Each Quad-Net is local to a quadrant. Before driving the column clock buffers, the quad-net is driven by the output of a mux which selects between the CLK pin input and an internally generated clock source (see Figure 13). Figure 13: Global Clock Structure Quad-Net Clock Network Internally generated clock, or clock from general routing network Global Clock (CLK) Input FF tPGCK tBGCK Global Clock Buffer (c) 2005 QuickLogic Corporation www.quicklogic.com * * * * * * 19 QL58x0 Enhanced QuickPCI Target Family Data Sheet Rev. I Dedicated Clock There is one dedicated clock in the larger device of the QL58x0 family (QL5840). This clock connects to the clock input of the Logic Cell and I/O registers, and RAM blocks through a hardwired connection and is multiplexed with the programmable clock input. The dedicated clock provides a fast global network with low skew. Users have the ability to select either the dedicated clock or the programmable clock (Figure 14). Figure 14: Dedicated Clock Circuitry within Logic Cell Logic Cell Programmable Clock or General Routing Dedicated Clock CLK NOTE: For more information on the clocking capabilities of the QL58x0 Enhanced QuickPCI Family, see QuickLogic Application Note 68 at http://www.quicklogic.com/images/appnote68.pdf. I/O Control and Local Hi-Drives Each bank of I/Os has two input-only pins that can be programmed to drive the RST, CLK, and EN inputs of I/Os in that bank. These input-only pins also serve as high drive inputs to a quadrant. These buffers can be driven by the internal logic both as an I/O control or high drive. For I/O constrained designs, these pins can be used for general purpose inputs. To provide more general purpose I/Os in the 208 PQFP package, the I/O controls pins are not bonded out. The performance of these resources is presented in Table 12. Table 12: I/O Control Network/Local High-Drive Destination TT, 25 C, 2.5 V I/O (far) I/O (near) Skew From Pad 1.00 ns 0.63 ns 0.37 ns From Array 1.14 ns 0.78 ns 0.36 ns Table 13 shows the total number of I/O control pins per device/package combination. These pins are not bonded out in the smaller devices and packages. This increases the number of bi-directional user I/Os available. Table 13: I/O Control Pins per Device/Package Combination Device QL5810 QL5820 QL5840 144 TQFP 196 TFBGA 208 PQFP 280 LFBGA 16 484 BGA 16 20 * www.quicklogic.com * * * * * (c) 2005 QuickLogic Corporation QL58x0 Enhanced QuickPCI Target Family Data Sheet Rev. I Programmable Logic Routing QL58x0 devices are engineered with six types of routing resources as follows: short (sometimes called segmented) wires, dual wires, quad wires, express wires, distributed networks, and default wires. Short wires span the length of one logic cell, always in the vertical direction. Dual wires run horizontally and span the length of two logic cells. Short and dual wires are predominantly used for local connections. Default wires supply VCC and GND (Logic `1' and Logic `0') to each column of logic cells. Quad wires have passive link interconnect elements every fourth logic cell. As a result, these wires are typically used to implement intermediate length or medium fan-out nets. Express lines run the length of the device uninterrupted. Each of these lines has a higher capacitance than a quad, dual, or short wire, but less capacitance than shorter wires connected to run the length of the device. The resistance will also be lower because the express wires don't require the use of pass links. Express wires provide higher performance for long routes or high fan-out nets. Distributed networks are described in Clock Networks on page 19. These wires span the programmable logic and are driven by quad-net buffers. Global Power-On Reset (POR) The QL58x0 device family features a global power-on reset. This reset is hardwired to all registers and resets them to Logic `0' upon power-up of the device. In QuickLogic devices, the asynchronous Reset input to flipflops has priority over the Set input; therefore, the Global POR will reset all flip-flops during power-up. If you want to set the flip-flops to Logic `1', you must assert the "Set" signal after the Global POR signal has been deasserted. Figure 15: Power-On Reset VCC Power-on Reset Q XXXXXXX 0 Low Power Mode Quiescent power consumption of all QL58x0 family devices can be reduced significantly by de-activating the charge pumps inside the architecture. By applying 3.3 V to the VPUMP pin, the internal charge pump is deactivated--this effectively reduces the static and dynamic power consumption of the device. The QL58x0 device family is fully functional and operational in the Low Power mode. Users who have a 3.3 V supply available in their system should take advantage of this low power feature by tying the VPUMP pin to 3.3 V. Otherwise, if a 3.3 V supply is not available, this pin should be tied to ground. (c) 2005 QuickLogic Corporation www.quicklogic.com * * * * * * 21 QL58x0 Enhanced QuickPCI Target Family Data Sheet Rev. I Joint Test Access Group (JTAG) Information Figure 16: JTAG Block Diagram TCK TMS TRSTB Tap Controller State Machine (16 States) Instruction Decode & Control Logic Instruction Register RDI Mux Boundary-Scan Register (Data Register) Mux TDO Bypass Register Internal Register I/O Registers User Defined Data Register Microprocessors and Application Specific Integrated Circuits (ASICs) pose many design challenges, one problem being the accessibility of test points. JTAG formed in response to this challenge, resulting in IEEE standard 1149.1, the Standard Test Access Port and Boundary Scan Architecture. The JTAG boundary scan test methodology allows complete observation and control of the boundary pins of a JTAG-compatible device through JTAG software. A Test Access Port (TAP) controller works in concert with the Instruction Register (IR), which allow users to run three required tests along with several user-defined tests. JTAG tests allow users to reduce system debug time, reuse test platforms and tools, and reuse subsystem tests for fuller verification of higher level system elements. The 1149.1 standard requires the following three tests: * Extest Instruction. The Extest Instruction performs a printed circuit board (PCB) interconnect test. This test places a device into an external boundary test mode, selecting the boundary scan register to be connected between the TAP Test Data In (TDI) and Test Data Out (TDO) pins. Boundary scan cells are preloaded with test patterns (through the Sample/Preload Instruction), and input boundary cells capture the input data for analysis. * Sample/Preload Instruction. The Sample/Preload Instruction allows a device to remain in its functional mode, while selecting the boundary scan register to be connected between the TDI and TDO pins. For this test, the boundary scan register can be accessed through a data scan operation, allowing users to sample the functional data entering and leaving the device. 22 * www.quicklogic.com * * * * * (c) 2005 QuickLogic Corporation QL58x0 Enhanced QuickPCI Target Family Data Sheet Rev. I * Bypass Instruction. The Bypass Instruction allows data to skip a device boundary scan entirely, so the data passes through the bypass register. The Bypass instruction allows users to test a device without passing through other devices. The bypass register is connected between the TDI and TDO pins, allowing serial data to be transferred through a device without affecting the operation of the device. JTAG BSDL Support * BSDL-Boundary Scan Description Language * Machine-readable data for test equipment to generate testing vectors and software * BSDL files available for all device/package combinations from QuickLogic * Extensive industry support available and ATVG (Automatic Test Vector Generation) Security Links There are several security links to disable reading logic from the array, and to disable JTAG access to the device. Programming these optional links completely disables access to the device from the outside world and provides an extra level of design security not possible in SRAM-based FPGAs. The option to program these links is selectable through QuickWorks in the Tools/Options/Device Programming window in SpDE. Power-Up Loading Link The flexibility link enables Power-Up Loading of the Embedded RAM blocks. If the link is programmed, the Power-Up Loading state machine is activated during power-up of the device. The state machine communicates with an external EPROM via the JTAG pins to download memory contents into the on-chip RAM. If the link is not programmed, Power-Up Loading is not enabled and the JTAG pins function as they normally would. The option to program this link is selectable through QuickWorks in the Tools/Options/Device Programming window in SpDE. For more information on Power-Up Loading, see QuickLogic Application Note 55 at http://www.quicklogic.com/images/appnote55.pdf. See the Power-Up Loading power-up sequencing requirement for proper functionality in Figure 17. (c) 2005 QuickLogic Corporation www.quicklogic.com * * * * * * 23 QL58x0 Enhanced QuickPCI Target Family Data Sheet Rev. I Figure 17: Required Power-Up Sequence When Using Power-Up Loading VCCIO VDED VDED2 VPUMP VCC Voltage VCC < 2 ms Time To use the power-up loading function in QL58x0, designers must ensure that VCC begins to ramp within a maximum of 2 ms of VCCIO, VDED, VDED2, and VPUMP. 24 * www.quicklogic.com * * * * * (c) 2005 QuickLogic Corporation QL58x0 Enhanced QuickPCI Target Family Data Sheet Rev. I Electrical Specifications DC Characteristics The DC Specifications are provided in Table 14 through Table 18. Table 14: Absolute Maximum Ratings Parameter VCC Voltage VCCIO Voltage INREF Voltage Input Voltage Value -0.5 V to 2.0 V -0.5 V to 4.0 V 0.5 V to VCCIO -0.5 V to VCCIO + 0.5 V Parameter Latch-up Immunity DC Input Current Leaded Package Storage Temperature Laminate Package (BGA) Storage Temperature Value 100 mA 20 mA -65 C to + 150 C -55 C to + 125 C Table 15: Recommended Operating Range Symbol VCC VCCIO TJ K Parameter Supply Voltage I/O Input Tolerance Voltage Junction Temperature -33A Speed Grade Delay Factor -33B Speed Grade -66C Speed Grade Military Min 1.71 1.71 -55 0.49 0.48 0.45 Max 1.89 3.60 125 1.57 1.40 1.32 Industrial Min 1.71 1.71 -40 0.50 0.50 0.47 Max 1.89 3.60 100 1.51 1.34 1.26 Commercial Min 1.71 1.71 0 0.54 0.53 0.50 Max 1.89 3.60 85 1.47 1.31 1.23 V V C n/a n/a n/a Unit (c) 2005 QuickLogic Corporation www.quicklogic.com * * * * * * 25 QL58x0 Enhanced QuickPCI Target Family Data Sheet Rev. I Table 16: DC Characteristics Symbol Il IOZ CI CCLOCK IOS IREF IPD IPUMP IPLL IVCCIO Parameter I or I/O Input Leakage Current 3-State Output Leakage Current I/O Input Capacitance Clock Input Capacitance Output Short Circuit Currenta Quiescent Current on INREF Current on programmable pull-down Quiescent Current on VPUMP Quiescent Current on each VCCPLL Conditions VI = VCCIO or GND VI = VCCIO or GND VO = GND VO = VCC VCC = 1.8 V VPUMP= 3.3 V 2.5 V 3.3 V VCCIO = 3.6 V VCCIO = 2.5 V VCCIO = 1.8 V Min -1 -15 40 -10 Max 1 1 8 8 -180 210 10 50 10 3 20 10 10 Units A A pF pF mA mA A A A mA Quiescent Current on VCCIO - A a. Only one output at a time. Duration should not exceed 30 seconds. Table 17: Quiescent ICC Characteristics Device QL5810 QL5820 QL5840 a, b VPUMP = 0 V 2 mA VPUMP = 3.3 V - a. For -33B/-66C commercial grade devices only. Maximum Quiescent ICC is 3 mA for all industrial grade devices and 5 mA for all military devices. b. Quiescent ICC is for current drawn by VCC and VDED. If any PLLs are used, see Table 16 for current drawn by each PLL. 26 * www.quicklogic.com * * * * * (c) 2005 QuickLogic Corporation QL58x0 Enhanced QuickPCI Target Family Data Sheet Rev. I Table 18: DC Input and Output Levelsa Symbol LVTTL LVCMOS2 LVCMOS18 GTL+ PCI SSTL2 SSTL3 INREF VMIN VMAX VMIN n/a n/a n/a 0.88 n/a 1.15 1.3 n/a n/a n/a 1.12 n/a 1.35 1.7 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 VIL VMAX 0.8 0.7 0.63 INREF - 0.2 0.3 x VCCIO INREF - 0.2 VMIN 2.2 1.7 1.2 INREF + 0.2 0.6 x VCCIO INREF + 0.2 VIH VMAX VCCIO + 0.3 VCCIO + 0.3 VCCIO + 0.3 VCCIO + 0.3 VOL VMAX 0.4 0.7 0.7 0.6 0.74 1.10 VOH VMIN 2.4 1.7 1.7 n/a 1.76 1.90 IOL mA 2.0 2.0 2.0 40 7.6 8 IOH mA -2.0 -2.0 -2.0 n/a -0.5 -7.6 -8 VCCIO + 0.5 0.1 x VCCIO 0.9 x VCCIO 1.5 VCCIO + 0.3 -0.3 INREF - 0.18 INREF + 0.18 VCCIO + 0.3 a. The data provided in Table 18 represents the JEDEC and PCI specification. QuickLogic devices either meet or exceed these requirements. For data specific to QuickLogic I/Os, see Table 22 through Table 28, Figure 8 and Figure 11, and Figure 39 through Figure 42. NOTE: All CLK, IOCTRL, and PLLIN pins are clamped to the VDED rail. Therefore, these pins can be driven up to VDED. All JTAG inputs are clamped to the VDED2 rail. These JTAG input pins can only be driven up to VDED2. Figure 18 through Figure 21 show the VIL and VIH characteristics for I/O and clock pins. Figure 18: VIL Maximum for I/O VILmax for IO 2.5 1.71 V 2 Voltage (V) 1.5 1 0.5 0 -55C -40C 0C 25C 70C 90C 110C 125C Junction Temperature 1.8 V 1.89 V 2.5 V 3.3 V 3.6 V (c) 2005 QuickLogic Corporation www.quicklogic.com * * * * * * 27 QL58x0 Enhanced QuickPCI Target Family Data Sheet Rev. I Figure 19: VIH Minimum for I/O VIHmin for IO 2.5 2 Voltage 1.5 1 0.5 0 -55C -40C 0C 25C 70C 90C 110C 125C 1.71 V 1.8 V 1.89 V 2.5 V 3.3 V 3.6 V Junction Temperature Figure 20: VIL Maximum for CLOCK Pins VILmax for CLOCK pins 2 1.71V Voltage (V) 1.5 1 0.5 0 -55C -40C 0C 25C 70C 90C 110C 125C 1.8 V 1.89 V 2.5 V 3.3 V 3.6 V Junction Temperature 28 * www.quicklogic.com * * * * * (c) 2005 QuickLogic Corporation QL58x0 Enhanced QuickPCI Target Family Data Sheet Rev. I Figure 21: VIH Minimum for CLOCK Pins VIHmin for CLOCK pins 2.5 2 Voltage (V) 1.5 1 0.5 0 -55C -40C 0C 25C 70C 90C 110C 125C Junction Temperature Figure 22 through Figure 26 show the output drive characteristics for the I/Os across various voltages and temperatures. Figure 22: Drive Current at VCCIO = 1.71 V 1.71 V 1.8 V 1.89 V 2.5 V 3.3 V 3.6 V Drive Current @ Vccio = 1.71 V 35 Drive Current (mA) 30 25 20 15 10 5 0 IOH: -55C IOL: -55C IOH: 25C IOL: 25C IOH: 125C IOL: 125C 0. 4 0. 6 0. 8 1. 6 0. 2 1. 2 1. 4 0 1 Output Voltage (V) 1. 71 (c) 2005 QuickLogic Corporation www.quicklogic.com * * * * * * 29 QL58x0 Enhanced QuickPCI Target Family Data Sheet Rev. I Figure 23: Drive Current at VCCIO = 1.8 V Drive Current @ Vccio = 1.8 V 40 35 30 25 20 15 10 5 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 Drive Current (mA) IOH: -55C IOL: -55C IOH: 25C IOL: 25C IOH: 125C IOL: 125C Output Voltage (V) Figure 24: Drive Current at VCCIO = 2.5 V Drive Current @ Vccio = 2.5V 80 70 60 50 40 30 20 10 0 0 0.5 1 1.5 2 2.5 Output Voltage (V) Drive Current (mA) IOH: -55C IOL: -55C IOH: 25C IOL: 25C IOH: 125C IOL: 125C 30 * www.quicklogic.com * * * * * (c) 2005 QuickLogic Corporation QL58x0 Enhanced QuickPCI Target Family Data Sheet Rev. I Figure 25: Drive Current at VCCIO = 3.3 V Drive Current @ Vccio = 3.3V 120 Drive Current (mA) 100 80 60 40 20 0 0 0.5 1 1.5 2 2.5 3 3.3 Output Voltage (V) IOH: -55C IOL: -55C IOH: 25C IOL: 25C IOH: 125C IOL: 125C Figure 26: Drive Current at VCCIO = 3.6 V Drive Current @ Vccio = 3.6V 140 Drive Current (mA) 120 100 80 60 40 20 0 0 0.5 1 1.5 2 2.5 3 3.3 3.6 Output Voltage (V) IOH: -55C IOL: -55C IOH: 25C IOL: 25C IOH: 125C IOL: 125C (c) 2005 QuickLogic Corporation www.quicklogic.com * * * * * * 31 QL58x0 Enhanced QuickPCI Target Family Data Sheet Rev. I Figure 27 through Figure 30 show the quiescent current for the QL5842 and QL5832 for each of the voltage supplies, across voltage and temperature. Quiescent current on VCC is a function of device utilization. The numbers in the following graphs were taken from 100% utilized designs. Figure 27: Quiescent Current on VCC for QL5842 and QL5832 Quiescent Current on VCC 800 700 600 500 uA 400 300 200 100 0 -40C 0C 25C 70C 90C Am bient Tem perature VCC=1.71V VCC=1.8V VCC=1.89V Figure 28: Quiescent Current for QL5842 and QL5832 at VDED = 1.8 V Quiescent Current on VDED 25 20 15 uA 10 5 0 -40C 0C 25C 70C 90C VDED=1.71V VDED=1.8V VDED=1.89V Am bient Tem perature 32 * www.quicklogic.com * * * * * (c) 2005 QuickLogic Corporation QL58x0 Enhanced QuickPCI Target Family Data Sheet Rev. I Figure 29: Quiescent Current for QL5842 and QL5832 at VDED = 3.3 V Quiescent Current on VDED 45 40 35 30 25 20 15 10 5 0 -40C 0C 25C 70C 90C Am bient Tem perature uA VDED=3.3V VDED=3.6V Figure 30: Quiescent Current for QL5842 and QL5832 at VDED = 2.5 V Quiescent Current on VDED 25 20 15 uA VDED=2.5V 10 5 0 -40C 0C 25C 70C 90C Am bient Tem perature (c) 2005 QuickLogic Corporation www.quicklogic.com * * * * * * 33 QL58x0 Enhanced QuickPCI Target Family Data Sheet Rev. I AC Characteristics The AC Specifications (at VCC = 1.8 V, TA = 25 C, Worst Case Corner, Speed Grade = -8 (K = 1.01)) are provided from Table 19 through Table 28. Logic Cell diagrams and waveforms are provided from Figure 31 through Figure 42. Figure 31: QL58x0 Device Family Logic Cell Table 19: Logic Cells Symbol tPD tSU tHL tCO tCWHI tCWLO tSET tRESET tSW tRW Parameter Combinatorial Delay of the longest path: time taken by the combinatorial circuit to output Setup time: time the synchronous input of the flip-flop must be stable before the active clock edge Hold time: time the synchronous input of the flip-flop must be stable after the active clock edge Clock-to-out delay: the amount of time taken by the flip-flop to output after the active clock edge. Clock High Time: required minimum time the clock stays high Clock Low Time: required minimum time that the clock stays low Set Delay: time between when the flip-flop is "set" (high) and when the output is consequently "set" (high) Reset Delay: time between when the flip-flop is "reset" (low) and when the output is consequently "reset" (low) Set Width: time that the SET signal must remain high/low Reset Width: time that the RESET signal must remain high/low Value Min 0.28 ns 0.10 ns 0 ns 0.22 ns 0.46 ns 0.46 ns 0.69 ns 1.09 ns 0.3 ns 0.3 ns Max 0.98 ns 0.25 ns 0 ns 0.52 ns 0.46 ns 0.46 ns 0.69 ns 1.09 ns 0.3 ns 0.3 ns 34 * www.quicklogic.com * * * * * (c) 2005 QuickLogic Corporation QL58x0 Enhanced QuickPCI Target Family Data Sheet Rev. I Figure 32: Logic Cell Flip-Flop SET D CLK RESET Q Figure 33: Logic Cell Flip-Flop Timings--First Waveform CLK tCWHI (min) SET tCWLO (min) RESET Q tRESET tRW tSET tSW Figure 34: Logic Cell Flip-Flop Timings--Second Waveform CLK D tSU tHL Q tCO * * * * (c) 2005 QuickLogic Corporation www.quicklogic.com * * 35 QL58x0 Enhanced QuickPCI Target Family Data Sheet Rev. I Table 20: QL58x0 Device Family Global Clock Delay Clock Segment tPGCK tBGCK Parameter Global clock pin delay to quad net Global clock tree delay (quad net to flip-flop) Value Min Max 1.92 ns 0.28 ns NOTE: When using a PLL, tPGCK and tBGCK are effectively zero due to delay adjustment by Phase Locked Loop feedback path. Figure 35: Global Clock Structure Timing Elements Quad-Net Clock Network Internally generated clock, or clock from general routing network Global Clock (CLK) Input FF tPGCK tBGCK Global Clock Buffer Figure 36: Dual-Port SRAM Cell [9:0] [17:0] WA WD WE WC LK RE R C LK RA RD AS Y NC R D R AM Module [9:0] [17:0] 36 * www.quicklogic.com * * * * * (c) 2005 QuickLogic Corporation QL58x0 Enhanced QuickPCI Target Family Data Sheet Rev. I Table 21: RAM Cell Synchronous Write Timing Symbol RAM Cell Synchronous Write Timing tSWA tHWA tSWD tHWD tSWE tHWE tWCRD WA setup time to WCLK: time the WRITE ADDRESS must be stable before the active edge of the WRITE CLOCK WA hold time to WCLK: time the WRITE ADDRESS must be stable after the active edge of the WRITE CLOCK WD setup time to WCLK: time the WRITE DATA must be stable before the active edge of the WRITE CLOCK WD hold time to WCLK: time the WRITE DATA must be stable after the active edge of the WRITE CLOCK WE setup time to WCLK: time the WRITE ENABLE must be stable before the active edge of the WRITE CLOCK WE hold time to WCLK: time the WRITE ENABLE must be stable after the active edge of the WRITE CLOCK WCLK to RD (WA = RA): time between the active WRITE CLOCK edge and the time when the data is available at RD 0.47 ns 0 ns 0.48 ns 0 ns 0 ns 0 ns 3.79 ns Parameter Value Min Max Figure 37: RAM Cell Synchronous Write Timing WCLK WA tSWA WD tSWD WE tSWE RD old data tWCRD tHWE new data tHWD tHWA (c) 2005 QuickLogic Corporation www.quicklogic.com * * * * * * 37 QL58x0 Enhanced QuickPCI Target Family Data Sheet Rev. I Table 22: RAM Cell Synchronous and Asynchronous Read Timing Symbol RAM Cell Synchronous Read Timing tSRA tHRA tSRE tHRE tRCRD RA setup time to RCLK: time the READ ADDRESS must be stable before the active edge of the READ CLOCK RA hold time to RCLK: time the READ ADDRESS must be stable after the active edge of the READ CLOCK RE setup time to WCLK: time the READ ENABLE must be stable before the active edge of the READ CLOCK RE hold time to WCLK: time the READ ENABLE must be stable after the active edge of the READ CLOCK RCLK to RD: time between the active READ CLOCK edge and the time when the data is available at RD RA to RD: time between when the READ ADDRESS is input and when the DATA is output 0.43 ns 0 ns 0.21 ns 0 ns 2.25 ns Parameter Value Min Max RAM Cell Asynchronous Read Timing rPDRD 1.99 ns Figure 38: RAM Cell Synchronous and Asynchronous Read Timing RCLK RA tSRA tHRA RE tSRE tHRE new data RD old data tRCRD rPDRD 38 * www.quicklogic.com * * * * * (c) 2005 QuickLogic Corporation QL58x0 Enhanced QuickPCI Target Family Data Sheet Rev. I Figure 39: QL58x0 Device Family I/O Cell Output Path PAD OUTPUT REGISTER Figure 40: QL58x0 Device Family I/O Cell Output Enable Timing tOUTHL H L H Z L H Z L tOUTLH H L H tPZH Z L H Z L tPZL tPHZ tPLZ (c) 2005 QuickLogic Corporation www.quicklogic.com * * * * * * 39 QL58x0 Enhanced QuickPCI Target Family Data Sheet Rev. I Table 23: QL58x0 Device Family I/O Cell Output Timing Symbol Output Register Cell Only tOUTLH tOUTHL tPZH tPZL tPHZ tPLZ tCOP Output Delay low to high (90% of H) Output Delay high to low (10% of L) Output Delay tri-state to high (90% of H) Output Delay tri-state to low (10% of L) Output Delay high to tri-State Output Delay low to tri-State Clock-to-out delay (does not include clock tree delays) Parameter Min Value (ns) Max 2.95 2.49 3.93 2.84 3.62 3.4 3.3 (fast slew) 5.49 (slow slew) Table 24: Output Slew Rates @ VCCIO = 3.3 V, T = 25 C Fast Slew Rising Edge Falling Edge 2.8 V/ns 2.86 V/ns Slow Slew 1.0 V/ns 1.0 V/ns Table 25: Output Slew Rates @ VCCIO = 2.5 V, T = 25 C Fast Slew Rising Edge Falling Edge 1.7 V/ns 1.9 V/ns Slow Slew 0.6 V/ns 0.6 V/ns Table 26: Output Slew Rates @ VCCIO = 1.8 V, T = 25 C Fast Slew Rising Edge Falling Edge Slow Slew - 40 * www.quicklogic.com * * * * * (c) 2005 QuickLogic Corporation QL58x0 Enhanced QuickPCI Target Family Data Sheet Rev. I Figure 41: QL58x0 Device Family I/O Cell Input Path tISU + tSID QE R D PAD Figure 42: QL58x0 Device Family Input Register Cell Timing R CLK D tIS U tIH L Q tIC O tIR S T E tIE S U tIE H I R i C ll T i i (c) 2005 QuickLogic Corporation www.quicklogic.com * * * * * * 41 QL58x0 Enhanced QuickPCI Target Family Data Sheet Rev. I Table 27: I/O Input Register Cell Timing Symbol tISU tIHL tICO tIRST tIESU tIEH Parameter Input register setup time: time the synchronous input of the flip-flop must be stable before the active clock edge Input register hold time: time the synchronous input of the flip-flop must be stable after the active clock edge Input register clock-to-out: time taken by the flip-flop to output after the active clock edge Input register reset delay: time between when the flip-flop is "reset"(low) and when the output is consequently "reset" (low) Input register clock enable setup time: time "enable" must be stable before the active clock edge Input register clock enable hold time: time "enable" must be stable after the active clock edge Value Min 2.15 ns 0 ns 0.4 ns 0 ns Max 0.3 ns 0.82 ns - Table 28: I/O Input Buffer Delays Symbol tSID (LVTTL) tSID (LVCMOS2) Parameter To get the total input delay add this delay to tISU LVTTL input delay: Low Voltage TTL for 3.3 V applications LVCMOS2 input delay: Low Voltage CMOS for 2.5 V and lower applications GTL+ input delay: Gunning Transceiver Logic SSTL3 input delay: Stub Series Terminated Logic for 3.3 V SSTL2 input delay: Stub Series Terminated Logic for 2.5 V Min Value Max 0.82 ns 0.82 ns 0.94 ns 0.94 ns 0.94 ns tSID (LVCMOS18) LVCMOS18 input delay: Low Voltage CMOS for 1.8 V applications tSID (GTL+) tSID (SSTL3) tSID (SSTL2) 42 * www.quicklogic.com * * * * * (c) 2005 QuickLogic Corporation QL58x0 Enhanced QuickPCI Target Family Data Sheet Rev. I Package Thermal Characteristics Thermal Resistance Equations: JC = (TJ - TC)/P JA = (TJ - TA)/P PMAX = (TJMAX - TAMAX)/ Parameter Description: JA JC: Junction-to-case thermal resistance JA: Junction-to-ambient thermal resistance TJ: Junction temperature TA: Ambient temperature P: Power dissipated by the device while operating PMAX: The maximum power dissipation for the device TJMAX: Maximum junction temperature TAMAX: Maximum ambient temperature NOTE: Maximum junction temperature (TJMAX) is 125C. To calculate the maximum power dissipation for a device package look up JA from Table 29, pick an appropriate TAMAX and use: PMAX = (125C - TAMAX)/ JA Table 29: Package Thermal Characteristics Device Package Description Package Code Package Type PS PBGA LFBGA PQFP LFBGA PQFP TFBGA TQFP TFBGA TQFP PT PQ PT PQ PT PF PT PF Pin Count 484 280 208 280 208 196 144 196 144 0 LFM 26.6 34 32 34 43.6 40 37 54 41 JA (C/W) 200 LFM 24.1 31.6 28 31.6 41 38 36 51.8 39 400 LFM 21.8 29.9 26.5 29.9 39 35.2 34 48 37 QL5840 QL5820 QL5810 (c) 2005 QuickLogic Corporation www.quicklogic.com * * * * * * 43 QL58x0 Enhanced QuickPCI Target Family Data Sheet Rev. I Kv and Kt Graphs Figure 43: Voltage Factor vs. Supply Voltage Voltage Factor vs. Supply Voltage 1.06 1.04 1.02 Kv 1 0.98 0.96 0.94 1.95 1.89 1.85 1.8 1.75 1.71 1.65 Supply Voltage (V) Kv Figure 44: Temperature Factor vs. Operating Temperature Temperature Factor vs. Operating Temperature 1.2 1.15 1.1 1.05 Kt 1 0.95 0.9 0.85 0.8 -60 -55 -40 0 25 85 125 130 Junction Temperature (C) Kt 44 * www.quicklogic.com * * * * * (c) 2005 QuickLogic Corporation QL58x0 Enhanced QuickPCI Target Family Data Sheet Rev. I Power vs. Operating Frequency The basic power equation which best models power consumption is given below: PTOTAL = 0.350 + f[0.0031 LC + 0.0948 CKBF + 0.01 CLBF + 0.0263 0.543 RAM + 0.20 PLL + 0.0035 INP + 0.0257 OUTP] (mW) Where: CKLD + LC is the total number of logic cells in the design CKBF = # of clock buffers CLBF = # of column clock buffers CKLD = # of loads connected to the column clock buffers RAM = # of RAM blocks PLL = # of PLLs INP is the number of input pins OUTP is the number of output pins NOTE: To learn more about power consumption, see QuickLogic Application Note 60 at http://www.quicklogic.com/images/appnote60.pdf. Power-up Sequencing Figure 45: Power-Up Sequencing VCCIO VDED VDED2 VPUMP VCC |VCCIO , VDED , VDED2 , VPUMP - VCC|MAX Voltage VCC 400 us When powering up a device, the VCC/VCCIO/VDED/VDED2 rails must take 400 s or longer to reach the maximum value (refer to Figure 45). NOTE: Ramping VCC, VCCIO, VPUMP, VDED, or VDED2 faster than 400 s can cause the device to behave improperly. For users with a limited power budget, ensure VCCIO, VDED, VDED2, and VPUMP are within 500 mV of VCC when ramping up the power supplies. www.quicklogic.com * * Ti * * * * (c) 2005 QuickLogic Corporation 45 QL58x0 Enhanced QuickPCI Target Family Data Sheet Rev. I Pin Descriptions Table 30: Pin Descriptions Pin Direction Function JTAG Pin Descriptions TDI/RSI I Test Data In for JTAG/RAM init. Serial Data In Active low Reset for JTAG/RAM init. reset out Test Mode Select for JTAG Test Clock for JTAG Hold HIGH during normal operation. Connects to serial PROM data in for RAM initialization. Connect to VDED2 if unused Hold LOW during normal operation. Connects to serial PROM reset for RAM initialization. Connect to GND if unused Hold HIGH during normal operation. Connect to VDED2 if not used for JTAG Hold HIGH or LOW during normal operation. Connect to VDED2 or GND if not used for JTAG Description TRSTB/RRO TMS TCK I/0 I I TDO/RCO O Connect to serial PROM clock for RAM initialization. Must be Test data out for JTAG/RAM init. left unconnected if not used for JTAG or RAM initialization. clock out The output voltage drive is specified by VDED. Dedicated Pin Descriptions Low skew global clock. This pin provides access to a dedicated, distributed network capable of driving the CLOCK, SET, RESET, F1, and A2 inputs to the Logic Cell, READ, and WRITE CLOCKS, Read and Write Enables of the Embedded RAM Blocks, CLOCK of the ECUs, and Output Enables of the I/Os. The voltage tolerance of this pin is specified by VDED. The I/O pin is a bi-directional pin, configurable to either an input-only, output-only, or bi-directional pin. The A inside the parenthesis means that the I/O is located in Bank A. If an I/O is not used, SpDE (QuickWorks Tool) provides the option of tying that pin to GND, VCC, or TriState. Connect to 1.8 V supply. This pin provides the flexibility to interface the device with either a 3.3 V, 2.5 V, or 1.8 V device. The A inside the parenthesis means that VCCIO is located in BANK A. Every I/O pin in Bank A will be tolerant of VCCIO input signals and will drive VCCIO level output signals. This pin must be connected to either 3.3 V, 2.5 V, or 1.8 V. VCCIO powers the the PLLOUT pins. Connect to ground. Clock input for PLL. The voltage tolerance of this pin is specified by VDED. Very low skew global clock. This pin provides access to a dedicated, distributed clock network capable of driving the CLOCK inputs of all sequential elements of the device (e.g., RAM, Flip Flops). The voltage tolerance of this pin is specified by VDED. Connect to GND. CLK I Global clock network pin I/O(A) I/O Input/Output pin VCC I Power supply pin VCCIO(A) I Input voltage tolerance pin GND PLLIN I I Ground pin PLL clock input DEDCLK I Dedicated clock pin GNDPLL I Ground pin for PLL 46 * www.quicklogic.com * * * * * (c) 2005 QuickLogic Corporation QL58x0 Enhanced QuickPCI Target Family Data Sheet Rev. I Table 30: Pin Descriptions (Continued) Pin Direction Function Description The INREF is the reference voltage pin for GTL+, SSTL2, and STTL3 standards. Follow the recommendations provided in Table 18 for the appropriate standard. The A inside the parenthesis means that INREF is located in BANK A. This pin should be tied to GND if voltage referenced standards are not used. Dedicated PLL output pin. Must be left unconnected if PLL is powered up and not held in reset, since PLLOUT will be driving the PLL-derived clock. May be left unconnected if PLL is held in reset or not powered up. PLLOUT pin is driven by VCCIO. For a list of each PLLOUT pin and the VCCIO pin that powers it see Table 31. This pin provides fast RESET, SET, CLOCK, and ENABLE access to the I/O cell flip-flops, providing fast clock-to-out and fast I/O response times. This pin can also double as a highdrive pin to the internal logic cells. The A inside the parenthesis means that IOCTRL is located in Bank A. There is an internal pulldown resistor to GND on this pin. This pin should be tied to GND if it is not used. For backwards compatibility with QL5632/QL5732, it can be tied to VDED or GND. If tied to VDED, it will draw no more than 20 A per IOCTRL pin due to current through the pulldown resistor. The voltage tolerance of this pin is specified by VDED. Note that the 208 PQFP package has no I/O control pins. This pin disables the internal charge pump for lower static power consumption. To disable the charge pump, connect VPUMP to 3.3 V. If the Disable Charge Pump feature is not used, connect VPUMP to GND. For backwards compatibility with QL5632/QL5732 devices, connect VPUMP to GND. This pin specifies the input voltage tolerance for CLK, DEDCLK, PLLIN, and IOCTRL dedicated input pins, as well as the output voltage drive TDO JTAG pins. If the PLLs are used, VDED must be the same as VCCPLL. The legal range for VDED is between 1.71 V and 3.6 V. For backwards compatibility with QL5632/QL5732 devices, connect VDED to 2.5 V. INREF(A) I Differential reference voltage PLLOUT O PLL output pin IOCTRL(A) I Highdrive input VPUMP I Charge Pump Disable VDED I Voltage tolerance for clocks, TDO JTAG output, and IOCTRL (c) 2005 QuickLogic Corporation www.quicklogic.com * * * * * * 47 QL58x0 Enhanced QuickPCI Target Family Data Sheet Rev. I Table 30: Pin Descriptions (Continued) Pin Direction Function Description These pins specify the input voltage tolerance for the JTAG input pins. The legal range for VDED2 is between 1.71 V and 3.6 V. These do not specify output voltage of the JTAG output, TDO. Refer to the VDED pin section for specifying the JTAG output voltage. Connect to 2.5 V or 3.3. V supply. For backwards compatibility with QL5632/QL5732 devices, connect to 2.5 V. To minimize static power consumption when designs do not utilize the PLLs, you may connect VCCPLL to GND. If VCCPLL is grounded, the PLL is disabled. If PLL_RESET is asserted, then CLKNET_OUT and PLLPAD_OUT are reset to 0. This signal must be asserted and then released in order for the LOCK_DETECT to work. If a PLL module is not used, then the associated PLLRST VDED2 I Voltage tolerance for JTAG pins (TDI, TMS, TCK, and TRSTB) VCCPLL I Power Supply pin for PLL PLL_RESET I PLL reset pin Table 31: PLLOUT Pin Supply Voltage PLLOUT PLLOUT(0) PLLOUT(1) PLLOUT(2) PLLOUT(3) VCCIO VCCIO(E) VCCIO(B) VCCIO(A) VCCIO(F) 48 * www.quicklogic.com * * * * * (c) 2005 QuickLogic Corporation QL58x0 Enhanced QuickPCI Target Family Data Sheet Rev. I Figure 46: QL5840 I/O Banks with Relevant Pins IOCTRL(A) VCCIO (A) INREF(A) VCCIO (A) INREF(A) IOCTRL(A) IO(A) IO BANK A VCCIO (H) INREF(H) IOCTRL(H) IO(H) IO BANK B VCCIO (C) INREF(C) IOCTRL(C) IO(C) IO BANK H IO(A) IO BANK C IO BANK G VCCIO (G) INREF(G) IOCTRL(G) IO(G) VCCIO (D) INREF(D) IOCTRL(D) IO(D) IO BANK D IO BANK F IO BANK E INREF(E) IO(E) INREF(F) IO(F) VCCIO (E) IOCTRL(E) Figure 1: QL5810 and QL5820 I/O Banks with Relevant Pins VCCIO (F) IOCTRL(F) IO BANK B VCCIO (A) IO(A) VCCIO (B IO(B) IO BANK A INREF (c) 2005 QuickLogic Corporation www.quicklogic.com * * * * * * 49 QL58x0 Enhanced QuickPCI Target Family Data Sheet Rev. I Recommended Unused Pin Terminations for QL58x0 Device Family All unused, general purpose I/O pins can be tied to VCC, GND, or HIZ (high impedance) internally using the Configuration Editor. This option is given in the bottom-right corner of the placement window. To use the Placement Editor, choose Constraint > Fix Placement in the Option pull-down menu of SpDE. The rest of the pins should be terminated at the board level in the manner presented in Table 32. Table 32: Recommended Unused Pin Terminations Signal Name Recommended Termination In earlier versions, the recommendation for unused PLLOUT pins was that they be connected to VCC or GND. This was acceptable for Rev. D (and earlier) silicon, including all 0.25 m devices. For Rev. G (and later) silicon this is not correct. Unused PLLOUT pins should be left unconnected. Used PLLOUT pins will normally be connected to inputs, but can also be left unconnected. For the truth table of PLLOUT connections, refer to Table 33. There is an internal pulldown resistor to GND on this pin. This pin should be tied to GND if it is not used. For backwards compatibility with Eclipse, it can be tied to VDED or GND. If tied to VDED, it will draw no more than 20 A per IOCTRL pin due to current through the pulldown resistor. Any unused clock pins should be connected to VDED or GND. If a PLL module is not used, then the associated PLLRST PLLOUT IOCTRL a. x represents a number. b. y represents an alphabetical character. Table 33: Recommended PLLOUT Terminations Truth Table PLL_RESET 0 1 Recommended PLLOUT Termination Must be left unconnected. May be left unconnected, or connected to GND. Must not be connected to VCC. 50 * www.quicklogic.com * * * * * (c) 2005 QuickLogic Corporation QL58x0 Enhanced QuickPCI Target Family Data Sheet Rev. I QL5810 - 144 TQFP Pinout Diagram Pin 1 Pin 109 QuickPCI QL5810-33BPF144C Pin 37 Pin 73 (c) 2005 QuickLogic Corporation www.quicklogic.com * * * * * * 51 QL58x0 Enhanced QuickPCI Target Family Data Sheet Rev. I QL5810 - 144 TQFP Pinout Table Table 34: QL5810 - 144 TQFP Pinout Table Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Function GND GND IO(A) IO(A) IO(A) IO(A) VCC IO(A) IO(A) IO(A) IO(A) IO(A) VCCIO(A) IO(A) TDI CLK(0) CLK(1) VCC IO(A) VDED IO(A) IO(A) GND VCCIO(A) IO(A) IO(A) IO(A) IO(A) IO(A) IO(A) IO(A) IO(A) IO(A) TDO GND IO(A) Pin 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 Function IO(A) GND IO(A) VCCIO(A) IO(A) IO(A) IO(A) IO(A) IO(A) IO(A) IO(A) IO(A) VCCIO(A) IO(A) IO(A) VCC TRSTB VDED2 IO(A) IO(A) IO(A) GND IO(A) VCC IO(A) IO(A) IO(A) IO(A) IO(A) IO(A) IO(A) IO(A) VCCIO(A) IO(A) VPUMP IO(A) Pin 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 Function IO(A) IO(B) GND IO(B) RSTN IO(B) VCC IO(B) AD(31) INREF AD(30) AD(29) AD(28) VCCIO(B) AD(27) AD(26) AD(25) (PCI)CLK CLK(3) VCC CLK(4) TMS AD(24) GND VCCIO(B) CBEN(3) IDSEL AD(23) AD(22) AD(21) AD(20) AD(19) AD(18) AD(17) GND AD(16) Pin 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 Function GND CBEN(2) VCCIO(B) FRAMEN DEVSELN TRDYN IRDYN STOPN PERRN SERRN PAR VCC CBEN(1) VCCIO(B) AD(15) AD(14) VCC TCK VDED2 AD(13) AD(12) GND AD(11) AD(10) AD(9) AD(8) CBEN(0) AD(7) AD(6) AD(5) AD(4) AD(3) VCCIO(B) AD(2) AD(1) AD(0) VCCIO(B) must be connected to VCCIO(PCI) 3.3 V. Summary: 47 PCI pins, 54 user I/O, and 4 GCLK. 52 * www.quicklogic.com * * * * * (c) 2005 QuickLogic Corporation QL58x0 Enhanced QuickPCI Target Family Data Sheet Rev. I QL5810 - 196 TFBGA Pinout Diagram Top QuickPCI QL5810-66CPT196C Bottom 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P Pin A1 Corner (c) 2005 QuickLogic Corporation www.quicklogic.com * * * * * * 53 QL58x0 Enhanced QuickPCI Target Family Data Sheet Rev. I QL5810 - 196 TFBGA Pinout Table Table 35: QL5810 - 196 TFBGA Pinout Table Ball A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 Function AD(23) CBEN(3) AD(25) AD(27) AD(24) AD(28) CLK(4) CLK(2) AD(31) RSTN INREF IO(B) IO(B) IO(B) AD(19) AD(21) AD(20) IO(B) AD(26) TMS VCC AD(30) IO(B) IO(B) IO(B) IO(B) IO(A) IO(A) DEVSELN AD(17) AD(18) VCC AD(22) VCC AD(29) (PCI)CLK IO(B) VCC IO(B) IO(A) Ball C13 C14 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 Function IO(A) IO(A) STOPN IRDYN AD(16) IDSEL IO(B) VCCIO(B) VCCIO(B) VDED VCCIO(B) IO(B) IO(B) VPUMP IO(A) IO(A) SERRN PERRN FRAMEN CBEN(2) VCCIO(B) GND GND GND GND IO(A) VCCIO(A) IO(A) IO(A) VCC AD(15) VCC TRDYN PAR VCCIO(B) GND GND GND GND IO(A) Ball F11 F12 F13 F14 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 J1 J2 J3 J4 J5 J6 J7 J8 Function IO(A) IO(A) IO(A) IO(A) AD(14) TCK CBEN(1) VCC GND GND GND GND GND GND IO(A) VCC IO(A) IO(A) AD(11) AD(12) VDED2 VCCIO(B) GND GND GND GND GND GND VCCIO(A) TRSTB VDED2 VCC AD(10) AD(9) AD(8) VCC AD(13) GND GND GND Ball J9 J10 J11 J12 J13 J14 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 M1 M2 M3 M4 M5 M6 Function GND GND IO(A) IO(A) IO(A) IO(A) CBEN(0) AD(6) AD(7) IO(B) VCCIO(B) VCCIO(A) GND GND VCCIO(A) VCCIO(A) IO(A) IO(A) IO(A) IO(A) AD(4) AD(3) AD(5) AD(0) IO(A) IO(A) VCCIO(A) VDED VDED VCCIO(A) VCC IO(A) IO(A) IO(A) AD(2) AD(1) IO(A) GND VCC TDI Ball M7 M8 M9 M10 M11 M12 M13 M14 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 Function VCC IO(A) IO(A) IO(A) IO(A) IO(A) IO(A) IO(A) IO(B) IO(B) IO(A) IO(A) IO(A) IO(A) IO(A) IO(A) IO(A) IO(A) IO(A) TDO IO(A) IO(A) IO(A) IO(A) IO(A) IO(A) IO(A) CLK(0) CLK(1) IO(A) IO(A) IO(A) IO(A) IO(A) IO(A) IO(A) VCCIO(B) must be connected to VCCIO(PCI) 3.3 V. Summary: 47 PCI pins, 78 user I/O, and 4 GCLK. 54 * www.quicklogic.com * * * * * (c) 2005 QuickLogic Corporation QL58x0 Enhanced QuickPCI Target Family Data Sheet Rev. I QL5820 - 144 TQFP Pinout Diagram Pin 1 Pin 109 QuickPCI QL5820-33BPF144C Pin 37 Pin 73 (c) 2005 QuickLogic Corporation www.quicklogic.com * * * * * * 55 QL58x0 Enhanced QuickPCI Target Family Data Sheet Rev. I QL5820 - 144 TQFP Pinout Table Table 36: QL5820 - 144 TQFP Pinout Table Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Function GND GND IO(A) IO(A) IO(A) IO(A) VCC IO(A) IO(A) IO(A) IO(A) IO(A) VCCIO(A) IO(A) TDI CLK(0) CLK(1) VCC IO(A) VDED IO(A) IO(A) GND VCCIO(A) IO(A) IO(A) IO(A) IO(A) IO(A) IO(A) IO(A) IO(A) IO(A) TDO GND IO(A) Pin 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 Function IO(A) GND IO(A) VCCIO(A) IO(A) IO(A) IO(A) IO(A) IO(A) IO(A) IO(A) IO(A) VCCIO(A) IO(A) IO(A) VCC TRSTB VDED2 IO(A) IO(A) IO(A) GND IO(A) VCC IO(A) IO(A) IO(A) IO(A) IO(A) IO(A) IO(A) IO(A) VCCIO(A) IO(A) VPUMP IO(A) Pin 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 Function IO(A) IO(B) GND IO(B) RSTN IO(B) VCC IO(B) AD(31) INREF AD(30) AD(29) AD(28) VCCIO(B) AD(27) AD(26) AD(25) (PCI)CLK CLK(3) VCC CLK(4) TMS AD(24) GND VCCIO(B) CBEN(3) IDSEL AD(23) AD(22) AD(21) AD(20) AD(19) AD(18) AD(17) GND AD(16) Pin 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 Function GND CBEN(2) VCCIO(B) FRAMEN DEVSELN TRDYN IRDYN STOPN PERRN SERRN PAR VCC CBEN(1) VCCIO(B) AD(15) AD(14) VCC TCK VDED2 AD(13) AD(12) GND AD(11) AD(10) AD(9) AD(8) CBEN(0) AD(7) AD(6) AD(5) AD(4) AD(3) VCCIO(B) AD(2) AD(1) AD(0) VCCIO(B) must be connected to VCCIO(PCI) 3.3 V. Summary: 47 PCI pins, 54 user I/O, and 4 GCLK. 56 * www.quicklogic.com * * * * * (c) 2005 QuickLogic Corporation QL58x0 Enhanced QuickPCI Target Family Data Sheet Rev. I QL5820 - 196 TFBGA Pinout Diagram Top QuickPCI QL5820-66CPT196C Bottom 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P Pin A1 Corner (c) 2005 QuickLogic Corporation www.quicklogic.com * * * * * * 57 QL58x0 Enhanced QuickPCI Target Family Data Sheet Rev. I QL5820 - 196 TFBGA Pinout Table Table 37: QL5820 - 196 TFBGA Pinout Table Ball A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 Function AD(23) CBEN(3) AD(25) AD(27) AD(24) AD(28) CLK(4) CLK(2) AD(31) RSTN INREF IO(B) IO(B) IO(B) AD(19) AD(21) AD(20) IO(B) AD(26) TMS VCC AD(30) IO(B) IO(B) IO(B) IO(B) IO(B) IO(B) DEVSELN AD(17) AD(18) VCC AD(22) VCC AD(29) (PCI)CLK IO(B) VCC IO(B) IO(A) Ball C13 C14 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 Function IO(A) IO(A) STOPN IRDYN AD(16) IDSEL IO(B) VCCIO(B) VCCIO(B) VDED VCCIO(B) IO(B) IO(A) VPUMP IO(A) IO(A) SERRN PERRN FRAMEN CBEN(2) VCCIO(B) GND GND GND GND IO(B) VCCIO(A) IO(A) IO(A) VCC AD(15) VCC TRDYN PAR VCCIO(B) GND GND GND GND IO(A) Ball F11 F12 F13 F14 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 J1 J2 J3 J4 J5 J6 J7 J8 Function IO(A) IO(A) IO(A) IO(A) AD(14) TCK CBEN(1) VCC GND GND GND GND GND GND IO(A) VCC IO(A) IO(A) AD(11) AD(12) VDED2 VCCIO(B) GND GND GND GND GND GND VCCIO(A) TRSTB VDED2 VCC AD(10) AD(9) AD(8) VCC AD(13) GND GND GND Ball J9 J10 J11 J12 J13 J14 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 M1 M2 M3 M4 M5 M6 Function GND GND IO(A) IO(A) IO(A) IO(A) CBEN(0) AD(6) AD(7) IO(A) VCCIO(B) VCCIO(A) GND GND VCCIO(A) VCCIO(A) IO(A) IO(A) IO(A) IO(A) AD(4) AD(3) AD(5) AD(0) IO(A) IO(A) VCCIO(A) VDED VDED VCCIO(A) VCC IO(A) IO(A) IO(A) AD(2) AD(1) IO(B) GND VCC TDI Ball M7 M8 M9 M10 M11 M12 M13 M14 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 Function VCC IO(A) IO(A) IO(A) IO(A) IO(A) IO(A) IO(A) IO(A) IO(A) IO(A) IO(A) IO(A) IO(A) IO(A) IO(A) IO(A) IO(A) IO(A) TDO IO(A) IO(A) IO(A) IO(A) IO(A) IO(A) IO(A) CLK(0) CLK(1) IO(A) IO(A) IO(A) IO(A) IO(A) IO(A) IO(A) VCCIO(B) must be connected to VCCIO(PCI) 3.3 V. Summary: 47 PCI pins, 78 user I/O, and 4 GCLK. 58 * www.quicklogic.com * * * * * (c) 2005 QuickLogic Corporation QL58x0 Enhanced QuickPCI Target Family Data Sheet Rev. I QL5820 - 208 PQFP Pinout Diagram Top QuickPCI QL5820-66CPQ208C (c) 2005 QuickLogic Corporation www.quicklogic.com * * * * * * 59 QL58x0 Enhanced QuickPCI Target Family Data Sheet Rev. I QL5820 - 208 PQFP Pinout Table Table 38: QL5820 - 208 PQFP Pinout Table Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 Function I/O(A) I/O(A) GND GND I/O(A) I/O(A) I/O(A) VCCIO(A) I/O(A) I/O(A) I/O(A) VCC I/O(A) I/O(A) I/O(A) I/O(A) I/O(A) I/O(A) VCCIO(A) I/O(A) GND I/O(A) TDI CLK(0) CLK(1) VCC I/O(A) I/O(A) VDED I/O(A) I/O(A) I/O(A) GND VCCIO(A) I/O(A) Pin 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 Function I/O(A) I/O(A) I/O(A) I/O(A) I/O(A) I/O(A) I/O(A) I/O(A) VCCIO(A) I/O(A) VCC I/O(A) I/O(A) GND TDO I/O(A) GND I/O(A) I/O(A) I/O(A) VDED I/O(A) GND I/O(A) VCCIO(A) I/O(A) I/O(A) I/O(A) I/O(A) I/O(A) I/O(A) I/O(A) I/O(A) I/O(A) I/O(A) Pin 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 Function I/O(A) VCCIO(A) I/O(A) I/O(A) GND VCC I/O(A) TRSTB VDED2 I/O(A) I/O(A) I/O(A) GND VCCIO(A) I/O(A) VCC I/O(A) I/O(A) VCC I/O(A) I/O(A) I/O(A) I/O(A) I/O(A) I/O(A) I/O(A) I/O(A) VCCIO(A) I/O(A) I/O(A) VPUMP I/O(A) I/O(A) GND I/O(B) Pin 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 Function I/O(B) I/O(B) GND I/O(B) I/O(B) VCCIO(B) I/O(B) VCC I/O(B) I/O(B) I/O(B) I/O(B) INREF I/O(B) I/O(B) I/O(B) VCCIO(B) GND RSTN I/O(B) I/O(B) I/O(B) CLK(2) VDED CLK(3) VCC (PCI)CLK TMS AD(31) AD(30) AD(29) GND VCCIO(B) AD(28) AD(27) Pin 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 Function AD(26) AD(25) AD(24) CBEN(3) I/O(B) VCC IDSEL AD(23) AD(22) VCCIO(B) AD(21) AD(20) GND AD(19) I/O(B) GND I/O(B) I/O(B) I/O(B) GND AD(18) VCCIO(B) AD(17) AD(16) VCC CBEN(2) FRAMEN IRDYN TRDYN I/O(B) DEVSELN STOPN PERRN SERRN VCC Pin 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 Function PAR VCCIO(B) GND CBEN(1) AD(15) AD(14) VCC TCK VDED2 AD(13) AD(12) AD(11) GND VCCIO(B) AD(10) AD(9) AD(8) CBEN(0) I/O(B) VCC AD(7) AD(6) AD(5) AD(4) AD(3) AD(2) AD(1) VCCIO(B) GND AD(0) I/O(B) I/O(B) I/O(B) VCCIO(B) must be connected to VCCIO(PCI) 3.3 V. Summary: 47 PCI pins, 97 user I/O, and 4 GCLK. 60 * www.quicklogic.com * * * * * (c) 2005 QuickLogic Corporation QL58x0 Enhanced QuickPCI Target Family Data Sheet Rev. I QL5820 - 280 LFBGA Pinout Diagram Top QuickPCI QL5820-33BPT280C Bottom Pin A1 Corner (c) 2005 QuickLogic Corporation www.quicklogic.com * * * * * * 61 QL58x0 Enhanced QuickPCI Target Family Data Sheet Rev. I QL5820 - 280 LFBGA Pinout Table Table 39: QL5820 - 280 LFBGA Pinout Table Ball A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 C1 C2 C3 C4 C5 C6 C7 C8 C9 Function NC GND AD(18) AD(20) IDSEL NC AD(26) AD(30) RSTN CLK(3) I/O(B) I/O(B) I/O(B) NC I/O(B) I/O(B) I/O(B) NC NC NC NC AD(19) AD(21) CBEN(3) NC AD(27) AD(31) TMS CLK(2) I/O(B) I/O(B) NC I/O(B) I/O(B) I/O(B) NC GND NC CBEN(2) NC AD(17) AD(22) VCCIO(B) NC AD(28) I/O(B) VCCIO(B) Ball C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 Function I/O(B) VCCIO(B) I/O(B) I/O(B) I/O(B) VCCIO(B) I/O(B) I/O(B) I/O(B) I/O(B) TRDYN IRDYN AD(16) AD(23) AD(24) AD(25) AD(29) I/O(B) (PCI) CLK I/O(B) I/O(B) I/O(B) INREF I/O(B) I/O(B) I/O(A) I/O(A) I/O(A) I/O(A) PERRN STOPN VCCIO(B) FRAMEN GND VCC VCC VDED VCC GND GND VCC VCC GND VPUMP I/O(A) VCCIO(A) NC Ball E19 F1 F2 F3 F4 F5 F15 F16 F17 F18 F19 G1 G2 G3 G4 G5 G15 G16 G17 G18 G19 H1 H2 H3 H4 H5 H15 H16 H17 H18 H19 J1 J2 J3 J4 J5 J15 J16 J17 J18 J19 K1 K2 K3 K4 K5 K15 Function NC NC NC SERRN DEVSELN GND VCC NC I/O(A) I/O(A) I/O(A) AD(14) AD(15) NC PAR VCC VCC I/O(A) I/O(A) I/O(A) I/O(A) AD(11) AD(12) AD(13) CBEN(1) VCC VCC VDED2 I/O(A) I/O(A) I/O(A) AD(8) AD(9) VCCIO(B) AD(10) GND VCC I/O(A) VCCIO(A) I/O(A) I/O(A) VDED2 TCK AD(7) CBEN(0) GND GND Ball K16 K17 K18 K19 L1 L2 L3 L4 L5 L15 L16 L17 L18 L19 M1 M2 M3 M4 M5 M15 M16 M17 M18 M19 N1 N2 N3 N4 N5 N15 N16 N17 N18 N19 P1 P2 P3 P4 P5 P15 P16 P17 P18 P19 R1 R2 R3 Function I/O(A) I/O(A) I/O(A) TRSTB AD(4) AD(5) VCCIO(B) AD(6) VCC GND I/O(A) VCCIO(A) I/O(A) I/O(A) AD(0) AD(1) AD(2) AD(3) VCC VDED NC I/O(A) I/O(A) I/O(A) NC I/O(B) I/O(B) I/O(B) VCC VCC I/O(A) I/O(A) NC NC I/O(B) I/O(B) NC NC VCC GND I/O(A) I/O(A) I/O(A) I/O(A) I/O(B) I/O(B) VCCIO(B) Ball R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 U1 U2 U3 U4 U5 U6 U7 U8 U9 U10 U11 U12 Function I/O(B) GND GND VCC VCC GND GND VCC VCC VCC VDED GND I/O(A) VCCIO(A) I/O(A) I/O(A) I/O(B) I/O(B) I/O(A) I/O(A) I/O(A) NC I/O(A) I/O(A) I/O(A) I/O(A) NC I/O(A) I/O(A) I/O(A) I/O(A) I/O(A) NC I/O(A) I/O(A) I/O(A) I/O(A) NC I/O(A) VCCIO(A) NC I/O(A) I/O(A) VCCIO(A) CLK(0) VCCIO(A) I/O(A) Ball U13 U14 U15 U16 U17 U18 U19 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 W15 W16 W17 W18 W19 Function I/O(A) NC VCCIO(A) I/O(A) TDO NC I/O(A) NC GND GND I/O(A) I/O(A) NC I/O(A) I/O(A) I/O(A) CLK(1) NC I/O(A) I/O(A) NC I/O(A) I/O(A) I/O(A) GND NC NC NC I/O(A) I/O(A) I/O(A) I/O(A) I/O(A) I/O(A) TDI I/O(A) I/O(A) I/O(A) I/O(A) NC I/O(A) I/O(A) I/O(A) I/O(A) NC VCCIO(B) must be connected to VCCIO(PCI) (3.3 V). Summary: 47 PCI pins, 118 User I/O and 5 GCLK. 62 * www.quicklogic.com * * * * * (c) 2005 QuickLogic Corporation QL58x0 Enhanced QuickPCI Target Family Data Sheet Rev. I QL5840 - 208 PQFP Pinout Diagram Top QuickPCI QL5840-33BPQ208C (c) 2005 QuickLogic Corporation www.quicklogic.com * * * * * * 63 QL58x0 Enhanced QuickPCI Target Family Data Sheet Rev. I QL5840 - 208 PQFP Pinout Table Table 40: QL5840 - 208 PQFP Pinout Table Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 Function PLLRST(3) VCCPLL(3) GND GND I/O(A) I/O(A) I/O(A) VCCIO(A) I/O(A) I/O(A) I/O(A) VCC INREF(A) I/O(A) I/O(A) I/O(A) I/O(A) I/O(A) VCCIO(A) I/O(A) GND I/O(A) TDI CLK(0) CLK(1) VCC CLK(2) PLLIN(2) CLK(3) PLLIN(1) VDED CLK(4) PLLIN(0) I/O(B) I/O(B) GND VCCIO(B) I/O(B) Pin 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 Function I/O(B) I/O(B) I/O(B) I/O(B) INREF(B) I/O(B) I/O(B) I/O(B) VCCIO(B) I/O(B) VCC I/O(B) I/O(B) GND TDO PLLOUT(1) GNDPLL(2) GND VCCPLL(2) PLLRST(2) VDED I/O(C) GND I/O(C) VCCIO(C) I/O(C) I/O(C) I/O(C) I/O(C) I/O(C) I/O(C) I/O(C) INREF(C) I/O(C) I/O(C) Pin 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 Function I/O(C) VCCIO(C) I/O(C) I/O(C) GND VCC I/O(C) TRSTB VDED2 I/O(D) I/O(D) I/O(D) GND VCCIO(D) I/O(D) VCC I/O(D) I/O(D) VCC I/O(D) I/O(D) I/O(D) INREF(D) I/O(D) I/O(D) I/O(D) I/O(D) VCCIO(D) I/O(D) I/O(D) VPUMP PLLOUT(0) GND GNDPLL(1) PLLRST(1) Pin 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 Function VCCPLL(1) I/O(E) GND I/O(E) I/O(E) VCCIO(E) I/O(E) VCC I/O(E) I/O(E) I/O(E) I/O(E) INREF(E) I/O(E) I/O(E) I/O(E) VCCIO(E) GND RSTN I/O(E) I/O(E) CLK(5) PLLIN(3) CLK(6) VDED CLK(7) VCC (PCI)CLK TMS AD(31) AD(30) AD(29) GND VCCIO(F) AD(28) AD(27) Pin 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 Function AD(26) AD(25) AD(24) CBEN(3) INREF(F) VCC IDSEL AD(23) AD(22) VCCIO(F) AD(21) AD(20) GND AD(19) PLLOUT(3) GNDPLL(0) GND VCCPLL(0) PLLRST(0) GND AD(18) VCCIO(G) AD(17) AD(16) VCC CBEN(2) FRAMEN IRDYN TRDYN INREF(G) DEVSELN STOPN PERRN SERRN VCC Pin 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 Function PAR VCCIO(G) GND CBEN(1) AD(15) AD(14) VCC TCK VDED2 AD(13) AD(12) AD(11) GND VCCIO(H) AD(10) AD(9) AD(8) CBEN(0) INREF(H) VCC AD(7) AD(6) AD(5) AD(4) AD(3) AD(2) AD(1) VCCIO(H) GND AD(0) PLLOUT(2) GND GNDPLL(3) VCCIO(E), VCCIO(F), VCCIO(G), and VCCIO(H) must be connected to VCCIO(PCI) 3.3 V. Summary: 47 PCI pins, 69 user I/O, and 8 GCLK. 64 * www.quicklogic.com * * * * * (c) 2005 QuickLogic Corporation QL58x0 Enhanced QuickPCI Target Family Data Sheet Rev. I QL5840 - 280 LFBGA Pinout Diagram Top QuickPCI QL5840-33BPT280C Bottom Pin A1 Corner (c) 2005 QuickLogic Corporation www.quicklogic.com * * * * * * 65 QL58x0 Enhanced QuickPCI Target Family Data Sheet Rev. I QL5840 - 280 LFBGA Pinout Table Table 41: QL5840 - 280 LFBGA Pinout Table Ball A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 C1 C2 C3 C4 C5 C6 C7 C8 C9 Function PLLOUT(3) GNDPLL(0) AD(18) AD(20) IDSEL IOCTRL(F) AD(26) AD(30) RSTN CLK(7) I/O(E) I/O(E) I/O(E) IOCTRL(E) I/O(E) I/O(E) I/O(E) PLLRST(1) GND PLLRST(0) GND AD(19) AD(21) CBEN(3) INREF(F) AD(27) AD(31) TMS CLK(6) I/O(E) I/O(E) IOCTRL(E) I/O(E) I/O(E) I/O(E) VCCPLL(1) GNDPLL(1) PLLOUT(0) CBEN(2) VCCPLL(0) AD(17) AD(22) VCCIO(F) IOCTRL(F) AD(28) I/O(F) VCCIO(F) Ball C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 Function CLK(5)/ PLLIN(3) VCCIO(E) I/O(E) I/O(E) I/O(E) VCCIO(E) I/O(E) I/O(E) I/O(E) I/O(E) TRDYN IRDYN AD(16) AD(23) AD(24) AD(25) AD(29) I/O(F) (PCI) CLK I/O(E) I/O(E) I/O(E) INREF(E) I/O(E) I/O(E) I/O(D) I/O(D) I/O(D) I/O(D) PERRN STOPN VCCIO(G) FRAMEN GND VCC VCC VDED VCC GND GND VCC VCC GND VPUMP I/O(D) VCCIO(D) INREF(D) Ball E19 F1 F2 F3 F4 F5 F15 F16 F17 F18 F19 G1 G2 G3 G4 G5 G15 G16 G17 G18 G19 H1 H2 H3 H4 H5 H15 H16 H17 H18 H19 J1 J2 J3 J4 J5 J15 J16 J17 J18 J19 K1 K2 K3 K4 K5 K15 Function IOCTRL(D) INREF(G) IOCTRL(G) SERRN DEVSELN GND VCC IOCTRL(D) I/O(D) I/O(D) I/O(D) AD(14) AD(15) IOCTRL(G) PAR VCC VCC I/O(D) I/O(D) I/O(D) I/O(D) AD(11) AD(12) AD(13) CBEN(1) VCC VCC VDED2 I/O(D) I/O(D) I/O(D) AD(8) AD(9) VCCIO(G) AD(10) GND VCC I/O(C) VCCIO(D) I/O(D) I/O(D) VDED2 TCK AD(7) CBEN(0) GND GND Ball K16 K17 K18 K19 L1 L2 L3 L4 L5 L15 L16 L17 L18 L19 M1 M2 M3 M4 M5 M15 M16 M17 M18 M19 N1 N2 N3 N4 N5 N15 N16 N17 N18 N19 P1 P2 P3 P4 P5 P15 P16 P17 P18 P19 R1 R2 R3 Function I/O(C) I/O(D) I/O(C) TRSTB AD(4) AD(5) VCCIO(H) AD(6) VCC GND I/O(C) VCCIO(C) I/O(C) I/O(C) AD(0) AD(1) AD(2) AD(3) VCC VDED INREF(C) I/O(C) I/O(C) I/O(C) IOCTRL(H) I/O(H) I/O(H) I/O(H) VCC VCC I/O(C) I/O(C) IOCTRL(C) IOCTRL(C) I/O(H) I/O(H) IOCTRL(H) INREF(H) VCC GND I/O(C) I/O(C) I/O(C) I/O(C) I/O(H) I/O(H) VCCIO(H) Ball R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 U1 U2 U3 U4 U5 U6 U7 U8 U9 U10 U11 U12 Function I/O(H) GND GND VCC VCC GND GND VCC VCC VCC VDED GND I/O(C) VCCIO(C) I/O(C) I/O(C) I/O(H) I/O(H) I/O(A) I/O(A) I/O(A) IOCTRL(A) I/O(A) I/O(A) I/O(A) I/O(A) CLK(3/) PLLIN(1) I/O(B) I/O(B) I/O(B) I/O(B) I/O(B) VCCPLL(2) I/O(B) I/O(B) I/O(A) I/O(A) VCCPLL(3) I/O(A) VCCIO(A) INREF(A) I/O(A) I/O(A) VCCIO(A) CLK(0) VCCIO(B) I/O(B) Ball U13 U14 U15 U16 U17 U18 U19 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 W15 W16 W17 W18 W19 Function I/O(B) IOCTRL(B) VCCIO(B) I/O(B) TDO PLLRST(2) I/O(B) PLLOUT(2) GNDPLL(3) GND I/O(A) I/O(A) IOCTRL(A) I/O(A) I/O(A) I/O(A) CLK(1) CLK(4) DEDCLK/ PLLIN(0) I/O(B) I/O(B) INREF(B) I/O(B) I/O(B) I/O(B) GNDPLL(2) GND GND PLLRST(3) I/O(A) I/O(A) I/O(A) I/O(A) I/O(A) I/O(A) TDI CLK(2)/ PLLIN(2) I/O(B) I/O(B) I/O(B) IOCTRL(B) I/O(B) I/O(B) I/O(B) I/O(B) PLLOUT(1) VCCIO(F), VCCIO(G) and VCCIO(H) must be connected to VCCIO(PCI) (3.3 V). Summary: 47 PCI pins, 117 User I/O and 8 GCLK. 66 * www.quicklogic.com * * * * * (c) 2005 QuickLogic Corporation QL58x0 Enhanced QuickPCI Target Family Data Sheet Rev. I QL5840 - 484 PBGA Pinout Diagrams Top QuickPCI QL5840-66CPS484C Bottom Pin A1 Corner 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T U V W Y AA AB (c) 2005 QuickLogic Corporation www.quicklogic.com * * * * * * 67 QL58x0 Enhanced QuickPCI Target Family Data Sheet Rev. I QL5840 - 484 PBGA Pinout Table Table 42: QL5840 - 484 PBGA Pinout Table Ball A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 C1 C2 C3 Function I/O(A) PLLRST(3) I/O(A) I/O(A) I/O(A) I/O(H) I/O(H) IOCTRL(H) AD(0) N/C N/C TCK AD(10) AD(13) SERRN I/O(G) IRDYN AD(17) AD(20) GND PLLOUT(3) IDSEL I/O(A) GND GNDPLL(3) GND I/O(A) I/O(H) I/O(H) INREF(H) I/O(H) AD(3) AD(6) N/C N/C N/C I/O(G)) DEVSELN FRAMEN AD(19) PLLRST(0) CBEN(3) AD(24) AD(28) I/O(A) I/O(A) VCCPLL(3) Ball C17 C18 C19 C20 C21 C22 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 Function I/O(G) AD(18) AD(23) GNDPLL(0) AD(27) AD(30) I/O(A) I/O(A) I/O(A) I/O(A) I/O(A) I/O(H) I/O(H) I/O(H) I/O(H) AD(4) AD(7) AD(8) AD(14) CBEN(1) IOCTRL(G) CBEN(2) AD(16) AD(22) VCCPLL(0) AD(26) AD(31) RSTN IOCTRL(A) I/O(A) I/O(A) I/O(A) I/O(A) I/O(H) N/C I/O(H) I/O(H) AD(5) VDED2 AD(9) AD(15) I/O(G) IOCTRL(G) STOPN INREF(G) I/O(G) AD(25) Ball F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 G17 G18 G19 G20 G21 G22 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 Function VCCIO(H) VCCIO(G) AD(12) VCCIO(PCI) N/C VCCIO(G) N/C I/O(F) I/O(F) IOCTRL(F) I/O(F) IOCTRL(F) I/O(A) I/O(A) I/O(A) I/O(A) I/O(A) I/O(A) GND I/O(H) I/O(H) I/O(H) CBEN(0) GND I/O(G) I/O(G) PAR VPUMP VCCIO(F) I/O(F) I/O(F) I/O(F) INREF(F) I/O(F) I/O(A) I/O(A) I/O(A) I/O(A) IOCTRL(A) VCCIO(A) I/O(H) GND VCC VCC VDED GND VCC Ball J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 J17 J18 J19 J20 J21 J22 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 K15 K16 K17 K18 K19 K20 K21 K22 L1 L2 L3 L4 L5 L6 L7 Function I/O(A) I/O(A) I/O(A) VCC GND VCC VCC GND VCC GND VCC AD(29) VCCIO(F) I/O(F) I/O(F) I/O(F) I/O(F) I/O(F) TDI I/O(A) I/O(A) I/O(A) I/O(A) VCCIO(A) I/O(A) VCC VCC GND GND GND GND VCC VCC I/O(F) I/O(F) I/O(F) I/O(F) I/O(F) I/O(F) I/O(F) CLK(4) DEDCLK/ PLLIN(0) CLK(0) CLK(2)/ PLLIN(2) I/O(A) I/O(A) I/O(A) GND Ball L21 L22 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 M15 M16 M17 M18 M19 M20 M21 M22 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 N16 N17 N18 N19 N20 N21 N22 P1 Function I/O(F) I/O(F) I/O(B) I/O(B) I/O(B) CLK(3)/ PLLIN(1) I/O(B) VCCIO(B) CLK(1) VCC VCC GND GND GND GND GND GND GND I/O(E) I/O(E) I/O(E) CLK(7) CLK(5)/ PLLIN(3) TMS I/O(B) I/O(B) I/O(B) I/O(B) I/O(B) I/O(B) I/O(B) VCC VCC GND GND GND GND VCC VCC I/O(E) VCCIO(E) I/O(E) I/O(E) I/O(E) I/O(E) I/O(E) I/O(B) Ball P15 P16 P17 P18 P19 P20 P21 P22 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 Function VDED I/O(E) I/O(E) I/O(E) I/O(E) I/O(E) I/O(E) I/O(E) I/O(B) INREF(B) I/O(B) I/O(B) I/O(B) I/O(B) I/O(B) GND VCC VCC GND VDED VCC VCC GND I/O(D) VCCIO(E) I/O(E) I/O(E) I/O(E) I/O(E) I/O(E) I/O(B) I/O(B) I/O(B) I/O(B) I/O(B) VCCIO(B) GND I/O(C) N/C TRSTB GND N/C I/O(D) N/C I/O(D) GND I/O(E) 68 * www.quicklogic.com * * * * * (c) 2005 QuickLogic Corporation QL58x0 Enhanced QuickPCI Target Family Data Sheet Rev. I Table 42: QL5840 - 484 PBGA Pinout Table (Continued) Ball C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 U9 U10 U11 U12 U13 U14 U15 U16 U17 U18 U19 U20 U21 U22 V1 V2 V3 V4 V5 V6 V7 Function PLLOUT(2) I/O(A) I/O(H) I/O(H) I/O(H) IOCTRL(H) I/O(H) AD(2) I/O(H) AD(11) I/O(G) PERRN TRDYN VCCIO(C) I/O(C) VCCIO(C) VCCIO(D) I/O(D) VCCIO(D) N/C VCCIO(D) VCCIO(E) I/O(E) I/O(E) IOCTRL(E) I/O(E) INREF(E) I/O(B) I/O(B) I/O(B) I/O(B) I/O(B) I/O(C) I/O(C) Ball E20 E21 E22 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 V20 V21 V22 W1 W2 W3 W4 W5 W6 Function I/O(F) I/O(F) I/O(F) I/O(A) INREF(A) I/O(A) I/O(A) I/O(A) VCCIO(A) VCCIO(H) I/O(H) VCCIO(H) AD(1) I/O(C) N/C I/O(C) I/O(C) VDED2 N/C I/O(D) I/O(D) INREF(D) I/O(D) I/O(E) I/O(E) I/O(E) I/O(E) I/O(E) I/O(B) I/O(B) I/O(B) I/O(B) I/O(B) I/O(C) Ball H14 H15 H16 H17 H18 H19 H20 H21 H22 J1 J2 J3 J4 W7 W8 W9 W10 W11 W12 W13 W14 W15 W16 W17 W18 W19 W20 W21 W22 Y1 Y2 Y3 Y4 Y5 Function VCC GND AD(21) I/O(F) I/O(F) I/O(F) I/O(F) I/O(F) I/O(F) I/O(A) I/O(A) I/O(A) I/O(A) N/C I/O(C) I/O(C) I/O(C) I/O(C) I/O(D) I/O(D) I/O(D) I/O(D) N/C I/O(D) I/O(E) I/O(E) I/O(E) I/O(E) I/O(E) I/O(B) I/O(B) VCCPLL(2) I/O(C) I/O(C) Ball L8 L9 L10 L11 L12 L13 L14 L15 L16 L17 L18 L19 L20 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20 Y21 Y22 AA1 AA2 AA3 AA4 Function GND GND GND GND GND GND VCC VCC CLK(6) VCCIO(F) I/O(F) (PCI)CLK I/O(F) I/O(C) I/O(C) IOCTRL(C) I/O(C) I/O(C) I/O(D) I/O(D) I/O(D) I/O(D) IOCTRL(D) I/O(D) I/O(D) I/O(E) PLLOUT(0) PLLRST(1) I/O(E) I/O(E) TDO PLLOUT(1) GND I/O(B) Ball P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 AA5 AA6 AA7 AA8 AA9 AA10 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21 AA22 AB1 AB2 AB3 Function I/O(B) I/O(B) I/O(B) I/O(B) VCCIO(B) I/O(B) VCC GND VCC GND VCC VCC GND I/O(C) I/O(C) I/O(C) INREF(C) I/O(C) I/O(C) I/O(C) I/O(D) I/O(D) I/O(D) I/O(D) I/O(D) I/O(D) I/O(D) I/O(E) GNDPLL(1) I/O(E) I/O(E) I/O(B) GNDPLL(2) PLLRST(2) Ball T18 T19 T20 T21 T22 U1 U2 U3 U4 U5 U6 U7 U8 AB4 AB5 AB6 AB7 AB8 AB9 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 Function I/O(E) I/O(E) I/O(E) IOCTRL(E) I/O(E) IOCTRL(B) I/O(B) IOCTRL(B) I/O(B) I/O(B) I/O(C) VCCIO(C) N/C I/O(B) I/O(B) I/O(C) I/O(C) IOCTRL(C) I/O(C) I/O(C) I/O(C) I/O(D) I/O(D) I/O(D) I/O(D) IOCTRL(D) I/O(D) I/O(D) I/O(E) GND VCCPLL(1) I/O(E) VCCIO(F) and VCCIO(G) must be connected to VCCIO(PCI) (3.3 V). Summary: 47 PCI pins, 264 user I/O, and 8 GCLK. (c) 2005 QuickLogic Corporation www.quicklogic.com * * * * * * 69 QL58x0 Enhanced QuickPCI Target Family Data Sheet Rev. I Package Mechanical Drawings 144 TFBGA Packaging Drawing 70 * www.quicklogic.com * * * * * (c) 2005 QuickLogic Corporation QL58x0 Enhanced QuickPCI Target Family Data Sheet Rev. I 196 TFBGA Packaging Drawing (c) 2005 QuickLogic Corporation www.quicklogic.com * * * * * * 71 QL58x0 Enhanced QuickPCI Target Family Data Sheet Rev. I 208 PQFP Packaging Drawing 72 * www.quicklogic.com * * * * * (c) 2005 QuickLogic Corporation QL58x0 Enhanced QuickPCI Target Family Data Sheet Rev. I 280 LFBGA Packaging Drawing (c) 2005 QuickLogic Corporation www.quicklogic.com * * * * * * 73 QL58x0 Enhanced QuickPCI Target Family Data Sheet Rev. I 484 PBGA Packaging Drawing 74 * www.quicklogic.com * * * * * (c) 2005 QuickLogic Corporation QL58x0 Enhanced QuickPCI Target Family Data Sheet Rev. I Packaging Information The QL58x0 device family product packaging information is presented in Table 43. NOTE: Military temperature range plastic packages will be added as follow on products to the commercial and industrial products. Table 43: Packaging Options Device Device Information Pin 144 TQFP Package Definitionsa 196 TFBGA QL5810 Pitch 0.50 mm 0.80 mm Pin 144 TQFP 196 TFBGA 208 PQFP 280 LFBGA a. PQFP BGA VQFP TFBGA LFBGA TQFP = = = = = = Plastic Quad Flat Pack Ball Grid Array Very Thin Quad Flat Pack Thin Fine Pitch Ball Grid Array Low Profile Fine Pitch Ball Grid Array Thin Quad Flat Pack QL5820 Pitch 0.50 mm 0.80 mm 0.50 mm 0.80 mm Pin 208 PQFP 280 LFBGA 484 PBGA QL5840 Pitch 0.50 mm 0.80 mm 1.00 mm Ordering Information QL QuickLogic Device Part Number: 5840, 5820, 5810 Speed Grade: -33A = 33 MHz PCI, Standard FPGA -33B = 33 MHz PCI, Fast FPGA -66C = 66 MHz PCI, Fastest FPGA Package Lead Count: PF144 (PFN144)* = 144-pin TQFP PQ208 (PQN208)* = 208-pin PQFP PT196 (PTN196)* = 196-ball TFBGA (0.8 mm) PT280 (PTN280)* = 280-ball LFBGA (0.8 mm) PS484 = 484-ball PBGA (1.0 mm) * Lead-free packaging is available, contact QuickLogic regarding availability (see Contact Information). 58x0 -33B PS484 C Operating Range: C = Commercial I = Industrial (c) 2005 QuickLogic Corporation www.quicklogic.com * * * * * * 75 QL58x0 Enhanced QuickPCI Target Family Data Sheet Rev. I Contact Information Phone: (408) 990-4000 (US) (905) 940-4149 (Canada) +(44) 1932 57 9011 (Europe - except Germany/Benelux) +(49) 89 930 86 170 (Germany/Benelux) +(86) 21 6867 0273 (Asia - except Japan) +(81) 45 470 5525 (Japan) E-mail: Sales: info@quicklogic.com www.quicklogic.com/sales Support: www.quicklogic.com/support Internet: www.quicklogic.com Revision History Revision A B C D Date October 2003 November 2003 December 2003 March 2004 Comments Wai-Leng Lim and Kathleen Murchek Bernhard Andretzky and Kathleen Murchek Updated Figure 1. Block Diagram Bernhard Andretzky and Kathleen Murchek Bernhard Andretzky and Kathleen Murchek Changed RAM information and made minor updates. Bernhard Andretzky and Kathleen Murchek Updated Performance Standards table and removed Military from Ordering Information. Updated AC Characteristics tables values. Updated PLL descriptions. Bernhard Andretzky and Kathleen Murchek Bernhard Andretzky and Kathleen Murchek Updated pin tables. Bernhard Andretzky and Kathleen Murchek Updated pin tables. Bernhard Andretzky, Mehul Kochar and Kathleen Murchek Added QL5820 - 280 device. Removed all QL5830 devices. Updated PLL information. Added lead-free packaging information. In the packaging information section, the pitch for the QL5810- and QL5822-196 TFBGA was corrected from 0.05 mm to 0.08 mm. E F G H June 2004 July 2004 August 2004 November 2004 I March 2005 76 * www.quicklogic.com * * * * * (c) 2005 QuickLogic Corporation QL58x0 Enhanced QuickPCI Target Family Data Sheet Rev. I Copyright and Trademark Information Copyright (c) 2005 QuickLogic Corporation. All Rights Reserved. The information contained in this document is protected by copyright. All rights are reserved by QuickLogic Corporation. QuickLogic Corporation reserves the right to modify this document without any obligation to notify any person or entity of such revision. Copying, duplicating, selling, or otherwise distributing any part of this product without the prior written consent of an authorized representative of QuickLogic is prohibited. QuickLogic and the QuickLogic logo, pASIC, ViaLink, DeskFab, and QuickWorks are registered trademarks of QuickLogic Corporation; Eclipse, Eclipse-II, QuickFC, QuickDSP, QuickDR, QuickSD, QuickTools, QuickCore, QuickPro, SpDE, WebASIC, and WebESP are trademarks of QuickLogic Corporation. (c) 2005 QuickLogic Corporation www.quicklogic.com * * * * * * 77 |
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