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| QS5931 LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER INDUSTRIAL TEMPERATURE RANGE LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER FEATURES: DESCRIPTION: QS5931 * * * * * * * * * * * * 5V operation Six low noise CMOS level outputs Q outputs, Q/2 output <500ps output skew, Q0-Q4 Outputs 3-state and reset while OE/RST low PLL disable feature for low frequency testing Internal loop filter RC network Internal VCO/2 option Balanced drive outputs 36mA ESD >2000V 80MHz maximum frequency Available in QSOP package The QS5931 Clock Driver uses an internal phase locked loop (PLL) to lock low skew outputs to a reference clock input. Six outputs are available: Q0-Q4, Q/2. Careful layout and design ensure < 500ps skew between the Q0-Q4, and Q/2 outputs. The QS5931 includes an internal RC filter which provides excellent jitter characteristics and eliminates the need for external components. Various combinations of feedback and a divide-by-2 in the VCO path allow applications to be customized for linear VCO operation over a wide range of input SYNC frequencies. The PLL can also be disabled by the PLL_EN signal to allow low frequency or DC testing. The QS5931 is designed for use in cost sensitive high-performance computing systems, workstations, multi-board computers, networking hardware, and mainframe systems. Several can be used in parallel or scattered throughout a system for guaranteed low skew, system-wide clock distribution networks. In the QSOP package, the QS5931 clock driver represents the best value in small form factor, high-performance clock management products. For more information on PLL clock driver products, see Application Note AN-227. FUNCTIONAL BLOCK DIAGRAM FEEDBACK PLL_EN FREQ _SEL SYNC O E/RST PH ASE DETECTO R LOO P FILTER 0 1 VCO 1 /2 0 R D R D R D R D R D R D Q Q Q Q Q Q Q Q /2 Q4 Q3 Q2 Q1 Q0 The IDT logo is a registered trademark of Integrated Device Technology, Inc. INDUSTRIAL TEMPERATURE RANGE 1 c 2002 Integrated Device Technology, Inc. JANUARY 2002 DSC-5817/2 QS5931 LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER INDUSTRIAL TEMPERATURE RANGE PIN CONFIGURATION ABSOLUTE MAXIMUM RATINGS(1) Symbol Description DC Input Voltage VIN Maximum Power Dissipation (TA = 85C) TSTG Storage Temperature Range Max -0.5 to +7 -0.5 to +5.5 0.5 -65 to +150 Unit V V W C AVDD/VDD Supply Voltage to Ground G ND O E/RST FEEDBACK AV DD VDD AG ND SYNC FREQ _SEL G ND Q0 1 2 3 4 5 6 7 8 9 10 SO 20-8 20 19 18 17 16 15 14 13 12 11 Q4 Q /2 G ND Q3 VDD Q2 G ND PLL_EN G ND Q1 NOTE: 1. Stresses beyond those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolutemaximum-rated conditions for extended periods may affect device reliability. CAPACITANCE (TA = +25C, f = 1MHz, VIN = 0V) Pins CIN COUT Typ. 3 4 Max. 4 5 Unit pF pF QSOP TOP VIEW PIN DESCRIPTION Pin Name SYNC FREQ_SEL FEEDBACK Q0 -Q4 Q/2 OE/RST PLL_EN VDD AVDD GND AGND I/O I I I O O I I -- -- -- -- Description Reference clock input VCO frequency select. For choosing optimal VCO operating frequency depending on input frequency. HIGH is for higher frequencies, LOW is for lower frequencies. PLL feedback input which is connected to either a Q or a Q/2 output. External feedback provides flexibility for different output frequency relationships. See the Frequency Selection Table for more information. Clock outputs Clock output. Matched in phase, but frequency is half the Q frequency. Output enable/asynchronous reset. Resets all output registers. When 0, all outputs are held in a tri-stated condition. When 1, outputs are enabled. PLL enable. Enables and disables the PLL. Allows the SYNC input to be single-stepped for system debug. Power supply for output buffers Power supply for phase lock loop and other internal circuitries Ground supply for output buffers Ground supply for phase lock loop and other internal circuitries OUTPUT FREQUENCY SPECIFICATIONS Industrial: TA = -40C to +85C, AVDD/VDD = 5.0V 10% Symbol FMAX_Q FMAX_Q/2 FMIN_Q FMIN_Q/2 Description Max Frequency, Q0 - Q4, Max Frequency, Q/2 Min Frequency, Q0 - Q4 Min Frequency, Q/2 - 50 50 25 10 5 - 66 66 33 10 5 - 80 80 40 10 5 Units MHz MHz MHz MHz 2 QS5931 LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER INDUSTRIAL TEMPERATURE RANGE FREQUENCY SELECTION TABLE SYNC (MHz) Output Used for FREQ_SEL HIGH HIGH LOW LOW Feedback Q/2 Q0 -Q4 Q/2 Q0 -Q4 Min. FMIN_Q/2 FMIN_Q FMIN_Q/2 /2 FMIN_Q /2 (allowable range) (1) Max FMAX _Q/2 FMAX _Q FMAX _Q/2 /2 FMAX _Q /2 Output Frequency Relationships Q/2 SYNC SYNC / 2 SYNC SYNC / 2 Q0 - Q4 SYNC X 2 SYNC SYNC X 2 SYNC NOTE: 1. Operation in the specified SYNC frequency range guarantees that the VCO will operate in its optimal range of 20MHz to FMAX_Q x2. Operation with Sync inputs outside specified frequency ranges may result in out-of-lock outputs. FREQ_SEL only affects VCO frequency and does not affect output frequencies. DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Industrial: TA = -40C to +85C, AVDD/VDD = 5.0V 10% Symbol VIH VIL VOH VOL VH IOZ IIN Parameter Input HIGH Voltage Input LOW Voltage Output HIGH Voltage Output LOW Voltage Input Hysteresis Output Leakage Current Input Leakage Current Conditions Guaranteed Logic HIGH Level Guaranteed Logic LOW Level IOH = -24mA IOH = -100A VDD = Min., IOL = 100A -- VOUT = VDD or GND, VDD = Max., Outputs Disabled AVDD = Max., VIN = AVDD or GND -- -- 5 A Min. 2 -- VDD -- 0.6 VDD -- 0.2 -- -- -- -- Typ. -- -- -- -- -- -- 100 -- Max. -- 0.8 -- -- 0.45 0.2 -- 5 mV A V Unit V V V VDD = Min., IOL = 24mA POWER SUPPLY CHARACTERISTICS Symbol IDDQ IDD IDDD Parameter Quiescent Power Supply Current Power Supply Current per Input HIGH Dynamic Power Supply Current per Output Test Conditions VDD = Max., OE/RST = LOW, SYNC = LOW, All outputs unloaded VDD = Max., VIN = 3V VDD = Max., CL = 0pF 1 0.2 30 0.3 A A/MHz Typ. -- Max. 1 Unit mA INPUT TIMING REQUIREMENTS Symbol tR, tF FI tPWC DH Input Clock Frequency, SYNC Duty Cycle, SYNC (2) (1) Description (1) Maximum input rise and fall times, 0.8V to 2V Input clock pulse, HIGH or LOW (2) Min. -- 2.5 2 25 Max. 3 FMAX _Q -- 75 Unit ns MHz ns % NOTES: 1. See Output Frequency and Frequency Selection tables for more detail on allowable SYNC input frequencies for different speed grades with different FEEDBACK and FREQ_SEL combinations. 2. Where pulse witdh implied by DH is less than tWPC limit, tWPC limit applies 3 QS5931 LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER INDUSTRIAL TEMPERATURE RANGE SWITCHING CHARACTERISTICS OVER OPERATING RANGE Symbol tSKR tSKF tPW tJ tPD tLOCK tPZH tPZL tPHZ tPLZ tR, tF Output Rise/Fall Times, 0.2VDD to 0.8VDD 0.3 2.5 ns Output Disable Time, OE/RST HIGH to LOW (3) 0 14 ns Parameter (1) Output Skew Between Rising Edges, Q0-Q4 and Q/2 Output Skew Between Falling Edges, Q0-Q4 and Q/2 Pulse Width, Q0-Q4, Q/2 outputs, 80MHz Cycle-to-Cycle Jitter (4) SYNC Input to Feedback Delay (5) SYNC to Phase Lock Output Enable Time, OE/RST LOW to HIGH (3) (2) (2) Min. -- -- TCY/2 - 0.4 -- 0.15 Max. 500 500 TCY/2 + 0.4 0.15 500 10 14 Unit ps ps ns ns ps ms ns - 500 -- 0 NOTES: 1. See Test Loads and Waveforms for test load and termination. 2. Skew specifications apply under identical environments (loading, temperature, VDD, device speed grade). 3. Measured in open loop mode PLL_EN = 0. 4. Jitter is characterized with Q output at 20MHz. See Frequency Selection Table for information on proper FREQ_SEL level for specified input frequencies. 5. tPD measured at device inputs at 1.5V, Q output at 80MHz. 4 QS5931 LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER INDUSTRIAL TEMPERATURE RANGE AC TEST LOADS AND WAVEFORMS VDD 300 7.0V O UTPU T 100 O UTP UT 300 100 30pF Test Circuit 1 1.0ns 1.0ns VDD 0.8VDD 0.5VDD 0.2VDD 0V tPW Test Circuit 2 tR tF 3.0V 2.0V Vth = 1.5V 0.8V 0V CMOS Input Test Waveform EN ABLE DISABLE CMOS Output Waveform 3V 1.5V CO NTROL IN PU T tPZL O UTP UT NOR M ALLY LOW SWITC H CLO SED 0.5VDD 0.3V tPZH SWITCH O UTP UT NO R MALLY HIG H O PEN 0.5VDD tPHZ 0.3V VOH VOL tPLZ 3.5V 0V 0V Enable and Disable Times TEST CIRCUIT 1 is used for output enable/disable parameters. TEST CIRCUIT 2 is used for all other timing parameters. 5 QS5931 LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER INDUSTRIAL TEMPERATURE RANGE AC TIMING DIAGRAM SYNC tPD FEEDBACK tJ Q tSK F Q0-Q4 tSK ALL Q/2 tSKR NOTES: 1. AC Timing Diagram applies to Q output connected to FEEDBACK and PE = GND. For PE = VDD, the negative edge of FEEDBACK aligns with the negative edge of SYNC input, and the negative edges of the multiplied and divided outputs align with the negative edge of SYNC. 2. All parameters are measured at 0.5VDD. 6 QS5931 LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER INDUSTRIAL TEMPERATURE RANGE PLL OPERATION The Phase Locked Loop (PLL) circuit included in the QS5931 provides for replication of incoming SYNC clock signals. Any manipulation of that signal, such as frequency multiplying, is performed by digital logic following the PLL (see the block diagram). The key advantage of the PLL circuit is to provide an effective zero propagation delay between the output and input signals. In fact, adding delay circuits in the feedback path, `propagation delay' can even be negative! A simplified schematic of the QS5931 PLL circuit is shown below: SIMPLIFIED DIAGRAM OF QS5931 FEEDBACK Q Q /2 INPU T PHASE DETECTO R VCO/2 /2 The phase difference between the output and the input frequencies feeds the VCO which drives the outputs. Whichever output is fed back, it will stabilize at the same frequency as the input. Hence, this is a true negative feedback closed loop system. In most applications, the output will optimally have zero phase shift with respect to the input. In fact, the internal loop filter on the QS5931 typically provides within 150ps of phase shift between input and output. If the user wishes to vary the phase difference (typically to compensate for backplane delays), this is most easily accomplished by adding delay circuits to the feedback path. The respective output used for feedback will be advanced by the amount of delay in the feedback path. All other outputs will retain their proper relationships to that output. 7 QS5931 LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER INDUSTRIAL TEMPERATURE RANGE ORDERING INFORMATION QS XXXX Device Type X Speed X Package Q Quarter Size Outline Package -50 -66 -80 50 MHz. max. frequency 66 MHz. max. frequency 80 MHz. max. frequency 5931 Low Skew CMOS PLL Clock Driver with Integrated Loop Filter CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com 8 for Tech Support: logichelp@idt.com (408) 654-6459 |
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