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S3C72Q5/P72Q5
4-BIT CMOS MICROCONTROLLER USER'S MANUAL Revision 3.2
Important Notice
The information in this publication has been carefully checked and is believed to be entirely accurate at the time of publication. Samsung assumes no responsibility, however, for possible errors or omissions, or for any consequences resulting from the use of the information contained herein. Samsung reserves the right to make changes in its products or product specifications with the intent to improve function or design at any time and without notice and is not required to update this documentation to reflect such changes. This publication does not convey to a purchaser of semiconductor devices described herein any license under the patent rights of Samsung or others. Samsung makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does Samsung assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability, including without limitation any consequential or incidental damages. S3C72Q5/P72Q5 4-Bit CMOS Microcontroller User's Manual, Revision 3.2 Publication Number: 23.2-S3-C72Q5/P72Q5-082005 (c) 2005 Samsung Electronics All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electric or mechanical, by photocopying, recording, or otherwise, without the prior written consent of Samsung Electronics. Samsung Electronics' microcontroller business has been awarded full ISO-9001 certification (BSI Certificate No. FM24653). All semiconductor products are designed and manufactured in accordance with the highest quality standards and objectives. Samsung Electronics Co., Ltd. San #24 Nongseo-Ri, Giheung- Eup Yongin-City, Gyeonggi-Do, Korea C.P.O. Box #37, Suwon 449-900 TEL: FAX: (82)-(031)-209-1934 (82)-(031)-209-1899 "Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals" must be validated for each customer application by the customer's technical experts. Samsung products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, for other applications intended to support or sustain life, or for any other application in which the failure of the Samsung product could create a situation where personal injury or death may occur. Should the Buyer purchase or use a Samsung product for any such unintended or unauthorized application, the Buyer shall indemnify and hold Samsung and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, expenses, and reasonable attorney fees arising out of, either directly or indirectly, any claim of personal injury or death that may be associated with such unintended or unauthorized use, even if such claim alleges that Samsung was negligent regarding the design or manufacture of said product.
Home Page: http://www.samsungsemi.com Printed in the Republic of Korea
NOTIFICATION OF REVISIONS
ORIGINATOR: PRODUCT NAME: DOCUMENT NAME: DOCUMENT NUMBER: EFFECTIVE DATE: SUMMARY:
Samsung Electronics, LSI Development Group, Ki-Heung, South Korea
S3C72Q5/P72Q5 4-bit CMOS Microcontroller
S3C72Q5/P72Q5 User's Manual, Revision 3.2
23.2-S3-C72Q5/P72Q5-082005
August, 2005
As a result of additional product testing and evaluation, some specifications published in S3C72Q5/P72Q5 User's Manual, Revision 2, have been changed. These changes for S3C72Q5/P72Q5 microcontroller, which are described in detail in the Revision Descriptions section below, are related to the followings: -- Chapter 14. Electrical Data
DIRECTIONS:
Please note the changes in your copy (copies) of the S3C72Q5/P72Q5 User's Manual, Revision 2. Or, simply attach the Revision Descriptions of the next page to S3C72Q5/P72Q5 User's Manual, Revision 2.
REVISION HISTORY
Revision - 3 3.1 3.2 Date - May, 2005 July, 2005 August, 2005 Third edition. Fourth edition. Fifth edition. Remark -
REVISION DESCRIPTIONS
1. ELECTRICAL DATA
Added Note "When the LCD display is on, LCD module current may be about 100uA." in the page 14-4.
2. OPERATING TEMPERATURE
Operating temperature is changed "-40C ~ +85C" to "-25C ~ +85C".
3. STOP CURRENT TEMPERATURE
Added test condition "TA = 25 C" on the stop current in the page 14-4.
4. PULL-UP RESISTOR TEMPERATURE
Added test condition "TA = 25 C" on the pull-up resistor in the page 14-3.
Preface
The S3C72Q5/P72Q5 Microcontroller User's Manual is designed for application designers and programmers who are using the S3C72Q5/P72Q5 microcontroller for application development. It is organized in two parts: Part I Programming Model Part II Hardware Descriptions
Part I contains software-related information to familiarize you with the microcontroller's architecture, programming model, instruction set, and interrupt structure. It has five sections: Section 1 Section 2 Section 3 Product Overview Address Spaces Addressing Modes Section 4 Section 5 Memory Map SAM48 Instruction Set
Section 1, "Product Overview," is a high-level introduction to the S3C72Q5/P72Q5, ranging from a general product description to detailed information about pin characteristics and circuit types. Section 2, "Address Spaces," introduces you to the S3C72Q5/P72Q5 programming model: the program memory (ROM) and data memory (RAM) structures and how to address them. Section 2 also includes information about stack operations, CPU registers, and the bit sequential carrier (BSC) register. Section 3, "Addressing Modes," descriptions types of addressing supported by the SAM48 instruction set (direct, indirect, and bit manipulation) and the addressing modes which are supported (1-bit, 4-bit, and 8-bit). Numberous programming examples make the information practical and usable. Section 4, "Memory Map," contains a detailed map of the addressable peripheral hardware registers in the memorymapped area of the RAM (bank 15). Section 4 also contains detailed descriptions in standard format of the most commonly used hardware registers. These easy-to-read register descriptions can be used as a quick-reference source when writing programs. Section 5, " SAM48 Instruction Set," first introduces the basic features and conventions of the SAM48 instruction set. Then, two summary tables orient you to the individual instructions: One table is a high-level summary of the most important information about each instruction; the other table is designed to give expert programmers a summary of binary code and instruction notation information. The final part of Section 5 contains detailed descriptions of each instruction in a standard format. Each instruction description includes one or more practical examples. A basic familiarity with the information in Part I will make it easier for you to understand the hardware descriptions in Part II. If you are familiar with the SAM48 product family and are reading this user's manual for the first time, we recommend that you read Sections 1-3 carefully, and just scan the detailed information in Sections 4 and 5 very briefly. Later, you can refer back to Sections 4 and 5 as necessary. Part II "hardware Descriptions," has detailed information about specific hardware components of the S3C72Q5/P72Q5 microcontroller. Also included in Part II are electrical, mechanical, OTP, and development tools data. Part II has 12 sections: Section 6 Section 7 Section 8 Section 9 Section 10 Section 11 Oscillator Circuit Interrupts Power-Down RESET I/O Ports Timers and Timer/Counter 0 Section Section Section Section Section Section 12 13 14 15 16 17 LCD Controller/Driver External Memory Interface Electrical Data Mechanical Data S3P72Q5 OTP Development Tools
Two order forms are included at the back of this manual to facilitate customer order for S3C72Q5/P72Q5 microcontrollers: the Mask ROM Order Form, and the Mask Option Selection Form. You can photocopy these forms, fill them out, and then forward them to your local Samsung Sales Representative.
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Table of Contents
Part I -- Programming Model
Section 1 Product Overview
Overview .............................................................................................................................................1-1 OTP ...................................................................................................................................................1-1 Features .............................................................................................................................................1-2 Block Diagram ....................................................................................................................................1-3 Pin Assignments.................................................................................................................................1-4 Pin Descriptions ..................................................................................................................................1-5 Pin Circuit Diagrams............................................................................................................................1-7
Section 2
Address Spaces
Program Memory (ROM) ......................................................................................................................2-1 Overview .....................................................................................................................................2-1 General-Purpose Memory Areas ...................................................................................................2-2 Vector Address Area ...................................................................................................................2-2 Instruction Reference Area ...........................................................................................................2-4 Data Memory (RAM)............................................................................................................................2-5 Overview .....................................................................................................................................2-5 Working Registers .......................................................................................................................2-9 Stack Operations ................................................................................................................................2-13 Stack Pointer (SP) ......................................................................................................................2-13 Push Operations .........................................................................................................................2-14 Pop Operations ...........................................................................................................................2-15 Bit Sequential Carrier (BSC) .................................................................................................................2-16 Program Counter (PC)..........................................................................................................................2-17 Program Status Word (PSW) ...............................................................................................................2-17 Interrupt Status Flags (IS0, IS1)....................................................................................................2-18 Emb Flag (EMB) .........................................................................................................................2-19 Erb Flag (ERB)............................................................................................................................2-20 Skip Condition Flags (SC2, SC1, SC0)..........................................................................................2-21 Carry Flag (C) .............................................................................................................................2-21
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Table of Contents (Continued)
Section 3 Addressing Modes
Overview .............................................................................................................................................3-1 EMB and ERB Initialization Values ...............................................................................................3-3 Enable Memory Bank Settings .....................................................................................................3-4 Select Bank Register (SB) ...........................................................................................................3-5 Direct And Indirect Addressing..............................................................................................................3-6 1-Bit Addressing..........................................................................................................................3-6 4-Bit Addressing..........................................................................................................................3-8 8-Bit Addressing..........................................................................................................................3-11
Section 4
Memory Map
Overview .............................................................................................................................................4-1 I/O Map For Hardware Registers ...................................................................................................4-1 Register Descriptions...................................................................................................................4-6
Section 5
SAM48 Instruction Set
Overview .............................................................................................................................................5-1 Instruction Set Features .......................................................................................................................5-1 Instruction Reference Area ...........................................................................................................5-2 Reducing Instruction Redundancy .................................................................................................5-3 Flexible Bit Manipulation ..............................................................................................................5-4 Instructions Which Have Skip Conditions .......................................................................................5-4 Instructions Which Affect The Carry Flag .......................................................................................5-4 ADC and SBC Instruction Skip Conditions .....................................................................................5-5 Symbols And Conventions....................................................................................................................5-6 Opcode Definitions ..............................................................................................................................5-7 High-Level Summary ............................................................................................................................5-8 Binary Code Summary .........................................................................................................................5-13 Instruction Descriptions........................................................................................................................5-23
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Table of Contents (Continued)
Part II -- Hardware Descriptions
Section 6 Oscillator Circuits
Overview .............................................................................................................................................6-1 Main-System Oscillator Circuits....................................................................................................6-3 Sub-System Oscillator Circuits.....................................................................................................6-3 Power Control Register (PCON) ....................................................................................................6-4 Instruction Cycle Times................................................................................................................6-5 System Clock Mode Register (SCMOD) ........................................................................................6-6 Switching The CPU Clock ............................................................................................................6-8 Clock Output Mode Register (CLMOD) ..........................................................................................6-10 Clock Output Circuit ....................................................................................................................6-11 Clock Output Procedure...............................................................................................................6-11
Section 7
Interrupts
Overview .............................................................................................................................................7-1 Vectored Interrupts ......................................................................................................................7-2 Multiple Interrupts........................................................................................................................7-5 Interrupt Priority Register (IPR) .....................................................................................................7-7 External Interrupt 0 and 1 Mode Registers (IMOD0, IMOD1) ............................................................7-8 External Interrupt 2 Mode Register (IMOD2) ...................................................................................7-10 Interrupt Flags .............................................................................................................................7-12
Section 8
Power-Down
Overview .............................................................................................................................................8-1 Idle Mode Timing Diagrams ..........................................................................................................8-4 Stop Mode Timing Diagrams.........................................................................................................8-5 Recommended Connections for Unused Pins .................................................................................8-7
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Table of Contents (Continued)
Section 9 RESET
Overview .............................................................................................................................................9-1 Hardware Register Values after RESET .........................................................................................9-1
Section 10
I/O Ports
Overview .............................................................................................................................................10-1 Port Mode Flags (PM FLAGS)......................................................................................................10-3 Pull-Up Resistor Mode Register (PUMOD0) ...................................................................................10-4 Port 0,1 Circuit Diagram...............................................................................................................10-6 Port 4 Circuit Diagram..................................................................................................................10-7 Port 5 Circuit Diagram..................................................................................................................10-8 Port 6 Circuit Diagram..................................................................................................................10-9 Port 7 Circuit Diagram..................................................................................................................10-10
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Table of Contents (Continued)
Section 11 Timers and Timer/Counter 0
Overview .............................................................................................................................................11-1 Basic Timer (BT) .................................................................................................................................11-2 Overview .....................................................................................................................................11-2 Basic Timer Mode Register (BMOD)..............................................................................................11-5 Basic Timer Counter (BCNT).........................................................................................................11-6 Basic Timer Operation Sequence..................................................................................................11-6 Watchdog Timer Mode Register (WDMOD)....................................................................................11-8 Watchdog Timer Counter (WDCNT) ...............................................................................................11-8 Watchdog Timer Counter Clear Flag (WDTCF) ...............................................................................11-8 8-Bit Timer/Counter 0 (TC0) ..................................................................................................................11-10 Overview .....................................................................................................................................11-10 TC0 Function Summary ...............................................................................................................11-10 TC0 Component Summary ...........................................................................................................11-11 TC0 Enable/Disable Procedure .....................................................................................................11-12 TC0 Programmable Timer/Counter Function ...................................................................................11-13 TC0 Operation Sequence .............................................................................................................11-13 TC0 Event Counter Function .........................................................................................................11-14 TC0 Clock Frequency Output........................................................................................................11-15 TC0 External Input Signal Divider ..................................................................................................11-16 TC0 Mode Register (TMOD0)........................................................................................................11-17 TC0 Counter Register (TCNT0)......................................................................................................11-19 TC0 Reference Register (TREF0) ..................................................................................................11-20 TC0 Output Enable Flag (TOE0)....................................................................................................11-20 TC0 Output Latch (TOL0) .............................................................................................................11-20 8-Bit Timer/Counter 1 (TC1) ..................................................................................................................11-22 Overview .....................................................................................................................................11-22 TC1 Function Summary ...............................................................................................................11-22 TC1 Component Summary ...........................................................................................................11-23 TC1 Enable/Disable Procedure .....................................................................................................11-24 TC1 Programmable Timer/Counter Function ...................................................................................11-25 TC1 Operation Sequence .............................................................................................................11-25 TC1 Mode Register (TMOD1)........................................................................................................11-26 TC1 Counter Register (TCNT1)......................................................................................................11-28 TC1 Reference Register (TREF1) ..................................................................................................11-29 Watch Timer .......................................................................................................................................11-30 Overview .....................................................................................................................................11-30 Watch Timer Mode Register (WMOD) ...........................................................................................11-32
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Table of Contents (Concluded)
Section 12 LCD Controller/Driver
Overview .............................................................................................................................................12-1 LCD Circuit Diagram ....................................................................................................................12-2 LCD Ram Address Area...............................................................................................................12-3 LCD Contrast Control Register (LCNST).........................................................................................12-4 LCD Output Control Register 0 (LCON0) ........................................................................................12-5 LCD Output Control Register 1 (LCON1) ........................................................................................12-5 LCD Mode Register (LMOD) .........................................................................................................12-6 Key Scan Register (KSR).............................................................................................................12-17
Section 13
External Memory Interface
Overview .............................................................................................................................................13-1 External Memory Control Register (EMCON)..................................................................................13-1 How to Access The External Memory............................................................................................13-3 External Memory Write Cycle Timing Diagram ...............................................................................13-6 External Memory Read Cycle Timing Diagram................................................................................13-6
Section 14
Electrical Data
Overview .............................................................................................................................................14-1 Timing Waveforms ...............................................................................................................................14-10
Section 15
Mechanical Data
Overview .............................................................................................................................................15-1
Section 16
S3P72Q5 OTP
Overview .............................................................................................................................................16-1 Operating Mode Characteristics....................................................................................................16-3
Section 17
Development Tools
Overview .............................................................................................................................................17-1 SHINE ........................................................................................................................................17-1 SAMA Assembler........................................................................................................................17-1 SASM57.....................................................................................................................................17-1 HEX2ROM ..................................................................................................................................17-1 Target Boards .............................................................................................................................17-1 OTPs .........................................................................................................................................17-1 TB72Q5 Target Board ..................................................................................................................17-3 Idle LED .....................................................................................................................................17-5 Stop LED....................................................................................................................................17-5
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List of Figures
Figure Number 1-1 1-2 1-3 1-4 1-5 1-6 1-7 1-8 1-9 1-10 1-11 1-12 1-13 1-14 1-15 1-16 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 3-1 3-2 4-1 6-1 6-2 6-3 6-4 6-5 6-6 6-7 7-1 7-2 7-3 7-4 7-5 7-6 Title Page Number
S3C72Q5/P72Q5 Specified Block Diagram ............................................................1-3 S3C72Q5 Pin Assignment Diagram.......................................................................1-4 Pin Circuit Type A ...............................................................................................1-7 Pin Circuit Type A-3.............................................................................................1-7 Pin Circuit Type B ...............................................................................................1-7 Pin Circuit Type C ...............................................................................................1-7 Pin Circuit Type E-2.............................................................................................1-8 Pin Circuit Type E-3.............................................................................................1-8 Pin Circuit Type H-4.............................................................................................1-9 Pin Circuit Type H-5.............................................................................................1-9 Pin Circuit Type H-6.............................................................................................1-9 Pin Circuit Type H-7.............................................................................................1-9 Pin Circuit Type H-9.............................................................................................1-10 Pin Circuit Type H-10...........................................................................................1-10 Pin Circuit Type H-11...........................................................................................1-10 Pin Circuit Type H-12...........................................................................................1-10 ROM Address Structure.......................................................................................2-2 Vector Address Map............................................................................................2-2 S3C72Q5 Data Memory (RAM) Map......................................................................2-6 Working Register Map .........................................................................................2-9 Register Pair Configuration ...................................................................................2-10 1-Bit, 4-Bit, and 8-Bit Accumulator........................................................................2-11 Push-Type Stack Operations ................................................................................2-14 Pop-Type Stack Operations..................................................................................2-15 RAM Address Structure .......................................................................................3-2 SMB and SRB Values in the SB Register..............................................................3-5 Register Description Format .................................................................................4-7 Clock Circuit Diagram ..........................................................................................6-2 Crystal/Ceramic Oscillator....................................................................................6-3 External Oscillator...............................................................................................6-3 RC Oscillator ......................................................................................................6-3 Crystal/Ceramic Oscillator....................................................................................6-3 External Oscillator...............................................................................................6-3 CLO Output Pin Circuit Diagram ...........................................................................6-11 Interrupt Execution Flowchart ...............................................................................7-3 Interrupt Control Circuit Diagram ...........................................................................7-4 Two-Level Interrupt Handling .................................................................................7-5 Multi-Level Interrupt Handling ................................................................................7-6 Circuit Diagram for INT0 and INT1 Pins ..................................................................7-9 Circuit Diagram for INT2 .......................................................................................7-10
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List of Figures (Continued)
Figure Number 8-1 8-2 8-3 8-4 9-1 10-1 10-3 10-4 10-5 10-6 11-1 11-2 11-3 11-4 11-5 11-6 12-1 12-2 12-3 12-4 12-5 12-6 12-7 12-8 12-9 12-10 12-11 12-12 12-13 13-1 13-2 13-3 Title Page Number
Timing When Idle Mode is Released by RESET......................................................8-4 Timing When Idle Mode is Released by an Interrupt ................................................8-4 Timing When Stop Mode is Released by RESET....................................................8-5 Timing When Stop Mode is Released by an Interrupt ..............................................8-5 Timing for Oscillation Stabilization after RESET......................................................9-1 Port 0,1 Circuit Diagram.......................................................................................10-6 Port 4 Circuit Diagram..........................................................................................10-7 Port 5 Circuit Diagram..........................................................................................10-8 Port 6 Circuit Diagram..........................................................................................10-9 Port 7 Circuit Diagram..........................................................................................10-10 Basic Timer Circuit Diagram .................................................................................11-4 TC0 Circuit Diagram.............................................................................................11-12 TC0 Timing Diagram ............................................................................................11-19 TC1 Circuit Diagram.............................................................................................11-24 TC1 Timing Diagram ............................................................................................11-28 Watch Timer Circuit Diagram................................................................................11-31 LCD Circuit Diagram ............................................................................................12-2 LCD Clock Circuit Diagram...................................................................................12-2 Display RAM Organization ...................................................................................12-3 LCD Voltage Dividing Resistors Connection ...........................................................12-8 RE, LE and Inputs Signal Waveform (1/9 Duty).......................................................12-9 LCD Signal Waveform for 1/9 Duty and 1/4 Bias .....................................................12-10 RE, LE and Inputs Signal Waveform (1/10 Duty).....................................................12-11 LCD Signal Waveform for 1/10 Duty and 1/4 Bias ...................................................12-12 RE, LE and Inputs Signal Waveform (1/11 Duty).....................................................12-13 LCD Signal Waveform for 1/11 Duty and 1/4 Bias ...................................................12-14 RE, LE and Inputs Signal Waveform (1/12 Duty).....................................................12-15 LCD Signal Waveform for 1/12 Duty and 1/4 Bias ...................................................12-16 Segment Pin Output Signal When LCON1.3 = 1.....................................................12-17 External Memory Write Cycle Timing Diagram .......................................................13-6 External Memory Read Cycle Timing Diagram........................................................13-6 External Interface Fuction Diagram (S3C72Q5, SRAM, EPROM, EEPROM).............13-7
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List of Figures (Continued)
Figure Number 14-1 14-2 14-3 14-4 14-5 14-6 14-7 14-6 14-7 15-1 16-1 16-2 17-1 17-2 17-3 17-4 Title Page Number
Standard Operating Voltage Range .......................................................................14-9 Stop Mode Release Timing When Initiated By RESET............................................14-10 Stop Mode Release Timing When Initiated By Interrupt Request ..............................14-10 A.C. Timing Measurement Points (Except for XIN and XTIN)......................................14-11 Input Timing for External Interrupts and Quasi-Interrupts..........................................14-11 Clock Timing Measurement at XIN .........................................................................14-12 Clock Timing Measurement at XT IN........................................................................14-12 TCL0 Timing........................................................................................................14-13 Input Timing for RESET Signal..............................................................................14-13 100-QFP-1420 Package Dimensions .....................................................................15-1 S3P72Q5 Pin Assignments (100-QFP Package) ....................................................16-2 Standard Operating Voltage Range .......................................................................16-5 SMDS Product Configuration (SMDS2+)................................................................17-2 TB72Q5 Target Board Configuration.......................................................................17-3 50-Pin Connectors for TB72Q5..............................................................................17-6 TB72Q5 Adapter Cable for 100-QFP Package (S3C72Q5/P72Q5) ............................17-6
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List of Tables
Table Number 1-1 2-1 2-2 2-3 2-4 2-5 2-6 2-7 3-1 3-2 3-3 3-4 4-1 4-2 5-1 5-2 5-3 5-4 5-5 5-6 5-7 5-8 5-9 5-10 5-11 5-12 5-13 5-14 5-15 5-16 5-17 5-18 5-19 5-20 6-1 6-2 6-3 6-4 6-5 6-6 Title Page Number
Pin Descriptions ..................................................................................................1-5 Program Memory Address Ranges........................................................................2-1 Data Memory Organization and Addressing ...........................................................2-7 Working Register Organization and Addressing......................................................2-10 BSC Register Organization...................................................................................2-16 Program Status Word Bit Descriptions ..................................................................2-17 Interrupt Status Flag Bit Settings ..........................................................................2-18 Valid Carry Flag Manipulation Instructions .............................................................2-21 RAM Addressing Not Affected by the EMB Value...................................................3-4 1-Bit Direct and Indirect RAM Addressing ..............................................................3-6 4-Bit Direct and Indirect RAM Addressing ..............................................................3-8 8-Bit Direct and Indirect RAM Addressing ..............................................................3-11 I/O Map for Memory Bank 15................................................................................4-2 I/O Map for Memory Bank 15................................................................................4-3 Valid 1-Byte Instruction Combinations for REF Look-Ups ........................................5-2 Bit Addressing Modes and Parameters..................................................................5-4 Skip Conditions for ADC and SBC Instructions .......................................................5-5 Data Type Symbols .............................................................................................5-6 Register Identifiers ...............................................................................................5-6 Instruction Operand Notation ................................................................................5-6 Opcode Definitions (Direct)...................................................................................5-7 Opcode Definitions (Indirect).................................................................................5-7 CPU Control Instructions -- High-Level Summary ...................................................5-9 Program Control Instructions -- High-Level Summary .............................................5-9 Data Transfer Instructions -- High-Level Summary..................................................5-10 Logic Instructions -- High-Level Summary .............................................................5-11 Arithmetic Instructions -- High-Level Summary ......................................................5-11 Bit Manipulation Instructions -- High-Level Summary..............................................5-12 CPU Control Instructions -- Binary Code Summary ................................................5-14 Program Control Instructions -- Binary Code Summary ..........................................5-15 Data Transfer Instructions -- Binary Code Summary...............................................5-16 Logic Instructions -- Binary Code Summary ..........................................................5-18 Arithmetic Instructions -- Binary Code Summary ...................................................5-19 Bit Manipulation Instructions -- Binary Code Summary...........................................5-20 Power Control Register (PCON) Organization.........................................................6-4 Instruction Cycle Times for CPU Clock Rates.........................................................6-5 System Clock Mode Register (SCMOD) Organization.............................................6-6 Main Oscillation Stop Mode..................................................................................6-7 Elapsed Machine Cycles During CPU Clock Switch................................................6-8 Clock Output Mode Register (CLMOD) Organization...............................................6-10
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List of Tables
Table Number 7-1 7-2 7-3 7-4 7-5 7-6 7-7 7-8 8-1 8-2 8-3 9-1 10-1 10-2 10-3 10-4 11-1 11-2 11-3 11-4 11-5 11-6 11-7 11-8 11-9 11-10 11-11 12-1 12-2 12-3 12-4 12-5 13-1 Title
(Continued)
Page Number
Interrupt Types and Corresponding Port Pin(s)........................................................7-1 IS1 and IS0 Bit Manipulation for Multi-Level Interrupt Handling..................................7-6 Standard Interrupt Priorities ..................................................................................7-7 Interrupt Priority Register Settings.........................................................................7-7 IMOD0 and IMOD1 Register Organization ..............................................................7-8 IMOD2 Register Bit Settings.................................................................................7-10 Interrupt Enable and Interrupt Request Flag Addresses ...........................................7-12 Interrupt Request Flag Conditions and Priorities .....................................................7-13 Hardware Operation During Power-Down Modes .....................................................8-2 System Operating Mode Comparison ....................................................................8-3 Unused Pin Connections for Reducing Power Consumption.....................................8-7 Hardware Register Values After RESET.................................................................9-2 I/O Port Overview.................................................................................................10-2 Port Pin Status During Instruction Execution..........................................................10-2 Port Mode Group Flags ........................................................................................10-3 Pull-Up Resistor Mode Register (PUMOD0) Organization ........................................10-4 Basic Timer Register Overview..............................................................................11-3 Basic Timer Mode Register (BMOD) Organization ..................................................11-5 Watchdog Timer Interval Time...............................................................................11-8 TC0 Register Overview .........................................................................................11-11 TMOD0 Settings for TCL0 Edge Detection .............................................................11-14 TC0 Mode Register (TMOD0) Organization.............................................................11-17 TMOD0.6, TMOD0.5, and TMOD0.4 Bit Settings ....................................................11-18 TC1 Register Overview .........................................................................................11-23 TC1 Mode Register (TMOD1) Organization.............................................................11-26 TMOD1.6, TMOD1.5, and TMOD1.4 Bit Settings ....................................................11-27 Watch Timer Mode Register (WMOD) Organization ................................................11-32 LCD Contrast Control Register (LCNST) Organization .............................................12-4 LCD Output Control Register (LCON0) Organization................................................12-5 LCD Output Control Register (LCON1) Organization................................................12-5 LCD Mode Control Register (LMOD) Organization...................................................12-7 KSR Organization................................................................................................12-17 External Memory Control Register (EMCON) Organization ......................................13-2
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List of Tables
Table Number 14-1 14-2 14-3 14-4 14-5 14-6 14-7 14-8 16-1 16-2 16-3 16-4 17-1 17-2 17-3 Title
(Continued)
Page Number
Absolute Maximum Ratings..................................................................................14-2 D.C Characteristics .............................................................................................14-2 Main System Clock Oscillator Characteristics........................................................14-5 Recommended Oscillator Constants .....................................................................14-6 Subsystem Clock Oscillator Characteristics ..........................................................14-7 Input/Output Capacitance.....................................................................................14-7 A.C. Electrical Characteristics..............................................................................14-8 RAM Data Retention Supply Voltage in Stop Mode.................................................14-9 Descriptions of Pins Used to Read/Write the EPROM.............................................16-3 Comparison of S3P72Q5 and S3C72Q5 Features ...................................................16-3 Operating Mode Selection Criteria.........................................................................16-3 D.C Characteristics .............................................................................................16-4 Power Selection Settings for TB72Q5....................................................................17-4 Main-clock Selection Settings for TB72Q5 .............................................................17-4 Sub-clock Selection Settings for TB72Q5 ..............................................................17-5
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List of Programming Tips
Description Page Number
Section 2: Address Spaces Defining Vectored Interrupts..................................................................................................................2-3 Using the REF Look-Up Table...............................................................................................................2-4 Clearing Data Memory Bank 0 ,and the page 0 in Bank 1........................................................................2-8 Selecting the Working Register Area.....................................................................................................2-12 Initializing the Stack Pointer .................................................................................................................2-13 Using the BSC Register to Output 16-Bit Data .......................................................................................2-16 Setting ISx Flags for Interrupt Processing ..............................................................................................2-18 Using the EMB Flag to Select Memory Banks .......................................................................................2-19 Using the ERB Flag to Select Register Banks........................................................................................2-20 Using the Carry Flag as a 1-Bit Accumulator..........................................................................................2-22 Section 3: Addressing Modes Initializing the EMB and ERB Flags.......................................................................................................3-3 1-Bit Addressing Modes .......................................................................................................................3-7 4-Bit Addressing Modes .......................................................................................................................3-8 8-Bit Addressing Modes .......................................................................................................................3-12 Section 5: SAM48 Instruction Set Example of the Instruction Redundancy Effect........................................................................................5-3 Section 6: Oscillator Circuits Setting the CPU Clock.........................................................................................................................6-4 Switching Between Main-system and Sub-system Clock ........................................................................6-9 CPU Clock Output to the CLO Pin ........................................................................................................6-11 Section 7: Interrupts Setting the INT Interrupt Priority ............................................................................................................7-8 Using INT2 as a Key Input Interrupt .......................................................................................................7-11 Section 8: Power-Down Reducing Power Consumption for Key Input Interrupt Processing.............................................................8-6
S3C72Q5/P72Q5 MICROCONTROLLER
xix
List of Programming Tips
Description
(Continued)
Page Number
Section 10: I/O Ports Configuring I/O Ports to Input or Output .................................................................................................10-3 Enabling and Disabling I/O Port Pull-Up Resistors ..................................................................................10-4 Section 11: Timers and Timer/Counter 0 Using the Basic Timer..........................................................................................................................11-7 Using the Watchdog Timer ...................................................................................................................11-9 TC0 Signal Output to the TCLO0 Pin .....................................................................................................11-15 External TCL0 Clock Output to the TCLO0 Pin .......................................................................................11-16 Restarting TC0 Counting Operation .......................................................................................................11-18 Setting a TC0 Timer Interval..................................................................................................................11-21 Restarting TC1 Counting Operation .......................................................................................................11-27 Setting a TC1 Timer Interval..................................................................................................................11-29 Using the Watch Timer ........................................................................................................................11-33 Section 13: External Memory Interface External Memory Interface....................................................................................................................13-4
xx
S3C72Q5/P72Q5 MICROCONTROLLER
List of Register Descriptions
Register Identifier BMOD CLMOD EMCON IE0, 1, IRQ0, 1 IE2, IRQ2 IEB, IRQB IEP0, IRQP0 IET0, IRQT0 IET1, IRQT1 IEW, IRQW IMOD0 IMOD1 IMOD2 IPR LCNST LCON0 LCON1 LMOD PASR PCON PMG0 PMG1 PMG2 PNE0 PSW PUMOD0 SCMOD TMOD0 TMOD1 TOE0 WDFLAG WDMOD WMOD Full Register Name Page Number
Basic Timer Mode Register ........................................................................4-8 Clock Output Mode Register.......................................................................4-9 External Memory Control Register...............................................................4-10 INT0, 1 Interrupt Enable/Request Flags........................................................4-11 INT2 Interrupt Enable/Request Flags ...........................................................4-12 INTB Interrupt Enable/Request Flags ...........................................................4-13 INTP0 Interrupt Enable/Request Flags .........................................................4-14 INTT0 Interrupt Enable/Request Flags..........................................................4-15 INTT1 Interrupt Enable/Request Flags..........................................................4-16 INTW Interrupt Enable/Request Flags ..........................................................4-17 External Interrupt 0 (INT0) Mode Register.....................................................4-18 External Interrupt 1 (INT1) Mode Register.....................................................4-19 External Interrupt 2 (INT2) Mode Register.....................................................4-20 Interrupt Priority Register............................................................................4-21 LCD Contrast Control Register....................................................................4-22 LCD Output Control Register 0....................................................................4-23 LCD Output Control Register 1....................................................................4-24 LCD Mode Register ...................................................................................4-25 Page Selection Register.............................................................................4-26 Power Control Register ..............................................................................4-27 Port I/O Mode Register 0 (Group 0: Port 0, 1)...............................................4-28 Port I/O Mode Register 1 (Group 1: Port 4, 5)...............................................4-29 Port I/O Mode Register 2 (Group 2: Port 6, 7)...............................................4-30 N-channel Open-drain Mode Register 0........................................................4-31 Program Status Word ................................................................................4-32 Pull-Up Resistor Mode Register ..................................................................4-33 System Clock Mode Control Register..........................................................4-34 Timer/Counter 0 Mode Register...................................................................4-35 Timer/Counter 1 Mode Register...................................................................4-36 Time/Output Enable Flag Register...............................................................4-37 Watch-Dog Timer's Counter Clear Flag........................................................4-38 Watch-Dog Timer Mode Control Register .....................................................4-39 Watch Timer Mode Register .......................................................................4-40
S3C72Q5/P72Q5 MICROCONTROLLER
xxi
List of Instruction Descriptions
Instruction Mnemonic ADC ADS AND BAND BITR BITS BOR BTSF BTST BTSTZ BXOR CALL CALLS CCF COM CPSE DECS DI EI IDLE INCS IRET JP JPS JR LD LDB LDC LDD LDI NOP OR POP PUSH Full Instruction Name Page Number
Add With Carry .....................................................................................5-24 Add and Skip on Overflow.......................................................................5-26 Locical AND..........................................................................................5-28 Bit Logical AND.....................................................................................5-29 Bit Reset ..............................................................................................5-31 Bit Set..................................................................................................5-33 Bit Logical OR.......................................................................................5-35 Bit Test and Skip on False.....................................................................5-37 Bit Test and Skip on True.......................................................................5-39 Bit Test and Skip on True; Clear Bit ........................................................5-41 Bit Exclusive OR ...................................................................................5-43 Call Procedure ......................................................................................5-45 Call Procedure (Short)............................................................................5-46 Complement Carry Flahg........................................................................5-47 Complement Accumulator ......................................................................5-48 Compare and Skip if Equal .....................................................................5-49 Decrement and Skip on Borrow...............................................................5-50 Disable Interrupts ..................................................................................5-51 Enable Interrupts ...................................................................................5-52 Idle Operation........................................................................................5-53 Increment and Skip on Carry ..................................................................5-54 Return from Interrupt ..............................................................................5-55 Jump....................................................................................................5-56 Jump (Short).........................................................................................5-57 Jump Relative (Very Short).....................................................................5-58 Load.....................................................................................................5-60 Load Bit................................................................................................5-64 Load Code Byte ....................................................................................5-66 Load Data Memory and Decrement .........................................................5-68 Load Data Memory and Increment...........................................................5-69 No Operation.........................................................................................5-70 Logical OR............................................................................................5-71 Pop from Stack .....................................................................................5-72 Push Onto Stack...................................................................................5-73
S3C72Q5/P72Q5 MICROCONTROLLER
xxiii
List of Instruction Descriptions
Instruction Mnemonic RCF REF RET RRC SBC SBS SCF SMB SRB SRET STOP VENT XCH XCHD XCHI XOR Full Instruction Name
(Continued)
Page Number
Reset Carry Flag ...................................................................................5-74 Reference Instruction .............................................................................5-75 Return from Subroutine ..........................................................................5-78 Rotate Accumulator Right Through Carry .................................................5-79 Subtract With Carry ...............................................................................5-80 Subtract ...............................................................................................5-82 Set Carry Flag.......................................................................................5-83 Select Memory Bank .............................................................................5-84 Select Register Bank .............................................................................5-85 Return from Subroutine and Skip.............................................................5-86 Stop Operation......................................................................................5-87 Load EMB, ERB, and Vector Address.....................................................5-88 Exchange A or EA With Nibble or Byte ...................................................5-90 Exchange and Decrement ......................................................................5-91 Exchange and Increment........................................................................5-92 Logical Exclusive OR.............................................................................5-93
xxiv
S3C72Q5/P72Q5 MICROCONTROLLER
S3C72Q5/P72Q5
PRODUCT OVERVIEW
1
OVERVIEW OTP
PRODUCT OVERVIEW
The S3C72Q5 is a SAM48 core-based 4-bit CMOS single-chip microcontroller. It has two timer/counters and LCD drivers. The S3C72Q5 is especially suited for use in data bank, telephone and LCD general purpose. It is built around the SAM48 core CPU and contains ROM, RAM, 39 I/O lines, programmable timer/counters, buzzer output, enough LCD dot matrix, external memory interface, and segment drive pins. The S3C72Q5 can be used for dedicated control functions in a variety of applications, and is especially designed for multi data bank, telephone and LCD game.
The S3C72Q5 microcontroller is also available in OTP (One Time Programmable) version, S3P72Q5. S3P72Q5 microcontroller has an on-chip 16K-byte one-time-programmable EPROM instead of masked ROM. The S3P72Q5 is comparable to S3C72Q5, both in function and in pin configuration.
1-1
PRODUCT OVERVIEW
S3C72Q5/P72Q5
FEATURES
Memory
* * *
LCD Display
* * * *
16 k x 8 bit program memory 5,120 x 4 bit data memory 144 x 5 bit LCD display memory
60 segments and 12 common terminals 9, 10, 11, and 12 common selectable Two internal resistor circuit for LCD bias (selectable) 16 level LCD contrast control (software)
39 I/O Pins
* *
I/O: 23 pins Output: maximum 16 pins for 1-bit level output (sharing with segment driver outputs) External Memory Interface
*
8-Bit Basic Timer
* *
512 k x 8 bit external memory access (19 address and 8 data pins-sharing with segment driver outputs) Six external memory selection pins (DM0-DM5) 1 data read and 1 data write pins (DR, DW-sharing with segment driver outputs)
Four internal timer functions Watch-dog timer
* *
8-Bit Timer/Counter 0
* * * *
Programmable 8-bit timer External event counter Arbitrary clock frequency output External clock signal divider
Power-Down Modes
* *
Idle mode (only CPU clock stops) Stop mode (Main-System clock, Sub-System clock and CPU clock stops)
8-Bit Timer/Counter 1
*
Oscillation Sources
* * * *
Programmable 8-bit timer
Crystal, ceramic, or External RC for system clock Main-system clock frequency: 0.4 MHz-6 MHz Sub-system clock frequency: 32,768 kHz CPU clock divider circuit (by 4,8, or 64)
Watch Timer
* *
Time interval generation: 0.5ms, 3.91ms at 32,768Hz 4 frequency (2/4/8/16 kHz) outputs to BUZ pin
Instruction Execution Times
*
0.67, 1.33, 10.7 s at 6 MHz 0.95, 1.91, 15.3 s at 4.19 MHz 122 s at 32.768 kHz
Interrupts
* * *
* *
Three external vectored interrupts: INT0, INT1, INTP0 Three internal vectored interrupts: INTB, INTT0, INTT1 Two quasi-interrupts: INTW, INT2
Operating Temperature
*
-25 C to 85 C
Operating Voltage Range Memory Mapped I/O Structure
*
1.8 V to 5.5 V
Package Type
*
100-pin QFP Package
1-2
S3C72Q5/P72Q5
PRODUCT OVERVIEW
BLOCK DIAGRAM
INTT0, INTT1, INTB, INTW INT0, INT1, INTP0, INT2
XIN XOUT RESET XTIN XTOUT I/O Port 0 Interrupt Control Block
P0.0-P0.3/K0-K3
8-Bit Timer/ Counter 0
Clock
Instruction Register
I/O Port 1
P1.0-P1.2/K4-K6 P4.0/TCL0 P4.1/TCLO0 P4.2/INT0 P4.3/INT1 P5.0-P5.1 P5.2/BUZ P5.3/CLO P6.0-P6.3/KS0KS3/DM0-DM3 P7.0/KS4/DM4 P7.1/KS5/DM5 /COM11 P7.2-P7.3/KS6KS7 /COM10-9 P8.0-P8.15/ SEG0-SEG15
I/O Port 4 8-Bit Timer/ Counter 1 Internal Interrupts Program Counter
I/O Port 5
Watch-dog Timer
Basic Timer Instruction Decoder Watch Timer Program Status Word I/O Port 6
COM0-COM8 COM9-COM11/P7.3-P7.1 SEG45-SEG59 SEG44/ DW SEG43/ DR SEG24-SEG42/A0-A18 SEG16-SEG23/D0-D7 SEG0-SEG15/P8.0-P8.15
I/O Port 7 LCD Driver/ Controller LCD Contrast Controller Data and Display Memory 16 K Byte Program Memory Arithmetic and Logic Unit Stack Pointer Output Port 8
External Memory Interface
Figure 1-1. S3C72Q5/P72Q5 Specified Block Diagram
1-3
PRODUCT OVERVIEW
S3C72Q5/P72Q5
PIN ASSIGNMENTS
SEG39/A15 SEG40/A16 SEG41/A17 SEG42/A18 SEG43/DR SEG44/DW SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 SEG38/A14 SEG37/A13 SEG36/A12 SEG35/A11 SEG34/A10 SEG33/A9 SEG32/A8 SEG31/A7 SEG30/A6 SEG29/A5 SEG28/A4 SEG27/A3 SEG26/A2 SEG25/A1 SEG24/A0 SEG23/D7 SEG22/D6 SEG21/D5 SEG20/D4 SEG19/D3 SEG18/D2 SEG17/D1 SEG16/D0 SEG15/P8.15 SEG14/P8.14 SEG13/P8.13 SEG12/P8.12 SEG11/P8.11 SEG10/P8.10 SEG9/P8.9
SEG59 COM4 COM5 COM6 COM7 COM8 P7.3/KS7/COM9 P7.2/KS6/COM10 P7.1/KS5/DM5/COM11 P7.0/KS4/DM4 P6.3/KS3/DM3 P6.2/KS2/DM2 P6.1/KS1/DM1 P6.0/KS0/DM0 VDD VSS XOUT XIN TEST XTIN XTOUT RESET P5.0 P5.1 P5.2/BUZ P5.3/CLO P4.0/TCL0 P4.1/TCLO0 P4.2/INT0 P4.3/INT1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
S3C72Q5
(100-QFP-1420C)
Figure 1-2. S3C72Q5 Pin Assignment Diagram
50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 SEG8/P8.8 SEG7/P8.7 SEG6/P8.6 SEG5/P8.5 SEG4/P8.4 SEG3/P8.3 SEG2/P8.2 SEG1/P8.1 SEG0/P8.0 COM3 COM2 COM1 COM0 P0.0/K0 P0.1/K1 P0.2/K2 P0.3/K3 P1.0/K4 P1.1/K5 P1.2/K6
1-4
S3C72Q5/P72Q5
PRODUCT OVERVIEW
PIN DESCRIPTIONS
Table 1-1. Pin Descriptions Pin Name P0.0-P0.3 P1.0-P1.2 Pin Type I/O Description 4-bit I/O port. 1, 4, and 8-bit read/write, and test are possible. Individual pin can be specified as input or output. 7-bit pull-up resistors are assignable by software. Pull-up resistors are automatically disabled for output pins. 4-bit I/O port. 1, 4, and 8-bit read/write, and test are possible. Individual pin can be specified as input or output. 4-bit pull-up resistors are assignable by software. Pull-up resistors are automatically disabled for output pins. Individual pins are software configurable as open-drain or pushpull output. 4-bit I/O port. 1, 4, and 8-bit read/write, and test are possible. Individual pin can be specified as input or output. 4-bit pull-up resistors are assignable by software. Pull- up resistors are automatically disabled for output pins. O 4-bit controllable output. (Dual function as segment output pins) LCD segment display signal output. I/O O LCD segment display signal output. LCD segment display signal output. LCD segment display signal output. LCD segment display signal output. LCD common signal output. I/O LCD common signal output. Circuit Type E-3 Pin Number 37-34 33-31 Share Pin K0-K3 K4-K6
P4.0 P4.1 P4.2 P4.3 P5.0-P5.1 P5.2 P5.3 P6.0-P6.3 P7.0 P7.1 P7.2-P7.3 P8.0-P8.15 SEG0-SEG15 SEG16-SEG23 SEG24-SEG42 SEG43,SEG44 SEG45-SEG59 COM0-COM8 COM9-COM10 COM11 INT0-INT1
NOTE:
E-2
27 28 29 30 23-24 25 26 14-11 10 9 8-7
TCL0 TCLO0 INT0 INT1 - BUZ CLO KS0-KS3/ DM0-DM3 KS4/DM4 KS5/DM5/COM11 KS6-KS7/COM10COM9 SEG0-SEG15 P8.0-P8.15 D0-D7 A0-A18 DR, DW - - P7.3-P7.2/ KS7-KS6 P7.1/KS5/DM5 P4.2-P4.3
E-3
H-9 H-9 H-10 H-11 H-11 H-5 H-4 H-12
42-57 42-57 58-65 66-84 85, 86 87-100,1 38-41 2-6 7-8 9
External interrupts. The triggering edge for INT0, and INT1 is selectable
E-2
29-30
P8 can be used to normal output port, when LCD display is off. The value of P8 is determined by KSR0-KSR3 regardless of LMOD.0. (refer to P12-17)
1-5
PRODUCT OVERVIEW
S3C72Q5/P72Q5
Table 1-1. Pin Descriptions (Continued) Pin Name BUZ CLO TCL0 TCLO0 K0-K6 KS0-KS4 KS5 KS6-KS7 DM0-DM4 DM5 D0-D7 A0-A18 DR, DW XIN, XOUT XTIN, XTOUT RESET VDD VSS TEST - - I - - I O External data memory select signal Data signal I/O Address signal out External data memory read/write signal Crystal, ceramic or RC oscillator pins for main system clock. Crystal oscillator pins for sub-system clock. Reset input (active low). Power supply. Ground. Test input: it must be connected to VSS Pin Type I/O Description 2,4,8 kHz or 16 kHz frequency output for buzzer signal. Clock output External clock input for Timer/Counter0 Timer/Counter0 clock output Vector interrupt input. K0-K6: falling edge detection Quasi-interrupt input for falling edge detection E-3 E-3 H-12 Circuit Type E-2 Pin Num. 25 26 27 28 37-31 14-10 9 8-7 14-10 58-65 66-84 85, 86 18, 17 20, 21 22 15 16 19 Share Pin P5.2 P5.3 P4.0 P4.1 P0.0-P1.2 P6.0-P7.0/ DM0-DM4 P7.1/DM5/COM11 P7.2-P7.3/ COM10-COM9 P6.0-P7.0/KS0-KS4 P7.1/KS5/COM11 SEG16-SEG23 SEG24-SEG42 SEG43, SEG44 - - - - - -
E-3 H-12 H-10 H-11 H-11 - - B - - -
1-6
S3C72Q5/P72Q5
PRODUCT OVERVIEW
PIN CIRCUIT DIAGRAMS
VDD
VDD Pull-Up Resistor
P-Channel In N-Channel
In Schmitt Trigger
Figure 1-3. Pin Circuit Type A
Figure 1-5. Pin Circuit Type B
VDD Pull-Up Resistor P-Channel Pull-Up Resistor Enable
VDD
Data
P-Channel Out
In Schmitt Trigger
Output Disable
N-Channel
Figure 1-4. Pin Circuit Type A-3
Figure 1-6. Pin Circuit Type C
1-7
PRODUCT OVERVIEW
S3C72Q5/P72Q5
VDD PNE Pull-up Resistor Pull-up Resistor Enable I/O N-CH
VDD
P-CH Data Output Disable
Schmitt Trigger
Figure 1-7. Pin Circuit Type E-2
VDD Pull-up Resistor Pull-up Resistor Enable Data Output Disable Circuit Type C P-CH
I/O
Schmitt Trigger
Figure 1-8. Pin Circuit Type E-3
1-8
S3C72Q5/P72Q5
PRODUCT OVERVIEW
VLC1
VLC1
VLC2
VLC2
COM Output Disable VLC4
Out
SEG Output Disable VLC3 Out
VSS
VSS
Key Strobe
N-CH
Figure 1-9. Pin Circuit Type H-4
Figure 1-11. Pin Circuit Type H-6
VLC1
VLC1
VLC2
VLC2
SEG
Out
COM Output Disable VLC3
Out
VLC3
VSS
VSS
Figure 1-10. Pin Circuit Type H-5
Figure 1-12. Pin Circuit Type H-7
1-9
PRODUCT OVERVIEW
S3C72Q5/P72Q5
VDD
Data Output Disable1 SEG Output Disable2 Key Strobe Circuit Type H-6
Out N-CH
P-CH Data Output Disable1 N-CH Out
N-CH
SEG Output Disable2 Circuit Type H-6
Figure 1-13. Pin Circuit Type H-9
Figure 1-15. Pin Circuit Type H-11
VDD
VDD
Resistor Enable
Pull-up Resistor P-CH
P-CH Data Output Disable1 SEG Output Disable2 Circuit Type H-6 N-CH I/O
COM Output Disable1 Data Output Disable2
Type H-7
Type C
I/O
Key Strobe
N-CH
Figure 1-14. Pin Circuit Type H-10
Figure 1-16. Pin Circuit Type H-12
1-10
S3C72Q5/P72Q5
ADDRESS SPACE
2
OVERVIEW
ADDRESS SPACES
PROGRAM MEMORY (ROM)
ROM maps for S3C72Q5 devices are mask programmable at the factory. In its standard configuration, the device's 16,384 bytes program memory has four areas that are directly addressable by the program counter (PC): -- 14-byte area for vector addresses -- 18-byte general-purpose area -- 96-byte instruction reference area -- 16,256-byte general-purpose area General-Purpose Program Memory Two program memory areas are allocated for general-purpose use: One area is 18-byte in size and the other is 16,256-byte. Vector Addresses A 14-byte vector address area is used to store the vector addresses required to execute system resets and interrupts. Start addresses for interrupt service routines are stored in this area, along with the values of the enable memory bank (EMB) and enable register bank (ERB) flags that are used to set their initial value for the corresponding service routines. The 14-byte area can be used alternately as general-purpose ROM. REF Instructions Locations 0020H-007FH are used as a reference area (look-up table) for 1-byte REF instructions. The REF instruction reduces the byte size of instruction operands. REF can reference one 2-byte instruction, two 1-byte instructions, and one 3-byte instructions which are stored in the look-up table. Unused look-up table addresses can be used as general-purpose ROM. Table 2-1. Program Memory Address Ranges ROM Area Function Vector address area General-purpose program memory REF instruction look-up table area General-purpose program memory Address Ranges 0000H-000DH 000EH-001FH 0020H-007FH 0080H-3FFFH Area Size (in Bytes) 14 18 96 16,256
2-1
ADDRESS SPACE
S3C72Q5/P72Q5
GENERAL-PURPOSE MEMORY AREAS The 18-byte area at ROM locations 000EH-001FH and the 16,256-byte area at ROM locations 0080H-3FFFH are used as general-purpose program memory. Unused locations in the vector address area and REF instruction look-up table areas can be used as general-purpose program memory. However, care must be taken not to overwrite live data when writing programs that use special-purpose areas of the ROM. VECTOR ADDRESS AREA The 14-byte vector address area of the ROM is used to store the vector addresses for executing system resets and interrupts. The starting addresses of interrupt service routines are stored in this area, along with the enable memory bank (EMB) and enable register bank (ERB) flag values that are needed to initialize the service routines. 16-byte vector addresses are organized as follows: EMB PC7 ERB PC6 0 PC5 PC12 PC4 PC11 PC3 PC10 PC2 PC9 PC1 PC8 PC0
To set up the vector address area for specific programs, use the instruction VENTn. The programming tips on the next page explain how to do this.
0000H Vector Address Area (14 bytes) 000DH 000EH General Purpose Area (18 bytes) 001FH 0020H Instruction Reference Area (96 bytes) 007FH 0080H
7 0000H
6
5
4
3
2
1
0
RESET
0002H
Basic Timer
0004H
INT0
0006H
INT1
0008H
INTP0
General Purpose Area (16,256 bytes)
000AH
Timer/Counter0
000CH
3FFFH
Timer/Counter1
Figure 2-1. ROM Address Structure
Figure 2-2. Vector Address Map
2-2
S3C72Q5/P72Q5
ADDRESS SPACE
F
PROGRAMMING TIP - Defining Vectored Interrupts
The following examples show you several ways you can define the vectored interrupt and instruction reference areas in program memory: 1. When all vector interrupts are used: ORG ; VENT0 VENT1 VENT2 VENT3 VENT4 VENT5 VENT6 2. 1,0,RESET 0,0,INTB 0,0,INT0 0,0,INT1 0,0,INTP0 0,0,INTT0 0,0,INTT1 ; ; ; ; ; ; ; EMB EMB EMB EMB EMB EMB EMB 1, ERB 0, ERB 0, ERB 0, ERB 0, ERB 0, ERB 0, ERB 0; Jump to RESET address by RESET 0; Jump to INTB address by INTB 0; Jump to INT0 address by INT0 0; Jump to INT1 address by INT1 0; Jump to INTP0 address by INTP0 0; Jump to INTT0 address by INTT0 0; Jump to INTT1 address by INTT1 0000H
When a specific vectored interrupt such as INT0, and INTT0 is not used, the unused vector interrupt locations must be skipped with the assembly instruction ORG so that jumps will address the correct locations: ORG 0000H EMB 1, ERB 0; Jump to RESET address by RESET EMB 0, ERB 0; Jump to INTB address by INTB INT0 interrupt not used EMB 0, ERB 0; Jump to INT1 address by INT1 EMB 0, ERB 0; Jump to INTP0 address by INTP0 INTT0 interrupt not used
; VENT0 VENT1 ORG VENT3 VENT4 ORG VENT6 3. 1,0,RESET 0,0,INTB 0006H 0,0,INT1 0,0,INTP0 000CH 0,0,INTT1 ; ; ; ; ; ;
; EMB 0, ERB 0; Jump to INTT1 address by INTT1
If an INT0 and INTT1 interrupt is not used and if its corresponding vector interrupt area is not fully utilized, or if it is not written by a ORG instruction in Example 2, a CPU malfunction will occur: ORG 0000H 1,0,RESET 0,0,INTB 0,0,INT1 0,0,INTP0 0,0,INTT0 ; ; ; ; ; EMB EMB EMB EMB EMB 1, ERB 0, ERB 0, ERB 0, ERB 0, ERB 0; Jump to RESET address by RESET 0; Jump to INTB address by INTB 0; Jump to INT1 address by INT1 0; Jump to INTP0 address by INTP0 0; Jump to INTT0 address by INTT0
; VENT0 VENT1 VENT3 VENT4 VENT5
In this example, when an INTP0 interrupt is generated, the corresponding vector area is not VENT4 INTP0, but VENT5 INTT0. This causes an INTP0 interrupt to jump incorrectly to the INTT0 address and causes a CPU malfunction to occur.
2-3
ADDRESS SPACE
S3C72Q5/P72Q5
INSTRUCTION REFERENCE AREA Using 1-byte REF instructions, you can easily reference instructions with larger byte sizes that are stored in addresses 0020H-007FH of program memory. This 96-byte area is called the REF instruction reference area, or look-up table. Locations in the REF look-up table may contain two 1-byte instructions, one 2-byte instruction, or one 3-byte instruction such as a JP (jump) or CALL. The starting address of the instruction you are referencing must always be an even number. To reference a JP or CALL instruction, it must be written to the reference area in a two-byte format: for JP, this format is TJP; for CALL, it is TCALL. In summary, there are three ways to the REF instruction: By using REF instructions, you can execute instructions larger than one byte. In summary, there are three ways you can use the REF instruction: -- Using the 1-byte REF instruction to execute one 2-byte or two 1-byte instructions -- Branching to any location by referencing a branch instruction stored in the look-up table -- Calling subroutines at any location by referencing a call instruction stored in the look-up table
F
PROGRAMMING TIP -- Using the REF Look-Up Table
Here is one example of how to use the REF instruction look-up table: ORG ; JMAIN KEYCK WATCH INCHL TJP BTSF TCALL LD INCS
* *
0020H MAIN KEYFG CLOCK @HL,A HL ; ; ; ; 0, MAIN 1, KEYFG CHECK 2, CALL CLOCK 3, (HL) A
ABC ; MAIN
LD ORG NOP NOP
* *
EA,#00H 0080
; 47, EA
#00H
REF REF REF REF REF
* *
KEYCK JMAIN WATCH INCHL ABC
; ; ; ; ;
BTSF KEYFG (1-byte instruction) KEYFG = 1, jump to MAIN (1-byte instruction) KEYFG = 0, CALL CLOCK (1-byte instruction) LD @HL,A : INCS HL LD EA,#00H (1-byte instruction)
2-4
S3C72Q5/P72Q5
ADDRESS SPACE
DATA MEMORY (RAM)
OVERVIEW In its standard configuration, the data memories have four areas: -- 32 x 4-bit working register area -- 224 x 4-bit general-purpose area in bank 0 which is also used as the stack area -- 20 pages with 256 x 4-bit in bank1
* *
19 pages for general purpose area (00H-12H page) 1 page for LCD Display data memory (13H page)
-- 128 x 4-bit area in bank 15 for memory-mapped I/O addresses To make it easier to reference, the data memory area has three memory banks -- bank 0, bank 1, and bank 15. The select memory bank instruction (SMB) is used to select the bank you want to select as working data memory. Data stored in RAM locations are 1-, 4-, and 8-bit addressable. One exception is the display data memory area, which is 8-bit addressable only. Initialization values for the data memory area are not defined by hardware therefore must be initialized by program software following power RESET. However, when RESET signal is generated in power-down mode, the most of the data memory contents are held. Bank 1 Page Selection Register (PASR) PASR is a 5-bit write -only register for selecting the page of bank1 ,and is mapped to the RAM address FA0H. It should be written by a 8-bit RAM control instruction only and the MSB 3 bits should be "0". PASR retains the previous value as long as change is not required, and the reset value is 0. Therefore, when it returns to the Bank 1 from other bank (Bank 0 or Bank 15) without changing the contents of PASR, the previously specified Bank 1 page is selected . The PASR must not be changed in the interrupt service routine because it's value cannot be recovered as the original value when the routine is finished.
2-5
ADDRESS SPACE
S3C72Q5/P72Q5
3 000H Bank 0 (EMB=1, SMB = 0 or EMB=0) 020H
2
1
0
Working Registers GeneralPurpose and/or Stack Registers 100H 100H 100H 100H 100H 100H 100H 100H Page Page 100H 100H (01H) (02H) Page Page 100H 100H (03H) (04H) Page Page Page (05H) (06H) Page Page (07H) 1FFH (0FH) (10H) Page Page 1FFH 1FFH (11H) (12H) 1FFH 1FFH 1FFH 1FFH 1FFH 1FFH 1FFH 1FFH 1FFH 100H 101H 102H 103H 104H 105H 106H 107H 108H 109H 10AH 10BH 110H
0FFH 100H GeneralPurpose Registers Page (00H) 1FFH
Bank 1 (EMB=1,SMB=1)
F80H Bank15 (EMB=1 SMB=15, or EMB=0) FFFH Peripheral Hardware Register
Display Data Registers Page (13H)
1ABH 1B0H 1B1H 1B2H 1B3H 1B4H 1B5H 1B6H 1B7H 1B8H 1B9H 1BAH 1BBH
Figure 2-3. S3C72Q5 Data Memory (RAM) Map
2-6
S3C72Q5/P72Q5
ADDRESS SPACE
Memory Banks 0, 1, and 15 Bank 0 (000H-0FFH) The lowest 32 nibbles of bank 0 (000H-01FH) are used as working registers; the next 224 nibbles (020H-0FFH) can be used both as stack area and as general-purpose data memory. Use the stack area for implementing subroutine calls and returns, and for interrupt processing. Bank 1 has the data memory of 20 pages, the 00H-12H pages for general purpose data memory are comprised of 256 x 4-bits, and the 13H page for LCD display data memory consists of 144 x 5-bits. The S3C72Q5 use specially a Bank 1 page selection register (PASR) for selecting one of these 20 pages. The microcontroller uses bank 15 for memory-mapped peripheral I/O. Fixed RAM locations for each peripheral hardware address are mapped into this area.
Bank 1
(100H-1FFH)
Bank 15
(F80H-FFFH)
Data Memory Addressing Modes The enable memory bank (EMB) flag controls the addressing mode for data memory banks 0, 1, or 15. When the EMB flag is logic zero, the addressable area is restricted to specific locations, depending on whether direct or indirect addressing is used. With direct addressing, you can access locations 000H-07FH of bank 0 and bank 15. With indirect addressing, only bank 0 (000H-0FFH) can be accessed. When the EMB flag is set to logic one, all three data memory banks can be accessed according to the current SMB value. For 8-bit addressing, two 4-bit registers are addressed as a register pair. Also, when using 8-bit instructions to address RAM locations, remember to use the even-numbered register address as the instruction operand. Working Registers The RAM working register area in data memory bank 0 is further divided into four register banks (bank 0, 1, 2, and, 3). Each register bank has eight 4-bit registers and paired 4-bit registers are 8-bit addressable. Register A is used as a 4-bit accumulator and register pair EA as an 8-bit extended accumulator. The carry flag bit can also be used as a 1-bit accumulator. Register pairs WX, WL, and HL are used as address pointers for indirect addressing. To limit the possibility of data corruption due to incorrect register addressing, it is advisable to use register bank 0 for the main program and banks 1, 2, and, 3 for interrupt service routines. LCD Data Register Area Bit values for LCD segment data are stored in data memory bank 1 (13H page). Register locations in this area that are not used to store LCD data can be assigned to general-purpose use. Table 2-2. Data Memory Organization and Addressing Addresses 000H-01FH 020H-0FFH 100H11FFH F80H-FFFH Working registers Stack and general-purpose registers General-purpose registers (00H-12H pages) LCD display data memory (the 13th page) I/O-mapped hardware registers 1 15 1 0, 1 1 15 Register Areas Bank 0 EMB Value 0, 1 SMB Value 0
NOTE: LCD data register is 13H page in data memory Bank 1.
2-7
ADDRESS SPACE
S3C72Q5/P72Q5
F
PROGRAMMING TIP - Clearing Data Memory Bank 0 ,and the page 0 in Bank 1
Clear bank 0 of the data memory area, and the page 0 of the data memory area in Bank 1 SMB LD LD RAMCLR SMB LD LD LD INCS JR SMB LD LD INCS JR 15 EA, #00H PASR, EA 1 HL,#00H A,#0H @HL,A HL RMCL1 0 HL,#20H @HL,A HL RMCL0 ; page 0 in Bank 1 clear
RMCL1
; ; Bank 0 clear
RMCL0
2-8
S3C72Q5/P72Q5
ADDRESS SPACE
WORKING REGISTERS Working registers, mapped to RAM address 000H-01FH in data memory bank 0, are used to temporarily store intermediate results during program execution, as well as pointer values used for indirect addressing. Unused registers may be used as general-purpose memory. Working register data can be manipulated as 1-bit unit, 4-bit unit, or using paired registers, as 8-bit unit.
000H 001H 002H 003H 004H 005H 006H 007H 008H 00FH 010H 017H 018H 01FH
A E L H X W Z Y Bank 1 Same as Bank 0 Bank 2 Same as Bank 0 Bank 3 Same as Bank 0 Register Bank 1 (ERB = 1, SRB = 1) Register Bank 2 (ERB = 1, SRB = 2) Register Bank 3 (ERB = 1, SRB = 3) Register Bank 0 (ERB = 0, or ERB = 1 and SRB = 0)
Figure 2-4. Working Register Map
2-9
ADDRESS SPACE
S3C72Q5/P72Q5
Working Register Banks For addressing purposes, the working register area is divided into four register banks - bank 0, bank 1, bank 2, and bank 3. Any one of these banks can be selected as the working register bank by the register bank selection instruction (SRB n) and by setting the status of the register bank enable flag (ERB). Generally, working register bank 0 is used for the main program, and banks 1, 2, and 3 for interrupt service routines. Following this convention helps to prevent possible data corruption during program execution due to contention in register bank addressing. Table 2-3. Working Register Organization and Addressing ERB Setting 3 0 0 2 0 SRB Settings 1 x 0 1 0 0 0 1 1
NOTE: 'x' means don't care.
Selected Register Bank 0 x 0 1 0 1 Always set to bank 0 Bank 0 Bank 1 Bank 2 Bank 3
Paired Working Registers Each of the register banks is subdivided into eight 4-bit registers. These registers, named Y, Z, W, X, H, L, E and A, can either be manipulated individually using 4-bit instructions, or together as register pairs for 8-bit data manipulation. The names of the 8-bit register pairs in each register bank are EA, HL, WX, YZ and WL. Registers A, L, X and Z always become the lower nibble when registers are addressed as 8-bit pairs. This makes a total of eight 4-bit registers or four 8-bit double registers in each of the four working register banks.
(MSB) Y
(LSB)
(MSB) Z
(LSB)
W
X
H
L
E
A
Figure 2-5. Register Pair Configuration
2-10
S3C72Q5/P72Q5
ADDRESS SPACE
Special-Purpose Working Registers Register A is used as a 4-bit accumulator and double register EA as an 8-bit accumulator. The carry flag can also be used as a 1-bit accumulator. 8-bit double registers WX, WL and HL are used as data pointers for indirect addressing. When the HL register serves as a data pointer, the instructions LDI, LDD, XCHI, and XCHD can make very efficient use of working registers as program loop counters by letting you transfer a value to the L register and increment or decrement it using a single instruction.
C
1-Bit Accumulator
A
4-Bit Accumulator
EA
8-Bit Accumulator
Figure 2-6. 1-Bit, 4-Bit, and 8-Bit Accumulator
Recommendation for Multiple Interrupt Processing If more than four interrupts are being processed at one time, you can avoid possible loss of working register data by using the PUSH RR instruction to save register contents to the stack before the service routines are executed in the same register bank. When the routines have been executed successfully, you can restore the register contents from the stack to working memory by using the POP instruction.
2-11
ADDRESS SPACE
S3C72Q5/P72Q5
F
1.
PROGRAMMING TIP -- Selecting the Working Register Area
The following examples show the correct programming method for selecting working register area: When ERB = "0": VENT2 ; INT0 PUSH SRB PUSH PUSH PUSH PUSH SMB LD LD LD INCS LD LD POP POP POP POP POP IRET 1,0,INT0 SB 2 HL WX YZ EA 0 EA,#00H 80H,EA HL,#40H HL WX,EA YZ,EA EA YZ WX HL SB ; EMB 1, ERB 0, Jump to INT0 address ; ; ; ; ; ; PUSH current SMB, SRB Instruction does not execute because ERB = "0" PUSH HL register contents to stack PUSH WX register contents to stack PUSH YZ register contents to stack PUSH EA register contents to stack
; ; ; ; ;
POP EA register contents from stack POP YZ register contents from stack POP WX register contents from stack POP HL register contents from stack POP current SMB, SRB
The POP instructions execute alternately with the PUSH instructions. If an SMB n instruction is used in an interrupt service routine, a PUSH and POP SB instruction must be used to store and restore the current SMB and SRB values, as shown in Example 2 below. 2. When ERB = "1": VENT2 ; INT0 PUSH SRB SMB LD LD LD INCS LD LD POP IRET 1,1,INT0 SB 2 0 EA,#00H 80H,EA HL,#40H HL WX,EA YZ,EA SB ; EMB 1, ERB 1, Jump to INT0 address ; Store current SMB, SRB ; Select register bank 2 because of ERB = "1"
; Restore SMB, SRB
2-12
S3C72Q5/P72Q5
ADDRESS SPACE
STACK OPERATIONS
STACK POINTER (SP) The stack pointer (SP) is an 8-bit register that stores the address used to access the stack, an area of data memory set aside for temporary storage of data and addresses. The SP can be read or written by 8-bit control instructions. When addressing the SP, bit 0 must always remain cleared to logic zero. F80H F81H SP3 SP7 SP2 SP6 SP1 SP5 "0" SP4
There are two basic stack operations: writing to the top of the stack (push), and reading from the top of the stack (pop). A push decrements the SP and a pop increments it so that the SP always points to the top address of the last data to be written to the stack. The program counter contents and program status word are stored in the stack area prior to the execution of a CALL or a PUSH instruction, or during interrupt service routines. Stack operation is a LIFO (Last In-First Out) type. The stack area is located in general-purpose data memory bank 0. During an interrupt or a subroutine, the PC value and the PSW are saved to the stack area. When the routine has been completed, the stack pointer is referenced to restore the PC and PSW, and the next instruction is executed. The SP can address stack registers in bank 0 (addresses 000H-0FFH) regardless of the current value of the enable memory bank (EMB) flag and the select memory bank (SMB) flag. Although general-purpose register areas can be used for stack operations, be careful to avoid data loss due to simultaneous use of the same register(s). Since the reset value of the stack pointer is not defined in firmware, we recommend that you initialize the stack pointer by program code to location 00H. This sets the first register of the stack area to 0FFH. NOTE A subroutine call occupies six nibbles in the stack; an interrupt requires six. When subroutine nesting or interrupt routines are used continuously, the stack area should be set in accordance with the maximum number of subroutine levels. To do this, estimate the number of nibbles that will be used for the subroutines or interrupts and set the stack area correspondingly.
F
1.
PROGRAMMING TIP -- Initializing the Stack Pointer
To initialize the stack pointer (SP): When EMB = "1": SMB LD LD 2. When EMB = "0": LD LD EA,#00H SP,EA ; Memory addressing area (00H-7FH, F80H-FFFH) 15 EA,#00H SP,EA ; Select memory bank 15 ; Bit 0 of accumulator A is always cleared to "0" ; Stack area initial address (0FFH) (SP) - 1
2-13
ADDRESS SPACE
S3C72Q5/P72Q5
PUSH OPERATIONS Three kinds of push operations reference the stack pointer (SP) to write data from the source register to the stack: PUSH instructions, CALL instructions, and interrupts. In each case, the SP is decremented by a number determined by the type of push operation and then points to the next available stack location. PUSH Instructions A PUSH instruction references the SP to write two 4-bit data nibbles to the stack. Two 4-bit stack addresses are referenced by the stack pointer: one for the upper register value and another for the lower register. After the PUSH has been executed, the SP is decremented by two and points to the next available stack location. CALL Instructions When a subroutine call is issued, the CALL instruction references the SP to write the PC's contents to six 4-bit stack locations. Current values for the enable memory bank (EMB) flag and the enable register bank (ERB) flag are also pushed to the stack. Since six 4-bit stack locations are used per CALL, you may nest subroutine calls up to the number of levels permitted in the stack. Interrupt Routines An interrupt routine references the SP to push the contents of the PC and the program status word (PSW) to the stack. Six 4-bit stack locations are used to store this data. After the interrupt has been executed, the SP is decremented by six and points to the next available stack location. During an interrupt sequence, subroutines may be nested up to the number of levels which are permitted in the stack area.
PUSH (After PUSH, SP
SP - 2)
CALL, LCALL (After CALL or LCALL, SP SP - 6 SP - 5 SP - 4 SP - 3 0 PC11 - PC8 PC14 - PC12 PC3 - PC0 PC7 - PC4 0 0
SP - 6) SP - 6 SP - 5 SP - 4 SP - 3 SP - 2 SP - 1 SP
Interrupt (When INT is acknowledged, SP SP - 6) PC11 - PC8 0 PC14 - PC12 PC3 - PC0 PC7 - PC4 IS1 C IS0 EMB ERB PSW SC2 SC1 SC0
SP - 2 SP - 1 SP
Lower Register Upper Register
SP - 2 SP - 1 SP
EMB ERB PSW 0 0 0
0
Figure 2-7. Push-Type Stack Operations
2-14
S3C72Q5/P72Q5
ADDRESS SPACE
POP OPERATIONS For each push operation, there is a corresponding pop operation to write data from the stack back to the source register or registers: for the PUSH instruction it is the POP instruction; for CALL, the instruction RET or SRET; for interrupts, the instruction IRET. When a pop operation occurs, the SP is incremented by a number determined by the type of operation and points to the next free stack location. POP Instructions A POP instruction references the SP to write data stored in two 4-bit stack locations back to the register pairs and SB register. The value of the lower 4-bit register is popped first, followed by the value of the upper 4-bit register. After the POP has been executed, the SP is incremented by two and points to the next free stack location. RET and SRET Instructions The end of a subroutine call is signaled by the return instruction, RET or SRET. The RET or SRET uses the SP to reference the six 4-bit stack locations used for the CALL and to write this data back to the PC, the EMB, and the ERB. After the RET or SRET has been executed, the SP is incremented by six and points to the next free stack location. IRET Instructions The end of an interrupt sequence is signaled by the instruction IRET. IRET references the SP to locate the six 4-bit stack addresses used for the interrupt and to write this data back to the PC and the PSW. After the IRET has been executed, the SP is incremented by six and points to the next free stack location.
(SP SP SP + 1 SP + 1
POP SP + 2) SP SP + 1 SP + 2 SP + 3 SP + 4 SP + 5 SP + 6 0 0 0
RET or SRET (SP SP + 6) PC11 - PC8 PC14 - PC12 PC3 - PC0 PC7 - PC4 EMB ERB PSW 0 0 0 0 SP SP + 1 SP + 2 SP + 3 SP + 4 SP + 5 SP + 6 IS1 C 0
(SP
IRET SP + 6)
Lower Register Upper Register
PC11 - PC8 PC14 - PC12 PC3 - PC0 PC7 - PC4 IS0 EMB ERB PSW SC2 SC1 SC0
Figure 2-8. Pop-Type Stack Operations
2-15
ADDRESS SPACE
S3C72Q5/P72Q5
BIT SEQUENTIAL CARRIER (BSC)
The BSC can be manipulated using 1-, 4-, and 8-bit RAM control instructions. RESET clears all BSC bit values to logic zero. Using the BSC, you can specify sequential addresses and bit locations using 1-bit indirect addressing (memb.@L). (Bit addressing is independent of the current EMB value.) In this way, programs can process 16-bit data by moving the bit location sequentially and then incrementing or decrementing the value of the L register. BSC data can also be manipulated using direct addressing. For 8-bit manipulations, the 4-bit register names BSC0 and BSC2 must be specified and the upper and lower 8 bits manipulated separately. If the values of the L register are 0H at BSC0.@L, the address and bit location assignment is FC0H.0. If the L register content is FH at BSC0.@L, the address and bit location assignment is FC3H.3. Table 2-4. BSC Register Organization Name BSC0 BSC1 BSC2 BSC3 Address FC0H FC1H FC2H FC3H Bit 3 BSC0.3 BSC1.3 BSC2.3 BSC3.3 Bit 2 BSC0.2 BSC1.2 BSC2.2 BSC3.2 Bit 1 BSC0.1 BSC1.1 BSC2.1 BSC3.1 Bit 0 BSC0.0 BSC1.0 BSC2.0 BSC3.0
F
PROGRAMMING TIP -- Using the BSC Register to Output 16-Bit Data
To use the bit sequential carrier (BSC) register to output 16-bit data (5937H) to the P2.0 pin: BITS SMB LD LD LD LD SMB LD LDB LDB INCS JR RET EMB 15 EA,#37H BSC0,EA EA,#59H BSC2,EA 0 L,#0H C,BSC0.@L P2.0,C L AGN
; ; BSC0 A, BSC1 E ; ; BSC2 A, BSC3 E ; ; ; P2.0 C
AGN
2-16
S3C72Q5/P72Q5
ADDRESS SPACE
PROGRAM COUNTER (PC)
A 13-bit program counter (PC) stores addresses for instruction fetches during program execution. Whenever a reset operation or an interrupt occurs, bits PC12 through PC0 are set to the vector address. Usually, the PC is incremented by the number of bytes of the instruction being fetched. One exception is the 1-byte REF instruction which is used to reference instructions stored in the ROM.
PROGRAM STATUS WORD (PSW)
The program status word (PSW) is an 8-bit word that defines system status and program execution status and which permits an interrupted process to resume operation after an interrupt request has been serviced. PSW values are mapped as follows: FB0H FB1H IS1 C IS0 SC2 EMB SC1 ERB SC0
The PSW can be manipulated by 1-bit or 4-bit read/write and by 8-bit read instructions, depending on the specific bit or bits being addressed. The PSW can be addressed during program execution regardless of the current value of the enable memory bank (EMB) flag. Part or all of the PSW is saved to stack prior to execution of a subroutine call or hardware interrupt. After the interrupt has been processed, the PSW values are popped from the stack back to the PSW address. When a RESET is generated, the EMB and ERB values are set according to the RESET vector address, and the carry flag is left undefined (or the current value is retained). PSW bits IS0, IS1, SC0, SC1, and SC2 are all cleared to logic zero. Table 2-5. Program Status Word Bit Descriptions PSW Bit Identifier IS1, IS0 EMB ERB C SC2, SC1, SC0 Description Interrupt status flags Enable memory bank flag Enable register bank flag Carry flag Program skip flags Bit Addressing 1, 4 1 1 1 8 Read/Write R/W R/W R/W R/W R
2-17
ADDRESS SPACE
S3C72Q5/P72Q5
INTERRUPT STATUS FLAGS (IS0, IS1) PSW bits IS0 and IS1 contain the current interrupt execution status values. You can manipulate IS0 and IS1 flags directly using 1-bit RAM control instructions. By manipulating interrupt status flags in conjunction with the interrupt priority register (IPR), you can process multiple interrupts by anticipating the next interrupt in an execution sequence. The interrupt priority control circuit determines the IS0 and IS1 settings in order to control multiple interrupt processing. When both interrupt status flags are set to "0", all interrupts are allowed. The priority with which interrupts are processed is then determined by the IPR. When an interrupt occurs, IS0 and IS1 are pushed to the stack as part of the PSW and are automatically incremented to the next higher priority level. Then, when the interrupt service routine ends with an IRET instruction, IS0 and IS1 values are restored to the PSW. Table 2-6 shows the effects of IS0 and IS1 flag settings. Since interrupt status flags can be addressed by write instructions, programs can exert direct control over interrupt processing status. Before interrupt status flags can be addressed, however, you must first execute a DI instruction to inhibit additional interrupt routines. When the bit manipulation has been completed, execute an EI instruction to re-enable interrupt processing. Table 2-6. Interrupt Status Flag Bit Settings IS1 Value 0 0 1 1 IS0 Value 0 1 0 1 Status of Currently Executing Process 0 1 2 - Effect of IS0 and IS1 Settings on Interrupt Request Control All interrupt requests are serviced Only high-priority interrupt(s) as determined in the interrupt priority register (IPR) are serviced No more interrupt requests are serviced Not applicable; these bit settings are undefined
F
INTB
PROGRAMMING TIP -- Setting ISx Flags for Interrupt Processing
The following instruction sequence shows how to use the IS0 and IS1 flags to control interrupt processing: DI BITR BITS EI * * * IRET ; ; ; ; Disable interrupt IS1 0 Allow interrupts according to IPR priority level Enable interrupt
IS1 IS0
2-18
S3C72Q5/P72Q5
ADDRESS SPACE
EMB FLAG (EMB) The EMB flag is used to allocate specific address locations in the RAM by modifying the upper 4 bits of 12-bit data memory addresses. In this way, it controls the addressing mode for data memory banks. When the EMB flag is "0", the data memory address space is restricted to addresses 0F80H-0FFFH of data memory bank 15 and 000H-07FH of bank 0, regardless of the SMB register contents. When the EMB flag is set to "1", the addressing area of data memory is expanded and all of data memory space can be accessed by using the appropriate SMB value.
F
PROGRAMMING TIP -- Using the EMB Flag to Select Memory Banks
EMB flag settings for memory bank selection: 1. When EMB = "0": SMB LD LD LD SMB LD LD SMB LD LD 2. When EMB = "1": SMB LD LD LD SMB LD LD SMB LD LD 1 A,#9H 90H,A 34H,A 0 90H,A 34H,A 15 20H,A 90H,A ; Select memory bank 1 ; ; ; ; ; ; ; ; (190H) A, bank 1 is selected (134H) A, bank 1 is selected Select memory bank 0 (090H) A, bank 0 is selected (034H) A, bank 0 is selected Select memory bank 15 Program error, but assembler does not detect it (F90H) A, bank 15 is selected 1 A,#9H 90H,A 34H,A 0 90H,A 34H,A 15 20H,A 90H,A ; Non-essential instruction since EMB = "0" ; ; ; ; ; ; ; ; (F90H) A, bank 15 is selected (034H) A, bank 0 is selected Non-essential instruction since EMB = "0" (F90H) A, bank 15 is selected (034H) A, bank 0 is selected Non-essential instruction, since EMB = "0" (020H) A, bank 0 is selected (F90H) A, bank 15 is selected
2-19
ADDRESS SPACE
S3C72Q5/P72Q5
ERB FLAG (ERB) The 1-bit register bank enable flag (ERB) determines the range of addressable working register area. When the ERB flag is "1", the working register area from register banks 0 to 3 is selected according to the register bank selection register (SRB). When the ERB flag is "0", register bank 0 is the selected working register area, regardless of the current value of the register bank selection register (SRB). When an internal RESET is generated, bit 6 of program memory address 0000H is written to the ERB flag. This automatically initializes the flag. When a vectored interrupt is generated, bit 6 of the respective address table in program memory is written to the ERB flag, setting the correct flag status before the interrupt service routine is executed. During the interrupt routine, the ERB value is automatically pushed to the stack area along with the other PSW bits. Afterwards, it is popped back to the FB0H.0 bit location. The initial ERB flag settings for each vectored interrupt are defined using VENTn instructions.
F PROGRAMMING TIP -- Using the ERB Flag to Select Register Banks
ERB flag settings for register bank selection: 1. When ERB = "0": SRB LD LD SRB LD SRB LD 2. When ERB = "1": SRB LD LD SRB LD SRB LD 1 EA,#34H HL,EA 2 YZ,EA 3 WX,EA ; ; ; ; ; ; ; Register bank 1 is selected Bank 1 EA #34H Bank 1 HL Bank 1 EA Register bank 2 is selected Bank 2 YZ BANK2 EA Register bank 3 is selected Bank 3 WX Bank 3 EA 1 EA,#34H HL,EA 2 YZ,EA 3 WX,EA ; Register bank 0 is selected (since ERB = "0", the SRB is configured to bank 0) ; Bank 0 EA #34H ; Bank 0 HL EA ; Register bank 0 is selected ; Bank 0 YZ EA ; Register bank 0 is selected ; Bank 0 WX EA
2-20
S3C72Q5/P72Q5
ADDRESS SPACE
SKIP CONDITION FLAGS (SC2, SC1, SC0) The skip condition flags SC2, SC1, and SC0 indicate the current program skip conditions and are set and reset automatically during program execution. Skip condition flags can only be addressed by 8-bit read instructions. Direct manipulation of the SC2, SC1, and SC0 bits is not allowed. CARRY FLAG (C) The carry flag is used to save the result of an overflow or borrow when executing arithmetic instructions involving a carry (ADC, SBC). The carry flag can also be used as a 1-bit accumulator for performing Boolean operations involving bit-addressed data memory. If an overflow or borrow condition occurs when executing arithmetic instructions with carry (ADC, SBC), the carry flag is set to "1". Otherwise, its value is "0". When a RESET occurs, the current value of the carry flag is retained during power-down mode, but when normal operating mode resumes, its value is undefined. The carry flag can be directly manipulated by predefined set of 1-bit read/write instructions, independent of other bits in the PSW. Only the ADC and SBC instructions, and the instructions listed in Table 2-7, affect the carry flag. Table 2-7. Valid Carry Flag Manipulation Instructions Operation Type Direct manipulation SCF RCF CCF BTST C Bit transfer LDB (operand) (1),C LDB C,(operand) (1) Boolean manipulation BAND C,(operand) (1) BOR C,(operand) (1) BXOR C,(operand) (1) Interrupt routine Return from interrupt INTn (2) IRET Instructions Carry Flag Manipulation Set carry flag to "1" Clear carry flag to "0" (reset carry flag) Invert carry flag value (complement carry flag) Test carry and skip if C = "1" Load carry flag value to the specified bit Load contents of the specified bit to carry flag AND the specified bit with contents of carry flag and save the result to the carry flag OR the specified bit with contents of carry flag and save the result to the carry flag XOR the specified bit with contents of carry flag and save the result to the carry flag Save carry flag to stack with other PSW bits Restore carry flag from stack with other PSW bits
NOTES: 1. The operand has three bit addressing formats: mema.a, memb.@L, and @H + DA.b. 2. 'INTn' refers to the specific interrupt being executed and is not an instruction.
2-21
ADDRESS SPACE
S3C72Q5/P72Q5
F
1.
PROGRAMMING TIP -- Using the Carry Flag as a 1-Bit Accumulator Set the carry flag to logic one: SCF LD LD ADC EA,#0C3H HL,#0AAH EA,HL ; ; ; ; C 1 EA #0C3H HL #0AAH EA #0C3H + #0AAH + #1H, C 1
2.
Logical-AND bit 3 of address 3FH with P2.0 and output the result to P5.0: LD LDB BAND LDB H,#3H C,@H+0FH.3 C,P2.0 P5.0,C ; ; ; ; ; Set the upper four bits of the address to the H register value C bit 3 of 3FH C C AND P2.0 Output result from carry flag to P5.0
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S3C72Q5/P72Q5
ADDRESSING MODES
3
OVERVIEW
ADDRESSING MODES
The enable memory bank flag, EMB, controls the two addressing modes for data memory. When the EMB flag is set to logic one, you can address the entire RAM area; when the EMB flag is cleared to logic zero, the addressable area in the RAM is restricted to specific locations. The EMB flag works in connection with the select memory bank instruction, SMBn. You will recall that the SMBn instruction is used to select RAM bank 0, 1, or 15. The SMB setting is always contained in the upper four bits of a 12-bit RAM address. For this reason, both addressing modes (EMB = "0" and EMB = "1") apply specifically to the memory bank indicated by the SMB instruction, and any restrictions to the addressable area within banks 0, 1, or 15. Direct and indirect 1-bit, 4-bit, and 8-bit addressing methods can be used. Several RAM locations are addressable at all times, regardless of the current EMB flag setting. Here are a few guidelines to keep in mind regarding data memory addressing: -- When you address peripheral hardware locations in bank 15, the mnemonic for the memory-mapped hardware component can be used as the operand in place of the actual address location. -- Display RAM locations in bank 1 are 8-bit addressable only. -- Always use an even-numbered RAM address as the operand in 8-bit direct and indirect addressing. -- With direct addressing, use the RAM address as the instruction operand; with indirect addressing, the instruction specifies a register which contains the operand's address.
3-1
ADDRESSING MODES
S3C72Q5/P72Q5
RAM Areas 000H 01FH 020H 07FH 080H
Addressing Mode
DA DA.b EMB = 0 EMB = 1
@HL @H+DA.b EMB = 0 EMB = 1
@WX @WL X
mema.b X
memb.@L X
Working Registers
Bank 0 (General Registers and Stack)
SMB = 0
SMB = 0
0FFH 100H
Bank 1
SMB = 1
SMB = 1
1FFH F80H Bank 15 (Peripheral Hardware Registers) FB0H FBFH FC0H FF0H
SMB = 15
SMB = 15
FFFH
NOTES: 1. 'X' means don't care. 2. Blank columns indicate RAM areas that are not addressable, given the addressing method and enable memory bank (EMB) flag setting shown in the column headers.
Figure 3-1. RAM Address Structure
3-2
S3C72Q5/P72Q5
ADDRESSING MODES
EMB AND ERB INITIALIZATION VALUES The EMB and ERB flag bits are set automatically by the values of the RESET vector address and the interrupt vector address. When a RESET is generated internally, bit 7 of program memory address 0000H is written to the EMB flag, initializing it automatically. When a vectored interrupt is generated, bit 7 of the respective vector address table is written to the EMB. This automatically sets the EMB flag status for the interrupt service routine. When the interrupt is serviced, the EMB value is automatically saved to stack and then restored when the interrupt routine has completed. At the beginning of a program, the initial EMB and ERB flag values for each vectored interrupt must be set by using VENT instruction. The EMB and ERB can be set or reset by bit manipulation instructions (BITS, BITR) despite the current SMB setting.
F PROGRAMMING TIP - Initializing the EMB and ERB Flags
The following assembly instructions show how to initialize the EMB and ERB flag settings: ORG VENT0 VENT1 VENT2 VENT3 VENT4 VENT5 VENT6
* * *
0000H 1,0, RESET 0,1,INTB 0,1,INT0 0,1,INT1 0,1,INTP0 0,1,INTT0 0,1,INTT1
; ; ; ; ; ; ; ;
ROM address assignment EMB 1, ERB 0, branch RESET EMB 0, ERB 1, branch INTB EMB 0, ERB 1, branch INT0 EMB 0, ERB 1, branch INT1 EMB 0, ERB 1, branch INTP0 EMB 0, ERB 1, branch INTT0 EMB 0, ERB 1, branch INTT1
RESET
BITR
EMB
3-3
ADDRESSING MODES
S3C72Q5/P72Q5
ENABLE MEMORY BANK SETTINGS EMB = "1" When the enable memory bank flag EMB is set to logic one, you can address the data memory bank specified by the select memory bank (SMB) value (0, 1, or 15) using 1-, 4-, or 8-bit instructions. You can use both direct and indirect addressing modes. The addressable RAM areas when EMB = "1" are as follows: If SMB = 0, If SMB = 1, If SMB = 15, EMB = "0" When the enable memory bank flag EMB is set to logic zero, the addressable area is defined independently of the SMB value, and is restricted to specific locations depending on whether a direct or indirect address mode is used. If EMB = "0", the addressable area is restricted to locations 000H-07FH in bank 0 and to locations F80H-FFFH in bank 15 for direct addressing. For indirect addressing, only locations 000H-0FFH in bank 0 are addressable, regardless of SMB value. To address the peripheral hardware register (bank 15) using indirect addressing, the EMB flag must first be set to "1" and the SMB value to "15". When a RESET occurs, the EMB flag is set to the value contained in bit 7 of ROM address 0000H. EMB-Independent Addressing At any time, several areas of the data memory can be addressed independent of the current status of the EMB flag. These exceptions are described in Table 3-1. Table 3-1. RAM Addressing Not Affected by the EMB Value Address 000H-0FFH Addressing Method 4-bit indirect addressing using WX and WL register pairs; 8-bit indirect addressing using SP 1-bit direct addressing 1-bit indirect addressing using the L register Affected Hardware Not applicable LD LD PSW, SCMOD, IEx, IRQx, I/O I/O BITS BITR BTST BAND Program Examples A,@WX EA,SP EMB IE2 F3H.@L C,P3.@L 000H-0FFH 100H-1FFH F80H-FFFH
FB0H-FBFH FF0H-FFFH FC0H-FFFH
3-4
S3C72Q5/P72Q5
ADDRESSING MODES
SELECT BANK REGISTER (SB) The select bank register (SB) is used to assign the memory bank and register bank. The 8-bit SB register consists of the 4-bit select register bank register (SRB) and the 4-bit select memory bank register (SMB), as shown in Figure 3-2. During interrupts and subroutine calls, SB register contents can be saved to stack in 8-bit units by the PUSH SB instruction. You later restore the value to the SB using the POP SB instruction.
SMB SB Register SMB 3 SMB 2 SMB 1 SMB 0 0 0
SRB SRB 1 SRB 0
Figure 3-2. SMB and SRB Values in the SB Register
Select Register Bank (SRB) Instruction The select register bank (SRB) value specifies which register bank is to be used as a working register bank. The SRB value is set by the 'SRB n' instruction, where n = 0, 1, 2, 3. One of the four register banks is selected by the combination of ERB flag status and the SRB value that is set using the 'SRB n' instruction. The current SRB value is retained until another register is requested by program software. PUSH SB and POP SB instructions are used to save and restore the contents of SRB during interrupts and subroutine calls. RESET clears the 4-bit SRB value to logic zero. Select Memory Bank (SMB) Instruction To select one of the three available data memory banks, you must execute an SMB n instruction specifying the number of the memory bank you want (0, 1, or 15). For example, the instruction 'SMB 1' selects bank 1 and 'SMB 15' selects bank 15. (And remember to enable the selected memory bank by making the appropriate EMB flag setting). The upper four bits of the 12-bit data memory address are stored in the SMB register. If the SMB value is not specified by software (or if a RESET does not occur) the current value is retained. RESET clears the 4-bit SMB value to logic zero. The PUSH SB and POP SB instructions save and restore the contents of the SMB register to and from the stack area during interrupts and subroutine calls.
3-5
ADDRESSING MODES
S3C72Q5/P72Q5
DIRECT AND INDIRECT ADDRESSING
1-bit, 4-bit, and 8-bit data stored in data memory locations can be addressed directly using a specific register or bit address as the instruction operand. Indirect addressing specifies a memory location that contains the required direct address. The KS57 instruction set supports 1-bit, 4-bit, and 8-bit indirect addressing. For 8-bit indirect addressing, an even-numbered RAM address must always be used as the instruction operand.
1-BIT ADDRESSING Table 3-2. 1-Bit Direct and Indirect RAM Addressing Operand Notation Addressing Mode Description EMB Flag Setting Addressable Area 000H-07FH DA.b Direct: bit is indicated by the RAM address (DA), memory bank selection, and specified bit number (b). 0 F80H-FFFH Memory Bank Bank 0 Bank 15 Hardware I/O Mapping - All 1-bit addressable peripherals (SMB = 15)
1 mema.b Direct: bit is indicated by addressable area (mema) and bit number (b). Indirect: address is indicated by the upper 6 bits of RAM area (memb) and the upper 2 bits of register L, and bit is indicated by the lower 2 bits or register L. Indirect: bit is indicated by the lower four bits of the address (DA), memory bank selection, and the H register identifier. x
000H-FFFH FB0H-FBFH FF0H-FFFH FC0H-FFFH
SMB = 0, 1, 15 Bank 15 IS0, IS1, EMB, ERB, IEx, IRQx, Pn.m Pn.m
memb.@L
x
Bank 15
@H + DA.b
0
000H-0FFH
Bank 0
-
1
000H-FFFH
SMB = 0, 1, 15 All 1-bit addressable peripherals (SMB = 15)
NOTE: 'x' means don't care.
3-6
S3C72Q5/P72Q5
ADDRESSING MODES
F
1.
PROGRAMMING TIP -- 1-Bit Addressing Modes
1-Bit Direct Addressing If EMB = "0": EQU EQU EQU SMB BITS BITS BTST BITS BITS 34H.3 85H.3 0BAH.0 0 AFLAG BFLAG CFLAG BFLAG P2.0
AFLAG BFLAG CFLAG
; ; ; ; ;
34H.3 1 F85H.3 1 If FBAH.0 = 1, skip Else if, FBAH.0 = 0, F85H.3 1 FF2H.0 (P2.0) 1
2.
If EMB = "1": EQU EQU EQU SMB BITS BITS BTST BITS BITS 34H.3 85H.3 0BAH.0 0 AFLAG BFLAG CFLAG BFLAG P2.0
AFLAG BFLAG CFLAG
; ; ; ; ;
34H.3 1 85H.3 1 If 0BAH.0 = 1, skip Else if 0BAH.0 = 0, 085H.3 1 FF2H.0 (P2.0) 1
1-Bit Indirect Addressing 1. If EMB = "0": EQU EQU EQU SMB LD BTSTZ BITS 34H.3 85H.3 0BAH.0 0 H,#0BH @H+CFLAG CFLAG
AFLAG BFLAG CFLAG
; H #0BH ; If 0BAH.0 = 1, 0BAH.0 0 and skip ; Else if 0BAH.0 = 0, FBAH.0 1
2.
If EMB = "1": EQU EQU EQU SMB LD BTSTZ BITS 34H.3 85H.3 0BAH.0 0 H,#0BH @H+CFLAG CFLAG
AFLAG BFLAG CFLAG
; H #0BH ; If 0BAH.0 = 1, 0BAH.0 0 and skip ; Else if 0BAH.0 = 0, 0BAH.0 1
3-7
ADDRESSING MODES
S3C72Q5/P72Q5
4-BIT ADDRESSING Table 3-3. 4-Bit Direct and Indirect RAM Addressing Operand Notation Addressing Mode Description EMB Flag Setting Addressable Area 000H-07FH DA Direct: 4-bit address indicated by the RAM address (DA) and the memory bank selection 0 F80H-FFFH Memory Bank Bank 0 Bank 15 Hardware I/O Mapping - All 4-bit addressable peripherals (SMB = 15) -
1 @HL Indirect: 4-bit address indicated by the memory bank selection and register HL 0
000H-FFFH 000H-0FFH
SMB = 0, 1, 15 Bank 0
1
000H-FFFH
SMB = 0, 1, 15
All 4-bit addressable peripherals (SMB = 15) -
@WX @WL
Indirect: 4-bit address indicated by register WX Indirect: 4-bit address indicated by register WL
x x
000H-0FFH 000H-0FFH
Bank 0 Bank 0
NOTE: 'x' means don't care.
3-8
S3C72Q5/P72Q5
ADDRESSING MODES
F
1.
PROGRAMMING TIP - 4-Bit Addressing Modes
4-Bit Direct Addressing If EMB = "0": EQU EQU SMB LD SMB LD LD 46H 85H 15 A,P4 0 ADATA,A BDATA,A
ADATA BDATA
; ; ; ; ;
Non-essential instruction, since EMB = "0" A (P4) Non-essential instruction, since EMB = "0" (046H) A (F85H (BMOD)) A
2.
If EMB = "1": EQU EQU SMB LD SMB LD LD 46H 85H 15 A,P4 0 ADATA,A BDATA,A
ADATA BDATA
; A (P4) ; (046H) A ; (085H) A
4-Bit Indirect Addressing (Example 1) 1. If EMB = "0", compare bank 0 locations 040H-046H with bank 0 locations 060H-066H: EQU EQU SMB LD LD LD CPSE SRET DECS JR RET 46H 66H 1 HL,#BDATA WX,#ADATA A,@WL A,@HL L COMP
ADATA BDATA
; Non-essential instruction, since EMB = "0" ; A bank 0 (040H-046H) ; If bank 0 (060H-066H) = A, skip
COMP
2.
If EMB = "1", compare bank 0 locations 040H-046H to bank 1 locations 160H-166H: EQU EQU SMB LD LD LD CPSE SRET DECS JR RET 46H 66H 1 HL,#BDATA WX,#ADATA A,@WL A,@HL L COMP
ADATA BDATA
COMP
; A bank 0 (040H-046H) ; If bank 1 (160H-166H) = A, skip
3-9
ADDRESSING MODES
S3C72Q5/P72Q5
F
1.
PROGRAMMING TIP -- 4-Bit Addressing Modes (Continued)
4-Bit Indirect Addressing (Example 2) If EMB = "0", exchange bank 0 locations 040H-046H with bank 0 locations 060H-066H: EQU EQU SMB LD LD LD XCHD JR 46H 66H 1 HL,#BDATA WX,#ADATA A,@WL A,@HL TRANS
ADATA BDATA
; Non-essential instruction, since EMB = "0" ; A bank 0 (040H-046H) ; Bank 0 (060H-066H) A
TRANS
2.
If EMB = "1", exchange bank 0 locations 040H-046H to bank 1 locations 160H-166H: EQU EQU SMB LD LD LD XCHD JR 46H 66H 1 HL,#BDATA WX,#ADATA A,@WL A,@HL TRANS
ADATA BDATA
TRANS
; A bank 0 (040H-046H) ; Bank 1 (160H-166H) A
3-10
S3C72Q5/P72Q5
ADDRESSING MODES
8-BIT ADDRESSING Table 3-4. 8-Bit Direct and Indirect RAM Addressing Instruction Notation Addressing Mode Description EMB Flag Setting Addressable Area 000H-07FH DA Direct: 8-bit address indicated by the RAM address (DA = even number) and memory bank selection 0 F80H-FFFH Memory Bank Bank 0 Bank 15 Hardware I/O Mapping - All 8-bit addressable peripherals (SMB = 15)
1 @HL Indirect: the 8-bit address indicated by the memory bank selection and register HL; (the 4-bit L register value must be an even number) 0
000H-FFFH 000H-0FFH
SMB = 0, 1, 15 Bank 0 -
1
000H-FFFH
SMB = 0, 1, 15
All 8-bit addressable peripherals (SMB = 15)
3-11
ADDRESSING MODES
S3C72Q5/P72Q5
F PROGRAMMING TIP - 8-Bit Addressing Modes
8-Bit Direct Addressing 1. If EMB = "0": EQU EQU SMB LD SMB LD LD 46H 8CH 15 EA,P4 0 ADATA,EA BDATA,EA
ADATA BDATA
; Non-essential instruction, since EMB = "0" ; E (P5), A (P4) ; (046H) A, (047H) E ; (F8CH) A, (F8DH) E
2.
If EMB = "1": EQU EQU SMB LD SMB LD LD 46H 8CH 15 EA,P4 0 ADATA,EA BDATA,EA
ADATA BDATA
; E (P5), A (P4) ; (046H) A, (047H) E ; (08CH) A, (08DH) E
8-Bit Indirect Addressing 1. If EMB = "0": EQU SMB LD LD 46H 1 HL,#ADATA EA,@HL ; Non-essential instruction, since EMB = "0" ; A (046H), E (047H)
ADATA
2.
If EMB = "1": EQU SMB LD LD 46H 1 HL,#ADATA EA,@HL
ADATA
; A (146H), E (147H)
3-12
S3C72Q5/P72Q5
MEMORY MAP
4
OVERVIEW
MEMORY MAP
To support program control of peripheral hardware, I/O addresses for peripherals are memory-mapped to bank 15 of the RAM. Memory mapping lets you use a mnemonic as the operand of an instruction in place of the specific memory location. Access to bank 15 is controlled by the select memory bank (SMB) instruction and by the enable memory bank flag (EMB) setting. If the EMB flag is "0", bank 15 can be addressed using direct addressing, regardless of the current SMB value. 1-bit direct and indirect addressing can be used for specific locations in bank 15, regardless of the current EMB value. I/O MAP FOR HARDWARE REGISTERS Table 4-1 contains detailed information about I/O mapping for peripheral hardware in bank 15 (register locations F80H-FFFH). Use the I/O map as a quick-reference source when writing application programs. The I/O map gives you the following information: -- Register address -- Register name (mnemonic for program addressing) -- Bit values (both addressable and non-manipulable) -- Read-only, write-only, or read and write addressability -- 1-bit, 4-bit, or 8-bit data manipulation characteristics
4-1
MEMORY MAP
S3C72Q5/P72Q5
Table 4-1. I/O Map for Memory Bank 15 Addressing 1-bit direct addressing 4-bit direct addressing 8-bit direct addressing 4-bit indirect addressing 8-bit indirect addressing 1-bit manipulating addressing Symbol DA.b Description The bit indicated by memory bank, DA and bit. (EMB=0, or EMB=1 and SMB 15) The address indicated by memory bank and DA. (EMB=0, or EMB=1 and SMB 15) The address (DA specifies an even address) indicated by memory bank and DA. (EMB=0, or EMB=1 and SMB 15) The address indicated by memory bank and HL register. (EMB=1 and SMB 15) The address indicated by memory bank and HL (the contents of the L register are even). (EMB=1 and SMB 15) The bit indicated by mema and bit. (regardless of the status of EMB and SMB) Affected Memory mapped I/O All peripheral hardware that can be manipulated in 1 bit. All peripheral hardware that can be manipulated in 4 bits. All peripheral hardware that can be manipulated in 8 bits. All peripheral hardware that can be manipulated in 4 bits. All peripheral hardware that can be manipulated in 8 bit. IS0, IS1, EMB, ERB, IEx, IRQx, Pn.m
DA
DA
@HL
@HL
mema.b memb.@L
The bit indicated by the lower 2 bits of the L Pn.m register of the address indicated by the upper 10 bits of memb and the upper 2 bits of the L reigster. (regardless of the status of EMB and SMB) The bit of the address indicated by memory bank, H register and the lower 4 bits of DA. (EMB=1 and SMB=15) All peripheral hardware that can be manipulated in 1 bit.
@H+DA.b
4-2
S3C72Q5/P72Q5
MEMORY MAP
Table 4-2. I/O Map for Memory Bank 15 Memory Bank 15 Address F80H F81H Register SP Bit 3 .3 .7 Bit 2 .2 .6 Bit 1 .1 .5 Bit 0 "0" .4 R/W R/W Addressing Mode 1-Bit No 4-Bit No 8-Bit Yes
Locations F82H-F84H are not mapped. F85H F86H F87H F88H F89H F8AH F8BH F8CH F8DH F8EH F8FH F90H F91H F92H LCON0 LCON1 TMOD0 LMOD LCNST WMOD .3 .7 .3 .7 .3 "0" .3 .3 .3 "0" "0" .2 "0" .2 "0" .2 .6 .2 .2 .2 .6 TOE0 .1 .5 .1 "0" .1 .5 .1 .1 "0" .5 "0" .0 .4 .0 "0" .0 .4 .0 .0 "0" .4 "0" R/W Yes Yes No W W W No No .3 Yes Yes No No No Yes W No No Yes W No No Yes W .3 (1) No Yes BMOD BCNT .3 .2 .1 .0 W R .3 No Yes No No Yes
Location F93H is not mapped. F94H F95H F96H F97H F98H F99H F9AH WDFLAG (2) WDMOD .3 .7 WDTCF .2 .6 "0" .1 .5 "0" .0 .4 "0" W .3 Yes No W No No Yes TREF0 W No No Yes TCNT0 R No No Yes
Locations F9BH-F9FH are not mapped. FA0H FA1H FA2H FA3H FA4H FA5H KSR0 KSR1 KSR2 KSR3 PASR .3 "0" .3 .3 .3 .3 .2 "0" .2 .2 .2 .2 .1 "0" .1 .1 .1 .1 .0 .4 .0 .0 .0 .0 W No Yes No W No No Yes
4-3
MEMORY MAP
S3C72Q5/P72Q5
Table 4-2. I/O Map for Memory Bank 15 (Continued) Memory Bank 15 Address FA6H FA7H FA8H FA9H FAAH FABH Locations FACH-FAFH are not mapped. FB0H FB1H FB2H FB3H FB4H FB5H FB6H FB7H FB8H FBAH FBBH FBCH FBDH FBEH FBFH FC0H FC1H FC2H FC3H FCAH FCBH FCCH FCDH FCEH EMAR2 EMAR1 BSC0 BSC1 BSC2 BSC3 Locations FC4H-FC9H are not mapped. EMAR0 .3 .7 .3/.11 .7/.15 "0" .2 .6 .2/.10 .6/.14 .2/.18 .1 .5 .1/.9 .5/.13 .1/.17 .0 .4 .0/.8 .4/.12 .0/.16 R/W No Yes No R/W No No Yes IPR PCON IMOD0 IMOD1 IMOD2 SCMOD PSW IS1 C (3) IME .3 "0" "0" "0" .3 "0" "0" "0" "0" "0" IE1 "0" IS0 SC2 .2 .2 "0" "0" .2 .2 "0" "0" "0" "0" "0" IRQ1 "0" EMB SC1 .1 .1 .1 .1 .1 "0" IEB IEW IET1 IET0 IEP0 IE0 IE2 ERB SC0 .0 .0 .0 .0 .0 .0 IRQB IRQW IRQT1 IRQT0 IRQP0 IRQ0 IRQ2 R/W R W W W W W W R/W R/W R/W R/W R/W R/W R/W R/W Yes No IME No No No No Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes No Yes Yes Yes Yes Yes No Yes Yes Yes Yes Yes Yes Yes Yes No No No No No No No No No No No No No Yes Yes TREF1 W No No Yes TCNT1 Register TMOD1 Bit 3 .3 "0" Bit 2 .2 .6 Bit 1 "0" .5 Bit 0 "0" .4 R No No Yes R/W W .3 Addressing Mode 1-Bit 4-Bit No 8-Bit Yes
Location FB9H is not mapped.
Location FCFH is not mapped.
4-4
S3C72Q5/P72Q5
MEMORY MAP
Table 4-2. I/O Map for Memory Bank 15 (Continued) Memory Bank 15 Address FD0H Register CLMOD Bit 3 .3 Bit 2 "0" Bit 1 .1 Bit 0 .0 R/W W Addressing Mode 1-Bit No 4-Bit Yes 8-Bit No
Location FD1H is not mapped. FD2H FD3H FD4H FD5H EMDR0 EMCON .3 .7 .3 .7 .2 .6 .2 .6 .1 .5 .1 .5 .0 .4 .0 .4 R/W No No Yes W No No Yes
Locations FD6H-FE5H are not mapped. FE6H FE7H FE8H FE9H FEAH FEBH FECH FEDH FEEH FEFH FF0H FF1H Port0 (P0) Port1 (P1) PMG2 PMG1 PMG0 PUMOD0(6) PNE0(5) .3 .7 "0" PUR7 PM0.3 "0" PM4.3 PM5.3 PM6.3 PM7.3 .3 "0" .2 .6 "0" PUR6 PM0.2 PM1.2 PM4.2 PM5.2 PM6.2 PM7.2 .2 .2/.6 .1 .5 "0" PUR5 PM0.1 PM1.1 PM4.1 PM5.1 PM6.1 PM7.1 .1 .1/.5 .0 .4 PUR0 PUR4 PM0.0 PM1.0 PM4.0 PM5.0 PM6.0 PM7.0 .0 .0/.4 R/W Yes Yes Yes W No No Yes W No No Yes W No No Yes W No No Yes W No No Yes
Locations FF2H-FF3H are not mapped. FF4H FF5H FF6H FF7H Port4 (P4) Port5 (P5) Port6 (P6) Port7 (P7) .3 .3/.7 .3 .3/.7 .2 .2/.6 .2 .2/.6 .1 .1/.5 .1 .1/.5 .0 .0/.4 .0 .0/.4 R/W Yes Yes Yes R/W Yes Yes Yes
NOTES: 1. Bit 3 in the WMOD register is read only. 2. F9AH.0, F9AH.1 and F9AH.2 are fixed to "0". 3. The carry flag can be read or written by specific bit manipulation instructions only. 4. The PNE0 register is used to select the output types of ports 4,5 (zero: push-pull output type, one: open-drain output type). The reset value of the PNE1 register is "00H". 5. The PUMOD0 register is used to enable/disable the internal pull-up resistors of port 0, 1, 4, 5, 6 and 7 (zero: disable, one: enable). The reset value of the PUMOD0 register is "00H".
4-5
MEMORY MAP
S3C72Q5/P72Q5
REGISTER DESCRIPTIONS In this section, register descriptions are presented in a consistent format to familiarize you with the memory-mapped I/O locations in bank 15 of the RAM. Figure 4-1 describes features of the register description format. Register descriptions are arranged in alphabetical order. Programmers can use this section as a quick-reference source when writing application programs. Counter registers, buffer registers, and reference registers, as well as the stack pointer and port I/O latches, are not included in these descriptions. More detailed information about how these registers are used is included in Part II of this manual, "Hardware Descriptions," in the context of the corresponding peripheral hardware module descriptions.
4-6
S3C72Q5/P72Q5
MEMORY MAP
Register and bit IDs used for bit addressing Register ID Register name
Name of individual bit or related bits Associated hardware module Register location in RAM bank 15
CLMOD - Clock Output Mode Control Register
Bit Identifier RESET Value Read/Write Bit Addressing CLMOD.3 3 .3 0 W 4 2 .2 0 W 4 1 .1 0 W 4 0 .0 0 W 4
CPU
FD0H
Enable/Disable Clock Output Control bit 0 0 Disable clock output at the CLO pin Enable clock output at the CLO pin
CLMOD.2
Bit 2 0 Always logic zero
CLMOD.1-.0
Clock Source and Frequency Selection Control Bits 0 0 1 1 0 1 0 1 Select CPU clock souce fx/4, fx/8, fx/64 (1.05 MHz, 524kHz, or 65.5 kHz), or fxt/4 Select system clock fxx/8 (524 kHz at 4.19 MHz) Select system clock fxx/16 (262 kHz at 4.19 MHz) Select system clock fxx/64 (65.5 kHz at 4.19 MHz)
R = Read-only W = Write-only R/W = Read/write Type of addressing that must be used to address the bit (1-bit, 4-bit, or 8-bit)
Bit value immediately after a RESET
Bit number in MSB to LSB order
Description of the effect of specific bit settings
Bit identifier used for bit addressing
Figure 4-1. Register Description Format
4-7
MEMORY MAP
S3C72Q5/P72Q5
BMOD -- Basic Timer Mode Register
Bit Identifier RESET Value Read/Write Bit Addressing BMOD.3 3 .3 0 W 1/4 2 .2 0 W 4 1 .1 0 W 4 0 .0 0 W 4
BT
F85H
Basic Timer Restart Bit 1 Restart basic timer, then clear IRQB flag, BCNT and BMOD.3 to logic zero
BMOD.2-.0
Input Clock Frequency and Interrupt Interval Time 0 0 1 1 0 1 0 1 0 1 1 1 Input clock frequency: Interrupt interval time (wait time): Input clock frequency: Interrupt interval time (wait time): Input clock frequency: Interrupt interval time (wait time): Input clock frequency: Interrupt interval time (wait time): fxx/212 (1.02 kHz) 220/fxx (250 ms) fxx/29 (8.18 kHz) 217/fxx (31.3 ms) fxx/27 (32.7 kHz) 215/fxx (7.82 ms) fxx/25 (131 kHz) 213/fxx (1.95 ms)
NOTES: 1. When a RESET occurs, the oscillator stabilization wait time is 31.3 ms (217/fxx) at 4.19 MHz. 2. 'fxx' is the system clock frequency (assume that fxx is 4.19 MHz).
4-8
S3C72Q5/P72Q5
MEMORY MAP
CLMOD -- Clock Output Mode Register
Bit Identifier RESET Value Read/Write Bit Addressing CLMOD.3 3 .3 0 W 4 2 "0" 0 W 4 1 .1 0 W 4 0 .0 0 W 4
CPU
FD0H
Enable/Disable Clock Output Control Bit 0 1 Disable clock output at the CLO pin Enable clock output at the CLO pin
CLMOD.2
Bit 2 0 Always logic zero
CLMOD.1-.0
Clock Source and Frequency Selection Control Bits 0 0 1 1 0 1 0 1 Select CPU clock source fx/4, fx/8, or fx/64 (1 MHz, 524 kHz, or 65.5 kHz) or fxt/4 Select system clock fxx/8 (524 kHz) Select system clock fxx/16 (262 kHz) Select system clock fxx/64 (65.5 kHz)
NOTE:
'fxx' is the system clock, given a clock frequency of 4.19 MHz.
4-9
MEMORY MAP
S3C72Q5/P72Q5
EMCON -- External Memory Control Register
Bit Identifier RESET Value Read/Write Bit Addressing EMCON.7 7 .7 0 W 8 6 .6 0 W 8 5 .5 0 W 8 4 .4 0 W 8 3 .3 0 W 8
CPU
2 .2 0 W 8
FD3H, FD2H
1 .1 0 W 8 0 .0 0 R/W 8
Memory Read/Write Control Bit 0 Memory read signal output 1 Memory write signal output Memory Access Clock Selection Bits 0 0 fxx/8 0 1 fxx/4 1 0 fxx/2 1 1 fxx/1 Address Increment Control Bit 0 The address(a value of EMAR2 - EMAR0) is not increased automatically after memory access. 1 The address(a value of EMAR2 - EMAR0) is increased automatically after memory access. Memory Selection Bits .3 .2 .1 External data memory selection 0 0 0 Data memory 0(DM0 active) 0 0 1 Data memory 1(DM1 active) 0 1 0 Data memory 2(DM2 active) 0 1 1 Data memory 3(DM3 active) 1 0 0 Data memory 4(DM4 active) 1 0 1 Data memory 5(DM5 active) Memory Access Start Bit 0 Not busy (read) 1 Start a memory access (write), Busy (read)
EMCON.6-.5
EMCON.4
EMCON.3-.1
EMCON.0
NOTES: 1. When it reads data from a external memory, the data are written to the register EMDR0. 2. When it writes data to a external memory, the data to the register EMDR0 are written to a external memory. 3. The external memory selection pins of P6.0/DM0 - P7.1/DM5 should be set to push-pull output and the latches should be set to logic "1". 4. P7.1/DM5/COM11 is not used as DM5, when it is selected to COM. For using DM5, this pin is set to output High. (in this case, this DM signal is falling to low on access start.) 5. EMCON.0 is cleared automatically when memory access is finished.
4-10
S3C72Q5/P72Q5
MEMORY MAP
IE0, IRQ0 -- INT0 Interrupt Enable/Request Flags IE1, IRQ1 -- INT1 Interrupt Enable/Request Flags
Bit Identifier RESET Value Read/Write Bit Addressing IE1 3 IE1 0 R/W 1/4 2 IRQ1 0 R/W 1/4 1 IE0 0 R/W 1/4 0 IRQ0 0 R/W 1/4
CPU CPU
FBEH FBEH
INT1 Interrupt Enable Flag 0 1 Disable interrupt requests at the INT1 pin Enable interrupt requests at the INT1 pin
IRQ1
INT1 Interrupt Request Flag - Generate INT1 interrupt (This bit is set and cleared by hardware when rising or falling edge detected at INT1 pin.)
IE0
INT0 Interrupt Enable Flag 0 1 Disable interrupt requests at the INT0 pin Enable interrupt requests at the INT0 pin
IRQ0
INT0 Interrupt Request Flag - Generate INT0 interrupt (This bit is set and cleared automatically by hardware when rising or falling edge detected at INT0 pin.)
4-11
MEMORY MAP
S3C72Q5/P72Q5
IE2, IRQ2 -- INT2 Interrupt Enable/Request Flags
Bit Identifier RESET Value Read/Write Bit Addressing .3-.2 3 "U" U R/W 1/4 Bits 3-2 U This bit is undefined. 2 "U" U R/W 1/4 1 IE2 0 R/W 1/4 0 IRQ2 0 R/W 1/4
CPU
FBFH
IE2
INT2 Interrupt Enable Flag 0 1 Disable INT2 interrupt requests at the KS0-KS7 pins Enable INT2 interrupt requests at the KS0-KS7 pins
IRQ2
INT2 Interrupt Request Flag - Generate INT2 quasi-interrupt (This bit is set and is not cleared automatically by hardware when a falling edge is detected at one of the KS0-KS7 pins. Since INT2 is a quasi-interrupt, IRQ2 flag must be cleared by software.)
NOTE:
The "U" means a undefined register bit
4-12
S3C72Q5/P72Q5
MEMORY MAP
IEB, IRQB -- INTB Interrupt Enable/Request Flags
Bit Identifier RESET Value Read/Write Bit Addressing .3-.2 3 "U" U R/W 1/4 Bits 3-2 U This bit is undefined. 2 "U" U R/W 1/4 1 IEB 0 R/W 1/4 0 IRQB 0 R/W 1/4
CPU
FB8H
IEB
INTB Interrupt Enable Flag 0 1 Disable INTB interrupt requests Enable INTB interrupt requests
IRQB
INTB Interrupt Request Flag - Generate INTB interrupt (This bit is set and cleared automatically by hardware when reference interval signal received from basic timer.)
NOTE: The "U" means a undefined register bit.
4-13
MEMORY MAP
S3C72Q5/P72Q5
IEP0, IRQP0 -- INTP0 Interrupt Enable/Request Flags
Bit Identifier RESET Value Read/Write Bit Addressing .3-.2 3 "U" U R/W 1/4 Bits 3-2 U This bit is undefined. 2 "U" U R/W 1/4 1 IEP0 0 R/W 1/4 0 IRQP0 0 R/W 1/4
CPU
FBDH
IEP0
INTS Interrupt Enable Flag 0 1 Disable INTP0 interrupt requests Enable INTP0 interrupt requests
IRQP0
INTS Interrupt Request Flag - Generate INTP0 interrupt (This bit is set and cleared automatically by hardware when falling edge is detected at K0-K3 pin.)
NOTES: 1. The "U" means a undefined register bit. 2. To use INTP0 interrupt, P0 and P1 must be set to external interrupt pins by LMOD.6-LMOD.4, input mode by PMG0 and pull-up resistor enable by PUMOD0.
4-14
S3C72Q5/P72Q5
MEMORY MAP
IET0, IRQT0 -- INTT0 Interrupt Enable/Request Flags
Bit Identifier RESET Value Read/Write Bit Addressing .3-.2 3 "U" U R/W 1/4 Bits 3-2 U This bit is undefined. 2 "U" U R/W 1/4 1 IET0 0 R/W 1/4 0 IRQT0 0 R/W 1/4
CPU
FBCH
IET0
INTT0 Interrupt Enable Flag 0 1 Disable INTT0 interrupt requests Enable INTT0 interrupt requests
IRQT0
INTT1 Interrupt Request Flag - Generate INTT0 interrupt (This bit is set and cleared automatically by hardware when contents of TCNT0 and TREF0 registers match.)
NOTE:
The "U" means a undefined register bit.
4-15
MEMORY MAP
S3C72Q5/P72Q5
IET1, IRQT1 -- INTT1 Interrupt Enable/Request Flags
Bit Identifier RESET Value Read/Write Bit Addressing .3-.2 3 "U" U R/W 1/4 Bits 3-2 U This bit is undefined. 2 "U" U R/W 1/4 1 IET1 0 R/W 1/4 0 IRQT1 0 R/W 1/4
CPU
FBBH
IET1
INTT1 Interrupt Enable Flag 0 1 Disable INTT1 interrupt requests Enable INTT1 interrupt requests
IRQT1
INTT1 Interrupt Request Flag - Generate INTT1 interrupt (This bit is set and cleared automatically by hardware when contents of TCNT1 and TREF1 registers match.)
NOTE:
The "U" means a undefined register bit.
4-16
S3C72Q5/P72Q5
MEMORY MAP
IEW, IRQW -- INTW Interrupt Enable/Request Flags
Bit Identifier RESET Value Read/Write Bit Addressing .3-.2 3 "U" U R/W 1/4 Bits 3-2 U This bit is undefined. 2 "U" U R/W 1/4 1 IEW 0 R/W 1/4 0 IRQW 0 R/W 1/4
CPU
FBAH
IEW
INTW Interrupt Enable Flag 0 1 Disable INTW interrupt requests Enable INTW interrupt requests
IRQW
INTW Interrupt Request Flag - Generate INTW interrupt (This bit is set when the timer interval is set to 0.5 seconds or 3.91 milliseconds.)
NOTES: 1. Since INTW is a quasi-interrupt, the IRQW flag must be cleared by software. 2. The "U" means a undefined register bit.
4-17
MEMORY MAP
S3C72Q5/P72Q5
IMOD0 -- External Interrupt 0 (INT0) Mode Register
Bit Identifier RESET Value Read/Write Bit Addressing IMOD0.3-.2 3 "0" 0 W 4 Bits 3-2 0 Always logic zero 2 "0" 0 W 4 1 .1 0 W 4 0 .0 0 W 4
CPU
FB4H
IMOD0.1-.0
External Interrupt Mode Control Bits 0 0 1 1 0 1 0 1 Interrupt requests are triggered by a rising edge Interrupt requests are triggered by a falling edge Interrupt requests are triggered by both rising and falling edges Interrupt request flag (IRQ0) cannot be set to logic one
4-18
S3C72Q5/P72Q5
MEMORY MAP
IMOD1 -- External Interrupt 1 (INT1) Mode Register
Bit Identifier RESET Value Read/Write Bit Addressing IMOD1.3-.2 3 "0" 0 W 4 Bits 3-2 0 Always logic zero 2 "0" 0 W 4 1 .1 0 W 4 0 .0 0 W 4
CPU
FB5H
IMOD1.1-.0
External Interrupt Mode Control Bits 0 0 1 1 0 1 0 1 Interrupt requests are triggered by a rising edge Interrupt requests are triggered by a falling edge Interrupt requests are triggered by both rising and falling edges Interrupt request flag (IRQ1) cannot be set to logic one
4-19
MEMORY MAP
S3C72Q5/P72Q5
IMOD2 -- External Interrupt 2 (INT2) Mode Register
Bit Identifier RESET Value Read/Write Bit Addressing IMOD2.3 3 "0" 0 W 4 Bits 3 0 Always logic zero 2 .2 0 W 4 1 .1 0 W 4 0 .0 0 W 4
CPU
FB6H
IMOD2.2-.0
External Interrupt 2 Edge Detection Selection Bit 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Interrupt request at KS0-KS3 triggered by falling edge Interrupt request at KS0-KS4 triggered by falling edge Interrupt request at KS0-KS5 triggered by falling edge Interrupt request at KS0-KS6 triggered by falling edge Interrupt request at KS0-KS7 triggered by falling edge Not available
4-20
S3C72Q5/P72Q5
MEMORY MAP
IPR -- Interrupt Priority Register
Bit Identifier RESET Value Read/Write Bit Addressing IME 3 IME 0 W 1/4 2 .2 0 W 4 1 .1 0 W 4 0 .0 0 W 4
CPU
FB2H
Interrupt Master Enable Bit 0 1 Disable all interrupt processing Enable processing for all interrupt servi ce requests
IPR.2-.0
Interrupt Priority Register Setting IPR.2 0 0 0 0 1 1 1 1 IPR.1 0 0 1 1 0 0 1 1 IPR.0 0 1 0 1 0 1 0 1 Result of IPR Bit Setting Normal interrupt handling according to default priority settings Process INTB interrupt at highest priority Process INT0 interrupt at highest priority Process INT1 interrupt at highest priority Process INTP0 interrupt at highest priority Process INTT0 interrupt at highest priority Process INTT1 interrupt at highest priority Not available
4-21
MEMORY MAP
S3C72Q5/P72Q5
LCNST -- LCD Contrast Control Register
Bit Identifier RESET Value Read/Write Bit Addressing LCNST.7 7 .7 0 W 8 6 "0" 0 W 8 5 "0" 0 W 8 4 "0" 0 W 8 3 .3 0 W 8
LCD
2 .2 0 W 8
F8BH, F8AH
1 .1 0 W 8 0 .0 0 W 8
Enable/Disable LCD Contrast Control Bit 0 1 Disable LCD contrast control Enable LCD contrast control
LCNST.6-.4
Bits 6-4 0 Always logic zero
LCNST.3-.0
LCD Contrast Level Control Bits(16 steps) .3 0 0 0 .2 0 0 0 .1 0 0 1 * * * * 1 1 1 1 16/16 step (The brightest level) ****** .0 0 1 0 Step 1/16 step (The dimmest level) 2/16 step 3/16 step
NOTE:
VLCD = VDD x (1-(16-n)/48), where n = 0 - 15(At normal LCD dividing resistors).
4-22
S3C72Q5/P72Q5
MEMORY MAP
LCON0 -- LCD Output Control Register 0
Bit Identifier RESET Value Read/Write Bit Addressing LCON0.3-.2 3 .3 0 W 4 Bits3-2 0 0 1 1 0 1 0 1 1/9 duty(COM0-COM8 select) 1/10 duty(COM0-COM9 select) 1/11 duty(COM0-COM10 select) 1/12 duty(COM0-COM11 select) 2 .2 0 W 4 1 "0" 0 W 4 0 "0" 0 W 4
LCD
F8EH
LCON0.1-.0
Bits 1-0 0 Always logic zero
NOTES: 1. COM has priority over normal port in P7.3/COM9-P7.1/COM11. This means these port are assigned to COM pins regardless of the value of PMG2, when duty is selected to 1/10, 1/11, or 1/12 at LCON0. 2. The port used COM must be set to output to prevent LCD display distortion.
4-23
MEMORY MAP
S3C72Q5/P72Q5
LCON1 -- LCD Output Control Register 1
Bit Identifier RESET Value Read/Write Bit Addressing LCON1.3-.0 3 .3 0 W 4 Bits 3-0 0 0 1 1 1 0 0 0 0 0 1 1 LCD display on Dimming mode 2 .2 0 W 4 1 .1 0 W 4 0 .0 0 W 4
LCD
F8FH
Key check signal output with LCD display off
NOTES: 1. To turn off LCD display, you must set LCON1 to 9 not 0. 2. P8 can be used to normal output port, when LCD display is off. The value of P8 is determined by KSR0-KSR3 regardless of LMOD.0. (refer to P12-17)
4-24
S3C72Q5/P72Q5
MEMORY MAP
LMOD -- LCD Mode Register
Bit Identifier RESET Value Read/Write Bit Addressing LMOD.7 7 "0" 0 W 8 6 .6 0 W 8 5 .5 0 W 8 4 .4 0 W 8 3 .3 0 W 8
LCD
2 .2 0 W 8
F8DH, F8CH
1 .1 0 W 8 0 .0 0 W 8
Bit 7 0 Always logic zero External Interrupt (INTP0) Pins Selection Bits (1) 0 0 0 Interrupt request at K0 triggered by falling edge 0 0 1 Interrupt request at K0-K1 triggered by falling edge 0 1 0 Interrupt request at K0-K2 triggered by falling edge 0 1 1 Interrupt request at K0-K3 triggered by falling edge 1 0 0 Interrupt request at K0-K4 triggered by falling edge 1 0 1 Interrupt request at K0-K5 triggered by falling edge 1 1 0 Interrupt request at K0-K6 triggered by falling edge 1 1 1 Interrupt request flag (IRQP0) cannot be set to logic one Watch Timer Clock Selection Bits (2) .3 .2 When main system clock is selected as watch timer clock by WMOD.0 0 0 fx/128 0 1 fx/64 1 0 fx/32 1 1 fx/16 LCD Dividing Resistor Selection Bit 0 Normal LCD dividing resistors 1 Diminish LCD dividing resistors to strengthen LCD drive Key Strobe Signal Output Control Bit(SEG0/P8.0 - SEG15/P8.15) 0 Enable key strobe signal output 1 Disable key strobe signal output (3)
LMOD.6 - .4
LMOD.3 - .2
LMOD.1
LMOD. 0
NOTES: 1. The pins which are not selected as external interrupts(K0 - K6) can be used to normal I/O. To use external interrupts, corresponding pins must be set to input and pull-up enable mode. 2. LCD clock can be selected only when main clock(fx) is used as clock source of watch timer. When sub clock(fxt) is used as clock source of watch timer, LCD clock is always fw/48(1/9 duty), fw/44(1/10 duty), fw/40(1/11 duty), or fw/36(1/12 duty). 3. Refer to page 12-7.
4-25
MEMORY MAP
S3C72Q5/P72Q5
PASR -- Page Selection Register
Bit Identifier RESET Value Read/Write Bit Addressing PASR.7-.5 7 "0" 0 W 8 Bits 7-5 0 Always logic zero 6 "0" 0 W 8 5 "0" 0 W 8 4 .4 0 W 8 3 .3 0 W 8
MEMORY
2 .2 0 W 8 1 .1 0 W 8
A1H, FA0H
0 .0 0 W 8
PASR.4-.0
Page Selection Register in the Bank1 0 0 0 0 0 0
* * * * * ******
0 0
0 1
00H page in the Bank1 01H page in the Bank1
1
0
0
1
1
13H page for LCD display register in the Bank1
4-26
S3C72Q5/P72Q5
MEMORY MAP
PCON -- Power Control Register
Bit Identifier RESET Value Read/Write Bit Addressing PCON.3- .2 3 .3 0 W 4 2 .2 0 W 4 1 .1 0 W 4 0 .0 0 W 4
CPU
FB3H
CPU Operating Mode Control Bits 0 0 1 0 1 0 Enable normal CPU operating mode Initiate idle power-down mode Initiate stop power-down mode
PCON.1- .0
CPU Clock Frequency Selection Bits 0 1 1 0 0 1 If SCMOD.0 = "0", fx/64; if SCMOD.0 = "1", fxt/4 If SCMOD.0 = "0", fx/8; if SCMOD.0 = "1", fxt/4 If SCMOD.0 = "0", fx/4; if SCMOD.0 = "1", fxt/4
NOTE:
'fx' is the main system clock; 'fxt' is the subsystem clock.
4-27
MEMORY MAP
S3C72Q5/P72Q5
PMG0
-- PORT I/O MODE REGISTER 0 (Group 0: Port 0,1)
7 "0" 0 W 8 6 PM1.2 0 W 8 5 PM1.1 0 W 8 4 PM1.0 0 W 8 3 PM0.3 0 W 8
I/O
2 PM0.2 0 W 8
FEBH, FEAH
1 PM0.1 0 W 8 0 PM0.0 0 W 8
Bit Identifier RESET Value Read/Write Bit Addressing PMG0.7
Bit 7 0 Always logic zero P1.2 I/O Mode Selection Flag 0 Set P1.2 to input mode 1 Set P1.2 to output mode P1.1 I/O Mode Selection Flag 0 Set P1.1 to input mode 1 Set P1.1 to output mode P1.0 I/O Mode Selection Flag 0 Set P1.0 to input mode 1 Set P1.0 to output mode P0.3 I/O Mode Selection Flag 0 Set P0.3 to input mode 1 Set P0.3 to output mode P0.2 I/O Mode Selection Flag 0 Set P0.2 to input mode 1 Set P0.2 to output mode P0.1 I/O Mode Selection Flag 0 Set P0.1 to input mode 1 Set P0.1 to output mode P0.0 I/O Mode Selection Flag 0 Set P0.0 to input mode 1 Set P0.0 to output mode
PM1.2
PM1.1
PM1.0
PM0.3
PM0.2
PM0.1
PM0.0
NOTE:
To used INTP0 interrupt, P0 and P1 must be set to external interrupt pins by LMOD.6-LMOD.4, input mode by PMG0 and pull-up resistor enable by PUMOD0.
4-28
S3C72Q5/P72Q5
MEMORY MAP
PMG1 -- PORT I/O MODE REGISTER 1(Group 1: Port 4,5)
Bit Identifier RESET Value Read/Write Bit Addressing PM5.3 7 PM5.3 0 W 8 6 PM5.2 0 W 8 5 PM5.1 0 W 8 4 PM5.0 0 W 8 3 PM4.3 0 W 8
I/O
2 PM4.2 0 W 8
FEDH, FECH
1 PM4.1 0 W 8 0 PM4.0 0 W 8
P5.3 I/O Mode Selection Flag 0 1 Set P5.3 to input mode Set P5.3 to output mode
PM5.2
P5.2 I/O Mode Selection Flag 0 1 Set P5.2 to input mode Set P5.2 to output mode
PM5.1
P5.1 I/O Mode Selection Flag 0 1 Set P5.1 to input mode Set P5.1 to output mode
PM5.0
P5.0 I/O Mode Selection Flag 0 1 Set P5.0 to input mode Set P5.0 to output mode
PM4.3
P4.3 I/O Mode Selection Flag 0 1 Set P4.3 to input mode Set P4.3 to output mode
PM4.2
P4.2 I/O Mode Selection Flag 0 1 Set P4.2 to input mode Set P4.2 to output mode
PM4.1
P4.1 I/O Mode Selection Flag 0 1 Set P4.1 to input mode Set P4.1 to output mode
PM4.0
P4.0 I/O Mode Selection Flag 0 1 Set P4.0 to input mode Set P4.0 to output mode
4-29
MEMORY MAP
S3C72Q5/P72Q5
PMG2 -- Port I/O Mode Register 2 (Group 2: Port 6,7)
Bit Identifier RESET Value Read/Write Bit Addressing PM7.3 7 PM7.3 0 W 8 6 PM7.2 0 W 8 5 PM7.1 0 W 8 4 PM7.0 0 W 8 3 PM6.3 0 W 8
I/O
2 PM6.2 0 W 8
FEFH, FEEH
1 PM6.1 0 W 8 0 PM6.0 0 W 8
P7.3 I/O Mode Selection Flag 0 Set P7.3 to input mode 1 Set P7.3 to output mode P7.2 I/O Mode Selection Flag 0 Set P7.2 to input mode 1 Set P7.2 to output mode P7.1 I/O Mode Selection Flag 0 Set P7.1 to input mode 1 Set P7.1 to output mode P7.0 I/O Mode Selection Flag 0 Set P7.0 to input mode 1 Set P7.0 to output mode P6.3 I/O Mode Selection Flag 0 Set P6.3 to input mode 1 Set P6.3 to output mode P6.2 I/O Mode Selection Flag 0 Set P6.2 to input mode 1 Set P6.2 to output mode P6.1 I/O Mode Selection Flag 0 Set P6.1 to input mode 1 Set P6.1 to output mode P6.0 I/O Mode Selection Flag 0 Set P6.0 to input mode 1 Set P6.0 to output mode
COM has priority over normal port in P7.3/COM9-P7.1/COM11. This means these port are assigned to COM pins regardless of the value of PMG2, when duty is selected to 1/10, 1/11 or 1/12 at LCON0.
PM7.2
PM7.1
PM7.0
PM6.3
PM6.2
PM6.1
PM6.0
NOTE:
4-30
S3C72Q5/P72Q5
MEMORY MAP
PNE0 -- N-Channel Open-Drain Mode Register 0
Bit Identifier RESET Value Read/Write Bit Addressing PNE0.7 7 .7 0 W 8 6 .6 0 W 8 5 .5 0 W 8 4 .4 0 W 8 3 .3 0 W 8
I/O
2 .2 0 W 8
FE7H, FE6H
1 .1 0 W 8 0 .0 0 W 8
P5.3 N-Channel Open-Drain Configurable Bit 0 1 Configure P5.3 as a push-pull Configure P5.3 as a n-channel open-drain
PNE0.6
P5.2 N-Channel Open-Drain Configurable Bit 0 1 Configure P5.2 as a push-pull Configure P5.2 as a n-channel open-drain
PNE0.5
P5.1 N-Channel Open-Drain Configurable Bit 0 1 Configure P5.1 as a push-pull Configure P5.1 as a n-channel open-drain
PNE0.4
P5.0 N-Channel Open-Drain Configurable Bit 0 1 Configure P5.0 as a push-pull Configure P5.0 as a n-channel open-drain
PNE0.3
P4.3 N-Channel Open-Drain Configurable Bit 0 1 Configure P4.3 as a push-pull Configure P4.3 as a n-channel open-drain
PNE0.2
P4.2 N-Channel Open-Drain Configurable Bit 0 1 Configure P4.2 as a push-pull Configure P4.2 as a n-channel open-drain
PNE0.1
P4.1 N-Channel Open-Drain Configurable Bit 0 1 Configure P4.1 as a push-pull Configure P4.1 as a n-channel open-drain
PNE0.0
P4.0 N-Channel Open-Drain Configurable Bit 0 1 Configure P4.0 as a push-pull Configure P4.0 as a n-channel open-drain
4-31
MEMORY MAP
S3C72Q5/P72Q5
PSW -- Program Status Word
Bit Identifier RESET Value Read/Write Bit Addressing C 7 C
(1)
CPU
6 SC2 0 R 8 5 SC1 0 R 8 4 SC0 0 R 8 3 IS1 0 R/W 1/4/8 2 IS0 0 R/W 1/4/8
FB1H, FB0H
1 EMB 0 R/W 1/4/8 0 ERB 0 R/W 1/4/8
R/W
(2)
Carry Flag 0 1 No overflow or borrow condition exists An overflow or borrow condition does exist
SC2-SC0
Skip Condition Flags 0 1 No skip condition exists; no direct manipulation of these bits is allowed A skip condition exists; no direct manipulation of these bits is allowed
IS1, IS0
Interrupt Status Flags 0 0 1 1 0 1 0 1 Service all interrupt requests Service only the high-priority interrupt(s) as determined in the interrupt priority register (IPR) Do not service any more interrupt requests Undefined
EMB
Enable Data Memory Bank Flag 0 1 Restrict program access to data memory to bank 15 (F80H-FFFH) and to the locations 000H-07FH in the bank 0 only Enable full access to data memory banks 0, 1, and 15
ERB
Enable Register Bank Flag 0 1 Select register bank 0 as working register area Select register banks 0, 1, 2, or 3 as working register area in accordance with the select register bank (SRB) instruction operand
NOTES: 1. The value of the carry flag after a RESET occurs during normal operation is undefined. If a RESET occurs during power-down mode (IDLE or STOP), the current value of the carry flag is retained. 2. The carry flag can only be addressed by a specific set of 1-bit manipulation instructions. See Section 2 for detailed information.
4-32
S3C72Q5/P72Q5
MEMORY MAP
PUMOD0 -- Pull-Up Resistor Mode Register
Bit Identifier RESET Value Read/Write Bit Addressing PUR7 7 PUR7 0 W 8 6 PUR6 0 W 8 5 PUR5 0 W 8 4 PUR4 0 W 8 3 "0" 0 W 8
I/O
2 "0" 0 W 8
FE9H, FE8H
1 "0" 0 W 8 0 PUR0 0 W 8
Connect/Disconnect Port 7 Pull-Up Resistor Control Bit 0 1 Disconnect port 7 pull-up resistor Connect port 7 pull-up resistor
PUR6
Connect/Disconnect Port 6 Pull-Up Resistor Control Bit 0 1 Disconnect port 6 pull-up resistor Connect port 6 pull-up resistor
PUR5
Connect/Disconnect Port 5 Pull-Up Resistor Control Bit 0 1 Disconnect port 5 pull-up resistor Connect port 5 pull-up resistor
PUR4
Connect/Disconnect Port 4 Pull-Up Resistor Control Bit 0 1 Disconnect port 4 pull-up resistor Connect port 4 pull-up resistor
PUMOD0.3-.1
Bit 3-1 0 Always logic zero
PUR0
Connect/Disconnect Port 0,1 Pull-Up Resistor Control Bit 0 1 Disconnect port 0,1 pull-up resistor Connect port 0,1 pull-up resistor
NOTES: 1. If port is set to output mode, pull-up resistor is disabled automatically. 2. When P0, P1 are used to external interrupt pins, the pull-up resistors of input mode are determined by key strobe signal (refer to P12-7).
4-33
MEMORY MAP
S3C72Q5/P72Q5
SCMOD -- System Clock Mode Control Register
Bit Identifier RESET Value Read/Write Bit Addressing SCMOD.3 3 .3 0 W 1 Bit 3 0 1 Enable main system clock Disable main system clock 2 .2 0 W 1 1 "0" 0 W 1 0 .0 0 W 1
CPU
FB7H
SCMOD.2
Bit 2 0 1 Enable sub system clock Disable sub system clock
SCMOD.1
Bit 1 0 Always logic zero
SCMOD.0
Bit 0 0 1 Select main system clock Select sub system clock
NOTES: 1. Sub-oscillation goes into stop mode only by SCMOD.2. PCON which revokes stop mode cannot stop the suboscillation. 2. You can use SCMOD.2 as follows (ex; after data bank was used, a few minutes have passed): Main operation sub-operation sub-idle (LCD on, after a few minutes later without any external input) sub operation main operation SCMOD.2 = 1 main stop mode (LCD off). 3. SCMOD bit3-0 can not be modified simultaneously by a 4 -bit instruction; They can only be modified by separate 1-bit instructions.
4-34
S3C72Q5/P72Q5
MEMORY MAP
TMOD0 -- Timer/Counter 0 Mode Register
Bit Identifier RESET Value Read/Write Bit Addressing TMOD0.7 7 "0" 0 W 8 Bit 7 0 Always logic zero 6 .6 0 W 8 5 .5 0 W 8 4 .4 0 W 8 3 .3 0 w 1/8
T/C0
2 .2 0 W 8
F90H, F91H
1 "0" 0 W 8 0 "0" 0 W 8
TMOD0.6-.4
Timer/Counter0 Input Clock Selection Bits (1) (2) 0 0 0 1 1 1 1 0 0 1 0 0 1 1 0 1 x 0 1 0 1 External clock input at TCL0 pin on rising edge External clock input at TCL0 pin on falling edge fxt(Subsystem clock: 32.768 kHz) fxx /210 (4.09 kHz) fxx/26 (65.5 kHz) fxx/24 (262kHz) fxx (4.19 MHz)
TMOD0.3
Clear Counter And Resume Counting Control Bit 1 Clear TCNT0, IRQT0, and TOL0 and resume counting immediately.(This bit is cleared automatically when counting starts)
TMOD0.2
Enable/Disable Timer/Counter0 Bit 0 1 Disable timer/counter0 ; retain TCNT0 contents Enable timer/counter0
TMOD0.1
Bit 1 0 Always logic zero
TMOD0.0
Bit 0 0 Always logic zero
NOTES: 1. 'fxx' is the system clock frequency (assume that fxx is 4.19MHz). 2. x is dont care.
4-35
MEMORY MAP
S3C72Q5/P72Q5
TMOD1 -- Timer/Counter 1 Mode Register
Bit Identifier RESET Value Read/Write Bit Addressing TMOD1.7 7 "0" 0 W 8 Bit 7 0 Always logic zero 6 .6 0 W 8 5 .5 0 W 8 4 .4 0 W 8 3 .3 0 W 1/8
T/C1
2 .2 0 W 8
FA7H, FA6H
1 "0" 0 W 8 0 "0" 0 W 8
TMOD1.6-.4
Timer/Counter1 Input Clock Selection Bits (1) (2) 0 1 1 1 1 1 0 0 1 1 x 0 1 0 1 fxt(Subsystem clock: 32.768 kHz) fxx /210 (4.09 kHz) fxx/26 (65.5 kHz) fxx/24 (262kHz) fxx (4.19 MHz)
TMOD1.3
Clear Counter And Resume Counting Control Bit 1 Clear TCNT1 and IRQT1 and resume counting immediately.(This bit is cleared automatically when counting starts)
TMOD1.2
Enable/Disable Timer/Counter1 Bit 0 1 Disable timer/counter1 ; retain TCNT1 contents Enable timer/counter1
TMOD1.1
Bit 1 0 Always logic zero
TMOD1.0
Bit 0 0 Always logic zero
NOTES: 1. 'fxx' is the system clock frequency (assume that fxx is 4.19MHz). 2. x is dont care.
4-36
S3C72Q5/P72Q5
MEMORY MAP
TOE0 -- Timer/Output Enable Flag Register
Bit Identifier RESET Value Read/Write Bit Addressing .3 3 "0" 0 R/W 1/4 Bit 3 0 Always logic zero 2 TOE0 0 R/W 1/4 1 "0" 0 R/W 1/4 0 "0" 0 R/W 1/4
T/C0
F92H
TOE0
Clear Counter And Resume Counting Control Bit 0 1 Disable timer/counter 0 clock output at the TCLO0 pin Enable timer/counter 0 clock output at the TCLO0 pin
.1-.0
Bit 1-0 0 Always logic zero
4-37
MEMORY MAP
S3C72Q5/P72Q5
WDFLAG -- Watch-Dog Timer's Counter Clear Flag
Bit Identifier RESET Value Read/Write Bit Addressing WDTCF 3 WDTCF 0 W 1/4 2 "0" 0 W 1/4 1 "0" 0 W 1/4 0 "0" 0 W 1/4
BT
F9AH.3
Watch-dog Timer's Counter Clear Bit 0 1 - Clear the WDT's counter to zero and restart the WDT's counter
WDFLAG.2-.0
Bit 2-0 0 Always logic zero
4-38
S3C72Q5/P72Q5
MEMORY MAP
WDMOD -- Watch-Dog Timer Mode Control Register
Bit Identifier RESET Value Read/Write Bit Addressing WDMOD.7-.0 7 .7 1 W 8 6 .6 0 W 8 5 .5 1 W 8 4 .4 0 W 8 3 .3 0 W 8
BT
2 .2 1 W 8
F99H, F98H
1 .1 0 W 8 0 .0 1 W 8
Watch-Dog Timer Enable/Disable Control 0 1 0 1 1 0 1 0 Disable watch-dog timer function Enable watch-dog timer function
Other Values
4-39
MEMORY MAP
S3C72Q5/P72Q5
WMOD -- Watch Timer Mode Register
Bit Identifier RESET Value Read/Write Bit Addressing WMOD.7 7 .7 0 W 8 6 .6 0 W 8 5 .5 0 W 8 4 .4 0 W 8 3 .3
(note)
WT
2 .2 0 W 8
F89H, F88H
1 .1 0 W 8 0 .0 0 W 8
R 1
Enable/Disable Buzzer Output Bit 0 1 Disable buzzer (BUZ) signal output at the BUZ pin Enable buzzer (BUZ) signal output at the BUZ pin
WMOD.6
Bit 6 0 Always logic zero
WMOD.5-.4
Output Buzzer Frequency Selection Bits 0 0 1 1 0 1 0 1 2 kHz buzzer (BUZ) signal output 4 kHz buzzer (BUZ) signal output 8 kHz buzzer (BUZ) signal output 16 kHz buzzer (BUZ) signal output
WMOD.3
XTINInput Level Control Bit 0 1 Input level to XT IN pin is low; 1-bit read-only addressable for tests Input level to XT IN pin is high; 1-bit read-only addressable for tests
WMOD.2
Enable/Disable Watch Timer Bit 0 1 Disable watch timer and clear frequency dividing circuits Enable watch timer
WMOD.1
Watch Timer Speed Control Bit 0 1 Normal speed: Set IRQW to 0.5 seconds High-speed operation: Set IRQW to 3.91 ms
WMOD.0
Watch Timer Clock Selection Bit 0 1 Select main system clock(fx)/128 as the watch timer clock Select main system clock (fx) as a LCD clock source. Select a subsystem clock as the watch timer clock Select a subsystem clock as a LCD clock source.
NOTE:
RESET sets WMOD.3 to the current input level of the subsystem clock, XTIN. If the input level is high, WMOD.3 is set to logic one; if low, WMOD.3 is cleared to zero along with all the other bits in the WMOD register
4-40
S3C72Q5/P72Q5
SAM48 INSTRUCTION SET
5
OVERVIEW
SAM48 INSTRUCTION SET
The SAM48 instruction set is specifically designed to support the large register files typically founded in most S3C7series microcontrollers. The SAM48 instruction set includes 1-bit, 4-bit, and 8-bit instructions for data manipulation, logical and arithmetic operations, program control, and CPU control. I/O instructions for peripheral hardware devices are flexible and easy to use. Symbolic hardware names can be substituted as the instruction operand in place of the actual address. Other important features of the SAM48 instruction set include: -- 1-byte referencing of long instructions (REF instruction) -- Redundant instruction reduction (string effect) -- Skip feature for ADC and SBC instructions Instruction operands conform to the operand format defined for each instruction. Several instructions have multiple operand formats. Predefined values or labels can be used as instruction operands when addressing immediate data. Many of the symbols for specific registers and flags may also be substituted as labels for operations such DA, mema, memb, b, and so on. Using instruction labels can greatly simplify programming and debugging tasks.
INSTRUCTION SET FEATURES
In this section, the following SAM48 instruction set features are described in detail: -- Instruction reference area -- Instruction redundancy reduction -- Flexible bit manipulation -- ADC and SBC instruction skip condition
NOTES: 1. The ROM size accessed by instruction may change for different devices in the SAM48 product family (JP, JPS, CALL, and CALLS). 2. The number of memory bank selected by SMB may change for different devices in the SAM48 product family. 3. The port names used in the instruction set may change for different devices in the SAM48 product family. 4. The interrupt names and the interrupt numbers used in the instruction set may change for different devices in the SAM 48 product family.
5-1
SAM48 INSTRUCTION SET
S3C72Q5/P72Q5
INSTRUCTION REFERENCE AREA Using the 1-byte REF (Reference) instruction, you can reference instructions stored in addresses 0020H-007FH of program memory (the REF instruction look-up table). The location referenced by REF may contain either two 1-byte instructions or a single 2-byte instruction. The starting address of the instruction being referenced must always be an even number. 3-byte instructions such as JP or CALL may also be referenced using REF. To reference these 3-byte instructions, the 2-byte pseudo commands TJP and TCALL must be written in the reference. The PC is not incremented when a REF instruction is executed. After it executes, the program's instruction execution sequence resumes at the address immediately following the REF instruction. By using REF instructions to execute instructions larger than one byte, as well as branches and subroutines, you can reduce the program size. To summarize, the REF instruction can be used in three ways: -- Using the 1-byte REF instruction to execute one 2-byte or two 1-byte instructions; -- Branching to any location by referencing a branch address that is stored in the look-up table; -- Calling subroutines at any location by referencing a call address that is stored in the look-up table. If necessary, a REF instruction can be circumvented by means of a skip operation prior to the REF in the execution sequence. In addition, the instruction immediately following a REF can also be skipped by using an appropriate reference instruction or instructions. Two-byte instruction can be referenced by using a REF instruction (An exception is XCH A, DA). If the MSB value of the first one-byte instruction in the reference area is "0", the instruction cannot be referenced by a REF instruction. Therefore, if you use REF to reference two 1-byte instruction stored in the reference area, specific combinations must be used for the first and second 1-byte instruction. These combination examples are described in Table 5-1. Table 5-1. Valid 1-Byte Instruction Combinations for REF Look-Ups First 1-Byte Instruction Instruction LD Operand A, #im Second 1-Byte Instruction Instruction INCS (note) INCS DECS (note) LD A, @RRa INCS (note) INCS DECS (note) LD @HL, A INCS (note) INCS DECS (note)
NOTE: The MSB value of the instruction is "0".
Operand R RRb R R RRb R R RRb R
5-2
S3C72Q5/P72Q5
SAM48 INSTRUCTION SET
REDUCING INSTRUCTION REDUNDANCY When redundant instructions such as LD A,#im and LD EA,#imm are used consecutively in a program sequence, only the first instruction is executed. The redundant instructions which follow are ignored, that is, they are handled like a NOP instruction. When LD HL,#imm instructions are used consecutively, redundant instructions are also ignored. In the following example, only the 'LD A, #im' instruction will be executed. The 8-bit load instruction which follows it is interpreted as redundant and is ignored: LD LD A,#im EA,#imm ; Load 4-bit immediate data (#im) to accumulator ; Load 8-bit immediate data (#imm) to extended accumulator
In this example, the statements 'LD A,#2H' and 'LD A,#3H' are ignored: BITR LD LD LD LD EMB A,#1H A,#2H A,#3H 23H,A
; ; ; ;
Execute instruction Ignore, redundant instruction Ignore, redundant instruction Execute instruction, 023H #1H
If consecutive LD HL, #imm instructions (load 8-bit immediate data to the 8-bit memory pointer pair, HL) are detected, only the first LD is executed and the LDs which immediately follow are ignored. For example, LD LD LD LD LD HL,#10H HL,#20H A,#3H EA,#35H @HL,A ; ; ; ; ; HL 10H Ignore, redundant instruction A 3H Ignore, redundant instruction (10H) 3H
If an instruction reference with a REF instruction has a redundancy effect, the following conditions apply: -- If the instruction preceding the REF has a redundancy effect, this effect is cancelled and the referenced instruction is not skipped. -- If the instruction following the REF has a redundancy effect, the instruction following the REF is skipped.
F
ABC
PROGRAMMING TIP -- Example of the Instruction Redundancy Effect ORG LD ORG * * * LD REF * * * REF LD 0020H EA,#30H 0080H
; Stored in REF instruction reference area
EA,#40H ABC
; Redundancy effect is encountered ; No skip (EA #30H)
ABC EA,#50H
; EA #30H ; Skip
5-3
SAM48 INSTRUCTION SET
S3C72Q5/P72Q5
FLEXIBLE BIT MANIPULATION In addition to normal bit manipulation instructions like set and clear, the SAM48 instruction set can also perform bit tests, bit transfers, and bit Boolean operations. Bits can also be addressed and manipulated by special bit addressing modes. Three types of bit addressing are supported: -- mema.b -- memb.@L -- @H+DA.b The parameters of these bit addressing modes are described in more detail in Table 5-2. Table 5-2. Bit Addressing Modes and Parameters Addressing Mode mema.b Addressable Peripherals ERB, EMB, IS1, IS0, IEx, IRQx Ports memb.@L @H+DA.b
NOTE:
Address Range FB0H-FBFH FF0H-FFFH FC0H-FFFH All bits of the memory bank specified by EMB and SMB that are bit-manipulatable
Ports, and BSC All bit-manipulatable peripheral hardware
Some device in the SAM48 product family don't have BSC.
INSTRUCTIONS WHICH HAVE SKIP CONDITIONS The following instructions have a skip function when an overflow or borrow occurs: XCHI XCHD LDI LDD INCS DECS ADS SBS
If there is an overflow or borrow from the result of an increment or decrement, a skip signal is generated and a skip is executed. However, the carry flag value is unaffected. The instructions BTST, BTSF, and CPSE also generate a skip signal and execute a skip when they meet a skip condition, and the carry flag value is also unaffected. INSTRUCTIONS WHICH AFFECT THE CARRY FLAG The only instructions which do not generate a skip signal, but which do affect the carry flag are as follows: ADC SBC SCF RCF CCF RRC LDB BAND BOR BXOR IRET C,(operand) C,(operand) C,(operand) C,(operand)
5-4
S3C72Q5/P72Q5
SAM48 INSTRUCTION SET
ADC AND SBC INSTRUCTION SKIP CONDITIONS The instructions 'ADC A,@HL' and 'SBC A,@HL' can generate a skip signal, and set or clear the carry flag, when they are executed in combination with the instruction 'ADS A,#im'. If an 'ADS A,#im' instruction immediately follows an 'ADC A,@HL' or 'SBC A,@HL' instruction in a program sequence, the ADS instruction does not skip the instruction following it, even if it has a skip function. If, however, an 'ADC A,@HL' or 'SBC A,@HL' instruction is immediately followed by an 'ADS A,#im' instruction, the ADC (or SBC) skips on overflow (or if there is no borrow) to the instruction immediately following the ADS, and program execution continues. Table 5-3 contains additional information and examples of the 'ADC A,@HL' and 'SBC A,@HL' skip feature. Table 5-3. Skip Conditions for ADC and SBC Instructions Sample Instruction Sequences ADC A,@HL ADS A,#im xxx xxx SBC A,@HL ADS A,#im xxx xxx 1 2 3 4 1 2 3 4 If the result of instruction 1 is: Overflow No overflow Borrow No borrow Then, the execution sequence is: 1, 3, 4 1, 2, 3, 4 1, 2, 3, 4 1, 3, 4 Reason ADS cannot skip instruction 3, even if it has a skip function. ADS cannot skip instruction 3, even if it has a skip function.
5-5
SAM48 INSTRUCTION SET
S3C72Q5/P72Q5
SYMBOLS AND CONVENTIONS
Table 5-4. Data Type Symbols Symbol d a b r f i t Data Type Immediate data Address data Bit data Register data Flag data Indirect addressing data memc x 0.5 immediate data Table 5-5. Register Identifiers Full Register Name 4-bit accumulator 4-bit working registers 8-bit extended accumulator 8-bit memory pointer 8-bit working registers Select register bank 'n' Select memory bank 'n' Carry flag Program status word Port 'n' 'm'-th bit of port 'n' Interrupt priority register Enable memory bank flag Enable register bank flag A E, L, H, X, W, Z, Y EA HL WX, YZ, WL SRB n SMB n C PSW Pn Pn.m IPR EMB ERB SB XOR OR AND [(RR)] ID Table 5-6. Instruction Operand Notation Symbol DA @ src dst (R) .b im imm # ADR ADRn R Ra RR RRa RRb RRc mema memb memc Definition Direct address Indirect address prefix Source operand Destination operand Contents of register R Bit location 4-bit immediate data (number) 8-bit immediate data (number) Immediate data prefix 000H-3FFFH immediate address 'n' bit address A, E, L, H, X, W, Z, Y E, L, H, X, W, Z, Y EA, HL, WX, YZ HL, WX, WL HL, WX, YZ WX, WL FB0H-FBFH, FF0H-FFFH FC0H-FFFH Code direct addressing: 0020H-007FH Select bank register (8 bits) Logical exclusive-OR Logical OR Logical AND Contents addressed by RR
5-6
S3C72Q5/P72Q5
SAM48 INSTRUCTION SET
OPCODE DEFINITIONS
Table 5-7. Opcode Definitions (Direct) Register A E L H X W Z Y EA HL WX YZ r2 0 0 0 0 1 1 1 1 0 0 1 1 r1 0 0 1 1 0 0 1 1 0 1 0 1 r0 0 1 0 1 0 1 0 1 0 0 0 0 Table 5-8. Opcode Definitions (Indirect) Register @HL @WX @WL i2 1 1 1 i1 0 1 1 i0 1 0 1
i = Immediate data for indirect addressing
r = Immediate data for register
CALCULATING ADDITIONAL MACHINE CYCLES FOR SKIPS
A machine cycle is defined as one cycle of the selected CPU clock. Three different clock rates can be selected using the PCON register. In this document, the letter 'S' is used in tables when describing the number of additional machine cycles required for an instruction to execute, given that the instruction has a skip function ('S' = skip). The addition number of machine cycles that will be required to perform the skip usually depends on the size of the instruction being skipped -- whether it is a 1-byte, 2-byte, or 3-byte instruction. A skip is also executed for SMB and SRB instructions. The values in additional machine cycles for 'S' for the three cases in which skip conditions occur are as follows: Case 1: No skip Case 2: Skip is 1-byte or 2-byte instruction Case 3: Skip is 3-byte instruction
NOTE:
S = 0 cycles S = 1 cycle S = 2 cycles
REF instructions are skipped in one machine cycle.
5-7
SAM48 INSTRUCTION SET
S3C72Q5/P72Q5
HIGH-LEVEL SUMMARY
This section contains a high-level summary of the SAM48 instruction set in table format. The tables are designed to familiarize you with the range of instructions that are available in each instruction category. These tables are a useful quick-reference resource when writing application programs. If you are reading this user's manual for the first time, however, you may want to scan this detailed information briefly, and then return to it later on. The following information is provided for each instruction: -- Instruction name -- Operand(s) -- Brief operation description -- Number of bytes of the instruction and operand(s) -- Number of machine cycles required to execute the instruction The tables in this section are arranged according to the following instruction categories: -- CPU control instructions -- Program control instructions -- Data transfer instructions -- Logic instructions -- Arithmetic instructions -- Bit manipulation instructions
5-8
S3C72Q5/P72Q5
SAM48 INSTRUCTION SET
Table 5-9. CPU Control Instructions -- High-Level Summary Name SCF RCF CCF EI DI IDLE STOP NOP SMB SRB REF VENTn n n memc EMB (0,1) ERB (0,1) ADR Operand - Operation Description Set carry flag to logic one Reset carry flag to logic zero Complement carry flag Enable all interrupts Disable all interrupts Engage CPU idle mode Engage CPU stop mode No operation Select memory bank Select register bank Reference code Load enable memory bank flag (EMB) and the enable register bank flag (ERB) and program counter to vector address, then branch to the corresponding location Bytes 1 1 1 2 2 2 2 1 2 2 1 2 Cycles 1 1 1 2 2 2 2 1 2 2 1 2
Table 5-10. Program Control Instructions -- High-Level Summary Name CPSE Operand R,#im @HL,#im A,R A,@HL EA,@HL EA,RR JP JPS JR ADR ADR #im @WX @EA CALL CALLS RET IRET SRET ADR ADR - - - Operation Description Compare and skip if register equals #im Compare and skip if indirect data memory equals #im Compare and skip if A equals R Compare and skip if A equals indirect data memory Compare and skip if EA equals indirect data memory Compare and skip if EA equals RR Jump to direct address (14 bits) Jump direct in page (12 bits) Jump to immediate address Branch relative to WX register Branch relative to EA Call direct in page (14 bits) Call direct in page (11 bits) Return from subroutine Return from interrupt Return from subroutine and skip Bytes 2 2 2 1 2 2 3 2 1 2 2 3 2 1 1 1 Cycles 2+S 2+S 2+S 1+S 2+S 2+S 3 2 2 3 3 4 3 3 3 3+S
5-9
SAM48 INSTRUCTION SET
S3C72Q5/P72Q5
Table 5-11. Data Transfer Instructions -- High-Level Summary Name XCH Operand A,DA A,Ra A,@RRa EA,DA EA,RRb EA,@HL XCHI XCHD LD A,@HL A,@HL A,#im A,@RRa A,DA A,Ra Ra,#im RR,#imm DA,A Ra,A EA,@HL EA,DA EA,RRb @HL,A DA,EA RRb,EA @HL,EA LDI LDD LDC RRC PUSH POP A,@HL A,@HL EA,@WX EA,@EA A RR SB RR SB Operation Description Exchange A and direct data memory contents Exchange A and register (Ra) contents Exchange A and indirect data memory Exchange EA and direct data memory contents Exchange EA and register pair (RRb) contents Exchange EA and indirect data memory contents Exchange A and indirect data memory contents; increment contents of register L and skip on carry Exchange A and indirect data memory contents; decrement contents of register L and skip on carry Load 4-bit immediate data to A Load indirect data memory contents to A Load direct data memory contents to A Load register contents to A Load 4-bit immediate data to register Load 8-bit immediate data to register Load contents of A to direct data memory Load contents of A to register Load indirect data memory contents to EA Load direct data memory contents to EA Load register contents to EA Load contents of A to indirect data memory Load contents of EA to data memory Load contents of EA to register Load contents of EA to indirect data memory Load indirect data memory to A; increment register L contents and skip on carry Load indirect data memory contents to A; decrement register L contents and skip on carry Load code byte from WX to EA Load code byte from EA to EA Rotate right through carry bit Push register pair onto stack Push SMB and SRB values onto stack Pop to register pair from stack Pop SMB and SRB values from stack Bytes 2 1 1 2 2 2 1 1 1 1 2 2 2 2 2 2 2 2 2 1 2 2 2 1 1 1 1 1 1 2 1 2 Cycles 2 1 1 2 2 2 2+S 2+S 1 1 2 2 2 2 2 2 2 2 2 1 2 2 2 2+S 2+S 3 3 1 1 2 1 2
5-10
S3C72Q5/P72Q5
SAM48 INSTRUCTION SET
Table 5-12. Logic Instructions -- High-Level Summary Name AND Operand A,#im A,@HL EA,RR RRb,EA OR A, #im A, @HL EA,RR RRb,EA XOR A,#im A,@HL EA,RR RRb,EA COM A Operation Description Logical-AND A immediate data to A Logical-AND A indirect data memory to A Logical-AND register pair (RR) to EA Logical-AND EA to register pair (RRb) Logical-OR immediate data to A Logical-OR indirect data memory contents to A Logical-OR double register to EA Logical-OR EA to double register Exclusive-OR immediate data to A Exclusive-OR indirect data memory to A Exclusive-OR register pair (RR) to EA Exclusive-OR register pair (RRb) to EA Complement accumulator (A) Table 5-13. Arithmetic Instructions -- High-Level Summary Name ADC Operand A,@HL EA,RR RRb,EA ADS A, #im EA,#imm A,@HL EA,RR RRb,EA SBC A,@HL EA,RR RRb,EA SBS A,@HL EA,RR RRb,EA DECS INCS R RR R DA @HL RRb Operation Description Add indirect data memory to A with carry Add register pair (RR) to EA with carry Add EA to register pair (RRb) with carry Add 4-bit immediate data to A and skip on carry Add 8-bit immediate data to EA and skip on carry Add indirect data memory to A and skip on carry Add register pair (RR) contents to EA and skip on carry Add EA to register pair (RRb) and skip on carry Subtract indirect data memory from A with carry Subtract register pair (RR) from EA with carry Subtract EA from register pair (RRb) with carry Subtract indirect data memory from A; skip on borrow Subtract register pair (RR) from EA; skip on borrow Subtract EA from register pair (RRb); skip on borrow Decrement register (R); skip on borrow Decrement register pair (RR); skip on borrow Increment register (R); skip on carry Increment direct data memory; skip on carry Increment indirect data memory; skip on carry Increment register pair (RRb); skip on carry Bytes 1 2 2 1 2 1 2 2 1 2 2 1 2 2 1 2 1 2 2 1 Cycles 1 2 2 1+S 2+S 1+S 2+S 2+S 1 2 2 1+S 2+S 2+S 1+S 2+S 1+S 2+S 2+S 1+S Bytes 2 1 2 2 2 1 2 2 2 1 2 2 2 Cycles 2 1 2 2 2 1 2 2 2 1 2 2 2
5-11
SAM48 INSTRUCTION SET
S3C72Q5/P72Q5
Table 5-14. Bit Manipulation Instructions -- High-Level Summary Name BTST C DA.b mema.b memb.@L @H+DA.b BTSF DA.b mema.b memb.@L @H+DA.b BTSTZ mema.b memb.@L @H+DA.b BITS DA.b mema.b memb.@L @H+DA.b BITR DA.b mema.b memb.@L @H+DA.b BAND C,mema.b C,memb.@L C,@H+DA.b BOR C,mema.b C,memb.@L C,@H+DA.b BXOR C,mema.b C,memb.@L C,@H+DA.b LDB mema.b,C memb.@L,C @H+DA.b,C C,mema.b C,memb.@L C,@H+DA.b Load specified memory bit to carry bit Load specified indirect memory bit to carry bit Load carry bit to a specified memory bit Load carry bit to a specified indirect memory bit Exclusive-OR carry with specified memory bit Logical-OR carry with specified memory bit Logical-AND carry flag with specified memory bit Clear specified memory bit to logic zero Set specified memory bit 2 2 Test specified bit; skip and clear if memory bit is set Test specified memory bit and skip if bit equals "0" Operand Operation Description Test specified bit and skip if carry flag is set Test specified bit and skip if memory bit is set Bytes 1 2 Cycles 1+S 2+S
5-12
S3C72Q5/P72Q5
SAM48 INSTRUCTION SET
BINARY CODE SUMMARY
This section contains binary code values and operation notation for each instruction in the SAM48 instruction set in an easy-to-read, tabular format. It is intended to be used as a quick-reference source for programmers who are experienced with the SAM48 instruction set. The same binary values and notation are also included in the detailed descriptions of individual instructions later in Section 5. If you are reading this user's manual for the first time, please just scan this very detailed information briefly. Most of the general information you will need to write application programs can be found in the high-level summary tables in the previous section. The following information is provided for each instruction: -- Instruction name -- Operand(s) -- Binary values -- Operation notation The tables in this section are arranged according to the following instruction categories: -- CPU control instructions -- Program control instructions -- Data transfer instructions -- Logic instructions -- Arithmetic instructions -- Bit manipulation instructions
5-13
SAM48 INSTRUCTION SET
S3C72Q5/P72Q5
Table 5-15. CPU Control Instructions -- Binary Code Summary Name SCF RCF CCF EI Operand -
1 1 1 1 1 1 1 1 1 0 1 0 1 0 1 0 0 1 1 1 1 t6 E R B 1 1 0 1 1 1 1 1 1 1 1 1 0 0 0 0 t5 a13
Binary Code
0 0 1 1 1 1 1 1 0 1 1 0 1 0 1 1 t4 0 0 0 1 0 1 0 1 0 1 0 0 1 d3 1 0 t3 1 1 1 1 0 1 0 1 0 1 0 0 1 d2 1 0 t2 1 1 1 1 1 1 1 1 1 1 1 0 0 d1 0 d1 t1 a9 1 0 0 1 0 0 0 1 1 1 1 0 1 d0 1 d0 t0 a8
Operation Notation C1 C0 CC IME 1 IME 0 PCON.2 1 PCON.3 1
DI
1 1
IDLE
1 1
STOP
1 1
NOP SMB n
1 1 0
No operation SMB n SRB n
SRB
n
1 0
(n = 0, 1, 2, 3)
REF VENTn
memc EMB (0,1) ERB (0,1) ADR
t7 E M B
PC13-0 memc.5-0+ (memc+1).7-0 ROM (2 x ROM (2 x ROM (2 x ROM (2 x (n = 0, 1, 2, n) 7-6 EMB, ERB n) 5-4 PC12,PC13 n) 3-0 PC11-8 n + 1) 7-0 PC7-0 3, 4, 5, 6, 7)
a12 a11 a10
a7
a6
a5
a4
a3
a2
a1
a0
5-14
S3C72Q5/P72Q5
SAM48 INSTRUCTION SET
Table 5-16. Program Control Instructions -- Binary Code Summary Name CPSE Operand R,#im
1 d3 1 d2 1 1 1 1 0 1 0 1 1 1 0 a6 0 a6 0 d1 0 1 0 1 1 0 0 0 1 0
Binary Code
1 d0 1 1 1 0 1 1 0 1 0 1 1 0 1 d3 1 1 1 1 1 1 1 1 0 r2 1 d2 1 r2 0 1 0 1 r2 0 0 r1 0 d1 0 r1 0 0 0 0 r1 1 a9 a1 a9 a1 1 r0 1 d0 1 r0 0 0 1 0 0 1 a8 a0 a8 a0
Operation Notation Skip if R = im
@HL,#im
1 0
Skip if (HL) = im
A,R
1 0
Skip if A = R
A,@HL EA,@HL
0 1 0
Skip if A = (HL) Skip if A = (HL), E = (HL+1)
EA,RR
1 1
Skip if EA = RR PC13-0 ADR13-0
JP
ADR
1 0 a7
a13 a12 a11 a10 a5 0 a5 a4 1 a4 a3 a2
JPS
ADR
1 a7
a11 a10 a3 a2
PC13-0 PC13-12 + ADR11-0 PC13-0 ADR (PC-15 to PC+16)
JR
#im
*
1 0 1 1 1 1 1 1 a6 1 a6 0 1 0 1 0 1 0 1 0 1 1 0 1 0 1 1 1 1 0 0 0 0 0 0 1 a9 a1 a9 a1 1 0 1 0 1 a8 a0 a8 a0
@WX
PC13-0 PC13-8 + (WX) PC13-0 PC13-8 + (EA) [(SP-1) (SP-2)] EMB, ERB [(SP-3) (SP-4)] PC7-0 [(SP-5) (SP-6)] PC13-8 [(SP-1) (SP-2)] EMB, ERB [(SP-3) (SP-4)] PC7-0 [(SP-5) (SP-6)] PC14-8
@EA
1 0
CALL
ADR
1 0 a7
a13 a12 a11 a10 a5 1 a5 a4 0 a4 a3 1 a3 a2 a10 a2
CALLS
ADR
1 a7
First Byte
Condition
a2 a2 a1 a1 a0 a0
* JR #im
0 0
0 0
0 0
1 0
a3 a3
PC PC+2 to PC+16 PC PC-1 to PC-15
5-15
SAM48 INSTRUCTION SET
S3C72Q5/P72Q5
Table 5-16. Program Control Instructions -- Binary Code Summary (Continued) Name RET Operand -
1 1 0
Binary Code
0 0 1 0 1
Operation Notation PC13-8 (SP + 1) (SP) PC7-0 (SP + 3) (SP + 2) EMB,ERB (SP + 4) SP SP + 6 PC13-8 (SP + 1) (SP) PC7-0 (SP + 3) (SP + 2) PSW (SP + 5) (SP + 4) SP SP + 6 PC13-8 (SP + 1) (SP) PC7-0 (SP + 3) (SP + 2) EMB,ERB (SP + 4) SP SP + 6
IRET
-
1
1
0
1
0
1
0
1
SRET
-
1
1
1
0
0
1
0
1
Table 5-17. Data Transfer Instructions -- Binary Code Summary Name XCH Operand A,DA
0 a7 1 a6 1 1 1 a6 1 1 1 0 1 1 0 0 0 a6 1 0 1 a5 1 1 0 a5 0 1 0 0 1 1 1 0 0 a5 0 0
Binary Code
1 a4 0 1 0 a4 1 0 1 0 1 1 1 0 0 a4 1 0 1 a3 1 1 1 a3 1 0 1 0 1 1 d3 1 1 a3 1 1 0 a2 r2 i2 1 a2 1 r2 1 0 0 0 d2 i2 1 a2 1 r2 0 a1 r1 i1 1 a1 0 r1 0 0 1 1 d1 i1 0 a1 0 r1 1 a0 r0 i0 1 a0 0 0 0 1 0 1 d0 i0 0 a0 1 r0
Operation Notation A DA A Ra A (RRa) A DA,E DA + 1 EA RRb A (HL), E (HL + 1) A (HL), then L L+1; skip if L = 0H A (HL), then L L-1; skip if L = 0FH A im A (RRa) A DA A Ra
A,Ra A,@RRa EA,DA
0 0 1 a7
EA,RRb
1 1
EA,@HL
1 0
XCHI XCHD LD
A,@HL A,@HL A,#im A,@RRa A,DA
0 0 1 1 1 a7
A,Ra
1 0
5-16
S3C72Q5/P72Q5
SAM48 INSTRUCTION SET
Table 5-17. Data Transfer Instructions -- Binary Code Summary (Continued) Name LD Operand Ra,#im
1 d3 1 d2 0 d6 0 a6 1 0 1 0 1 a6 1 1 1 1 a6 1 1 1 0 0 0 1 1 0 0 1 1 0 d1 0 d5 0 a5 0 0 0 0 0 a5 0 1 0 0 a5 0 1 0 0 0 0 0 0 0 1 0 1
Binary Code
1 d0 0 d4 0 a4 1 0 1 0 0 a4 1 1 0 0 a4 1 1 1 0 0 0 0 0 0 0 1 0 1 1 0 d3 1 a3 1 0 1 1 1 a3 1 1 0 1 a3 1 0 1 0 1 1 1 1 1 1 1 0 0 r2 r2 d2 0 a2 1 r2 1 0 1 a2 1 r2 1 1 a2 1 r2 1 0 0 0 1 0 0 r2 1 1 0 r1 r1 d1 0 a1 0 r1 0 0 1 a1 0 r1 0 0 a1 0 r1 0 0 1 1 0 0 0 r1 0 1 1 r0 1 d0 1 a0 1 r0 0 0 0 a0 0 0 0 1 a0 0 0 0 0 0 1 0 0 0 1 1 1
Operation Notation Ra im RR imm DA A Ra A A (HL), E (HL + 1) A DA, E DA + 1 EA RRb (HL) A DA A, DA + 1 E RRb EA (HL) A, (HL + 1) E A (HL), then L L+1; skip if L = 0H A (HL), then L L-1; skip if L = 0FH EA [PC13-8 + (WX)] EA [PC13-8 + (EA)] C A.0, A3 C A.n-1 A.n (n = 1, 2, 3) ((SP-1)) ((SP-2)) (RR), (SP) (SP)-2 ((SP-1)) (SMB), ((SP-2)) (SRB), (SP) (SP)-2
RR,#imm
1 d7
DA,A
1 a7
Ra,A
1 0
EA,@HL
1 0
EA,DA
1 a7
EA,RRb
1 1
@HL,A DA,EA
1 1 a7
RRb,EA
1 1
@HL,EA
1 0
LDI LDD LDC
A,@HL A,@HL EA,@WX EA,@EA
1 1 1 1 1 0 1 0
RRC PUSH
A RR SB
5-17
SAM48 INSTRUCTION SET
S3C72Q5/P72Q5
Table 5-17. Data Transfer Instructions -- Binary Code Summary (Concluded) Name POP Operand RR SB
0 0 1
Binary Code
0 1 r2 r1 0
Operation Notation RRL (SP), RRH (SP + 1) SP SP + 2 (SRB) (SP), SMB (SP + 1), SP SP + 2
1 0
1 1
0 1
1 0
1 0
1 1
0 1
1 0
Table 5-18. Logic Instructions -- Binary Code Summary Name AND Operand A,#im
1 0 1 0 0 1 0 1 0 1 0 0 1 0 1 0 1 0 0 1 0 1 0 1 0 0 0 1 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1 0 1 0 1
Binary Code
1 1 1 1 1 1 1 1 0 1 1 0 1 0 1 1 1 1 1 1 1 1 1 1 d3 1 1 1 1 0 1 d3 1 1 1 1 0 1 d3 1 1 0 1 0 1 1 1 d2 0 1 r2 1 r2 1 d2 0 1 r2 1 r2 1 d2 0 1 r2 1 r2 1 1 0 d1 0 0 r1 0 r1 0 d1 1 0 r1 0 r1 0 d1 1 0 r1 0 r1 0 1 1 d0 1 0 0 0 0 1 d0 0 0 0 0 0 1 d0 1 0 0 0 0 1 1
Operation Notation A A AND im A A AND (HL) EA EA AND RR RRb RRb AND EA A A OR im A A OR (HL) EA EA OR RR RRb RRb OR EA A A XOR im A A XOR (HL) EA EA XOR (RR) RRb RRb XOR EA A A
A,@HL EA,RR
0 1 0
RRb,EA
1 0
OR
A, #im
1 0
A, @HL EA,RR
0 1 0
RRb,EA
1 0
XOR
A,#im
1 0
A,@HL EA,RR
0 1 0
RRb,EA
1 0
COM
A
1 0
5-18
S3C72Q5/P72Q5
SAM48 INSTRUCTION SET
Table 5-19. Arithmetic Instructions -- Binary Code Summary Name ADC Operand A,@HL EA,RR
0 1 1 0 1 0 1 0 0 1 d6 0 1 0 1 0 0 1 1 1 1 0 1 0 1 0 1 1 1 1 1 a6 1 1 0 1 0 1 0 1 1 0 d5 1 0 0 0 0 1 0 0 0 0 1 0 1 0 1 0 0 0 0 0 a5 0 1 0
Binary Code
1 1 0 1 0 0 0 d4 1 1 1 1 1 1 1 0 1 0 1 1 1 1 1 0 1 1 1 0 a4 1 0 0 1 1 1 1 0 d3 1 d3 1 1 1 1 0 1 1 1 1 0 1 1 1 1 0 1 1 1 1 1 a3 1 0 0 1 1 r2 1 r2 d2 0 d2 1 1 r2 1 r2 1 1 r2 1 r2 1 1 r2 1 r2 r2 1 r2 r2 0 a2 1 0 r2 1 0 r1 0 r1 d1 0 d1 1 0 r1 0 r1 0 0 r1 0 r1 0 0 r1 0 r1 r1 0 r1 r1 1 a1 0 1 r1 0 0 0 0 0 d0 1 d0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 r0 0 0 r0 0 a0 1 0 0
Operation Notation C, A A + (HL) + C C, EA EA + RR + C C, RRb RRb + EA + C A A + im; skip on carry EA EA + imm; skip on carry A A+ (HL); skip on carry EA EA + RR; skip on carry RRb RRb + EA; skip on carry C,A A - (HL) - C C, EA EA -RR - C C,RRb RRb - EA - C A A - (HL); skip on borrow EA EA - RR; skip on borrow RRb RRb - EA; skip on borrow R R-1; skip on borrow RR RR-1; skip on borrow R R + 1; skip on carry DA DA + 1; skip on carry (HL) (HL) + 1; skip on carry RRb RRb + 1; skip on carry
RRb,EA
1 1
ADS
A, #im EA,#imm
1 1 d7
A,@HL EA,RR
0 1 1
RRb,EA
1 1
SBC
A,@HL EA,RR
0 1 1
RRb,EA
1 1
SBS
A,@HL EA,RR
0 1 1
RRb,EA
1 1
DECS
R RR
0 1 1
INCS
R DA
0 1 a7
@HL
1 0
RRb
1
5-19
SAM48 INSTRUCTION SET
S3C72Q5/P72Q5
Table 5-20. Bit Manipulation Instructions -- Binary Code Summary Name BTST C DA.b Operand
1 1 a7 1 1 a6 1 0 b1 a5 1
Binary Code
1 b0 a4 1 0 0 a3 1 1 0 a2 0 1 1 a1 0 1 1 a0 1
Operation Notation Skip if C = 1 Skip if DA.b = 1
mema.b
*
1
Skip if mema.b = 1
memb.@L
1 0
1 1 1 0 1 a6 1
1 0 1 b1 b1 a5 1
1 0 1 b0 b0 a4 1
1 a5 1 a3 0 a3 1
0 a4 0 a2 0 a2 0
0 a3 0 a1 1 a1 0
1 a2 1 a0 0 a0 0
Skip if [memb.7-2 + L.3-2]. [L.1-0] = 1
@H+DA.b
1 0
Skip if [H + DA.3-0].b = 1
BTSF
DA.b
1 a7
Skip if DA.b = 0
mema.b
*
1
Skip if mema.b = 0
memb.@L
1 0
1 1 1 0 1
1 0 1 b1 1
1 0 1 b0 1
1 a5 1 a3 1
0 a4 0 a2 1
0 a3 0 a1 0
0 a2 0 a0 1
Skip if [memb.7-2 + L.3-2]. [L.1-0] = 0
@H DA.b
1 0
Skip if [H + DA.3-0].b = 0
BTSTZ
mema.b
*
1
Skip if mema.b = 1 and clear
memb.@L
1 0
1 1 1 0 1 a6 1
1 0 1 b1 b1 a5 1
1 0 1 b0 b0 a4 1
1 a5 1 a3 0 a3 1
1 a4 1 a2 0 a2 1
0 a3 0 a1 0 a1 1
1 a2 1 a0 1 a0 1
Skip if [memb.7-2 + L.3-2]. [L.1-0] = 1 and clear
@H+DA.b
1 0
Skip if [H + DA.3-0].b =1 and clear DA.b 1 mema.b 1 [memb.7-2 + L.3-2].[L.1-0] 1 [H + DA.3-0].b 1
BITS
DA.b
1 a7
mema.b
*
1
memb.@L
1 0
1 1 1 0
1 0 1 b1
1 0 1 b0
1 a5 1 a3
1 a4 1 a2
1 a3 1 a1
1 a2 1 a0
@H+DA.b
1 0
5-20
S3C72Q5/P72Q5
SAM48 INSTRUCTION SET
Table 5-20. Bit Manipulation Instructions -- Binary Code Summary (Continued) Name BITR Operand DA.b
1 a7 1 a6 1 b1 a5 1
Binary Code
b0 a4 1 0 a3 1 0 a2 1 0 a1 1 0 a0 0
Operation Notation DA.b 0 mema.b 0 [memb.7-2 + L3-2].[L.1-0] 0 [H + DA.3-0].b 0 C C AND mema.b C C AND [memb.7-2 + L.3-2]. [L.1-0] C C AND [H + DA.3-0].b C C OR mema.b C C OR [memb.7-2 + L.3-2]. [L.1-0] C C OR [H + DA.3-0].b C C XOR mema.b C C XOR [memb.7-2 + L.3-2]. [L.1-0] C C XOR [H + DA.3-0].b
mema.b
*
1
memb.@L
1 0
1 1 1 0 1
1 0 1 b1 1
1 0 1 b0 1
1 a5 1 a3 0
1 a4 1 a2 1
1 a3 1 a1 0
0 a2 0 a0 1
@H+DA.b
1 0
BAND
C,mema.b
*
1
C,memb.@L
1 0
1 1 1 0 1
1 0 1 b1 1
1 0 1 b0 1
0 a5 0 a3 0
1 a4 1 a2 1
0 a3 0 a1 1
1 a2 1 a0 0
C,@H+DA.b
1 0
BOR
C,mema.b
*
1
C,memb.@L
1 0
1 1 1 0 1
1 0 1 b1 1
1 0 1 b0 1
0 a5 0 a3 0
1 a4 1 a2 1
1 a3 1 a1 1
0 a2 0 a0 1
C,@H+DA.b
1 0
BXOR
C,mema.b
*
1
C,memb.@L
1 0
1 1 1 0
1 0 1 b1
1 0 1 b0
0 a5 0 a3
1 a4 1 a2
1 a3 1 a1
1 a2 1 a0
C,@H+DA.b
1 0
Second Byte
Bit Addresses
a2 a2 a1 a1 a0 a0
* mema.b
1 1
0 1
b1 b1
b0 b0
a3 a3
FB0H-FBFH FF0H-FFFH
5-21
SAM48 INSTRUCTION SET
S3C72Q5/P72Q5
Table 5-20. Bit Manipulation Instructions -- Binary Code Summary (Concluded) Name LDB Operand mema.b,C Binary Code
1 1 1 1 1 1 0 0
Operation Notation mema.b C memb.7-2 + [L.3-2]. [L.1-0] C H + [DA.3-0].b (C) C mema.b C memb.7-2 + [L.3-2] . [L.1-0] C [H + DA.3-0].b
*
memb.@L,C
1 0
1 1 1 0 1
1 0 1 b1 1
1 0 1 b0 1
1 a5 1 a3 0
1 a4 1 a2 1
0 a3 0 a1 0
0 a2 0 a0 0
@H+DA.b,C
1 0
C,mema.b
*
1
C,memb.@L
1 0
1 1 1 0
1 0 1 b1
1 0 1 b0
0 a5 0 a3
1 a4 1 a2
0 a3 0 a1
0 a2 0 a0
C,@H+DA.b
1 0
Second Byte
Bit Addresses
a2 a2 a1 a1 a0 a0
* mema.b
1 1
0 1
b1 b1
b0 b0
a3 a3
FB0H-FBFH FFF0H-FFFH
5-22
S3C72Q5/P72Q5
SAM48 INSTRUCTION SET
INSTRUCTION DESCRIPTIONS
This section contains detailed information and programming examples for each instruction of the SAM48 instruction set. Information is arranged in a consistent format to improve readability and for use as a quick-reference resource for application programmers. If you are reading this user's manual for the first time, please just scan this very detailed information briefly in order to acquaint yourself with the basic features of the instruction set. The information elements of the instruction description format are as follows: -- Instruction name (mnemonic) -- Full instruction name -- Source/destination format of the instruction operand -- Operation overview (from the "High-Level Summary" table) -- Textual description of the instruction's effect -- Binary code overview (from the "Binary Code Summary" table) -- Programming example(s) to show how the instruction is used
5-23
SAM48 INSTRUCTION SET
S3C72Q5/P72Q5
ADC -- ADD With Carry
ADC Operation: dst,src Operand A,@HL EA,RR RRb,EA Operation Summary Add indirect data memory to A with carry Add register pair (RR) to EA with carry Add EA to register pair (RRb) with carry Bytes 1 2 2 Cycles 1 2 2
Description:
The source operand, along with the setting of the carry flag, is added to the destination operand and the sum is stored in the destination. The contents of the source are unaffected. If there is an overflow from the most significant bit of the result, the carry flag is set; otherwise, the carry flag is cleared. If 'ADC A,@HL' is followed by an 'ADS A,#im' instruction in a program, ADC skips the ADS instruction if an overflow occurs. If there is no overflow, the ADS instruction is executed normally. (This condition is valid only for 'ADC A,@HL' instructions. If an overflow occurs following an 'ADS A,#im' instruction, the next instruction will not be skipped.) Operand A,@HL EA,RR 0 1 1 RRb,EA 1 1 0 1 0 1 0 1 0 1 0 1 Binary Code 1 1 0 1 0 1 1 1 1 0 1 1 r2 1 r2 1 0 r1 0 r1 0 0 0 0 0 C, RRb RRb + EA + C Operation Notation C, A A + (HL) + C C, EA EA + RR + C
Examples:
1.
The extended accumulator contains the value 0C3H, register pair HL the value 0AAH, and the carry flag is set to "1": SCF ADC JPS ; C "1" ; EA 0C3H + 0AAH + 1H = 6EH, C "1" ; Jump to XXX; no skip after ADC
EA,HL XXX
2.
If the extended accumulator contains the value 0C3H, register pair HL the value 0AAH, and the carry flag is cleared to "0": RCF ADC JPS ; C "0" ; EA 0C3H + 0AAH + 0H = 6DH, C "1" ; Jump to XXX; no skip after ADC
EA,HL XXX
5-24
S3C72Q5/P72Q5
SAM48 INSTRUCTION SET
ADC -- Add with Carry
ADC Examples: (Continued) 3. If ADC A,@HL is followed by an ADS A,#im, the ADC skips on carry to the instruction immediately after the ADS. An ADS instruction immediately after the ADC does not skip even if an overflow occurs. This function is useful for decimal adjustment operations. 8 + 9 decimal addition (the contents of the address specified by the HL register is 9H): RCF LD ADS ADC ADS JPS b. ; ; ; ; ; C "0" A 8H A 8H + 6H = 0EH A OEH + 9H + C(0) = 7H, C "1" Skip this instruction because C = "1" after ADC result
a.
A,#8H A,#6H A,@HL A,#0AH XXX
3 + 4 decimal addition (the contents of the address specified by the HL register is 4H): RCF LD ADS ADC ADS ; ; ; ; ; ; ; C "0" A 3H A 3H + 6H = 9H A 9H + 4H + C(0) = 0DH No skip. A 0DH + 0AH = 7H (The skip function for 'ADS A,#im' is inhibited after an 'ADC A,@HL' instruction even if an overflow occurs.)
A,#3H A,#6H A,@HL A,#0AH
JPS
XXX
5-25
SAM48 INSTRUCTION SET
S3C72Q5/P72Q5
ADS -- Add and Skip on Overflow
ADS Operation: dst,src Operand A, #im EA,#imm A,@HL EA,RR RRb,EA Operation Summary Add 4-bit immediate data to A and skip on overflow Add 8-bit immediate data to EA and skip on overflow Add indirect data memory to A and skip on overflow Add register pair (RR) contents to EA and skip on overflow Add EA to register pair (RRb) and skip on overflow Bytes 1 2 1 2 2 Cycles 1+S 2+S 1+S 2+S 2+S
Description:
The source operand is added to the destination operand and the sum is stored in the destination. The contents of the source are unaffected. If there is an overflow from the most significant bit of the result, the skip signal is generated and a skip is executed, but the carry flag value is unaffected. If 'ADS A,#im' follows an 'ADC A,@HL' instruction in a program, ADC skips the ADS instruction if an overflow occurs. If there is no overflow, the ADS instruction is executed normally. This skip condition is valid only for 'ADC A,@HL' instructions, however. If an overflow occurs following an ADS instruction, the next instruction is not skipped. Operand A, #im EA,#imm 1 1 d7 A,@HL EA,RR 0 1 1 RRb,EA 1 1 0 1 d6 0 1 0 1 0 1 0 d5 1 0 0 0 0 Binary Code 0 0 d4 1 1 1 1 1 d3 1 d3 1 1 1 1 0 d2 0 d2 1 1 r2 1 r2 d1 0 d1 1 0 r1 0 r1 d0 1 d0 1 0 0 0 0 RRb RRb + EA; skip on overflow A A + (HL); skip on overflow EA EA + RR; skip on overflow Operation Notation A A + im; skip on overflow EA EA + imm; skip on overflow
Examples:
1.
The extended accumulator contains the value 0C3H, register pair HL the value 0AAH, and the carry flag = "0": ADS JPS JPS EA,HL XXX YYY ; ; ; ; EA 0C3H + 0AAH = 6DH ADS skips on overflow, but carry flag value is not affected. This instruction is skipped since ADS had an overflow. Jump to YYY.
5-26
S3C72Q5/P72Q5
SAM48 INSTRUCTION SET
ADS -- Add and Skip on Overflow
ADS Examples: (Continued) 2. If the extended accumulator contains the value 0C3H, register pair HL the value 12H, and the carry flag = "0": ADS JPS EA,HL XXX ; EA 0C3H + 12H = 0D5H ; Jump to XXX; no skip after ADS.
3. If 'ADC A,@HL' is followed by an 'ADS A,#im', the ADC skips on overflow to the instruction immediately after the ADS. An 'ADS A,#im' instruction immediately after the 'ADC A,@HL' does not skip even if overflow occurs. This function is useful for decimal adjustment operations. a. 8 + 9 decimal addition (the contents of the address specified by the HL register is 9H): RCF LD ADS ADC ADS JPS b. ; ; ; ; ; C "0" A 8H A 8H + 6H = 0EH A OEH + 9H + C(0) = 7H, C "1" Skip this instruction because C = "1" after ADC result.
A,#8H A,#6H A,@HL A,#0AH XXX
3 + 4 decimal addition (the contents of the address specified by the HL register is 4H): RCF LD ADS ADC ADS ; ; ; ; ; ; ; C "0" A 3H A 3H + 6H = 9H A 9H + 4H + C(0) = 0DH, C "0" No skip. A 0DH + 0AH = 7H (The skip function for 'ADS A,#im' is inhibited after an 'ADC A,@HL' instruction even if an overflow occurs.)
A,#3H A,#6H A,@HL A,#0AH
JPS
XXX
5-27
SAM48 INSTRUCTION SET
S3C72Q5/P72Q5
AND -- Logical AND
AND Operation: dst,src Operand A,#im A,@HL EA,RR RRb,EA Operation Summary Logical-AND A immediate data to A Logical-AND A indirect data memory to A Logical-AND register pair (RR) to EA Logical-AND EA to register pair (RRb) Bytes 2 1 2 2 Cycles 2 1 2 2
Description:
The source operand is logically ANDed with the destination operand. The result is stored in the destination. The logical AND operation results in a "1" whenever the corresponding bits in the two operands are both "1"; otherwise a "0" is stored in the corresponding destination bit. The contents of the source are unaffected. Operand A,#im 1 0 A,@HL EA,RR 0 1 0 RRb,EA 1 0 1 0 0 1 0 1 0 0 0 1 0 0 0 0 Binary Code 1 1 1 1 1 1 1 1 d3 1 1 1 1 0 1 d2 0 1 r2 1 r2 0 d1 0 0 r1 0 r1 1 d0 1 0 0 0 0 RRb RRb AND EA A A AND (HL) EA EA AND RR Operation Notation A A AND im
Example:
If the extended accumulator contains the value 0C3H (11000011B) and register pair HL the value 55H (01010101B), the instruction AND EA,HL
leaves the value 41H (01000001B) in the extended accumulator EA .
5-28
S3C72Q5/P72Q5
SAM48 INSTRUCTION SET
BAND -- Bit Logical AND
BAND Operation: C,src.b Operand C,mema.b C,memb.@L C,@H+DA.b Operation Summary Logical-AND carry flag with memory bit Bytes 2 2 2 Cycles 2 2 2
Description:
The specified bit of the source is logically ANDed with the carry flag bit value. If the Boolean value of the source bit is a logic zero, the carry flag is cleared to "0"; otherwise, the current carry flag setting is left unaltered. The bit value of the source operand is not affected. Operand C,mema.b Binary Code 1 1 1 1 0 1 0 1 Operation Notation C C AND mema.b C C AND [memb.7-2 + L.3-2]. [L.1-0] C C AND [H + DA.3-0].b
*
C,memb.@L
1 0
1 1 1 0
1 0 1 b1
1 0 1 b0
0 a5 0 a3
1 a4 1 a2
0 a3 0 a1
1 a2 1 a0
C,@H+DA.b
1 0
Second Byte
Bit Addresses a2 a2 a1 a1 a0 a0 FB0H-FBFH FF0H-FFFH
* mema.b
1 1
0 1
b1 b1
b0 b0
a3 a3
Examples:
1.
The following instructions set the carry flag if P1.0 (port 1.0) is equal to "1" (and assuming the carry flag is already set to "1"): SMB BAND 15 C,P1.0 ; C "1" ; If P1.0 = "1", C "1" ; If P1.0 = "0", C "0"
2.
Assume the P1 address is FF1H and the value for register L is 5H (0101B). The address (memb.7-2) is 111100B; (L.3-2) is 01B. The resulting address is 11110001B or FF1H, specifying P1. The bit value for the BAND instruction, (L.1-0) is 01B which specifies bit 1. Therefore, P1.@L = P1.1: LD BAND L,#5H C,P1.@L
; P1.@L is specified as P1.1 ; C AND P1.1
5-29
SAM48 INSTRUCTION SET
S3C72Q5/P72Q5
BAND -- Bit Logical AND
BAND Examples: (Continued) 3. Register H contains the value 2H and FLAG = 20H.3. The address of H is 0010B and FLAG(3-0) is 0000B. The resulting address is 00100000B or 20H. The bit value for the BAND instruction is 3. Therefore, @H+FLAG = 20H.3: FLAG LD BAND EQU 20H.3 H,#2H C,@H+FLAG
; C AND FLAG (20H.3)
5-30
S3C72Q5/P72Q5
SAM48 INSTRUCTION SET
BITR -- Bit Reset
BITR Operation: dst.b Operand DA.b mema.b memb.@L @H+DA.b Operation Summary Clear specified memory bit to logic zero Bytes 2 2 2 2 Cycles 2 2 2 2
Description:
A BITR instruction clears to logic zero (resets) the specified bit within the destination operand. No other bits in the destination are affected. Operand DA.b 1 a7 mema.b 1 a6 1 b1 a5 1 Binary Code b0 a4 1 0 a3 1 0 a2 1 0 a1 1 0 a0 0 mema.b 0 [memb.7-2 + L3-2].[L.1-0] 0 [H + DA.3-0].b 0 Operation Notation DA.b 0
*
1
memb.@L
1 0
1 1 1 0
1 0 1 b1
1 0 1 b0
1 a5 1 a3
1 a4 1 a2
1 a3 1 a1
0 a2 0 a0
@H+DA.b
1 0
Second Byte
Bit Addresses a2 a2 a1 a1 a0 a0 FB0H-FBFH FF0H-FFFH
* mema.b
1 1
0 1
b1 b1
b0 b0
a3 a3
Examples:
1.
If the bit location 30H.2 in the RAM has a current value of "1". The following instruction clears the third bit of location 30H to"0": BITR 30H.2 ; 30H.2 "0"
2.
You can use BITR in the same way to manipulate a port address bit: BITR P0.0 ; P0.0 "0"
5-31
SAM48 INSTRUCTION SET
S3C72Q5/P72Q5
BITR -- Bit Reset
BITR Examples: (Continued) 3. For clearing P0.2, P0.3, and P1.0-P1.3 to "0": LD BITR INCS CPSE JR 4. L,#2H P0.@L L L,#8H BP2
BP2
; First, P0.@2H = P0.2 ; (111100B) + 00B.10B = 0F0H.2
If bank 0, location 0A0H.0 is cleared (and regardless of whether the EMB value is logic zero), BITR has the following effect: FLAG EQU * * * BITR * * * LD BITR 0A0H.0
EMB
H,#0AH @H+FLAG; Bank 0 (AH + 0H).0 = 0A0H.0 "0"
NOTE:
Since the BITR instruction is used for output functions, the pin names used in the examples above may change for different devices in the SAM48 product family.
5-32
S3C72Q5/P72Q5
SAM48 INSTRUCTION SET
BITS -- Bit Set
BITS Operation: dst.b Operand DA.b mema.b memb.@L @H+DA.b Operation Summary Set specified memory bit Bytes 2 2 2 2 Cycles 2 2 2 2
Description:
This instruction sets the specified bit within the destination without affecting any other bits in the destination. BITS can manipulate any bit that is addressable using direct or indirect addressing modes. Operand DA.b 1 a7 mema.b 1 a6 1 b1 a5 1 Binary Code b0 a4 1 0 a3 1 0 a2 1 0 a1 1 1 a0 1 mema.b 1 [memb.7-2 + L.3-2].[L.1-0] 1 [H + DA.3-0] 1 Operation Notation DA.b 1
*
1
memb.@L
1 0
1 1 1 0
1 0 1 b1
1 0 1 b0
1 a5 1 a3
1 a4 1 a2
1 a3 1 a1
1 a2 1 a0
@H+DA.b
1 0
Second Byte
Bit Addresses a2 a2 a1 a1 a0 a0 FB0H-FBFH FF0H-FFFH
* mema.b
1 1
0 1
b1 b1
b0 b0
a3 a3
Examples:
1.
If the bit location 30H.2 in the RAM has a current value of "0", the following instruction sets the second bit of location 30H to "1". BITS 30H.2 ; 30H.2 "1"
2.
You can use BITS in the same way to manipulate a port address bit: BITS P0.0 ; P0.0 "1"
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SAM48 INSTRUCTION SET
S3C72Q5/P72Q5
BITS -- Bit Set
BITS Examples: (Continued) 3. For setting P0.2, P0.3, and P1.0-P1.3 to "1": LD BITS INCS CPSE JR 4. L,#2H P0.@L L L,#8H BP2
BP2
; First, P0.@2H = P0.2 ; (111100B) + 00B.10B = 0F0H.2
If bank 0, location 0A0H.0, is set to "1" and the EMB = "0", BITS has the following effect: FLAG EQU * * * BITR * * * LD BITS 0A0H.0
EMB
H,#0AH @H+FLAG; Bank 0 (AH + 0H).0 = 0A0H.0 "1"
NOTE:
Since the BITS instruction is used for output functions, pin names used in the examples above may change for different devices in the SAM48 product family.
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S3C72Q5/P72Q5
SAM48 INSTRUCTION SET
BOR -- Bit Logical OR
BOR Operation: C,src.b Operand C,mema.b C,memb.@L C,@H+DA.b Operation Summary Logical-OR carry with specified memory bit Bytes 2 2 2 Cycles 2 2 2
Description:
The specified bit of the source is logically ORed with the carry flag bit value. The value of the source is unaffected. Operand C,mema.b Binary Code 1 1 1 1 0 1 1 0 Operation Notation C C OR mema.b C C OR [memb.7-2 + L.3-2]. [L.1-0] C C OR [H + DA.3-0].b
*
C,memb.@L
1 0
1 1 1 0
1 0 1 b1
1 0 1 b0
0 a5 0 a3
1 a4 1 a2
1 a3 1 a1
0 a2 0 a0
C,@H+DA.b
1 0
Second Byte
Bit Addresses a2 a2 a1 a1 a0 a0 FB0H-FBFH FF0H-FFFH
* mema.b
1 1
0 1
b1 b1
b0 b0
a3 a3
Examples:
1.
The carry flag is logically ORed with the P1.0 value: RCF BOR ; C "0" ; If P1.0 = "1", then C "1"; if P1.0 = "0", then C "0"
C,P1.0
2.
The P1 address is FF1H and register L contains the value 1H (0001B). The address (memb.7-2) is 111100B and (L.3-2) = 00B. The resulting address is 11110000B or FF0H, specifying P0. The bit value for the BOR instruction, (L.1-0) is 01B which specifies bit 1. Therefore, P1.@L = P0.1: LD BOR L,#1H C,P1.@L
; P1.@L is specified as P0.1; C OR P0.1
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SAM48 INSTRUCTION SET
S3C72Q5/P72Q5
BOR -- Bit Logical OR
BOR Examples: (Continued) 3. Register H contains the value 2H and FLAG = 20H.3. The address of H is 0010B and 0) is 0000B. The resulting address is 00100000B or 20H. The bit value for the BOR instruction is 3. Therefore, @H+FLAG = 20H.3: FLAG LD BOR EQU 20H.3 H,#2H C,@H+FLAG FLAG(3-
; C OR FLAG (20H.3)
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S3C72Q5/P72Q5
SAM48 INSTRUCTION SET
BTSF -- Bit Test and Skip on False
BTSF Operation: dst.b Operand DA.b mema.b memb.@L @H+DA.b Operation Summary Test specified memory bit and skip if bit equals "0" Bytes 2 2 2 2 Cycles 2+S 2+S 2+S 2+S
Description:
The specified bit within the destination operand is tested. If it is a "0", the BTSF instruction skips the instruction which immediately follows it; otherwise the instruction following the BTSF is executed. The destination bit value is not affected. Operand DA.b 1 a7 mema.b 1 a6 1 1 1 1 0 b1 a5 1 1 0 1 b1 Binary Code b0 a4 1 1 0 1 b0 0 a3 1 1 a5 1 a3 0 a2 0 0 a4 0 a2 1 a1 0 0 a3 0 a1 0 a0 0 0 a2 0 a0 Skip if [H + DA.3-0].b = 0 Skip if mema.b = 0 Skip if [memb.7-2 + L.3-2]. [L.1-0] = 0 Operation Notation Skip if DA.b = 0
*
1 1 0
memb.@L
@H + DA.b
1 0
Second Byte
Bit Addresses a2 a2 a1 a1 a0 a0 FB0H-FBFH FF0H-FFFH
*
mema.b
1 1
0 1
b1 b1
b0 b0
a3 a3
Examples:
1. If RAM bit location 30H.2 is set to "0", the following instruction sequence will cause the program to continue execution from the instruction identifed as LABEL2: BTSF RET JP 2. 30H.2 LABEL2 ; If 30H.2 = "0", then skip ; If 30H.2 = "1", return
You can use BTSF in the same way to test a port pin address bit: P1.0 LABEL3 ; If P1.0 = "0", then skip ; If P1.0 = "1", then return
BTSF RET JP
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SAM48 INSTRUCTION SET
S3C72Q5/P72Q5
BTSF -- Bit Test and Skip on False
BTSF Examples: (Continued) 3. P0.2, P0.3 and P1.0-P1.3 are tested: LD BTSF RET INCS CPSE JR 4. L,#2H P0.@L
BP2
; First, P1.@2H = P0.2 ; (111100B) + 00B.10B = 0F0H.2
L L,#8H BP2
Bank 0, location 0A0H.0, is tested and (regardless of the current EMB value) BTSF has the following effect: FLAG EQU * * * BITR * * * LD BTSF RET * * * 0A0H.0
EMB
H,#0AH @H+FLAG; If bank 0 (AH + 0H).0 = 0A0H.0 = "0", then skip
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S3C72Q5/P72Q5
SAM48 INSTRUCTION SET
BTST -- Bit Test and Skip on True
BTST Operation: C DA.b mema.b memb.@L @H+DA.b dst.b Operand Operation Summary Test carry bit and skip if set (= "1") Test specified bit and skip if memory bit is set Bytes 1 2 2 2 2 Cycles 1+S 2+S 2+S 2+S 2+S
Description:
The specified bit within the destination operand is tested. If it is "1", the instruction that immediately follows the BTST instruction is skipped; otherwise the instruction following the BTST instruction is executed. The destination bit value is not affected. Operand C DA.b 1 1 a7 mema.b 1 1 a6 1 0 b1 a5 1 Binary Code 1 b0 a4 1 0 0 a3 1 1 0 a2 0 1 1 a1 0 1 1 a0 1 Skip if mema.b = 1 Operation Notation Skip if C = 1 Skip if DA.b = 1
*
1
memb.@L
1 0
1 1 1 0
1 0 1 b1
1 0 1 b0
1 a5 1 a3
0 a4 0 a2
0 a3 0 a1
1 a2 1 a0
Skip if [memb.7-2 + L.3-2]. [L.1-0] = 1
@H+DA.b
1 0
Skip if [H + DA.3-0].b = 1
Second Byte
Bit Addresses a2 a2 a1 a1 a0 a0 FB0H-FBFH FF0H-FFFH
* mema.b
1 1
0 1
b1 b1
b0 b0
a3 a3
Examples:
1.
If RAM bit location 30H.2 is set to "0", the following instruction sequence will execute instruction: BTST RET JP 30H.2 LABEL2 ; If 30H.2 = "1", then skip ; If 30H.2 = "0", return
the RET
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SAM48 INSTRUCTION SET
S3C72Q5/P72Q5
BTST -- Bit Test and Skip on True
BTST Examples: (Continued) 2. You can use BTST in the same way to test a port pin address bit: BTST RET JP 3. P1.0 LABEL3 ; If P1.0 = "1", then skip ; If P1.0 = "0", then return
P0.2, P0.3 and P1.0-P1.3 are tested : LD BTST RET INCS CPSE JR L,#2H P0.@L
BP2
; First, P0.@2H = P0.2 ; (111100B) + 00B.10B = 0F0H.2
L L,#8H BP2
4.
Bank 0, location 0A0H.0, is tested and (regardless of the current EMB value) BTST has the following effect: FLAG EQU * * * BITR * * * LD BTST RET * * * 0A0H.0
EMB
H,#0AH @H+FLAG; If bank 0 (AH + 0H).0 = 0A0H.0 = "1", then skip
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S3C72Q5/P72Q5
SAM48 INSTRUCTION SET
BTSTZ -- Bit Test and Skip on True; Clear Bit
BTSTZ Operation: dst.b Operand mema.b memb.@L @H+DA.b Operation Summary Test specified bit; skip and clear if memory bit is set Bytes 2 2 2 Cycles 2+S 2+S 2+S
Description:
The specified bit within the destination operand is tested. If it is a "1", the instruction immediately following the BTSTZ instruction is skipped; otherwise the instruction following the BTSTZ is executed. The destination bit value is cleared. Operand mema.b Binary Code 1 1 1 1 1 1 0 1 Operation Notation Skip if mema.b = 1 and clear
*
memb.@L
1 0
1 1 1 0
1 0 1 b1
1 0 1 b0
1 a5 1 a3
1 a4 1 a2
0 a3 0 a1
1 a2 1 a0
Skip if [memb.7-2 + L.3-2]. [L.1-0] = 1 and clear
@H+DA.b
1 0
Skip if [H + DA.3-0].b =1 and clear
Second Byte
Bit Addresses a2 a2 a1 a1 a0 a0 FB0H-FBFH FF0H-FFFH
* mema.b
1 1
0 1
b1 b1
b0 b0
a3 a3
Examples:
1.
Port pin P0.0 is toggled by checking the P0.0 value (level): BTSTZ BITS JP P0.0 P0.0 LABEL3 ; If P0.0 = "1", then P0.0 "0" and skip ; If P0.0 = "0", then P0.0 "1"
2.
For toggling P2.2, P2.3 and P3.0-P3.3: LD BTSTZ BITS INCS JR L,#0AH P2.@L P2.@L L BP2
BP2
; First, P2.@0AH = P2.2 ; (111100B) + 10B.10B = 0F2H.2
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SAM48 INSTRUCTION SET
S3C72Q5/P72Q5
BTSTZ -- Bit Test and Skip on True; Clear Bit
BTSTZ Examples: (Continued) 3. Bank 0, location 0A0H.0, is tested and EMB = "0": FLAG EQU * * * BITR * * * LD BTSTZ BITS 0A0H.0
EMB
H,#0AH @H+FLAG; If bank 0 (AH + 0H).0 = 0A0H.0 = "1", clear and skip @H+FLAG; If 0A0H.0 = "0", then 0A0H.0 "1"
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S3C72Q5/P72Q5
SAM48 INSTRUCTION SET
BXOR -- Bit Exclusive OR
BXOR Operation: C,src.b Operand C,mema.b C,memb.@L C,@H+DA.b Operation Summary Exclusive-OR carry with memory bit Bytes 2 2 2 Cycles 2 2 2
Description:
The specified bit of the source is logically XORed with the carry bit value. The resultant bit is written to the carry flag. The source value is unaffected. Operand C,mema.b Binary Code 1 1 1 1 0 1 1 1 Operation Notation C C XOR mema.b C C XOR [memb.7-2 + L.3-2]. [L.1-0] C C XOR [H + DA.3-0].b
*
C,memb.@L
1 0
1 1 1 0
1 0 1 b1
1 0 1 b0
0 a5 0 a3
1 a4 1 a2
1 a3 1 a1
1 a2 1 a0
C,@H+DA.b
1 0
Second Byte
Bit Addresses a2 a2 a1 a1 a0 a0 FB0H-FBFH FF0H-FFFH
* mema.b
1 1
0 1
b1 b1
b0 b0
a3 a3
Examples:
1.
The carry flag is logically XORed with the P1.0 value: RCF BXOR ; C "0" ; If P1.0 = "1", then C "1"; if P1.0 = "0", then C "0"
C,P1.0
2.
The P1 address is FF1H and register L contains the value 1H (0001B). The address (memb.7-2) is 111100B and (L.3-2) = 00B. The resulting address is 11110000B or FF0H, specifying P0. The bit value for the BXOR instruction, (L.1-0) is 01B which specifies bit 1. Therefore, P1.@L = P0.1: LD BXOR L,#1H C,P0.@L
; P1.@L is specified as P0.1; C XOR P0.1
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SAM48 INSTRUCTION SET
S3C72Q5/P72Q5
BXOR -- Bit Exclusive OR
BXOR (Continued)
Examples:
3. Register H contains the value 2H and FLAG = 20H.3. The address of H is 0010B and 0) is 0000B. The resulting address is 00100000B or 20H. The bit value for the BOR instruction is 3. Therefore, @H+FLAG = 20H.3: FLAG LD BXOR EQU 20H.3 H,#2H C,@H+FLAG
FLAG(3-
; C XOR FLAG (20H.3)
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S3C72Q5/P72Q5
SAM48 INSTRUCTION SET
CALL -- Call Procedure
CALL Operation: dst Operand ADR Operation Summary Call direct in page (14 bits) Bytes 3 Cycles 4
Description:
CALL calls a subroutine located at the destination address. The instruction adds three to the program counter to generate the return address and then pushes the result onto the stack, decreasing the stack pointer by six. The EMB and ERB are also pushed to the stack. Program execution continues with the instruction at this address. The subroutine may therefore begin anywhere in the full 16 K byte program memory address space. Operand ADR 1 0 a7 1 1 a6 0 a13 a5 Binary Code 1 a12 a4 1 0 1 a9 a1 1 a8 a0 Operation Notation [(SP-1) (SP-2)] EMB, ERB [(SP-3) (SP-4)] PC7-0 [(SP-5) (SP-6)] PC13-8
a11 a10 a3 a2
Example:
The stack pointer value is 00H and the label 'PLAY' is assigned to program memory location 0E3FH. Executing the instruction CALL PLAY
at location 0123H will generate the following values: SP 0FFH 0FEH 0FDH 0FCH 0FBH 0FAH PC = = = = = = = = 0FAH 0H EMB, ERB 2H 3H 0H 1H 0E3FH
Data is written to stack locations 0FFH - 0FAH as follows: SP - 6 SP - 5 SP - 4 SP - 3 SP - 2 SP - 1 SP (0FAH) (0FBH) (0FCH) (0FDH) (0FEH) (0FFH) (00H) 0 0 0 PC11 - PC8 0 PC13 PC12
PC3 - PC0 PC7 - PC4 0 0 EMB 0 ERB 0
5-45
SAM48 INSTRUCTION SET
S3C72Q5/P72Q5
CALLS -- Call Procedure (Short)
CALLS Operation: dst Operand ADR Operation Summary Call direct in page (11 bits) Bytes 2 Cycles 3
Description:
The CALLS instruction unconditionally calls a subroutine located at the indicated address. The instruction increments the PC twice to obtain the address of the following instruction. Then, it pushes the result onto the stack, decreasing the stack pointer six times. The higher bits of the PC, with the exception of the lower 11 bits, are cleared. The CALLS instruction can be used in the all range (0000H-3FFFH), but the subroutine must therefore be located within the 2 K byte block (0000H-07FFH) of program memory. Operand ADR 1 a7 1 a6 1 a5 Binary Code 0 a4 1 a3 a10 a2 a9 a1 a8 a0 Operation Notation [(SP-1) (SP-2)] EMB, ERB [(SP-3) (SP-4)] PC7-0 [(SP-5) (SP-6)] PC14-8
Example:
The stack pointer value is 00H and the label 'PLAY' is assigned to program memory location 0345H. Executing the instruction CALLS PLAY
at location 0123H will generate the following values: SP 0FFH 0FEH 0FDH 0FCH 0FBH 0FAH PC = = = = = = = = 0FAH 0H EMB, ERB 2H 3H 0H 1H 0345H
Data is written to stack locations 0FFH - 0FAH as follows: SP - 6 SP - 5 SP - 4 SP - 3 SP - 2 SP - 1 SP (0FAH) (0FBH) (0FCH) (0FDH) (0FEH) (0FFH) (00H) 0 0 0 PC11 - PC8 PC14 PC13 PC12
PC3 - PC0 PC7 - PC4 0 0 EMB 0 ERB 0
5-46
S3C72Q5/P72Q5
SAM48 INSTRUCTION SET
CCF -- Complement Carry Flag
CCF Operation: Operand - Operation Summary Complement carry flag Bytes 1 Cycles 1
Description:
The carry flag is complemented; if C = "1" it is changed to C = "0" and vice-versa. Operand - 1 1 0 Binary Code 1 0 1 1 0 CC Operation Notation
Example:
If the carry flag is logic zero, the instruction CCF changes the value to logic one.
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SAM48 INSTRUCTION SET
S3C72Q5/P72Q5
COM -- Complement Accumulator
COM Operation: A Operand A Operation Summary Complement accumulator (A) Bytes 2 Cycles 2
Description:
The accumulator value is complemented; if the bit value of A is "1", it is changed to "0" and vice versa. Operand A 1 0 1 0 0 1 Binary Code 1 1 1 1 1 1 0 1 1 1 A A Operation Notation
Example:
If the accumulator contains the value 4H (0100B), the instruction COM A
leaves the value 0BH (1011B) in the accumulator.
5-48
S3C72Q5/P72Q5
SAM48 INSTRUCTION SET
CPSE -- Compare and Skip If Equal
CPSE Operation: dst,src Operand R,#im @HL,#im A,R A,@HL EA,@HL EA,RR Operation Summary Compare and skip if register equals #im Compare and skip if indirect data memory equals #im Compare and skip if A equals R Compare and skip if A equals indirect data memory Compare and skip if EA equals indirect data memory Compare and skip if EA equals RR Bytes 2 2 2 1 2 2 Cycles 2+S 2+S 2+S 1+S 2+S 2+S
Description:
CPSE compares the source operand (subtracts it from) the destination operand, and skips the next instruction if the values are equal. Neither operand is affected by the comparison. Operand R,#im 1 d3 @HL,#im 1 0 A,R 1 0 A,@HL EA,@HL 0 1 0 EA,RR 1 1 1 d2 1 1 1 1 0 1 0 1 1 0 d1 0 1 0 1 1 0 0 0 1 Binary Code 1 d0 1 1 1 0 1 1 0 1 0 1 0 1 d3 1 1 1 1 1 1 1 0 r2 1 d2 1 r2 0 1 0 1 r2 0 r1 0 d1 0 r1 0 0 0 0 r1 1 r0 1 d0 1 r0 0 0 1 0 0 Skip if EA = RR Skip if A = (HL) Skip if A = (HL), E = (HL+1) Skip if A = R Skip if (HL) = im Operation Notation Skip if R = im
Example:
The extended accumulator contains the value 34H and register pair HL contains 56H. The second instruction (RET) in the instruction sequence CPSE RET EA,HL
is not skipped. That is, the subroutine returns since the result of the comparison is 'not equal.'
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SAM48 INSTRUCTION SET
S3C72Q5/P72Q5
DECS -- Decrement and Skip on Borrow
DECS Operation: R RR dst Operand Operation Summary Decrement register (R); skip on borrow Decrement register pair (RR); skip on borrow Bytes 1 2 Cycles 1+S 2+S
Description:
The destination is decremented by one. An original value of 00H will underflow to 0FFH. If a borrow occurs, a skip is executed. The carry flag value is unaffected. Operand R RR 0 1 1 1 1 1 0 0 0 Binary Code 0 1 1 1 1 1 r2 1 r2 r1 0 r1 r0 0 0 Operation Notation R R-1; skip on borrow RR RR-1; skip on borrow
Examples:
1.
Register pair HL contains the value 7FH (01111111B). The following instruction leaves the value 7EH in register pair HL: DECS HL
2.
Register A contains the value 0H. The following instruction sequence leaves the value 0FFH in register A. Since a "borrow" occurs, the 'CALL PLAY1' instruction is skipped and the 'CALL PLAY2' instruction is executed: DECS CALL CALL A PLAY1 PLAY2 ; "Borrow" occurs ; Skipped ; Executed
5-50
S3C72Q5/P72Q5
SAM48 INSTRUCTION SET
DI -- Disable Interrupts
DI Operation: Operand - Operation Summary Disable all interrupts Bytes 2 Cycles 2
Description:
Bit 3 of the interrupt priority register IPR, IME, is cleared to logic zero, disabling all interrupts. Interrupts can still set their respective interrupt status latches, but the CPU will not directly service them. Operand - 1 1 1 0 1 1 Binary Code 1 1 1 0 1 0 1 1 0 0 Operation Notation IME 0
Example:
If the IME bit (bit 3 of the IPR) is logic one (e.g., all instructions are enabled), the instruction DI sets the IME bit to logic zero, disabling all interrupts.
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SAM48 INSTRUCTION SET
S3C72Q5/P72Q5
EI -- Enable Interrupts
EI Operation: Operand - Operation Summary Enable all interrupts Bytes 2 Cycles 2
Description:
Bit 3 of the interrupt priority register IPR (IME) is set to logic one. This allows all interrupts to be serviced when they occur, assuming they are enabled. If an interrupt's status latch was previously enabled by an interrupt, this interrupt can also be serviced. Operand - 1 1 1 0 1 1 Binary Code 1 1 1 0 1 0 1 1 1 0 Operation Notation IME 1
Example:
If the IME bit (bit 3 of the IPR) is logic zero (e.g., all instructions are disabled), the instruction EI sets the IME bit to logic one, enabling all interrupts.
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S3C72Q5/P72Q5
SAM48 INSTRUCTION SET
IDLE -- Idle Operation
IDLE Operation: Operand - Operation Summary Engage CPU idle mode Bytes 2 Cycles 2
Description:
IDLE causes the CPU clock to stop while the system clock continues oscillating by setting bit 2 of the power control register (PCON). After an IDLE instruction has been executed, peripheral hardware remains operative. In application programs, an IDLE instruction must be immediately followed by at least three NOP instructions. This ensures an adequate time interval for the clock to stabilize before the next instruction is executed. If three or more NOP instructions are not used after IDLE instruction, leakage current could be flown because of the floating state in the internal bus. Operand - 1 1 1 0 1 1 Binary Code 1 0 1 0 1 0 1 1 1 1 Operation Notation PCON.2 1
Example:
The instruction sequence IDLE NOP NOP NOP sets bit 2 of the PCON register to logic one, stopping the CPU clock. The three NOP instructions provide the necessary timing delay for clock stabilization before the next instruction in the program sequence is executed.
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SAM48 INSTRUCTION SET
S3C72Q5/P72Q5
INCS -- Increment and Skip on Carry
INCS Operation: R DA @HL RRb dst Operand Operation Summary Increment register (R); skip on carry Increment direct data memory; skip on carry Increment indirect data memory; skip on carry Increment register pair (RRb); skip on carry Bytes 1 2 2 1 Cycles 1+S 2+S 2+S 1+S
Description:
The instruction INCS increments the value of the destination operand by one. An original value of 0FH will, for example, overflow to 00H. If a carry occurs, the next instruction is skipped. The carry flag value is unaffected. Operand R DA 0 1 a7 @HL 1 0 RRb 1 1 1 a6 1 1 0 0 0 a5 0 1 0 Binary Code 1 0 a4 1 0 0 1 1 a3 1 0 0 r2 0 a2 1 0 r2 r1 1 a1 0 1 r1 r0 0 a0 1 0 0 RRb RRb + 1; skip on carry (HL) (HL) + 1; skip on carry Operation Notation R R + 1; skip on carry DA DA + 1; skip on carry
Example:
Register pair HL contains the value 7EH (01111110B). RAM location 7EH contains 0FH. The instruction sequence INCS INCS INCS @HL HL @HL ; 7EH "0" ; Skip ; 7EH "1"
leaves the register pair HL with the value 7EH and RAM location 7EH with the value 1H. Since a carry occurred, the second instruction is skipped. The carry flag value remains unchanged.
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S3C72Q5/P72Q5
SAM48 INSTRUCTION SET
IRET -- Return From Interrupt
IRET Operation: Operand - Operation Summary Return from interrupt Bytes 1 Cycles 3
Description:
IRET is used at the end of an interrupt service routine. It pops the PC values successively from the stack and restores them to the program counter. The stack pointer is incremented by six and the PSW, enable memory bank (EMB) bit, and enable register bank (ERB) bit are also automatically restored to their pre-interrupt values. Program execution continues from the resulting address, which is generally the instruction immediately after the point at which the interrupt request was detected. If a lower-level or same-level interrupt was pending when the IRET was executed, IRET will be executed before the pending interrupt is processed. Since the 'a14' bit of an interrupt return address is not stored in the stack, this bit location is always interpreted as a logic zero. The starting address in the ROM must for this reason be located in 0000H-3FFFH. Operand - 1 1 0 Binary Code 1 0 1 0 1 Operation Notation PC13-8 (SP + 1) (SP) PC7-0 SP + 3) (SP + 2) PSW (SP + 5) (SP + 4) SP SP + 6
Example:
The stack pointer contains the value 0FAH. An interrupt is detected in the instruction at location 0123H. RAM locations 0FDH, 0FCH, and 0FAH contain the values 2H, 3H, and 1H, respectively. The instruction IRET leaves the stack pointer with the value 00H and the program returns to continue execution at location 0123H. During a return from interrupt, data is popped from the stack to the program counter. The data in stack locations 0FFH-0FAH is organized as follows:
SP SP + 1 SP + 2 SP + 3 SP + 4 SP + 5 SP + 6
(0FAH) (0FBH) (0FCH) (0FDH) (0FEH) (0FFH) (00H) IS1 C 0
PC11 - PC8 0 PC13 PC12
PC3 - PC0 PC7 - PC4 IS0 SC2 EMB SC1 ERB SC0
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SAM48 INSTRUCTION SET
S3C72Q5/P72Q5
JP -- Jump
JP Operation: dst Operand ADR Operation Summary Jump to direct address (14 bits) Bytes 3 Cycles 3
Description:
JP causes an unconditional branch to the indicated address by replacing the contents of the program counter with the address specified in the destination operand. The destination can be anywhere in the 16 K byte program memory address space. Operand ADR 1 0 a7 1 0 a6 0 a13 a5 Binary Code 1 a12 a4 1 0 1 a9 a1 1 a8 a0 Operation Notation PC13-0 ADR13-0
a11 a10 a3 a2
Example:
The label 'SYSCON' is assigned to the instruction at program location 07FFH. The instruction JP SYSCON
at location 0123H will load the program counter with the value 07FFH.
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S3C72Q5/P72Q5
SAM48 INSTRUCTION SET
JPS -- Jump (Short)
JPS Operation: dst Operand ADR Operation Summary Jump direct in page (12 bits) Bytes 2 Cycles 2
Description:
JPS causes an unconditional branch to the indicated address with the 4 K byte program memory address space. Bits 0-11 of the program counter are replaced with the directly specified address. The destination address for this jump is specified to the assembler by a label or by an actual address in program memory. Operand ADR 1 a7 0 a6 0 a5 Binary Code 1 a4 a11 a10 a3 a2 a9 a1 a8 a0 Operation Notation PC13-0 PC13-12 + ADR11-0
Example:
The label 'SUB' is assigned to the instruction at program memory location 00FFH. The instruction JPS SUB
at location 0EABH will load the program counter with the value 00FFH. Normally, the JPS instruction jumps to the address in the block in which the instruction is located. If the first byte of the instruction code is located at address xFFEH or xFFFH, the instruction will jump to the next block. If the instruction 'JPS SUB' were located instead at program memory address 0FFEH or 0FFFH, the instruction 'JPS SUB' would load the PC with the value 10FFH, causing a program malfunction.
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SAM48 INSTRUCTION SET
S3C72Q5/P72Q5
JR -- Jump Relative (Very Short)
JR Operation: dst Operand #im @WX @EA Operation Summary Branch to relative immediate address Branch relative to contents of WX register Branch relative to contents of EA Bytes 1 2 2 Cycles 2 3 3
Description:
JR causes the relative address to be added to the program counter and passes control to the instruction whose address is now in the PC. The range of the relative address is current PC - 15 to current PC + 16. The destination address for this jump is specified to the assembler by a label, an actual address, or by immediate data using a plus sign (+) or a minus sign (-). For immediate addressing, the (+) range is from 2 to 16 and the (-) range is from -1 to -15. If a 0, 1, or any other number that is outside these ranges are used, the assembler interprets it as an error. For JR @WX and JR @EA branch relative instructions, the valid range for the relative address is 0H0FFH. The destination address for these jumps can be specified to the assembler by a label that lies anywhere within the current 256-byte block. Normally, the 'JR @WX' and 'JR @EA' instructions jump to the address in the page in which the instruction is located. However, if the first byte of the instruction code is located at address xxFEH or xxFFH, the instruction will jump to the next page. Operand #im Binary Code Operation Notation PC13-0 ADR (PC-15 to PC+16) 1 0 @EA 1 0 1 1 1 1 0 1 0 1 1 0 1 0 1 0 1 0 1 1 1 0 0 0 0 0 1 0 1 0 PC13-0 PC13-8 + (EA) PC13-0 PC13-8 + (WX)
*
@WX
First Byte
Condition a2 a2 a1 a1 a0 a0 PC PC+2 to PC+16 PC PC-1 to PC-15
* JR #im
0 0
0 0
0 0
1 0
a3 a3
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S3C72Q5/P72Q5
SAM48 INSTRUCTION SET
JR -- Jump Relative (Very Short)
JR Examples: (Continued) 1. A short form for a relative jump to label 'KK' is the instruction JR KK
where 'KK' must be within the allowed range of current PC-15 to current PC+16. The JR instruction has in this case the effect of an unconditional JP instruction. 2. In the following instruction sequence, if the instruction 'LD WX, #02H' were to be executed in place of 'LD WX,#00H', the program would jump to 1004H and 'JPS CCC' would be executed. If 'LD WX,#03H' were to be executed, the jump would be to1006H and 'JPS DDD' would be executed. ORG JPS JPS JPS JPS LD LD ADS JR 1000H AAA BBB CCC DDD WX,#00H ; WX 00H EA,WX WX,EA ; WX (WX) + (EA) @WX ; Current PC12-8 (10H) + WX (00H) = 1000H ; Jump to address 1000H and execute JPS AAA
XXX
3.
Here is another example: ORG LD LD LD LD LD JPS XXX JR 1100H A,#0H A,#1H A,#2H A,#3H 30H,A YYY LD @EA
; Address 30H A EA,#00H ; EA 00H ; Jump to address 1100H ; Address 30H 00H
If 'LD EA,#01H' were to be executed in place of 'LD EA,#00H', the program would jump to 1101H and address 30H would contain the value 1H. If 'LD EA,#02H' were to be executed, the jump would be to 1102H and address 30H would contain the value 2H.
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SAM48 INSTRUCTION SET
S3C72Q5/P72Q5
LD -- Load
LD Operation: dst,src Operand A,#im A,@RRa A,DA A,Ra Ra,#im RR,#imm DA,A Ra,A EA,@HL EA,DA EA,RRb @HL,A DA,EA RRb,EA @HL,EA Operation Summary Load 4-bit immediate data to A Load indirect data memory contents to A Load direct data memory contents to A Load register contents to A Load 4-bit immediate data to register Load 8-bit immediate data to register Load contents of A to direct data memory Load contents of A to register Load indirect data memory contents to EA Load direct data memory contents to EA Load register contents to EA Load contents of A to indirect data memory Load contents of EA to data memory Load contents of EA to register Load contents of EA to indirect data memory Bytes 1 1 2 2 2 2 2 2 2 2 2 1 2 2 2 Cycles 1 1 2 2 2 2 2 2 2 2 2 1 2 2 2
Description:
The contents of the source are loaded into the destination. The source's contents are unaffected. If an instruction such as 'LD A,#im' (LD EA,#imm) or 'LD HL,#imm' is written more than two times in succession, only the first LD will be executed; the other similar instructions that immediately follow the first LD will be treated like a NOP. This is called the 'redundancy effect' (see examples below). Operand A,#im A,@RRa A,DA 1 1 1 a7 A,Ra 1 0 Ra,#im 1 d3 0 0 0 a6 1 0 1 d2 1 0 0 a5 0 0 0 d1 Binary Code 1 0 0 a4 1 0 1 d0 d3 1 1 a3 1 1 1 1 d2 i2 1 a2 1 r2 0 r2 d1 i1 0 a1 0 r1 0 r1 d0 i0 0 a0 1 r0 1 r0 Ra im A Ra A im A (RRa) A DA Operation Notation
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SAM48 INSTRUCTION SET
LD -- Load
LD Description: (Continued) Operand RR,#imm 1 d7 DA,A 1 a7 Ra,A 1 0 EA,@HL 1 0 EA,DA 1 a7 EA,RRb 1 1 @HL,A DA,EA 1 1 a7 RRb,EA 1 1 @HL,EA 1 0 0 d6 0 a6 1 0 1 0 1 a6 1 1 1 1 a6 1 1 1 0 0 d5 0 a5 0 0 0 0 0 a5 0 1 0 0 a5 0 1 0 0 Binary Code 0 d4 0 a4 1 0 1 0 0 a4 1 1 0 0 a4 1 1 1 0 0 d3 1 a3 1 0 1 1 1 a3 1 1 0 1 a3 1 0 1 0 r2 d2 0 a2 1 r2 1 0 1 a2 1 r2 1 1 a2 1 r2 1 0 r1 d1 0 a1 0 r1 0 0 1 a1 0 r1 0 0 a1 0 r1 0 0 1 d0 1 a0 1 r0 0 0 0 a0 0 0 0 1 a0 0 0 0 0 (HL) A, (HL + 1) E RRb EA (HL) A DA A, DA + 1 E EA RRb A DA, E DA + 1 A (HL), E (HL + 1) Ra A DA A Operation Notation RR imm
Examples:
1.
RAM location 30H contains the value 4H. The RAM location values are 40H, 41H and 0AH, 3H respectively. The following instruction sequence leaves the value 40H in point pair HL, 0AH in the accumulator and in RAM location 40H, and 3H in register E. LD LD LD LD LD HL,#30H A,@HL HL,#40H EA,@HL @HL,A ; ; ; ; ; HL 30H A 4H HL 40H A 0AH, E 3H RAM (40H) 0AH
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SAM48 INSTRUCTION SET
S3C72Q5/P72Q5
LD -- Load
LD Examples: (Continued) 2. If an instruction such as LD A,#im (LD EA,#imm) or LD HL,#imm is written more than two times in succession, only the first LD is executed; the next instructions are treated as NOPs. Here are two examples of this 'redundancy effect': LD LD LD LD LD LD LD LD LD A,#1H EA,#2H A,#3H 23H,A HL,#10H HL,#20H A,#3H EA,#35 @HL,A ; ; ; ; ; ; ; ; ; A 1H NOP NOP (23H) 1H HL 10H NOP A 3H NOP (10H) 3H
The following table contains descriptions of special characteristics of the LD instruction when used in different addressing modes: Instruction LD A,#im Operation Description and Guidelines Since the 'redundancy effect' occurs with instructions like LD EA,#imm, if this instruction is used consecutively, the second and additional instructions of the same type will be treated like NOPs.
LD
A,@RRa Load the data memory contents pointed to by 8-bit RRa register pairs (HL, WX, WL) to the A register. A,DA A,Ra Ra,#im Load direct data memory contents to the A register. Load 4-bit register Ra (E, L, H, X, W, Z, Y) to the A register. Load 4-bit immediate data into the Ra register (E, L, H, X, W, Y, Z). Load 8-bit immediate data into the Ra register (EA, HL, WX, YZ). There is a redundancy effect if the operation addresses the HL or EA registers. Load contents of register A to direct data memory address. Load contents of register A to 4-bit Ra register (E, L, H, X, W, Z, Y).
LD LD LD
LD RR,#imm LD LD DA,A Ra,A
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SAM48 INSTRUCTION SET
LD -- Load
LD Examples: (Concluded) Instruction LD Operation Description and Guidelines
EA,@HL Load data memory contents pointed to by 8-bit register HL to the A register, and the contents of HL+1 to the E register. The contents of register L must be an even number. If the number is odd, the LSB of register L is recognized as a logic zero (an even number), and it is not replaced with the true value. For example, 'LD HL,#36H' loads immediate 36H to HL and the next instruction 'LD EA,@HL' loads the contents of 36H to register A and the contents of 37H to register E. EA,DA Load direct data memory contents of DA to the A register, and the next direct data memory contents of DA + 1 to the E register. The DA value must be an even number. If it is an odd number, the LSB of DA is recognized as a logic zero (an even number), and it is not replaced with the true value. For example, 'LD EA,37H' loads the contents of 36H to the A register and the contents of 37H to the E register. Load 8-bit RRb register (HL, WX, YZ) to the EA register. H, W, and Y register values are loaded into the E register, and the L, X, and Z values into the A register. Load A register contents to data memory location pointed to by the 8-bit HL register value. Load the A register contents to direct data memory and the E register contents to the next direct data memory location. The DA value must be an even number. If it is an odd number, the LSB of the DA value is recognized as logic zero (an even number), and is not replaced with the true value. Load contents of EA to the 8-bit RRb register (HL, WX, YZ). The E register is loaded into the H, W, and Y register and the A register into the L, X, and Z register.
LD
LD
EA,RRb
LD
@HL,A
LD
DA,EA
LD
RRb,EA
LD
@HL,EA Load the A register to data memory location pointed to by the 8-bit HL register, and the E register contents to the next location, HL + 1. The contents of the L register must be an even number. If the number is odd, the LSB of the L register is recognized as logic zero (an even number), and is not replaced with the true value. For example, 'LD HL,#36H' loads immediate 36H to register HL; the instruction 'LD @HL,EA' loads the contents of A into address 36H and the contents of E into address 37H.
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SAM48 INSTRUCTION SET
S3C72Q5/P72Q5
LDB -- Load Bit
LDB LDB Operation: dst,src.b dst.b,src Operand mema.b,C memb.@L,C @H+DA.b,C C,mema.b C,memb.@L C,@H+DA.b Load memory bit to a specified carry bit Load indirect memory bit to a specified carry bit Operation Summary Load carry bit to a specified memory bit Load carry bit to a specified indirect memory bit Bytes 2 2 2 2 2 2 Cycles 2 2 2 2 2 2
Description:
The Boolean variable indicated by the first or second operand is copied into the location specified by the second or first operand. One of the operands must be the carry flag; the other may be any directly or indirectly addressable bit. The source is unaffected. Operand mema.b,C Binary Code 1 1 1 1 1 1 0 0 Operation Notation mema.b C memb.7-2 + [L.3-2]. [L.1-0] C H + [DA.3-0].b (C) C mema.b C memb.7-2 + [L.3-2] . [L.1-0] C [H + DA.3-0].b
*
memb.@L,C
1 0
1 1 1 0 1
1 0 1 b1 1
1 0 1 b0 1
1 a5 1 a3 0
1 a4 1 a2 1
0 a3 0 a1 0
0 a2 0 a0 0
@H+DA.b,C
1 0
C,mema.b*
1
C,memb.@L
1 0
1 1 1 0
1 0 1 b1
1 0 1 b0
0 a5 0 a3
1 a4 1 a2
0 a3 0 a1
0 a2 0 a0
C,@H+DA.b
1 0
Second Byte
Bit Addresses a2 a2 a1 a1 a0 a0 FB0H-FBFH FF0H-FFFH
*
mema.b
1 1
0 1
b1 b1
b0 b0
a3 a3
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SAM48 INSTRUCTION SET
LDB -- Load Bit
LDB Examples: (Continued) 1. The carry flag is set and the data value at input pin P1.0 is logic zero. The following instruction clears the carry flag to logic zero. LDB 2. C,P1.0
The P1 address is FF1H and the L register contains the value 9H (1001B). The address (memb.7-2) is 111100B and (L.3-2) is 10B. The resulting address is 11110010B or FF2H and P2 is addressed. The bit value (L.1-0) is specified as 01B (bit 1). LD LDB L,#9H CO,P1.@L ; P1.@L specifies P2.1 and C P2.1
3.
The H register contains the value 2H and FLAG = 20H.3. The address for H is 0010B and for FLAG(3-0) the address is 0000B. The resulting address is 00100000B or 20H. The bit value is 3. Therefore, @H+FLAG = 20H.3. FLAG LD LDB EQU 20H.3 H,#2H C,@H+FLAG
; C FLAG (20H.3)
4.
The following instruction sequence sets the carry flag and the loads the "1" data value to the output pin P2.0, setting it to output mode: SCF LDB ; C "1" ; P2.0 "1"
P2.0,C
5.
The P1 address is FF1H and L = 9H (1001B). The address (memb.7-2) is 111100B and (L.3-2) is 10B. The resulting address, 11110010B specifies P2. The bit value (L.1-0) is specified as 01B (bit 1). Therefore, P1.@L = P2.1. SCF LD LDB ; C "1" L,#9H P1.@L,C ; P1.@L specifies P2.1 ; P2.1 "1"
6.
In this example, H = 2H and FLAG = 20H.3 and the address 20H is specified. Since the bit value is 3, @H+FLAG = 20H.3: FLAG RCF LD LDB EQU 20H.3 ; C "0" H,#2H @H+FLAG,C ; FLAG(20H.3) "0"
NOTE:
Port pin names used in examples 4 and 5 may vary with different SAM48 devices.
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SAM48 INSTRUCTION SET
S3C72Q5/P72Q5
LDC -- Load Code Byte
LDC Operation: dst,src Operand EA,@WX EA,@EA Operation Summary Load code byte from WX to EA Load code byte from EA to EA Bytes 1 1 Cycles 3 3
Description:
This instruction is used to load a byte from program memory into an extended accumulator. The address of the byte fetched is the six highest bit values in the program counter and the contents of an 8-bit working register (either WX or EA). The contents of the source are unaffected. Operand EA,@WX EA,@EA 1 1 1 1 0 0 Binary Code 0 0 1 1 1 0 0 0 0 0 Operation Notation EA [PC13-8 + (WX)] EA [PC13-8 + (EA)]
Examples:
1. The following instructions will load one of four values defined by the define byte (DB) to the extended accumulator: LD CALL JPS ORG DB DB DB DB DISPLAY RET EA,#00H DISPLAY MAIN 0500H 66H 77H 88H 99H LDC
directive
EA,@EA ; EA address 0500H = 66H
If the instruction 'LD EA,#01H' is executed in place of 'LD EA,#00H', The content of 0501H (77H) is loaded to the EA register. If 'LD EA,#02H' is executed, the content of address 0502H (88H) is loaded to EA.
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SAM48 INSTRUCTION SET
LDC -- Load Code Byte
LDC Examples: (Continued) 2. The following instructions will load one of four values defined by the define byte (DB) directive to the extended accumulator: ORG DB DB DB DB DISPLAY LDC RET 0500H 66H 77H 88H 99H LD WX,#00H EA,@WX ; EA address 0500H = 66H
If the instruction 'LD WX,#01H' is executed in place of 'LD WX,#00H', then EA address 0501H = 77H. If the instruction 'LD WX,#02H' is executed in place of 'LD WX,#00H', then EA address 0502H = 88H. 3. Normally, the LDC EA, @EA and the LDC EA, @WX instructions reference the table data on the page on which the instruction is located. If, however, the instruction is located at address xxFFH, it will reference table data on the next page. In this example, the upper 4 bits of the address at location 0200H is loaded into register E and the lower 4 bits into register A: ORG 01FDH 01FFH 01FDH LD LDC WX,#00H EA,@WX ; E upper 4 bits of 0200H address ; A lower 4 bits of 0200H address
4.
Here is another example of page referencing with the LDC instruction: ORG DB SMB LD LD LDC LD 0100H 67H 0 HL,#30H WX,#00H EA,@WX @HL,EA
; Even number ; E upper 4 bits of 0100H address ; A lower 4 bits of 0100H address ; RAM (30H) 7, RAM (31H) 6
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SAM48 INSTRUCTION SET
S3C72Q5/P72Q5
LDD -- Load Data Memory and Decrement
LDD Operation: dst Operand A,@HL Operation Summary Load indirect data memory contents to A; decrement register L contents and skip on borrow Bytes 1 Cycles 2+S
Description:
The contents of a data memory location are loaded into the accumulator, and the contents of the register L are decreased by one. If a "borrow" occurs (e.g., if the resulting value in register L is 0FH), the next instruction is skipped. The contents of data memory and the carry flag value are not affected. Operand A,@HL 1 0 0 Binary Code 0 1 0 1 1 Operation Notation A (HL), then L L-1; skip if L = 0FH
Example:
In this example, assume that register pair HL contains 20H and internal RAM location 20H contains the value 0FH: LD LDD JPS JPS HL,#20H A,@HL XXX YYY ; A (HL) and L L-1 ; Skip ; H 2H and L 0FH
The instruction 'JPS XXX' is skipped since a "borrow" occurred after the 'LDD A,@HL' and instruction 'JPS YYY' is executed.
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SAM48 INSTRUCTION SET
LDI -- Load Data Memory and Increment
LDI Operation: dst,src Operand A,@HL Operation Summary Load indirect data memory to A; increment register L contents and skip on overflow Bytes 1 Cycles 2+S
Description:
The contents of a data memory location are loaded into the accumulator, and the contents of the register L are incremented by one. If an overflow occurs (e.g., if the resulting value in register L is 0H), the next instruction is skipped. The contents of data memory and the carry flag value are not affected. Operand A,@HL 1 0 0 Binary Code 0 1 0 1 0 Operation Notation A (HL), then L L+1; skip if L = 0H
Example:
Assume that register pair HL contains the address 2FH and internal RAM location 2FH contains the value 0FH: LD LDI JPS JPS HL,#2FH A,@HL XXX YYY ; A (HL) and L L+1 ; Skip ; H 2H and L 0H
The instruction 'JPS XXX' is skipped since an overflow occurred after the 'LDI A,@HL' and the instruction 'JPS YYY' is executed.
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SAM48 INSTRUCTION SET
S3C72Q5/P72Q5
NOP -- No Operation
NOP Operation: Operand - No operation Operation Summary Bytes 1 Cycles 1
Description:
No operation is performed by a NOP instruction. It is typically used for timing delays. One NOP causes a 1-cycle delay: with a 1 s cycle time, five NOPs would therefore cause a 5 s delay. Program execution continues with the instruction immediately following the NOP. Only the PC is affected. At least three NOP instructions should follow a STOP or IDLE instruction. Operand - 1 0 1 Binary Code 0 0 0 0 0 Operation Notation No operation
Example:
Three NOP instructions follow the STOP instruction to provide a short interval for clock stabilization before power-down mode is initiated: STOP NOP NOP NOP
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SAM48 INSTRUCTION SET
OR -- Logical OR
OR Operation: dst,src Operand A, #im A, @HL EA,RR RRb,EA Operation Summary Logical-OR immediate data to A Logical-OR indirect data memory contents to A Logical-OR double register to EA Logical-OR EA to double register Bytes 2 1 2 2 Cycles 2 1 2 2
Description:
The source operand is logically ORed with the destination operand. The result is stored in the destination. The contents of the source are unaffected. Operand A, #im 1 0 A, @HL EA,RR 0 1 0 RRb,EA 1 0 1 0 0 1 0 1 0 0 1 1 0 1 0 1 Binary Code 1 0 1 1 0 1 0 1 d3 1 1 1 1 0 1 d2 0 1 r2 1 r2 0 d1 1 0 r1 0 r1 1 d0 0 0 0 0 0 RRb RRb OR EA A A OR (HL) EA EA OR RR Operation Notation A A OR im
Example:
If the accumulator contains the value 0C3H (11000011B) and register pair HL the value 55H (01010101B), the instruction OR EA,@HL
leaves the value 0D7H (11010111B) in the accumulator .
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S3C72Q5/P72Q5
POP -- POP From Stack
POP Operation: dst Operand RR SB Operation Summary Pop to register pair from stack Pop SMB and SRB values from stack Bytes 1 2 Cycles 1 2
Description:
The contents of the RAM location addressed by the stack pointer is read, and the SP is incremented by two. The value read is then transferred to the variable indicated by the destination operand. Operand RR SB 0 1 0 0 1 1 1 0 1 Binary Code 0 1 0 1 1 0 r2 1 1 r1 0 1 0 1 0 Operation Notation RRL (SP), RRH (SP+1) SP SP+2 (SRB) (SP), SMB (SP+1), SP SP+2
Example:
The SP value is equal to 0EDH, and RAM locations 0EFH through 0EDH contain the values 2H, 3H, and 4H, respectively. The instruction POP HL
leaves the stack pointer set to 0EFH and the data pointer pair HL set to 34H.
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SAM48 INSTRUCTION SET
PUSH -- PUSH onto Stack
PUSH Operation: src Operand RR SB Operation Summary Push register pair onto stack Push SMB and SRB values onto stack Bytes 1 2 Cycles 1 2
Description:
The SP is then decreased by two and the contents of the source operand are copied into the RAM location addressed by the stack pointer, thereby adding a new element to the top of the stack. Operand RR SB 0 1 0 0 1 1 1 0 1 Binary Code 0 1 0 1 1 0 r2 1 1 r1 0 1 1 1 1 Operation Notation (SP-1) RRH, (SP-2) RRL SP SP-2 (SP-1) SMB, (SP-2) SRB; (SP) SP-2
Example:
As an interrupt service routine begins, the stack pointer contains the value 0FAH and the data pointer register pair HL contains the value 20H. The instruction PUSH HL
leaves the stack pointer set to 0F8H and stores the values 2H and 0H in RAM locations 0F9H and 0F8H, respectively.
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SAM48 INSTRUCTION SET
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RCF -- Reset Carry Flag
RCF Operation: Operand - Operation Summary Reset carry flag to logic zero Bytes 1 Cycles 1
Description:
The carry flag is cleared to logic zero, regardless of its previous value. Operand - 1 1 1 Binary Code 0 0 1 1 0 C0 Operation Notation
Example:
Assuming the carry flag is set to logic one, the instruction RCF resets (clears) the carry flag to logic zero.
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SAM48 INSTRUCTION SET
REF -- Reference Instruction
REF Operation: dst Operand memc
NOTE:
Operation Summary Reference code
Bytes 1
Cycles 1(note)
The instruction referenced by REF determines instruction cycles.
Description:
The REF instruction is used to rewrite into 1-byte form, arbitrary 2-byte or 3-byte instructions (or two 1-byte instructions) stored in the REF instruction reference area in program memory. REF reduces the number of program memory accesses for a program. Operand memc t7 t6 t5 Binary Code t4 t3 t2 t1 t0 Operation Notation PC13-0 memc5-0 + (memc+1).7-0
TJP and TCALL are 2-byte pseudo-instructions that are used only to specify the reference area: 1. When the reference area is specified by the TJP instruction, memc.7-6 = 00 PC13-0 memc.5-0 + (memc+1).7-0 When the reference area is specified by the TCALL instruction, memc.7-6 = 01 [(SP-1) (SP-2)] EMB, ERB [(SP-3) (SP-4)] PC7-0 [(SP-5) (SP-6)] PC13-8 SP SP-6 PC-0 memc.5-0 + (memc+1).7-0
2.
When the reference area is specified by any other instruction, the 'memc' and 'memc + 1' instructions are executed. Instructions referenced by REF occupy 2 bytes of memory space (for two 1-byte instructions or one 2-byte instruction) and must be written as an even number from 0020H to 007FH in ROM. In addition, the destination address of the TJP and TCALL instructions must be located with the 3FFFH address. TJP and TCALL are reference instructions for JP/JPS and CALL/CALLS. If the instruction following a REF is subject to the 'redundancy effect', the redundant instruction is skipped. If, however, the REF follows a redundant instruction, it is executed. On the other hand, the binary code of a REF instruction is 1 byte. The upper 4 bits become the higher address bits of the referenced instruction, and the lower 4 bits of the referenced instruction becomes the lower address, producing a total of 8 bits or 1 byte (see Example 3 below).
NOTE: If the MSB value of the first one-byte binary code in instruction is "0", the instruction cannot be referenced by a REF instruction.
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REF -- Reference Instruction
REF Examples: (Continued) 1. Instructions can be executed efficiently using REF, as shown in the following example: ORG AAA BBB CCC DDD 0020H
LD HL,#00H LD EA,#FFH TCALL SUB1 TJP SUB2 * * * ORG 0080H REF AAA REF BBB REF CCC REF DDD
; ; ; ;
LD LD CALL JP
HL,#00H EA,#FFH SUB1 SUB2
2.
The following example shows how the REF instruction is executed in relation to LD instructions that have a 'redundancy effect': ORG AAA LD * * * ORG LD REF * * * REF LD SRB 0020H EA,#40H
0100H EA,#30H AAA
;
Not skipped
AAA EA,#50H 2
;
Skipped
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SAM48 INSTRUCTION SET
REF -- Reference Instruction
REF Examples: (Concluded) 3. In this example the binary code of 'REF A1' at locations 20H-21H is 20H, for 'REF A2' at locations 22H-23H, it is 21H, and for 'REF A3' at 24H-25H, the binary code is 22H :
Opcode
Symbol
Instruction ORG 0020H HL,#00H HL,#03H HL,#05H HL,#10H HL,#26H HL,#08H HL,#0FH HL,#0F0H HL,#067H SUB1 SUB2
83 83 83 83 83 83 83 83 83 41 01
00 03 05 10 26 08 0F F0 67 0B 0D
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11
LD LD LD LD LD LD LD LD LD TCALL TJP * * * ORG REF REF REF REF REF REF REF REF REF REF REF
0100H A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 ; ; ; ; ; ; ; ; ; ; ; LD LD LD LD LD LD LD LD LD CALL JP HL,#00H HL,#03H HL,#05H HL,#10H HL,#26H HL,#08H HL,#0FH HL,#0F0H HL,#067H SUB1 SUB2
20 21 22 23 24 25 26 27 30 31 32
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SAM48 INSTRUCTION SET
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RET -- Return From Subroutine
RET Operation: Operand - Operation Summary Return from subroutine Bytes 1 Cycles 3
Description:
RET pops the PC values successively from the stack, incrementing the stack pointer by six. Program execution continues from the resulting address, generally the instruction immediately following a CALL or CALLS. Operand - 1 1 0 Binary Code 0 0 1 0 1 Operation Notation PC13-8 (SP + 1) (SP) PC7-0 (SP + 3) (SP + 2) EMB,ERB (SP + 4) SP SP + 6
Example:
The stack pointer contains the value 0FAH. RAM locations 0FAH, 0FBH, 0FCH, and 0FDH contain 1H, 0H, 5H, and 2H, respectively. The instruction RET leaves the stack pointer with the new value of 00H and program execution continues from location 0125H. During a return from subroutine, PC values are popped from stack locations as follows:
SP SP + 1 SP + 2 SP + 3 SP + 4 SP + 5 SP + 6
(0FAH) (0FBH) (0FCH) (0FDH) (0FEH) (0FFH) (000H) 0 0 0
PC11 - PC8 0 PC13 PC12
PC3 - PC0 PC7 - PC4 0 0 EMB 0 ERB 0
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SAM48 INSTRUCTION SET
RRC -- Rotate Accumulator Right through Carry
RRC Operation: A Operand A Operation Summary Rotate right through carry bit Bytes 1 Cycles 1
Description:
The four bits in the accumulator and the carry flag are together rotated one bit to the right. Bit 0 moves into the carry flag and the original carry value moves into the bit 3 accumulator position.
3 C 0
Operand A 1 0 0
Binary Code 0 1 0 0 0
Operation Notation C A.0, A3 C A.n-1 A.n (n = 1, 2, 3)
Example:
The accumulator contains the value 5H (0101B) and the carry flag is cleared to logic zero. The instruction RRC A
leaves the accumulator with the value 2H (0010B) and the carry flag set to logic one. NOTE The number of memory bank selected by SMB may change for different devices in the SAM48 product family.
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SBC -- Subtract With Carry
SBC Operation: dst,src Operand A,@HL EA,RR RRb,EA Operation Summary Subtract indirect data memory from A with carry Subtract register pair (RR) from EA with carry Subtract EA from register pair (RRb) with carry Bytes 1 2 2 Cycles 1 2 2
Description:
SBC subtracts the source and carry flag value from the destination operand, leaving the result in the destination. SBC sets the carry flag if a borrow is needed for the most significant bit; otherwise it clears the carry flag. The contents of the source are unaffected. If the carry flag was set before the SBC instruction was executed, a borrow was needed for the previous step in multiple precision subtraction. In this case, the carry bit is subtracted from the destination along with the source operand. Operand A,@HL EA,RR 0 1 1 RRb,EA 1 1 0 1 1 1 1 1 0 0 0 0 Binary Code 1 1 0 1 0 1 1 1 1 0 1 1 r2 1 r2 0 0 r1 0 r1 0 0 0 0 0 C,RRb RRb - EA - C Operation Notation C,A A - (HL) - C C, EA EA -RR - C
Examples:
1.
The extended accumulator contains the value 0C3H, register pair HL the value 0AAH, and the carry flag is set to "1": SCF SBC JPS ; C "1" ; EA 0C3H - 0AAH - 1H, C "0" ; Jump to XXX; no skip after SBC
EA,HL XXX
2.
If the extended accumulator contains the value 0C3H, register pair HL the value 0AAH, and the carry flag is cleared to "0": RCF SBC JPS ; C "0" ; EA 0C3H - 0AAH - 0H = 19H, C "0" ; Jump to XXX; no skip after SBC
EA,HL XXX
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SBC -- Subtract with Carry
SBC Examples: (Continued) 3. If SBC A,@HL is followed by an ADS A,#im, the SBC skips on 'no borrow' to the instruction immediately after the ADS. An 'ADS A,#im' instruction immediately after the 'SBC A,@HL' instruction does not skip even if an overflow occurs. This function is useful for decimal adjustment operations. 8 - 6 decimal addition (the contents of the address specified by the HL register is 6H): RCF LD SBC ADS JPS b. ; ; ; ; C "0" A 8H A 8H - 6H - C(0) = 2H, C "0" Skip this instruction because no borrow after SBC result
a.
A,#8H A,@HL A,#0AH XXX
3 - 4 decimal addition (the contents of the address specified by the HL register is 4H): RCF LD SBC ADS ; ; ; ; ; ; C "0" A 3H A 3H - 4H - C(0) = 0FH, C "1" No skip. A 0FH + 0AH = 9H (The skip function of 'ADS A,#im' is inhibited after a 'SBC A,@HL' instruction even if an overflow occurs.)
A,#3H A,@HL A,#0AH
JPS
XXX
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SBS -- Subtract
SBS Operation: dst,src Operand A,@HL EA,RR RRb,EA Operation Summary Subtract indirect data memory from A; skip on borrow Subtract register pair (RR) from EA; skip on borrow Subtract EA from register pair (RRb); skip on borrow Bytes 1 2 2 Cycles 1+S 2+S 2+S
Description:
The source operand is subtracted from the destination operand and the result is stored in the destination. The contents of the source are unaffected. A skip is executed if a borrow occurs. The value of the carry flag is not affected. Operand A,@HL EA,RR 0 1 1 RRb,EA 1 1 0 1 0 1 0 1 0 1 0 1 Binary Code 1 1 1 1 1 1 1 1 1 0 1 1 r2 1 r2 0 0 r1 0 r1 1 0 0 0 0 RRb RRb - EA; skip on borrow Operation Notation A A - (HL); skip on borrow EA EA - RR; skip on borrow
Examples:
1.
The accumulator contains the value 0C3H, register pair HL contains the value 0C7H, and the carry flag is cleared to logic zero: RCF SBS ; ; ; ; ; ; C "0" EA 0C3H - 0C7H SBS instruction skips on borrow, but carry flag value is not affected Skip because a borrow occurred Jump to YYY is executed
EA,HL
JPS JPS 2.
XXX YYY
The accumulator contains the value 0AFH, register pair HL contains the value 0AAH, and the carry flag is set to logic one: SCF SBS JPS ; ; ; ; C "1" EA 0AFH - 0AAH Jump to XXX JPS was not skipped since no "borrow" occurred after SBS
EA,HL XXX
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SCF -- Set Carry Flag
SCF Operation: Operand - Operation Summary Set carry flag to logic one Bytes 1 Cycles 1
Description:
The SCF instruction sets the carry flag to logic one, regardless of its previous value. Operand - 1 1 1 Binary Code 0 0 1 1 1 C1 Operation Notation
Example:
If the carry flag is cleared to logic zero, the instruction SCF sets the carry flag to logic one.
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SMB -- Select Memory Bank
SMB Operation: n Operand n Operation Summary Select memory bank Bytes 2 Cycles 2
Description:
The SMB instruction sets the upper four bits of a 12-bit data memory address to select a specific memory bank. The constants 0, 1, and 15 are usually used as the SMB operand to select the corresponding memory bank. All references to data memory addresses fall within the following address ranges: Please note that since data memory spaces differ for various devices in the SAM4 product family, the 'n' value of the SMB instruction will also vary. Addresses 000H-01FH 020H-0FFH N00H-NFFH Register Areas Working registers Stack and general-purpose registers General-purpose registers Display registers F80H-FFFH I/O-mapped hardware registers n (n = 1-14) 15 n (n = 1-14) 15 Bank 0 SMB 0
The enable memory bank (EMB) flag must always be set to "1" in order for the SMB instruction to execute successfully for memory bank 0 - 15. Format n 1 0 1 1 0 0 Binary Code 1 0 1 d3 1 d2 0 d1 1 d0 Operation Notation SMB n
Example:
If the EMB flag is set, the instruction SMB 0
selects the data memory address range for bank 0 (000H-0FFH) as the working memory bank.
NOTES: 1. Number of memory bank selected by SMB may change for different device in the SAM48 product family. 2. After RESET, the SMB value is zero.
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SAM48 INSTRUCTION SET
SRB -- Select Register Bank
SRB Operation: n Operand n Operation Summary Select register bank Bytes 2 Cycles 2
Description:
The SRB instruction selects one of four register banks in the working register memory area. The constant value used with SRB is 0, 1, 2, or 3. The following table shows the effect of SRB settings: ERB Setting 3 0 0 SRB Settings 2 0 1 x 0 1 0 0 0 1 1
NOTE: 'x' = not applicable.
Selected Register Bank 0 x 0 1 0 1 Always set to bank 0 Bank 0 Bank 1 Bank 2 Bank 3
The enable register bank flag (ERB) must always be set for the SRB instruction to execute successfully for register banks 0, 1, 2, and 3. In addition, if the ERB value is logic zero, register bank 0 is always selected, regardless of the SRB value. Operand n 1 0 1 1 0 0 Binary Code 1 1 1 0 1 0 0 d1 1 d0 Operation Notation SRB n (n = 0, 1, 2, 3)
Example:
If the ERB flag is set, the instruction SRB 3
selects register bank 3 (018H-01FH) as the working memory register bank.
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SRET -- Return from Subroutine and Skip
SRET Operation: Operand - Operation Summary Return from subroutine and skip Bytes 1 Cycles 3+S
Description:
SRET is normally used to return to the previously executing procedure at the end of a subroutine that was initiated by a CALL or CALLS instruction. SRET skips the resulting address, which is generally the instruction immediately after the point at which the subroutine was called. Then, program execution continues from the resulting address and the contents of the location addressed by the stack pointer are popped into the program counter. Operand - 1 1 1 Binary Code 0 0 1 0 1 Operation Notation PC13-8 (SP + 1) (SP) PC7-0 (SP + 3) (SP + 2) EMB,ERB (SP + 4) SP SP + 6
Example:
If the stack pointer contains the value 0FAH and RAM locations 0FAH, 0FBH, 0FCH, and 0FDH contain the values 1H, 0H, 5H, and 2H, respectively, the instruction SRET leaves the stack pointer with the value 00H and the program returns to continue execution at location 0125H, then skips unconditionally. During a return from subroutine, data is popped from the stack to the PC as follows:
SP SP + 1 SP + 2 SP + 3 SP + 4 SP + 5 SP + 6
(0FAH) (0FBH) (0FCH) (0FDH) (0FEH) (0FFH) (000H) 0 0 0
PC11 - PC8 0 PC13 PC12
PC3 - PC0 PC7 - PC4 0 0 EMB 0 ERB 0
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SAM48 INSTRUCTION SET
STOP -- Stop Operation
STOP Operation: Operand - Operation Summary Engage CPU stop mode Bytes 2 Cycles 2
Description:
The STOP instruction stops the system clock by setting bit 3 of the power control register (PCON) to logic one. When STOP executes, all system operations are halted with the exception of some peripheral hardware with special power-down mode operating conditions. In application programs, a STOP instruction must be immediately followed by at least three NOP instructions. This ensures an adequate time interval for the clock to stabilize before the next instruction is executed. If three or more NOP instructions are not used after STOP instruction, leakage current could be flown because of the floating state in the internal bus. Operand - 1 1 1 0 1 1 Binary Code 1 1 1 0 1 0 1 1 1 1 Operation Notation PCON.3 1
Example:
Given that bit 3 of the PCON register is cleared to logic zero, and all systems are operational, the instruction sequence STOP NOP NOP NOP sets bit 3 of the PCON register to logic one, stopping all controller operations (with the exception of some peripheral hardware). The three NOP instructions provide the necessary timing delay for clock stabilization before the next instruction in the program sequence is executed.
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VENT -- Load EMB, ERB, and Vector Address
VENTn Operation: dst Operand EMB (0,1) ERB (0,1) ADR Operation Summary Load enable memory bank flag (EMB) and the enable register bank flag (ERB) and program counter to vector address, then branch to the corresponding location. Bytes 2 Cycles 2
Description:
The VENT instruction loads the contents of the enable memory bank flag (EMB) and enable register bank flag (ERB) into the respective vector addresses. It then points the interrupt service routine to the corresponding branching locations. The program counter is loaded automatically with the respective vector addresses which indicate the starting address of the respective vector interrupt service routines. The EMB and ERB flags should be modified using VENT before the vector interrupts are acknowledged. Then, when an interrupt is generated, the EMB and ERB values of the previous routine are automatically pushed onto the stack and then popped back when the routine is completed. After the return from interrupt (IRET) you do not need to set the EMB and ERB values again. Instead, use BITR and BITS to clear these values in your program routine. The starting addresses for vector interrupts and reset operations are pointed to by the VENTn instruction. These starting addresses must be located in ROM ranges 0000H-3FFFH. Generally, the VENTn instructions are coded starting at location 0000H. The format for VENT instructions is as follows: VENTn d1,d2,ADDR
EMB d1 ("0" or "1") ERB d2 ("0" or "1") PC ADDR (address to branch n = device-specific module address code (n = 0-n) Operand EMB (0,1) ERB (0,1) ADR E M B E R B a13 Binary Code a12 a11 a10 a9 a8 Operation Notation ROM (2 x n) 7-6 EMB, ERB ROM (2 x n) 5-4 PC13, PC12 ROM (2 x n) 3-0 PC12-8 ROM (2 x n + 1) 7-0 PC7-0 (n = 0, 1, 2, 3, 4, 5, 6, 7)
a7
a6
a5
a4
a3
a2
a1
a0
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VENT -- Load EMB, ERB, and Vector Address
VENTn Example: (Continued) The instruction sequence ORG VENT0 VENT1 VENT2 VENT3 VENT4 VENT5 VENT6 VENT7 0000H 1,0,RESET 0,1,INTA 0,1,INTB 0,1,INTC 0,1,INTD 0,1,INTE 0,1,INTF 0,1,INTG
causes the program sequence to branch to the RESET routine labeled RESET, setting EMB to "1" and ERB to "0" when RESET is activated. When a basic timer interrupt is generated, VENT1 causes the program to branch to the basic timer's interrupt service routine, INTA, and to set the EMB value to "0" and the ERB value to "1". VENT2 then branches to INTB, VENT3 to INTC, and so on, setting the appropriate EMB and ERB values.
NOTE: the The number of VENTn interrupt names used in the examples above may change for different devices in SAM48 product family.
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XCH -- Exchange A or EA with Nibble or Byte
XCH Operation: dst,src Operand A,DA A,Ra A,@RRa EA,DA EA,RRb EA,@HL Operation Summary Exchange A and data memory contents Exchange A and register (Ra) contents Exchange A and indirect data memory Exchange EA and direct data memory contents Exchange EA and register pair (RRb) contents Exchange EA and indirect data memory contents Bytes 2 1 1 2 2 2 Cycles 2 1 1 2 2 2
Description:
The instruction XCH loads the accumulator with the contents of the indicated destination variable and writes the original contents of the accumulator to the source. Operand A,DA 0 a7 A,Ra A,@RRa EA,DA 0 0 1 a7 EA,RRb 1 1 EA,@HL 1 0 1 a6 1 1 1 a6 1 1 1 0 1 a5 1 1 0 a5 0 1 0 0 Binary Code 1 a4 0 1 0 a4 1 0 1 0 1 a3 1 1 1 a3 1 0 1 0 0 a2 r2 i2 1 a2 1 r2 1 0 0 a1 r1 i1 1 a1 0 r1 0 0 1 a0 r0 i0 1 a0 0 0 0 1 A (HL), E (HL + 1) EA RRb A Ra A (RRa) A DA,E DA + 1 Operation Notation A DA
Example:
Double register HL contains the address 20H. The accumulator contains the value 3FH (00111111B) and internal RAM location 20H the value 75H (01110101B). The instruction XCH EA,@HL
leaves RAM location 20H with the value 3FH (00111111B) and the extended accumulator with the value 75H (01110101B).
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XCHD -- Exchange and Decrement
XCHD Operation: dst,src Operand A,@HL Operation Summary Exchange A and data memory contents; decrement contents of register L and skip on borrow Bytes 1 Cycles 2+S
Description:
The instruction XCHD exchanges the contents of the accumulator with the RAM location addressed by register pair HL and then decrements the contents of register L. If the content of register L is 0FH, the next instruction is skipped. The value of the carry flag is not affected. Operand A,@HL 0 1 1 Binary Code 1 1 0 1 1 Operation Notation A (HL), then L L-1; skip if L = 0FH
Example:
Register pair HL contains the address 20H and internal RAM location 20H contains the value 0FH: LD HL,#20H LD A,#0H XCHD JPS JPS YYY XCHD * * *
A,@HL XXX YYY A,@HL
; A 0FH and L L - 1, (HL) "0" ; Skipped since a borrow occurred ; H 2H, L 0FH ; (2FH) 0FH, A (2FH), L L - 1 = 0EH
The 'JPS YYY' instruction is executed since a skip occurs after the XCHD instruction.
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XCHI -- Exchange and Increment
XCHI Operation: dst,src Operand A,@HL Operation Summary Exchange A and data memory contents; increment contents of register L and skip on overflow Bytes 1 Cycles 2+S
Description:
The instruction XCHI exchanges the contents of the accumulator with the RAM location addressed by register pair HL and then increments the contents of register L. If the content of register L is 0H, a skip is executed. The value of the carry flag is not affected. Operand A,@HL 0 1 1 Binary Code 1 1 0 1 0 Operation Notation A (HL), then L L+1; skip if L = 0H
Example:
Register pair HL contains the address 2FH and internal RAM location 2FH contains 0FH: LD LD XCHI JPS JPS YYY HL,#2FH A,#0H A,@HL XXX ; YYY XCHI * * * A,@HL
; A 0FH and L L + 1 = 0, (HL) "0" Skipped since an overflow occurred ; H 2H, L 0H ; (20H) 0FH, A (20H), L L + 1 = 1H
The 'JPS YYY' instruction is executed since a skip occurs after the XCHI instruction.
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XOR -- Logical Exclusive OR
XOR Operation: dst,src Operand A,#im A,@HL EA,RR RRb,EA Operation Summary Exclusive-OR immediate data to A Exclusive-OR indirect data memory to A Exclusive-OR register pair (RR) to EA Exclusive-OR register pair (RRb) to EA Bytes 2 1 2 2 Cycles 2 1 2 2
Description:
XOR performs a bitwise logical XOR operation between the source and destination variables and stores the result in the destination. The source contents are unaffected. Operand A,#im 1 0 A,@HL EA,RR 0 1 0 RRb,EA 1 0 1 0 0 1 0 1 0 0 1 1 0 1 0 1 Binary Code 1 1 1 1 1 1 1 1 d3 1 1 0 1 0 1 d2 0 1 r2 1 r2 0 d1 1 0 r1 0 r1 1 d0 1 0 0 0 0 RRb RRb XOR EA A A XOR (HL) EA EA XOR (RR) Operation Notation A A XOR im
Example:
If the extended accumulator contains 0C3H (11000011B) and register pair HL contains 55H (01010101B), the instruction XOR EA,HL
leaves the value 96H (10010110B) in the extended accumulator.
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OSCILLATOR CIRCUITS
6
OVERVIEW
-- Basic timer -- Watch timer
OSCILLATOR CIRCUITS
The S3C72Q5 microcontroller has two oscillator circuits: a main-system clock circuit, and a sub-system clock circuit. The CPU and peripheral hardware operate on the system clock frequency supplied through these circuits. Specifically, a clock pulse is required by the following peripheral modules: -- LCD controller -- Timer/counter 0 -- Timer/counter 1 -- Clock output circuit CPU Clock Notation In this document, the following notation is used for descriptions of the CPU clock: fx Main-system clock
fxt Sub-system clock fxx Selected system clock Clock Control Registers When the system clock mode control register SCMOD and the power control register PCON registers are both cleared to zero after RESET, the normal CPU operating mode is enabled, a main-system clock of fx/64 is selected, and main-system clock oscillation is initiated. The power control register, PCON, is used to select normal CPU operating mode or one of two power-down modes -- stop or idle. Bits 3 and 2 of the PCON register can be manipulated by a STOP or IDLE instruction to engage stop or idle power-down mode. The system clock mode control register, SCMOD, lets you select the main-system clock (fx) or a sub-system clock (fxt) as the CPU clock and to start (or stop) main-system clock oscillation. The resulting clock source, either mainsystem clock or sub-system clock, is referred to as the selected system clock (fxx). The main-system clock is selected and oscillation started when all SCMOD bits are cleared to logic zero. By setting SCMOD.3 and SCMOD.0 to different values, you can select a sub-system clock source and start or stop mainsystem clock oscillation. To stop main-system clock oscillation, you must use the STOP instruction (assuming the main-system clock is selected) or manipulate SCMOD.3 to "1" (assuming the sub-system clock is selected). The main-system clock frequencies can be divided by 4, 8, or 64 and a sub-system clock frequencies can only be divided by 4. By manipulating PCON bits 1 and 0, you select one of the following frequencies as the CPU Clock, fx/4, fxt/4, fx/8, fx/64.
6-1
OSCILLATOR CIRCUITS
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Using a Sub-system Clock If a sub-system clock is being used as the selected system clock, the idle power-down mode can be initiated by executing an IDLE instruction. Since the sub-system clock source cannot be stopped internally, you cannot, however, use a STOP instruction to enable the stop power-down mode. The watch timer, buzzer and LCD display operate normally with a sub-system clock source, since they operate at very low speed (as low as 122 s at 32.768 kHz) and with very low power consumption.
Main-system Oscillator Circuit
fx
fxt
Sub-system Oscillator Circuit
Watch Timer LCD Controller
Selector XIN XOUT fxx Oscillator Stop
Oscillator Stop XTIN XTOUT
1/1-1/4096 Frequency dividing Circuit 1/2 1/16 Basic Timer Watch Timer LCD Controller Clock Output Circuit Timer/Counter 0/1
SCMOD.3 SCMOD.0 SCMOD.2 Selector fx/1, 2, 16 fxt Selector
1/4 PCON.0 PCON.1 Idle Stop PCON.2 PCON.3 Oscillator Control Circuit Wait release signal Internal RESET signal Power down release signal fx: Main-system clock fxt: Sub-system clock fxx: Selected system clock CPU stop signal (IDLE mode) CPU Clock
PCON.3, .2 clear
Figure 6-1. Clock Circuit Diagram
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OSCILLATOR CIRCUITS
MAIN-SYSTEM OSCILLATOR CIRCUITS
SUB-SYSTEM OSCILLATOR CIRCUITS
XIN
XTIN
XOUT 32.768 kHz
XTOUT
Figure 6-2. Crystal/Ceramic Oscillator
Figure 6-5. Crystal/Ceramic Oscillator
XIN External Clock XOUT
XT IN
XT OUT
Figure 6-3. External Oscillator
Figure 6-6. External Oscillator
XIN R XOUT
Figure 6-4. RC Oscillator
6-3
OSCILLATOR CIRCUITS
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POWER CONTROL REGISTER (PCON) The power control register, PCON, is a 4-bit register that is used to select the CPU clock frequency and to control CPU operating and power-down modes. PCON can be addressed directly by 4-bit write instructions or indirectly by the instructions IDLE and STOP. FB3H PCON.3 PCON.2 PCON.1 PCON.0
PCON bits 3 and 2 are addressed by the STOP and IDLE instructions, respectively, to engage the idle and stop power-down modes. Idle and stop modes can be initiated by these instruction despite the current value of the enable memory bank flag (EMB). PCON bits 1 and 0 are used to select a specific system clock frequency. There are two basic choices: -- Main-system clock (fx) or sub-system clock (fxt); -- Divided fx/4, 8, 64 or fxt/4 clock frequency. PCON.1 and PCON.0 settings are also connected with the system clock mode control register, SCMOD. If SCMOD.0 = "0" the main-system clock is always selected by the PCON.1 and PCON.0 setting; if SCMOD.0 = "1" the sub-system clock is selected. RESET sets PCON register values (and SCMOD) to logic zero: SCMOD.3 and SCMOD.0 select the main-system clock (fx) and start clock oscillation; PCON.1 and PCON.0 divide the selected fx frequency by 64, and PCON.3 and PCON.2 enable normal CPU operating mode. Table 6-1. Power Control Register (PCON) Organization PCON Bit Settings PCON.3 0 0 1 PCON.2 0 1 0 Normal CPU operating mode Idle power-down mode Stop power-down mode Resulting CPU Operating Mode
PCON Bit Settings PCON.1 0 1 1 PCON.0 0 0 1
Resulting CPU Clock Frequency If SCMOD.0 = "0" fx/64 fx/8 fx/4 If SCMOD.0 = "1" fxt/4
F PROGRAMMING TIP -- Setting the CPU Clock
To set the CPU clock to 0.95 s at 4.19 MHz: BITS SMB LD LD EMB 15 A,#3H PCON,A
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OSCILLATOR CIRCUITS
INSTRUCTION CYCLE TIMES The unit of time that equals one machine cycle varies depending on whether the main-system clock (fx) or a subsystem clock (fxt) is used, and on how the oscillator clock signal is divided (by 4, 8, or 64). Table 6-2 shows corresponding cycle times in microseconds. Table 6-2. Instruction Cycle Times for CPU Clock Rates Selected CPU Clock fx/64 fx/8 fx/4 fxt/4 Resulting Frequency 65.5 kHz 524.0 kHz 1.05 MHz 8.19 kHz fxt = 32.768 kHz fx = 4.19 MHz Oscillation Source Cycle Time (sec) 15.3 1.91 0.95 122.0
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SYSTEM CLOCK MODE REGISTER (SCMOD) The system clock mode register, SCMOD, is a 4-bit register that is used to select the CPU clock and to control main and sub-system clock oscillation. The SCMOD is mapped to the RAM address FB7H. The main clock oscillation is stopped by setting SCMOD.3 when the clock source is subsystem clock and subsystem clock can be stopped by setting SCMOD.2 when the clock source is main system clock. SCMOD.0, SCMOD.3 cannot be simultaneously modified. The subsystem clock is stopped only by setting SCMOD.2, and PCON which revokes stop mode cannot stop the subsystem clock. The stop of subsystem clock is released by RESET when the selected system clock is main system clock or subsystem clock and is released by setting SCMOD.2 when the selected system clock is main system clock. RESET clears all SCMOD values to logic zero, selecting the main system clock (fx) as the CPU clock and starting clock oscillation. The reset value of the SCMOD is "0" SCMOD.0, SCMOD.2, and SCMOD.3 bits can be manipulated by 1-bit write instructions (In other words, SCMOD.0, SCMOD.2, and SCMOD.3 cannot be modified simultaneously by a 4-bit write). Bit 1 is always logic zero. FB7H SCMOD.3 SCMOD.2 "0" SCMOD.0
A subsystem clock (fxt) can be selected as the system clock by manipulating the SCMOD.3 and SCMOD.0 bit settings. If SCMOD.3 = "0" and SCMOD.0 = "1", the subsystem clock is selected and main system clock oscillation continues. If SCMOD.3 = "1" and SCMOD.0 = "1", fxt is selected, but main system clock oscillation stops. Even if you have selected fx as the CPU clock, setting SCMOD.3 to "1" will stop main system clock oscillation, and malfunction may be occured. To operate safely, main system clock should be stopped by a stop instruction is main system clock mode. Table 6-3. System Clock Mode Register (SCMOD) Organization SCMOD Register Bit Settings SCMOD.3 0 0 1 SCMOD.0 0 1 1 Resulting Clock Selection CPU Clock Source fx fxt fxt fx Oscillation On On Off
SCMOD.2 0 1
NOTE:
Sub-oscillation on/off Enable sub system clock Disable sub system clock
You can use SCMOD.2 as follows (ex; after data bank was used, a few minutes have passed): Main operation sub-operation sub-idle (LCD on, after a few minutes later without any external input) suboperation main operation SCMOD.2 = 1 main stop mode (LCD off).
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OSCILLATOR CIRCUITS
Table 6-4. Main Oscillation Stop Mode Mode Main Oscillation STOP Mode Condition Main oscillator runs. Sub oscillator runs (stops). System clock is the main oscillation clock. Method to issue Osc Stop STOP instruction: Main oscillator stops. CPU is in idle mode. Sub oscillator still runs (stops). Osc Stop Release Source (2) Interrupt and RESET: After releasing stop mode, main oscillation starts and oscillation stabilization time is elapsed. And then the CPU operates. Oscillation stabilization time is 1/ {256 x BT clock (fx)}. RESET: Interrupt can't start the main oscillation. Therefore, the CPU operation can never be restarted. BT overflow, interrupt, and RESET: After the overflow of basic timer [1/ {256 x BT clock (fxt)}], CPU operation and main oscillation automatically start. Set SCMOD.3 to "0" or RESET
When SCMOD.3 is set to "1" (1), main oscillator stops, halting the CPU operation. Sub oscillator still runs (stops). Main oscillator runs. Sub oscillator runs. System clock is the sub oscillation clock. STOP instruction (1): Main oscillator stops. CPU is in idle mode. Sub oscillator still runs (stops). Sub oscillator still runs. When SCMOD.3 is set to "1", main oscillator stops. The CPU, however, would still operate. Sub oscillator still runs. Sub Oscillation STOP Mode Main oscillator runs. Sub oscillator runs. System clock is the main oscillation clock. Main oscillator runs (stops). Sub oscillator runs. System clock is the sub oscillation clock. When SCMOD.2 to "1", sub oscillator stops, while main oscillator and the CPU would still operate. When SCMOD.2 to "1", sub oscillator stops, halting the CPU operation. Main oscillator still runs (stops).
Set SCMOD.2 to "0" or RESET
RESET
NOTES: 1. This mode must not be used. 2. Oscillation stabilization time by interrupt is 1/(256 x BT clocks). Oscillation stabilization time by a reset is 31.3ms at 4.19 MHz, main oscillation clock.
6-7
OSCILLATOR CIRCUITS
S3C72Q5/P72Q5
SWITCHING THE CPU CLOCK Together, bit settings in the power control register, PCON, and the system clock mode register, SCMOD, determine whether a main system or a subsystem clock is selected as the CPU clock, and also how this frequency is to be divided. This makes it possible to switch dynamically between main and subsystem clocks and to modify operating frequencies. SCMOD.3, SCMOD.2, and SCMOD.0 select the main system clock (fx) or a subsystem clock (fxt) and start or stop main system and sub system clock oscillation. PCON.1 and PCON.0 control the frequency divider circuit, and divide the selected fx clock by 4, 8, or 64,or fxt clock by 4. NOTE A clock switch operation does not go into effect immediately when you make the SCMOD and PCON register modifications -- the previously selected clock continues to run for a certain number of machine cycles. For example, you are using the default CPU clock (normal operating mode and a main system clock of fx/64) and you want to switch from the fx clock to a subsystem clock and to stop the main system clock. To do this, you first need to set SCMOD.0 to "1". This switches the clock from fx to fxt but allows main system clock oscillation to continue. Before the switch actually goes into effect, a certain number of machine cycles must elapse. After this time interval, you can then disable main system clock oscillation by setting SCMOD.3 to "1". This same 'stepped' approach must be taken to switch from a subsystem clock to the main system clock: first, clear SCMOD.3 to "0" to enable main system clock oscillation. Then, after a certain number of machine cycles has elapsed, select the main system clock by clearing all SCMOD values to logic zero. Following a RESET, CPU operation starts with the lowest main system clock frequency of 15.3 s at 4.19 MHz after the standard oscillation stabilization interval of 31.3 ms has elapsed. Table 6-5 details the number of machine cycles that must elapse before a CPU clock switch modification goes into effect. Table 6-5. Elapsed Machine Cycles During CPU Clock Switch
AFTER BEFORE PCON.1 = 0 PCON.0 = 0 SCMOD.0 = 0 PCON.1 = 1 PCON.0 = 0 PCON.1 = 1 PCON.0 = 1 SCMOD.0 = 1 PCON.1 = 0 PCON.0 = 0 SCMOD.0 = 0 PCON.1 = 1 PCON.0 = 0 PCON.1 = 1 PCON.0 = 1 SCMOD.0 = 1
N/A
1 MACHINE CYCLE
1 MACHINE CYCLE
N/A
8 MACHINE CYCLES
N/A
1 MACHINE CYCLES
N/A
16 MACHINE CYCLES
1 MACHINE CYCLES
N/A
fx / 4fxt
N/A
N/A
1MACHINE CYCLES
N/A
NOTES: 1. Even if oscillation is stopped by setting SCMOD.3 during main system clock operation, the stop mode is not entered. 2. Since the XIN input is connected internally to VSS to avoid current leakage due to the crystal oscillator in stop mode, do 3. 4. 5. not set SCMOD.3 to "1" or do not use stop instruction when an external clock is used as the main system clock. When the system clock is switched to the subsystem clock, it is necessary to disable any interrupts which may occur during the time intervals shown in Table 6 -5. 'N/A' means 'not available'. fx: Main-system clock, fxt: Sub-system clock. When fx is 4.19 MHz, and fxt is 32.768 kHz.
6-8
S3C72Q5/P72Q5
OSCILLATOR CIRCUITS
F
PROGRAMMING TIP -- Switching Between Main-system and Sub-system Clock
1. Switch from the main-system clock to the sub-system clock: MA2SUB BITS CALL BITS RET LD NOP NOP DECS JR RET SCMOD.0 DLY80 SCMOD.3 A,#0FH ; Switches to sub-system clock ; Delay 80 machine cycles ; Stop the main-system clock
DLY80 DEL1
A DEL1
2. Switch from the sub-system clock to the main-system clock: SUB2MA BITR CALL CALL BITR RET SCMOD.3 DLY80 DLY80 SCMOD.0 ; Start main-system clock oscillation ; Delay 80 machine cycles ; Switch to main-system clock
6-9
OSCILLATOR CIRCUITS
S3C72Q5/P72Q5
CLOCK OUTPUT MODE REGISTER (CLMOD) The clock output mode register, CLMOD, is a 4-bit register that is used to enable or disable clock output to the CLO pin and to select the CPU clock source and frequency. CLMOD is addressable by 4-bit write instructions only. FD0H CLMOD.3 "0" CLMOD.1 CLMOD.0
RESET clears CLMOD to logic zero, which automatically selects the CPU clock as the clock source (without initiating clock oscillation), and disables clock output. CLMOD.3 is the enable/disable clock output control bit; CLMOD.1 and CLMOD.0 are used to select one of four possible clock sources and frequencies: normal CPU clock, fxx/8, fxx/16, or fxx/64. Table 6-6. Clock Output Mode Register (CLMOD) Organization CLMOD Bit Settings CLMOD.1 0 0 1 1 CLMOD.0 0 1 0 1 Clock Source CPU clock (fx/4, fx/8, fx/64, fxt/4) fxx/8 fxx/16 fxx/64 Resulting Clock Output Frequency 1.05MHz,524kHz,65.5kHz or 8.19kHz 523.8 kHz 261.9 kHz 65.5 kHz
CLMOD.3 0 1
Result of CLMOD.3 Setting Disable clock output at the CLO pin. Enable clock output at the CLO pin.
NOTES: 1. fx : Main-system clock 2. fxt: Sub-system clock 3. Frequencies assume that fxx, fx = 4,19MHz, and fxt = 32.768kHz
6-10
S3C72Q5/P72Q5
OSCILLATOR CIRCUITS
CLOCK OUTPUT CIRCUIT The clock output circuit, used to output clock pulses to the CLO pin, has the following components: -- 4-bit clock output mode register (CLMOD) -- Clock selector -- Port mode flag -- CLO output pin
CLMOD.3 CLMOD.2 4 CLMOD.1 CLMOD.0 CLOCK SELECTOR P5.3 Latch CLO
PM5.3
CLOCKS (CPU clock, fxx/8, fxx/16, fxx/64)
Figure 6-7. CLO Output Pin Circuit Diagram
CLOCK OUTPUT PROCEDURE The procedure for outputting clock pulses to the CLO pin may be summarized as follows: 1. 2. 3. 4. 5. Disable clock output by clearing CLMOD.3 to logic zero. Set the clock output frequency (CLMOD.1, CLMOD.0). Load a "0" to the output latch of the CLO pin. Set the port mode flag to output mode. Enable clock output by setting CLMOD.3 to logic one.
F
PROGRAMMING TIP -- CPU Clock Output to the CLO Pin
To output the CPU clock to the CLO pin: BITS SMB LD LD BITR LD LD EMB 15 EA,#80H PMG1,EA P5.3 A,#8H CLMOD,A
; P5.3 ? Output mode ; Clear the CLO pin output latch
6-11
S3C72Q5/P72Q5
INTERRUPTS
7
OVERVIEW
INTERRUPTS
The S3C72Q5's interrupt control circuit has five functional components: -- Interrupt enable flags (IEx) -- Interrupt request flags (IRQx) -- Interrupt master enable register (IME) -- Interrupt priority register (IPR) -- Power-down release signal circuit Three kinds of interrupts are supported: -- Internal interrupts generated by on-chip processes -- External interrupts generated by external peripheral devices -- Quasi-interrupts used for edge detection and as clock sources
Table 7-1. Interrupt Types and Corresponding Port Pin(s) Interrupt Type External interrupts Internal interrupts Quasi-interrupts Interrupt Name INT0, INT1, INTP0 INTB, INTT0, INTT1 INT2 INTW Corresponding Port Pins P4.2, P4.3, P0 (K0-K3) Not applicable P6, P7 (KS0-KS7) Not applicable
7-1
INTERRUPTS
S3C72Q5/P72Q5
VECTORED INTERRUPTS Interrupt requests may be processed as vectored interrupts in hardware, or they can be generated by program software. A vectored interrupt is generated when the following flags and register settings, corresponding to the specific interrupt (INTn) are set to logic one: -- Interrupt enable flag (IEx) -- Interrupt master enable flag (IME) -- Interrupt request flag (IRQx) -- Interrupt status flags (IS0, IS1) -- Interrupt priority register (IPR) If all conditions are satisfied for the execution of a requested service routine, the start address of the interrupt is loaded into the program counter and the program starts executing the service routine from this address. EMB and ERB flags for RAM memory banks and registers are stored in the vector address area of the ROM during interrupt service routines. The flags are stored at the beginning of the program with the VENT instruction. The initial flag values determine the vectors for resets and interrupts. Enable flag values are saved during the main routine, as well as during service routines. Any changes that are made to enable flag values during a service routine are not stored in the vector address. When an interrupt occurs, the EMB and ERB values before the interrupt is initiated are saved along with the program status word (PSW), and the EMB and the ERB flag for the interrupt are fetched from the respective vector address. Then, if necessary, you can modify the enable flags during the interrupt service routine. When the interrupt service routine is returned to the main routine by the IRET instruction, the original values saved in the stack are restored and the main program continues program execution with these values. Software-Generated Interrupts To generate an interrupt request from software, the program manipulates the appropriate IRQx flag. When the interrupt request flag value is set, it is retained until all other conditions for the vectored interrupt have been met, and the service routine can be initiated. Multiple Interrupts By manipulating the two interrupt status flags (IS0 and IS1), you can control service routine initialization and thereby process multiple interrupts simultaneously. If more than four interrupts are being processed at one time, you can avoid possible loss of working register data by using the PUSH RR instruction to save register contents to the stack before the service routines are executed in the same register bank. When the routines have executed successfully, you can restore the register contents from the stack to working memory by using the POP instruction. Power-Down Mode Release An interrupt can be used to release power-down mode (stop or idle). Interrupts for power-down mode release are initiated by setting the corresponding interrupt enable flag. Even if the IME flag is cleared to zero, power-down mode will be released by an interrupt request signal when the interrupt enable flag has been set. In such cases, the interrupt routine will not be executed since IME = "0".
7-2
S3C72Q5/P72Q5
INTERRUPTS
Interrupt is generated (INT xx)
Request flag (IRQx)
1 No
IEx = 1?
Retain value until IEx = 1
Generate corresponding vector interrupt and release power-down mode No
IME = 1? Yes Yes IS1, 0 = 0, 0? No IS1, 0 = 0, 1? Yes High-priority interrupt ? Yes IS1, 0 = 1, 0 IS1, 0 = 1, 0
Retain value until IME = 1
Retain value until interrupt service routine is completed No
No
Store contents of PC and PSW in the stack area and the contents of PC are set by the contents to corresponding vector address
The corresponding IRQx is automatically reset
Jump to interrupt start address
Figure 7-1. Interrupt Execution Flowchart
7-3
INTERRUPTS
S3C72Q5/P72Q5
IMOD0 IE2 IMOD1 INTB INT0 INT1 @ K0-K6 INTT0 INTT1 INTW KS0-KS7 Selector @ IRQB IRQ0 IRQ1 IRQP0 IRQT0 IRQT1 IRQW IRQ2 IEW IET1 IET0 IEP0 IE1 IE0 IEB
IMOD2
Power-Down Mode Release Signal IME IPR Interrupt Control Unit IS1 IS0
@ = Edge Detection Circuit
Vector Interrupt Generator
Figure 7-2. Interrupt Control Circuit Diagram
7-4
S3C72Q5/P72Q5
INTERRUPTS
MULTIPLE INTERRUPTS The interrupt controller can serve multiple interrupts in two ways: as two-level interrupts, where either all interrupt requests or only those of highest priority are serviced, or as multi-level interrupts, when the interrupt service routine for a lower-priority request is accepted during the execution of a higher priority routine. Two-Level Interrupt Handling Two-level interrupt handling is the standard method for processing multiple interrupts. When the IS1 and IS0 bits of the PSW (FB0H.3 and FB0H.2, respectively) are both logic zero, program execution mode is normal and all interrupt requests are serviced (see Figure 7-3). Whenever an interrupt request is accepted, IS1 and IS0 are incremented by one, and the values are stored in the stack along with the other PSW bits. After the interrupt routine has been serviced, the modified IS1 and IS0 values are automatically restored from the stack by an IRET instruction. IS0 and IS1 can be manipulated directly by 1-bit write instructions, regardless of the current value of the enable memory bank flag (EMB). Before you can modify an interrupt service flag, however, you must first disable interrupt processing with a DI instruction. When IS1 = "0" and IS0 = "1", all interrupt service routines are inhibited except for the highest priority interrupt currently defined by the interrupt priority register (IPR).
Normal Program Processing (Status 0) INT Disable Set IPR INT Enable Low or High Level Interrupt Generated
High or Low Level Interrupt Processing (Status 1) High Level Interrupt Processing (Status 2)
High Level Interrupt Generated
Figure 7-3. Two-Level Interrupt Handling
7-5
INTERRUPTS
S3C72Q5/P72Q5
Multi-Level Interrupt Handling With multi-level interrupt handling, a lower-priority interrupt request can be executed while a high-priority interrupt is being serviced. This is done by manipulating the interrupt status flags, IS0 and IS1 (see Table 7-2). When an interrupt is requested during normal program execution, interrupt status flags IS0 and IS1 are set to "1" and "0", respectively. This setting allows only highest-priority interrupts to be serviced. When a high-priority request is accepted, both interrupt status flags are then cleared to "0" by software so that a request of any priority level can be serviced. In this way, the high- and low-priority requests can be serviced in parallel (see Figure 7-4). Table 7-2. IS1 and IS0 Bit Manipulation for Multi-Level Interrupt Handling Process Status Before INT IS1 0 1 2 - 0 0 1 1 IS0 0 1 0 1 All interrupt requests are serviced. Only high-priority interrupts as determined by the current settings in the IPR register are serviced. No additional interrupt requests will be serviced. Value undefined Effect of ISx Bit Setting After INT ACK IS1 0 1 - - IS0 1 0 - -
Normal Program Processing (Status 0) INT Disable Set IPR INT Enable Low or High Level Interrupt Generated
Single Interrupt 2-Level Interrupt
INT Disable Modify Status INT Enable Low or High Level Interrupt Generated
Status 1
3-Level Interrupt
Status 0 High Level Interrupt Generated Status 1 Status 2
Status 0
Figure 7-4. Multi-Level Interrupt Handling
7-6
S3C72Q5/P72Q5
INTERRUPTS
INTERRUPT PRIORITY REGISTER (IPR) The 4-bit interrupt priority register (IPR) is used to control multi-level interrupt handling and its reset value is logic zero. Before the IPR can be modified by 4-bit write instructions, all interrupts must first be disabled by a DI instruction. FB2H IME IPR.2 IPR.1 IPR.0
By manipulating the IPR settings, you can choose to process all interrupt requests with the same priority level, or you can select one type of interrupt for high-priority processing. A low-priority interrupt can itself be interrupted by a high-priority interrupt, but not by another low-priority interrupt. A high-priority interrupt cannot be interrupted by any other interrupt source. Table 7-3. Standard Interrupt Priorities Interrupt INTB INT0 INT1 INTP0 INTT0 INTT1 Default Priority 1 2 3 4 5 6
The MSB of the IPR, the interrupt master enable flag (IME), enables and disables all interrupt processing. Even if an interrupt request flag and its corresponding enable flag are set, a service routine cannot be executed until the IME flag is set to logic one. The IME flag can be directly manipulated by EI and DI instructions, regardless of the current enable memory bank (EMB) value. Table 7-4. Interrupt Priority Register Settings IPR.2 0 0 0 0 1 1 1 1
NOTE:
IPR.1 0 0 1 1 0 0 1 1
IPR.0 0 1 0 1 0 1 0 1
Result of IPR Bit Setting Normal interrupt handling according to default priority settings. Process INTB interrupt at highest priority Process INT0 interrupt at highest priority Process INT1 interrupt at highest priority Process INTP0 interrupt at highest priority Process INTT0 interrupt at highest priority Process INTT1 interrupt at highest priority N/A
During normal interrupt processing, interrupts are processed in the order in which they occur. If two or more interrupt requests are received simultaneously, the priority level is determined according to the standard interrupt priorities in Table 7-3 (the default priority assigned by hardware when the lower three IPR bits = "0"). In this case, the higher-priority interrupt request is serviced and the other interrupt is inhibited. Then, when the high-priority interrupt is returned from its service routine by an IRET instruction, the inhibited service routine is started.
7-7
INTERRUPTS
S3C72Q5/P72Q5
F
PROGRAMMING TIP -- Setting The INT Interrupt Priority
The following instruction sequence sets the INT1 interrupt to high priority: BITS SMB DI LD LD EI EMB 15 ; IPR.3 (IME) 0 A,#3H IPR,A ; IPR.3 (IME) 1
EXTERNAL INTERRUPT 0 and 1 MODE REGISTERS (IMOD0, IMOD1) The following components are used to process external interrupts at the INT0 and INT1 pin: -- Edge detection circuit -- Two mode registers, IMOD0 and IMOD1 The mode registers are used to control the triggering edge of the input signal. IMOD0 and IMOD1 settings let you choose either the rising or falling edge of the incoming signal as the interrupt request trigger. FB4H FB5H "0" "0" "0" "0" IMOD0.1 IMOD1.1 IMOD0.0 IMOD1.0
IMOD0 and IMOD1 are addressable by 4-bit write instructions. RESET clears all IMOD values to logic zero, selecting rising edges as the trigger for incoming interrupt requests. Table 7-5. IMOD0 and IMOD1 Register Organization IMODx "0" "0" IMODx.1 0 0 1 1
NOTE: "x" means "0" or "1"
IMODx.0 0 1 0 1
Effect of IMOD Settings Rising edge detection Falling edge detection Both rising and falling edge detection IRQ0 flag cannot be set to "1"
7-8
S3C72Q5/P72Q5
INTERRUPTS
EXTERNAL INTERRUPT 0 AND 1 MODE REGISTERS (Continued) -- You can use INT0/INT1 to release power-down mode
INTx
EDGE Detection
IRQx
IMODx
NOTE:
"x" is "0" or "1"
Figure 7-5. Circuit Diagram for INT0 and INT1 Pins When modifying the IMOD0 and IMOD1 registers, it is possible to accidentally set an interrupt request flag. To avoid unwanted interrupts, take these precautions when writing your programs: 1. 2. 3. 4. 5. Disable all interrupts with a DI instruction. Modify the IMOD0 or IMOD1 register. Clear all relevant interrupt request flags. Enable the interrupt by setting the appropriate IEx flag. Enable all interrupts with an EI instruction.
INT0 and INT1 are same in the function.
NOTE:
7-9
INTERRUPTS
S3C72Q5/P72Q5
EXTERNAL INTERRUPT 2 MODE REGISTER (IMOD2) To generate a key interrupt on a falling edge at KS0-KS7, all KS0-KS7 pins must be configured to input mode. IMOD2 is write-only register that can be written by 4-bit RAM control instruction only. It is mapped to the RAM address FB6H and the reset value of IMOD2 is 0. FB6H "0" IMOD2.2 IMOD2.1 IMOD2.0
When a falling edge in any one of KS0-KS7 pins is detected, IRQ2 is set and the release signal of power down mode is generated. INT2, however, does not generate a vector interrupt. Among the pins which were selected as key interrupt, one or more pins which are in input low or output low don't execute a key interrupt function. Table 7-6. IMOD2 Register Bit Settings IMOD2 0 IMOD2.2 0 0 0 0 1 IMOD2.1 0 0 1 1 0 IMOD2.0 0 1 0 1 0 Effect of IMOD2 Settings Select falling edge of KS0-KS3 Select falling edge of KS0-KS4 Select falling edge of KS0-KS5 Select falling edge of KS0-KS6 Select falling edge of KS0-KS7
P6.0/KS0 P6.1/KS1 P6.2/KS2 P6.3/KS3
P6.4/KS4
A B MUX C D S0 S1
A MUX B S Falling Edge Detection Circuit
P6.5/KS5
P6.6/KS6
P6.7/KS7 IRQ2
IMOD2.1 IMOD2.0 IMOD2.2
Figure 7-6. Circuit Diagram for INT2
7-10
S3C72Q5/P72Q5
INTERRUPTS
F
PROGRAMMING TIP -- Using INT2 as a Key Input Interrupt
When the INT2 interrupt is used as a key entry interrupt, the selected key interrupt source pin must be set to input: 1. When KS0-KS3 are selected (four pins): BITS SMB LD LD LD LD LD LD EMB 15 A,#0H IMOD2,A EA,#00H PMG2,EA A,#40H PUMOD0,A
; (IMOD2) #0H, KS0-KS3 falling edge select ; P6 input mode ; Enable P6 pull-up resistors
7-11
INTERRUPTS
S3C72Q5/P72Q5
INTERRUPT FLAGS There are three types of interrupt flags: interrupt request and interrupt enable flags that correspond to each interrupt, the interrupt master enable flag, which enables or disables all interrupt processing. Interrupt Master Enable Flag (IME) The interrupt master enable flag, IME, enables or disables all interrupt processing. Therefore, even when an IRQx flag is set and its corresponding IEx flag is enabled, the interrupt service routine is not executed until the IME flag is set to logic one. The IME flag is located in the IPR register (IPR.3). It can be directly be manipulated by EI and DI instructions, regardless of the current value of the enable memory bank flag (EMB). IME 0 1 IPR.2 IPR.1 IPR.0 Effect of Bit Settings Inhibit all interrupts Enable all interrupts
Interrupt Enable Flags (IEx) IEx flags, when set to logical one, enable specific interrupt requests to be serviced. When the interrupt request flag is set to logical one, an interrupt will not be serviced until its corresponding IEx flag is also enabled. Interrupt enable flags can be read, written, or tested directly by 1-bit instructions. IEx flags can be addressed directly at their specific RAM addresses, despite the current value of the enable memory bank (EMB) flag. Table 7-7. Interrupt Enable and Interrupt Request Flag Addresses Address FB8H FBAH FBBH FBCH FBDH FBEH FBFH Bit 3 "U" "U" "U" "U" "U" IE1 "U" Bit 2 "U" "U" "U" "U" "U" IRQ1 "U" Bit 1 IEB IEW IET1 IET0 IEP0 IE0 IE2 Bit 0 IRQB IRQW IRQT1 IRQT0 IRQP0 IRQ0 IRQ2
NOTES: 1. IEx refers to all interrupt enable flags. 2. IRQx refers to all interrupt request flags. 3. IEx = 0 is interrupt disable mode. 4. IEx = 1 is interrupt enable mode.
7-12
S3C72Q5/P72Q5
INTERRUPTS
Interrupt Request Flags (IRQx) Interrupt request flags are read/write addressable by 1-bit or 4-bit instructions. IRQx flags can be addressed directly at their specific RAM addresses, regardless of the current value of the enable memory bank (EMB) flag. When a specific IRQx flag is set to logic one, the corresponding interrupt request is generated. The flag is then automatically cleared to logic zero when the interrupt has been serviced. Exceptions are the watch timer interrupt request flags, IRQW, and the external interrupt 2 flag IRQ2, which must be cleared by software after the interrupt service routine has executed. IRQx flags are also used to execute interrupt requests from software. In summary, follow these guidelines for using IRQx flags: 1. 2. 3. IRQx is set to request an interrupt when an interrupt meets the set condition for interrupt generation. IRQx is set to "1" by hardware and then cleared by hardware when the interrupt has been serviced (with the exception of IRQW and IRQ2). When IRQx is set to "1" by software, an interrupt is generated.
Table 7-8. Interrupt Request Flag Conditions and Priorities Interrupt Source INTB INT0 INT1 INTP0 INTT0 INTT1 INT2 (note) INTW
NOTE:
Internal/ External I E E E I I E I
Pre-condition for IRQx Flag Setting Reference time interval signal from basic timer Rising or falling edge detected at INT0 pin Rising or falling edge detected at INT1 pin Falling edge detected at K0-K6 (P0.0-P1.2) Signals for TCNT0 and TREF0 registers match Signals for TCNT1 and TREF1 registers match Falling edge is detected at any of the KS0-KS7 pins Time interval of 0.5 s or 3.19 ms
Interrupt Priority 1 2 3 4 5 6 - -
IRQ Flag Name IRQB IRQ0 IRQ1 IRQP0 IRQT0 IRQT1 IRQ2 IRQW
Refer to page 7-10, 7-11.
7-13
S3C72Q5/P72Q5
POWER-DOWN
8
OVERVIEW
POWER-DOWN
The S3C72Q5 microcontroller has two power-down modes to reduce power consumption: idle and stop. Idle mode is initiated by the IDLE instruction and stop mode by the instruction STOP. (Several NOP instructions must always follow an IDLE or STOP instruction in a program.) In idle mode, the CPU clock stops while peripherals and the oscillation source continue to operate normally. When RESET occurs during normal operation or during a power-down mode, a reset operation is initiated and the CPU enters idle mode. When the standard oscillation stabilization time interval (31.3 ms at 4.19 MHz) has elapsed, normal CPU operation resumes. In stop mode, main-system clock oscillation is halted (assuming it is currently operating), and peripheral hardware components are powered-down. The effect of stop mode on specific peripheral hardware components -- CPU, basic timer, serial I/O, timer/ counters 0 and 1, watch timer, and LCD controller -- and on external interrupt requests, is detailed in Table 8-1. Idle or stop modes are terminated either by a RESET, or by an interrupt which is enabled by the corresponding interrupt enable flag, IEx. When power-down mode is terminated by RESET, a normal reset operation is executed. Assuming that both the interrupt enable flag and the interrupt request flag are set to "1", power-down mode is released immediately upon entering power-down mode. When an interrupt is used to release power-down mode, the operation differs depending on the value of the interrupt master enable flag (IME): -- If the IME flag = "0"; If the power down mode release signal is generated, after releasing the power-down mode, program execution starts immediately under the instruction to enter power down mode without execution of interrupt service routine. The interrupt request flag remains set to logic one. -- If the IME flag = "1"; If the power down mode release signal is generated, after releasing the power down mode, two instructions following the instruction to enter power down mode are executed first and the interrupt service routine is executed, finally program is resumed. However, when the release signal is caused by INT2 or INTW, the operation is identical to the IME = "0" condition because INT2 and INTW are a quasi-interrupt. NOTE Do not use stop mode if you are using an external clock source because XIN input must be restricted internally to VSS to reduce current leakage.
8-1
POWER-DOWN
S3C72Q5/P72Q5
Table 8-1. Hardware Operation During Power-Down Modes Operation Instruction System clock status STOP Stop Mode IDLE Idle Mode
STOP mode can be used only if the main-system IDLE mode can be used if the mainclock is selected as system clock (CPU clock) system clock or sub-system clock is selected as system clock (CPU clock) Main-system clock oscillation stops Only CPU clock oscillation stops (main and sub-system clock oscillation continues) Basic timer operates (with IRQB set at each reference interval) Timer/counter 0 operates Timer/counter 1 operates Watch timer operates LCD controller operates INT0, INT1, INT2 and INTP0 are acknowledged. All CPU operations are disabled Interrupt request signals are enable by an interrupt enable flag or by RESET input.
Clock oscillator
Basic timer Timer/counter 0 Timer/counter1 Watch timer LCD controller External interrupts CPU Mode release signal
Basic timer stops Operates only if TCL0 is selected as the counter clock Timer/counter1 stops Operates only if sub-system clock (fxt) is selected as the counter clock Operates only if a sub-system clock is selected as LCDCK INT0,INT1,INT2 and INTP0 are acknowledged. All CPU operations are disabled Interrupt request signals are enable by an interrupt enable flag or by RESET input.
8-2
S3C72Q5/P72Q5
POWER-DOWN
Table 8-2. System Operating Mode Comparison Mode Main operating mode Condition Main oscillator runs. Sub oscillator runs System clock is the main oscillation clock. Main oscillator runs. Sub oscillator runs System clock is the main oscillation clock. Main oscillator runs. Sub oscillator runs. System clock is the main oscillation clock. Main oscillator is stopped by SCMOD.3. Sub oscillator runs. System clock is the sub oscillation clock. Main oscillator is stopped by SCMOD.3. Sub oscillator runs. System clock is the sub oscillation clock. IDLE instruction IDLE instruction STOP/IDLE Mode Start Method - Current Consumption A
Main Idle mode
B
Main Stop mode
STOP instruction
D
Sub operating mode
-
C
Sub ldle Mode
D
NOTE:
The current consumption is: A > B > C > D
8-3
POWER-DOWN
S3C72Q5/P72Q5
IDLE MODE TIMING DIAGRAMS
Idle Istruction RESET
Oscillator Stabilization Wait Time (31.3 ms/4.19 MHz)
Normal Mode
Normal Mode
Normal Mode
Clock Signal
Normal Oscillation
Figure 8-1. Timing When Idle Mode is Released by RESET
Idle Istruction Mode Release Signal Normal Mode Idle Mode Interrupt Acknowledge (IME = 1)
Normal Mode
Clock Signal
Normal Oscillation
Figure 8-2. Timing When Idle Mode is Released by an Interrupt
8-4
S3C72Q5/P72Q5
POWER-DOWN
STOP MODE TIMING DIAGRAMS
Stop Istruction RESET
Oscillator Stabilization Wait Time (31.3 ms/4.19 MHz)
Normal Mode
Stop mode
Idle Mode
Normal Mode
Clock Signal
Oscillation Stops
Oscillation Resumes
Figure 8-3. Timing When Stop Mode is Released by RESET
Stop Istruction Mode Release signal Normal Mode Stop mode
Oscillator Stabilization Wait Time (BMOD Setting) INT Ack(Ime=1)
Idle Mode
Normal Mode
Clock Signal
Oscillation Stops
Oscillation Resumes
Figure 8-4. Timing When Stop Mode is Released by an Interrupt
8-5
POWER-DOWN
S3C72Q5/P72Q5
F
PROGRAMMING TIP -- Reducing Power Consumption for Key Input Interrupt Processing
The following code shows real-time clock and interrupt processing for key inputs to reduce power consumption. In this example, the system clock source is switched from the main-system clock to a sub-system clock and the LCD display is turned on:
KEYCLK subroutine
DI CALL SMB LD LD LD LD SMB BITR BITR BITS BITS
MA2SUB 15 EA,#00H P4,EA A,#4H IMOD2,A 0 IRQW IRQ2 IEW IE2 WATDIS IRQ2 CIDLE SUB2MA
; Main-system clock
sub-system clock switch
; All key strobe outputs to low level ; Select KS0-KS7 enable
CLKS1
CALL BTSTZ JR CALL EI RET
; Execute clock and display changing subroutine ; Sub-system clock main-system clock switch
subroutine
CIDLE
IDLE NOP NOP NOP JPS
; Engage idle mode
CLKS1
8-6
S3C72Q5/P72Q5
POWER-DOWN
RECOMMENDED CONNECTIONS FOR UNUSED PINS To reduce overall power consumption, please configure unused pins according to the guidelines described in Table 83. Table 8-3. Unused Pin Connections for Reducing Power Consumption Pin/Share Pin Names P0.0-P0.3/K0-K3 P1.0-P1.2/K4-K6 P4.0/TCL0 P4.1/TCLO0 P5.0-P5.1 P5.2/BUZ P6.0-P6.3/KS0-KS3/DM0-DM3 P7.0/KS4/DM4 P7.1/KS5/DM5/COM11 P7.2-P7.3/KS6-KS7/COM10-COM11 P4.2/ INT0-P4.3/INT1 SEG0-SEG15/P8.0-P8.15 SEG16-SEG23/D0-D7 SEG24-SEG42/A0-A18 SEG43-SEG44/DR, DW SEG45-SEG59 COM0-COM11 TEST Recommended Connection Input mode: Connect to VDD Output mode: No connection
Connect to VDD No connection
Connect to VSS
8-7
S3C72Q5/P72Q5
RESET
9
OVERVIEW
-- Carry flag
RESET
When a RESET signal is input during normal operation or power-down mode, a hardware reset operation is initiated and the CPU enters idle mode. Then, when the standard oscillation stabilization interval of 31.3 ms at 4.19 MHz has elapsed, normal system operation resumes. Regardless of when the RESET occurs -- during normal operating mode or during a power-down mode -- most hardware register values are set to the reset values described in Table 9-1. The current status of several register values is, however, always retained when a RESET occurs during idle or stop mode; If a RESET occurs during normal operating mode, their values are undefined. Current values that are retained in this case are as follows:
-- Data memory values -- General-purpose registers E, A, L, H, X, W, Z, and Y
Oscillator Stabilization Wait Time (31.3 ms/4.19 MHz) RESET Input
Normal Mode or Power-Down Mode
Normal Mode
Idle Mode
Normal Mode
RESET Operation
Figure 9-1. Timing for Oscillation Stabilization After RESET
HARDWARE REGISTER VALUES AFTER RESET Table 9-1 gives you detailed information about hardware register values after a RESET occurs during power-down mode or during normal operation.
9-1
RESET
S3C72Q5/P72Q5
Table 9-1. Hardware Register Values After RESET Hardware Component or Subcomponent Program counter (PC) If RESET Occurs During Power Down Mode Lower six bits of address 0000H are transferred to PC13-8, and the contents of 0001H to PC7-0. If RESET Occurs During Normal Operating Lower six bits of address 0000H are transferred to PC13-8, and the contents of 0001H to PC7-0.
Program Status Word (PSW): Carry flag (C) Skip flag (SC0-SC2) Interrupt status flags (IS0, IS1) Bank enable flags (EMB, ERB) Retained 0 0 Bit 6 of address 0000H in program memory is transferred to the ERB flag, and bit 7 of the address to the EMB flag. Undefined Undefined 0 0 Bit 6 of address 0000H in program memory is transferred to the ERB flag, and bit 7 of the address to the EMB flag. Undefined
Stack pointer (SP) Data Memory (RAM): Registers E, A, L, H, X, W, Z, Y General-purpose registers Bank selection registers (SMB, SRB) BSC register (BSC0-BSC3) Bank1 page select register (PASR) Key scan register (KSR0-KSR3) Clocks: Power control register (PCON) Clock output mode register (CLMOD) System clock mode register (SCMOD) Interrupts: Interrupt request flags (IRQx) Interrupt enable flags (IEx) Interrupt priority flag (IPR) Interrupt master enable flag (IME) INT0 mode register (IMOD0) INT1 mode register (IMOD1) INT2 mode register (IMOD2)
NOTE:
Values retained Values retained (note) 15, 0 0 0 0
Undefined Undefined 15, 0 0 0 0
0 0 0
0 0 0
0 0 0 0 0 0 0
0 0 0 0 0 0 0
The values of the 0F8H-0FDH are not retained when a RESET signal is input.
9-2
S3C72Q5/P72Q5
RESET
Table 9-1. Hardware Register Values After RESET (Continued) Hardware Component or Subcomponent I/O Ports: Output buffers Output latches Port mode flags (PM) Pull-up resistor mode reg (PUMOD0) Basic Timer: Count register (BCNT) Mode register (BMOD) Watch-dog Timer: Watch-dog timer mode selection (WDMOD) Watch-dog timer counter clear flag(WDFLAG) Timer/Counter 0: Count register (TCNT0) Reference register (TREF0) Mode register (TMOD0) Output enable flag (TOE0) Timer/Counter 1: Count register (TCNT1) Reference register (TREF1) Mode register (TMOD1) Watch Timer: Watch timer mode register (WMOD) LCD Driver/Controller: LCD mode register (LMOD0/1) Display data memory Output buffers 0 Values retained Off 0 Undefined Off 0 0 0 FFH 0 0 FFH 0 0 FFH 0 0 0 FFH 0 0 A5 0 A5 0 Undefined 0 Undefined 0 Off 0 0 0 Off 0 0 0 If RESET Occurs During Power Down Mode If RESET Occurs During Normal Operation
9-3
S3C72Q5/P72Q5
I/O PORTS
10
OVERVIEW
Port Mode Flags Output Ports 8
I/O PORTS
The S3C72Q5 has 39 I/O Lines. There are total of 16 output pins, 23 configurable I/O pins, for a total number of 39 pins.
Port mode flags (PM) are used to configure I/O ports to input or output mode by setting or clearing the corresponding I/O buffer. PM flags are stored in one 8-bit, 4-bit register and are addressable by 8-bit, 4-bit write instructions respectively.
Output ports 8 consists of 16 pins that can be used either for LCD segment data output or for normal 1-bit output. When LCD display is off, P8 can be used to normal output. The value of P8 is determined by KSR0-KSR3 regardless of LMOD.0. (refer to P12-17) Pull-up Resistor Mode Register (PUMOD0) The pull-up resistor mode register (PUMOD0) is 8-bit register used to assign internal pull-up resistors by software to specific I/O ports. When a configurable I/O port pin is used as an output pin, its assigned pull-up resistor is automatically disabled, even though the pin's pull-up is enabled by a corresponding PUMOD0 bit setting. PUMOD0 is addressable by 8-bit write instructions only. RESET clears PUMOD0 register values to logic zero, automatically disconnecting all software-assignable port pull-up resistors. N-channel Open-drain Mode Register (PNE0) The n-channel open-drain mode register (PNE0) is used to configure outputs as n-channel open-drain outputs or as push-pull outputs.
10-1
I/O PORTS
S3C72Q5/P72Q5
Table 10-1. I/O Port Overview Port 0 1 I/O I/O Pins 4 3 Pin Names P0.0-P0.3 (K0 - K3) P1.0-P1.2 (K4 - K6) P4.0-P4.3 P5.0-P5.3 Address FF0H FF1H Function Description 4-bit I/O port. 1,4, and 8-bit read/write, and test are possible. Individual pins can be specified as input or output. 7-bit pull-up resistors are assignable by software. Pull-up resistors are automatically disabled for output pins. 4-bit I/O port. 1, 4, and 8-bit read/write, and test are possible. 4-bit unit pins are software configurable as input or output. Individual pins are software configurable as open-drain or push-pull output. 4-bit pull-up resistors are assignable by software and pull-up resistors are automatically disabled for output pins. 4-bit I/O port. 1,4, and 8-bit read/write, and test are possible. Individual pins can be specified as input or output. 4-bit pull-up resistors are assignable by software. Pull-up resistors are automatically disabled for output pins. 4-bit controllable output
4 5
4 4
FF4H FF5H
6 7
4 4
P6.0-P6.3 P7.0-P7.3
FF6H FF7H
8
O
16
P8.0-P8.15
FA2HFA5H
Table 10-2. Port Pin Status During Instruction Execution Instruction Type 1-bit test 1-bit input 4-bit input 8-bit input 1-bit output 4-bit output 8-bit output Example BTST LDB LD LD BITR LD LD P0.1 C,P1.3 A,P6 EA,P4 P4.0 P5,A P6,EA Input Mode Status Input or test data at each pin Output Mode Status Input or test data at output latch
Output latch contents undefined Transfer accumulator data to the output latch
Output pin status is modified Transfer accumulator data to the output pin
10-2
S3C72Q5/P72Q5
I/O PORTS
PORT MODE FLAGS (PM FLAGS) Port mode flags (PM) are used to configure I/O ports to input or output mode by setting or clearing the corresponding I/O buffer. PM flags are stored in one 8-bit registers and are addressable by 8-bit write instructions refectively. For convenient program reference, PM flags are organized into three groups -- PMG0, PMG1, and PMG2 as shown in Table 10-3. When a PM flag is "0", the port is set to input mode; when it is "1", the port is enabled for output. RESET clears all port mode flags to logical zero, automatically configuring the corresponding I/O ports to input mode. Table 10-3. Port Mode Group Flags PM Group ID PMG0 Address FEAH FEBH PMG1 FECH FEDH PMG2 FEEH FEEH
NOTE:
Bit 3 PM 0.3 "0" PM 4.3 PM 5.3 PM 6.3 PM 7.3
Bit 2 PM 0.2 PM 1.2 PM 4.2 PM 5.2 PM 6.2 PM 7.2
Bit 1 PM 0.1 PM 1.1 PM 4.1 PM 5.1 PM 6.1 PM 7.1
Bit 0 PM 0.0 PM 1.0 PM 4.0 PM 5.0 PM 6.0 PM 7.0
If bit = "0", the corresponding I/O pin is set to input mode. If bit = "1", the pin is set to output mode. All flags are cleared to "0" following RESET.
To use INTP0 interrupt, P0 and P1 must be set to external interrupt pins by LMOD.6-LMOD.4, input mode by PMG0 and pull-up resistor enable by PUMOD0.
F PROGRAMMING TIP -- Configuring I/O Ports to Input or Output
Configure P4 as an output port: BITS SMB LD LD EMB 15 EA,#0FH PMG1,EA
; P4 Output
10-3
I/O PORTS
S3C72Q5/P72Q5
PULL-UP RESISTOR MODE REGISTER (PUMOD0) The pull-up resistor mode register (PUMOD0) is an 8-bit register used to assign internal pull-up resistors by software to specific I/O ports. When a configurable I/O port pin is used as an output pin, its assigned pull-up resistor is automatically disabled even though the pin's pull-up is enabled by a corresponding PUMOD0 bit setting. RESET clears PUMOD0 register values to logic zero, automatically disconnecting all software-assignable port pull-up resistors. Table 10-4. Pull-Up Resistor Mode Register (PUMOD0) Organization Bit Name PUMOD0.7 0 1 PUMOD0.6 0 1 PUMOD0.5 0 1 PUMOD0.4 0 1 PUMOD0.3 PUMOD0.2 PUMOD0.1 PUMOD0.0 0 0 0 0 1
NOTE:
PUMOD0 function Disconnect port 7 pull-up resistor Connect port 7 pull-up resistor Disconnect port 6 pull-up resistor Connect port 6 pull-up resistor Disconnect port 5 pull-up resistor Connect port 5 pull-up resistor Disconnect port 4 pull-up resistor Connect port 4 pull-up resistor Always logic zero Always logic zero Always logic zero Disconnect port 0,1 pull-up resistor Connect port 0,1 pull-up resistor
When P0, P1 are used to external interrupt pins, the pull-up resistors of input mode are determined by key strobe signal (refer to P12-7).
F PROGRAMMING TIP -- Enabling and Disabling I/O Port Pull-Up Resistors
P6 enable pull-up resistors. BITS SMB LD LD EMB 15 EA,#40H PUMOD0,EA
; P6 pull-up resistor enable
10-4
S3C72Q5/P72Q5
I/O PORTS
N-channel Open-drain Mode Register (PNE0) PNE0 Address FE6H FE7H Bit3 PNE4.3 PNE5.3 Bit2 PNE4.2 PNE5.2 Bit1 PNE4.1 PNE5.1 Bit0 PNE4.0 PNE5.0
The n-channel open-drain mode register, PNE0, is used to configure port4 and 5 to n-channel open-drain outputs or as push-pull outputs. When a bit in the PNE0 register is set to one, the corresponding output pin is configured to nchannel open-drain; when set to "0", the output pin is configured to push-pull. The PNE0 register consists of an 8-bit, as shown above. PNE0 can be addressed by 8-bit write instructions only.
10-5
I/O PORTS
S3C72Q5/P72Q5
PORT 0,1 CIRCUIT DIAGRAM
RE
VDD
RE
VDD
PM0.0 PM0.1 PM0.2 PM0.3 PM1.0 PM1.1 PM1.2
P0.0/K0 P0.1/K1 P0.2/K2 P0.3/K3 P1.0/K4 P1.1/K5 P1.2/K6 PM0.0
Output Latch
1, 4, 8 A
PM0.1
A B
PM0.2
M CU XY D S0 S1 A B Y M CU X D S0 S1
PM0.3
MUX AY BS
Falling Edge Detection Circuit
RE PM0.0
Internal Latch
IRQP0
PM0.1
PM0.2 LMOD.4 LMOD.5 RE: Resistor Enable LE: Latch Enable RE LE LMOD.6
NOTES: 1. The pull-up resistor enable(RE) signal is automatically generated and synchronized to LCD segment signals. 2. When a port pin serves as an output, its pull-up resistor is automatically disabled regradless of PUMOD0.
Figure 10-1. Port 0,1 Circuit Diagram
10-6
S3C72Q5/P72Q5
I/O PORTS
PORT 4 CIRCUIT DIAGRAM
VDD PNE4.3 PNE4.2 PUR4 PNE4.0 PNE4.1 PM4.3
PM4.2
PM4.1
PM4.0 P4.0/TCLO P4.1/TCLO0 P4.2/INT0 P4.3/INT1 Type A TCLO0 Type A Type A Type A CMOS Push-Pull or N-Channel Open-Drain VDD PM4.0 PM4.1 PM4.2 PM4.3 INT0 INT1 NOTE: When a port pin serves as an output, its pull-up resistor is automatically disabled, even though the port's pull-up resistor is enabled by bit settings in the pull-up resistor-mode register (PUMOD0). TCL0 M U X 1, 4, 8
Output Latch
1, 4, 8
Type A PNE4.x
P-Ch Input Data PM4.x x=0-3 Output Data N-Ch
Figure 10-2. Port 4 Circuit Diagram
10-7
I/O PORTS
S3C72Q5/P72Q5
PORT 5 CIRCUIT DIAGRAM
VDD PNE5.3 PNE5.2 PUR5 PNE5.0 PM5.3 PNE5.1
PM5.2
PM5.1
PM5.0 P5.0 P5.1 P5.2/BUZ P5.3/CLO Type B Type B BUZ Type B Type B CLO
Output Latch
1, 4, 8
Type B PNE5.x VDD
CMOS Push-Pull or N-Channel Open-Drain
P-Ch Input Data PM5.x x=0-3 Output Data N-Ch
PM5.0 PM5.1 PM5.2 PM5.3
M U X 1, 4, 8
NOTES: 1. When a port pin serves as an output, its pull-up resistor is automatically disabled, even though the port's pull-up resistor is enabled by bit settings in the pull-up resistor-mode register (PUMOD0). 2. If this port is set to output ports, the input signal is not transmitted to the MUX.
Figure 10-3. Port 5 Circuit Diagram
10-8
S3C72Q5/P72Q5
I/O PORTS
PORT 6 CIRCUIT DIAGRAM
VDD
PUMOD0.6 PM6.3
PM6.2
PM6.1
PM6.0 P6.0/KS0 P6.1/KS1 P6.2/KS2 P6.3/KS3
Output Latch
1, 4, 8
PM6.0 PM6.1 PM6.2 PM6.3 KS3 NOTE: KS2 KS1 KS0
M U X 1, 4, 8
When a port pin serves as an output, its pull-up resistor is automatically disabled, even though the port's pull-up resistor is enabled by bit settings in the pull-up resistor-mode register (PUMOD0).
Figure 10-4. Port 6 Circuit Diagram
10-9
I/O PORTS
S3C72Q5/P72Q5
PORT 7 CIRCUIT DIAGRAM
VDD
PUMOD0.7 PM7.3
PM7.2
PM7.1
PM7.0 P7.0/KS4 P7.1/KS5 P7.2/KS6 P7.3/KS7
Output Latch
1, 4, 8
PM7.0 PM7.1 PM7.2 PM7.3 KS7 NOTE: KS6 KS5 KS4
M U X 1, 4, 8
When a port pin serves as an output, its pull-up resistor is automatically disabled, even though the port's pull-up resistor is enabled by bit settings in the pull-up resistor-mode register (PUMOD0).
Figure 10-5. Port 7 Circuit Diagram
10-10
S3C72Q5/P72Q5
TIMERS and TIMER/COUNTERS
11
OVERVIEW
-- Watch timer (WT)
TIMERS and TIMER/COUNTERS
The S3C72Q5 microcontroller has two timers, and two timer/counters modules: -- 8-bit basic timer (BT) -- 8-bit timer/counter 0 (TC0) -- 8-bit timer/counter 1 (TC1)
The 8-bit basic timer (BT) is the microcontroller's main interval timer and watch-dog timer. It generates an interrupt request at a fixed time interval when the appropriate modification is made to its mode register. The basic timer also is used to determine clock oscillation stabilization time when stop mode is released by an interrupt and after a RESET. The 8-bit timer/counter 0 (TC0) is a programmable timer/counter that is used primarily for event counting and for clock frequency modification and output. The 8-bit timer/counter 1 (TC1) is a programmable timer/counter that is used primarily for event counting and for clock frequency modification. The watch timer (WT) module consists of an 8-bit watch timer mode register, a clock selector, and a frequency divider circuit. Watch timer functions include real-time and watch-time measurement, main and subsystem clock interval timing, buzzer output generation. It also generates a clock signal for the LCD controller.
11-1
TIMERS and TIMER/COUNTERS
S3C72Q5/P72Q5
BASIC TIMER (BT)
OVERVIEW The 8-bit basic timer (BT) has six functional components: -- Clock selector logic -- 4-bit mode register (BMOD) -- 8-bit counter register (BCNT) -- 8-bit watchdog timer mode register (WDMOD) -- Watchdog timer counter clear flag (WDTCF) -- 3-bit watchdog timer counter register(WDCNT) The basic timer generates interrupt requests at precise intervals, based on the frequency of the system clock. You can use the basic timer as a "watchdog" timer for monitoring system events or use BT output to stabilize clock oscillation when stop mode is released by an interrupt and following RESET. Bit settings in the basic timer mode register BMOD turns the BT module on and off, selects the input clock frequency, and controls interrupt or stabilization intervals. Interval Timer Function The basic timer's primary function is to measure elapsed time intervals. The standard time interval is equal to 256 basic timer clock pulses. To restart the basic timer, one bit setting is required: bit 3 of the mode register BMOD should be set to logic one. The input clock frequency and the interrupt and stabilization interval are selected by loading the appropriate bit values to BMOD.2-BMOD.0. The 8-bit counter register, BCNT, is incremented each time a clock signal is detected that corresponds to the frequency selected by BMOD. BCNT continues incrementing as it counts BT clocks until an overflow occurs ( 255). An overflow causes the BT interrupt request flag (IRQB) to be set to logic one to signal that the designated time interval has elapsed. An interrupt request is than generated, BCNT is cleared to logic zero, and counting continues from 00H. Watchdog Timer Function The basic timer can also be used as a "watchdog" timer to signal the occurrence of system or program operation error. For this purpose, instruction that clear the watchdog timer (BITS WDTCF) should be executed at proper points in a program within given period. If an instruction that clears the watchdog timer is not executed within the given period and the watchdog timer overflows, reset signal is generated and the system restarts with reset status. An operation of watchdog timer is as follows: -- Write some values (except #5AH) to watchdog timer mode register, WDMOD. -- If WDCNT overflows, system reset is generated.
11-2
S3C72Q5/P72Q5
TIMERS and TIMER/COUNTERS
Oscillation Stabilization Interval Control Bits 2-0 of the BMOD register are used to select the input clock frequency for the basic timer. This setting also determines the time interval (also referred to as `wait time') required to stabilize clock signal oscillation when stop mode is released by an interrupt. When a RESET signal is inputted, the standard stabilization interval for system clock oscillation following the RESET is 31.3 ms at 4.19 MHz. Table 11-1. Basic Timer Register Overview Register Name BMOD Type Control Description Controls the clock frequency (mode) of the basic timer; also, the oscillation stabilization interval after stop mode release or RESET Counts clock pulses matching the BMOD frequency setting Controls watchdog timer operation. Clears the watchdog timer's counter. Size 4-bit RAM Address F85H Addressing Mode 4-bit write-only; BMOD.3: 1-bit writeable 8-bit read-only 8-bit write-only 1-, 4-bit write Reset Value "0"
BCNT WDMOD WDTCF
NOTE:
Counter Control Control
8-bit 8-bit 1-bit
F86H-F87H F98H-F99H F9AH.3
U (note) A5H "0"
'U' means the value is undetermined after a RESET.
11-3
TIMERS and TIMER/COUNTERS
S3C72Q5/P72Q5
"Clear" Signal Clear BCNT Clock Selector Overflow BCNT IRQB 1-Bit R/W 8 Clock Input 1 Pulse Period = BT Input Clock 2 8 (1/2 Duty) CPU Clock Start Signal (Power-Down Release) Clear IRQB Interrupt Request
BITS Instruction 4
BMOD.3 BMOD.2 BMOD.1 BMOD.0
3-Bit Counter WDCNT Clear WDMOD 8 WDTFC WAIT (note) RESET Stop Clear BITS Instruction DELAY Overflow Reset Signal Generation RESET
NOTES: 1. WAIT means stabilization time after RESET or stabilization time after stop mode release. 2. The RESET signal can be generated if the WDMOD is toggled for 8 times where "toggle" means change from 5AH to other value and vice versa. 3. When the watchdog timer is enabled or the 3-bit counter of the watchdog timer is cleared to "0", the BCNT value is not clearedbut increased continuously. As a result, the 3-bit counter of the watchdog timer (WDCNT) cna be increased by 1. For example, when the BMOD value is x000B and the watchdog timer is enabled, the watchdog timer interval time is from 2 3 x 2 12 x 2 8/fxx to (23 - 1) x 2 12 x 2 8/fxx.
Figure 11-1. Basic Timer Circuit Diagram
11-4
S3C72Q5/P72Q5
TIMERS and TIMER/COUNTERS
BASIC TIMER MODE REGISTER (BMOD) The basic timer mode register, BMOD, is a 4-bit write-only register. Bit 3, the basic timer start control bit, is also 1bit addressable. All BMOD values are set to logic zero following RESET and interrupt request signal generation is set to the longest interval. (BT counter operation cannot be stopped.) BMOD settings have the following effects: -- Restart the basic timer; -- Control the frequency of clock signal input to the basic timer; -- Determine time interval required for clock oscillation to stabilize following the release of stop mode by an interrupt. By loading different values into the BMOD register, you can dynamically modify the basic timer clock frequency during program execution. Four BT frequencies, ranging from fxx/212 to fxx/25, are selectable. Since BMOD's reset value is logic zero, the default clock frequency setting is fxx/212. The most significant bit of the BMOD register, BMOD.3, is used to restart the basic timer. When BMOD.3 is set to logic one (enabled) by a 1-bit write instruction, the contents of the BT counter register (BCNT) and the BT interrupt request flag (IRQB) are both cleared to logic zero, and timer operation is restarted. The combination of bit settings in the remaining three registers -- BMOD.2, BMOD.1, and BMOD.0 -- determine the clock input frequency and oscillation stabilization interval. Table 11-2. Basic Timer Mode Register (BMOD) Organization BMOD.3 1 Basic Timer Enable/Disable Control Bit Restart basic timer; clear IRQB, BCNT, and BMOD.3 to "0"
BMOD.2 0 0 1 1
BMOD.1 0 1 0 1
BMOD.0 0 1 1 1
Basic Timer Input Clock fxx/212 (1.02 kHz) fxx/29 (8.18 kHz) fxx/27 (32.7 kHz) fxx/25 (131 kHz)
Interrupt Interval Time (Wait Time) 220/fxx (250 ms) 217/fxx (31.3 ms) 215/fxx (7.82 ms) 213/fxx (1.95 ms)
NOTES: 1. Clock frequencies and interrupt interval time assume a system oscillator clock frequency (fxx) of 4.19 MHz. 2. fxx = selected system clock frequency. 3. Wait time is the time required to stabilize clock signal oscillation after stop mode is released. The data in the table column 'Interrupt Interval Time' can also be interpreted as "Oscillation Stabilization." 4. The standard stabilization time for system clock oscillation following a RESET is 31.3 ms at 4.19 MHz.
11-5
TIMERS and TIMER/COUNTERS
S3C72Q5/P72Q5
BASIC TIMER COUNTER (BCNT) BCNT is an 8-bit counter for the basic timer. It can be addressed by 8-bit read instructions. RESET leaves the BCNT counter value undetermined. BCNT is automatically cleared to logic zero whenever the BMOD register control bit (BMOD.3) is set to "1" to restart the basic timer. It is incremented each time a clock pulse of the frequency determined by the current BMOD bit settings is detected. When BCNT has incremented to hexadecimal 'FFH' (.255 clock pulses), it is cleared to '00H' and an overflow is generated. The overflow causes the interrupt request flag, IRQB, to be set to logic one. When the interrupt request is generated, BCNT immediately resumes counting incoming clock signals.
NOTE Always execute a BCNT read operation twice to eliminate the possibility of reading unstable data while the counter is incrementing. If, after two consecutive reads, the BCNT values match, you can select the latter value as valid data. Until the results of the consecutive reads match, however, the read operation must be repeated until the validation condition is met.
BASIC TIMER OPERATION SEQUENCE The basic timer's sequence of operations may be summarized as follows: 1. 2. 3. 4. 5. 6. 7. Set BMOD.3 to logic one to restart the basic timer BCNT is then incremented by one after each clock pulse corresponding to BMOD selection BCNT overflows if BCNT.255 (BCNT = FFH) When an overflow occurs, the IRQB flag is set by hardware to logic one The interrupt request is generated BCNT is then cleared by hardware to logic zero Basic timer resumes counting clock pulses
11-6
S3C72Q5/P72Q5
TIMERS and TIMER/COUNTERS
F PROGRAMMING TIP -- Using the Basic Timer
1. To read the basic timer count register (BCNT): BITS SMB LD LD LD CPSE JR EMB 15 EA,BCNT YZ,EA EA,BCNT EA,YZ BCNTR
BCNTR
2.
When stop mode is released by an interrupt, set the oscillation stabilization interval to 31.3ms (at 4.19 MHz): BITS SMB LD LD NOP STOP NOP NOP NOP EMB 15 A,#0BH BMOD,A
; Wait time is 31.3ms ; Set stop power-down mode
CPU Operation
Normal Operating Mode
Stop Mode
Idle Mode (31.3 ms)
Normal Operating Mode
STOP Instruction
Stop Mode is Released by Interrupt
3.
To set the basic timer interrupt interval time to 1.95 ms (at 4.19 MHz): BITS SMB LD LD EI BITS EMB 15 A,#0FH BMOD,A IEB ; Basic timer interrupt enable flag is set to "1"
4.
Clear BCNT and the IRQB flag and restart the basic timer: BITS SMB BITS EMB 15 BMOD.3
11-7
TIMERS and TIMER/COUNTERS
S3C72Q5/P72Q5
WATCHDOG TIMER MODE REGISTER (WDMOD) The watchdog timer mode register, WDMOD, is a 8-bit write-only register. WDMOD register controls to enable or disable the watchdog function. WDMOD values are set to logic "A5H" following RESET and this value enables the watchdog timer. Watchdog timer is set to the longest interval because BT overflow signal is generated with the longest interval. WDMOD 5AH Any other value Watchdog Timer Enable/Disable Control Disable watchdog timer function Enable watchdog timer function
WATCHDOG TIMER COUNTER (WDCNT) The watchdog timer counter, WDCNT, is a 3-bit counter. WDCNT is automatically cleared to logic zero, and restarts whenever the WDTCF register control bit is set to "1". RESET, stop, and wait signal clears the WDCNT to logic zero also. WDCNT increments each time a clock pulse of the overflow frequency determined by the current BMOD bit setting is generated. When WDCNT has incremented to hexadecimal "07H", it is cleared to "00H" and an overflow is generated. The overflow causes the system RESET. When the interrupt request is generated, BCNT immediately resumes counting incoming clock signals. WATCHDOG TIMER COUNTER CLEAR FLAG (WDTCF) The watchdog timer counter clear flag, WDTCF, is a 1-bit write instruction. When WDTCF is set to one, it clears the WDCNT to zero and restarts the WDCNT. WDTCF register bits 2-0 are always logic zero. Table 11-3. Watchdog Timer Interval Time BMOD x000b x011b x101b x111b BT Input Clock fxx/212 fxx/29 fxx/27 fxx/25 WDCNT Input Clock fxx/(212 x 28) fxx/(29 x 28) fxx/(27 x 28) fxx/(25 x 28) WDT Interval Time (7 or 8) 3 x (212 x 28)/fxx = 1.75-2 sec (7 or 8) 3 x (29 x 28)/fxx = 218.7-250 ms (7 or 8) 3 x (27 x 28)/fxx = 54.6-62.5 ms (7 or 8)3 x (25 x 28)/fxx = 13.6-15.6 ms
NOTES: 1. Clock frequencies assume a system oscillator clock frequency (fxx) of 4.19 MHz. 2. fxx = system clock frequency.
11-8
S3C72Q5/P72Q5
TIMERS and TIMER/COUNTERS
F
PROGRAMMING TIP -- Using the Watchdog Timer DI LD LD
* * *
RESET
EA,#00H SP,EA
LD LD
* * *
A,#0DH BMOD,A
; WDCNT input clock is 7.82 ms
MAIN
BITS
* * *
WDTCF
; Main routine operation period must be shorter than ; watchdog-timer's period
JP
MAIN
11-9
TIMERS and TIMER/COUNTERS
S3C72Q5/P72Q5
8-BIT TIMER/COUNTER 0 (TC0)
OVERVIEW Timer/counter 0 (TC0) is used to count system 'events' by identifying the transition (high-to-low or low-to-high) of incoming square wave signals. To indicate that an event has occurred, or that a specified time interval has elapsed, TC0 generates an interrupt request. By counting signal transitions and comparing the current counter value with the reference register value, TC0 can be used to measure specific time intervals. TC0 has a reloadable counter that consists of two parts: an 8-bit reference register (TREF0) into which you write the counter reference value, and an 8-bit counter register (TCNT0) whose value is automatically incremented by counter logic. An 8-bit mode register, TMOD0, is used to activate the timer/counter and to select the basic clock frequency to be used for timer/counter operations. To dynamically modify the basic frequency, new values can be loaded into the TMOD0 register during program execution. TC0 FUNCTION SUMMARY 8-bit programmable timer External event counter Generates interrupts at specific time intervals based on the selected clock frequency. Counts various system "events" based on edge detection of external clock signals at the TC0 input pin, TCL0. To start the event counting operation, TMOD0.2 is set to "1" and TMOD0.6 is cleared to "0". Outputs selectable clock frequencies to the TC0 output pin, TCLO0. Divides the frequency of an incoming external clock signal according to a modifiable reference value (TREF0), and outputs the modified frequency to the TCLO0 pin.
Arbitrary frequency output External signal divider
11-10
S3C72Q5/P72Q5
TIMERS and TIMER/COUNTERS
TC0 COMPONENT SUMMARY Mode register (TMOD0) Reference register (TREF0) Counter register (TCNT0) Clock selector circuit 8-bit comparator Activates the timer/counter and selects the internal clock frequency or the external clock source at the TCL0 pin. Stores the reference value for the desired number of clock pulses between interrupt requests. Counts internal or external clock pulses based on the bit settings in TMOD0 and TREF0. Together with the mode register (TMOD0), lets you select one of four internal clock frequencies or an external clock. Determines when to generate an interrupt by comparing the current value of the counter register (TCNT0) with the reference value previously programmed into the reference register (TREF0). Must be set to logic one before the contents of the TOL0 latch can be output to TCLO0. Cleared when TC0 operation starts and the TC0 interrupt service routine is executed and enabled whenever the counter value and reference value coincide. Must be set to logic one before the interrupt requests generated by timer/counter 0 can be processed. Table 11-4. TC0 Register Overview Register Name TMOD0 Type Control Description Controls TC0 enable/disable (bit 2); clears and resumes counting operation (bit 3); sets input clock and clock frequency (bits 6-4) Counts clock pulses matching the TMOD0 frequency setting Stores reference value for the timer/counter 0 interval setting Controls timer/counter 0 output to the TCLO0 pin Size 8-bit RAM Address F90H-F91H Addressing Mode 8-bit writeonly; (TMOD0.3 is also 1-bit writeable) 8-bit read-only 8-bit write-only 1-bit and 4-bit read/write Reset Value "0"
Output enable flag (TOE0) Interrupt request flag (IRQT0) Interrupt enable flag (IET0)
TCNT0 TREF0 TOE0
Counter Reference Flag
8-bit 8-bit 1-bit
F94H-F95H F96H-F97H F92H.2
"0" FFH "0"
11-11
TIMERS and TIMER/COUNTERS
S3C72Q5/P72Q5
Clocks (fxx/2 10, fxx/2 6, fxx/2 4, fxx) fxt TCL0 TMOD0.7 TMOD0.6 TMOD0.5 8 TMOD0.4 Clear TMOD0.3 TMOD0.2 TMOD0.1 TMOD0.0 Clear IRQT0 Set Clear Inverted TOL0 Clock Selector 8 TCNT0 8-Bit Comparator 8 TREF0
TCLO0
PM4
P4.1
TOE0
Figure 11-2. TC0 Circuit Diagram
TC0 ENABLE/DISABLE PROCEDURE Enable Timer/Counter 0 -- Set TMOD0.2 to logic one -- Set the TC0 interrupt enable flag IET0 to logic one -- Set TMOD0.3 to logic one TCNT0, IRQT0, and TOL0 are cleared to logic zero, and timer/counter operation starts. Disable Timer/Counter 0 -- Set TMOD0.2 to logic zero Clock signal input to the counter register TCNT0 is halted. The current TCNT0 value is retained and can be read if necessary.
11-12
S3C72Q5/P72Q5
TIMERS and TIMER/COUNTERS
TC0 PROGRAMMABLE TIMER/COUNTER FUNCTION Timer/counter 0 can be programmed to generate interrupt requests at various intervals based on the selected system clock frequency. Its 8-bit TC0 mode register TMOD0 is used to activate the timer/counter and to select the clock frequency. The reference register TREF0 stores the value for the number of clock pulses to be generated between interrupt requests. The counter register, TCNT0, counts the incoming clock pulses, which are compared to the TREF0 value as TCNT0 is incremented. When there is a match (TREF0 = TCNT0), an interrupt request is generated. To program timer/counter 0 to generate interrupt requests at specific intervals, choose one of five internal clock frequencies (divisions of the system clock, fxx,fxt) and load a counter reference value into the TREF0 register. TCNT0 is incremented each time an internal counter pulse is detected with the reference clock frequency specified by TMOD0.4-TMOD0.6 settings. To generate an interrupt request, the TC0 interrupt request flag (IRQT0) is set to logic one, the status of TOL0 is inverted, and the interrupt is generated. The content of TCNT0 is then cleared to 00H and TC0 continues counting. The interrupt request mechanism for TC0 includes an interrupt enable flag (IET0) and an interrupt request flag (IRQT0). TC0 OPERATION SEQUENCE The general sequence of operations for using TC0 can be summarized as follows: 1. 2. 3. 4. 5. 6. 7. 8. 9. Set TMOD0.2 to "1" to enable TC0 Set TMOD0.6 to "1" to enable the system clock (fxx) input Set TMOD0.5 and TMOD0.4 bits to desired internal frequency (fxx/2n) Load a value to TREF0 to specify the interval between interrupt requests Set the TC0 interrupt enable flag (IET0) to "1" Set TMOD0.3 bit to "1" to clear TCNT0, IRQT0, and TOL0 and start counting TCNT0 increments with each internal clock pulse When the comparator shows TCNT0 = TREF0, the IRQT0 flag is set to "1", and an interrupt request is generated. Output latch (TOL0) logic toggles high or low
10. TCNT0 is cleared to 00H and counting resumes 11. Programmable timer/counter operation continues until TMOD0.2 is cleared to "0".
11-13
TIMERS and TIMER/COUNTERS
S3C72Q5/P72Q5
TC0 EVENT COUNTER FUNCTION Timer/counter 0 can monitor or detect system 'events' by using the external clock input at the TCL0 pin (I/O port 4.0) as the counter source. The TC0 mode register selects rising or falling edge detection for incoming clock signals. The counter register TCNT0 is incremented each time the selected state transition of the external clock signal occurs. With the exception of the different TMOD0.4-TMOD0.6 settings, the operation sequence for TC0's event counter function is identical to its programmable timer/counter function. To activate the TC0 event counter function, -- Set TMOD0.2 to "1" to enable TC0; -- Clear TMOD0.6 to "0" to select the external clock source at the TCL0 pin; -- Select TCL0 edge detection for rising or falling signal edges by loading the appropriate values to TMOD0.5 and TMOD0.4. -- P4.0 must be set to input mode.
Table 11-5. TMOD0 Settings for TCL0 Edge Detection TMOD0.5 0 0
NOTE:
TMOD0.4 0 1
TCL0 Edge Detection Rising edges Falling edges
If you set P4.0 to a open-drain, you can use P4.0 as TCLO pin for external TCO clock, even if P4.0 is set to output mode.
11-14
S3C72Q5/P72Q5
TIMERS and TIMER/COUNTERS
TC0 CLOCK FREQUENCY OUTPUT Using timer/counter 0, a modifiable clock frequency can be output to the TC0 clock output pin, TCLO0. To select the clock frequency, load the appropriate values to the TC0 mode register, TMOD0. The clock interval is selected by loading the desired reference value into the reference register TREF0. To enable the output to the TCLO0 pin at I/O port 4.1, the following conditions must be met: -- TC0 output enable flag TOE0 must be set to "1" -- I/O mode flag for P4.1 (PM4) must be set to output mode ("1") -- Output latch value for P4.1 must be set to "0" In summary, the operational sequence required to output a TC0-generated clock signal to the TCLO0 pin is as follows: 1. 2. 3. 4. 5. 6. Load a reference value to TREF0. Set the internal clock frequency in TMOD0. Initiate TC0 clock output to TCLO0 (TMOD0.2 = "1"). Set port 4 mode flag (PM4) to "1". Set P4.1 output latch to "0". Set TOE0 flag to "1".
Each time TCNT0 overflows and an interrupt request is generated, the state of the output latch TOL0 is inverted and the TC0-generated clock signal is output to the TCLO0 pin.
F PROGRAMMING TIP -- TC0 Signal Output to the TCLO0 Pin
Output a 30 ms pulse width signal to the TCLO0 pin (at 4.19 MHz): BITS SMB LD LD LD LD LD LD BITR BITS EMB 15 EA,#79H TREF0,EA EA,#4CH TMOD0,EA A,#1H PMG2,A P4.1 TOE0
; P4.1 ?utput mode o ; P4.1clear
11-15
TIMERS and TIMER/COUNTERS
S3C72Q5/P72Q5
TC0 EXTERNAL INPUT SIGNAL DIVIDER By selecting an external clock source and loading a reference value into the TC0 reference register, TREF0, you can divide the incoming clock signal by the TREF0 value and then output this modified clock frequency to the TCLO0 pin. The sequence of operations used to divide external clock input can be summarized as follows: 1. 2. 3. 4. 5. 6. Load a signal divider value to the TREF0 register Clear TMOD0.6 to "0" to enable external clock input at the TCL0 pin Set TMOD0.5 and TMOD0.4 to desired TCL0 signal edge detection Set port 4 mode flag (PM4) to output ("1") Set P4.1 output latch to "0" Set TOE0 flag to "1" to enable output of the divided frequency to the TCLO0 pin
F PROGRAMMING TIP -- External TCL0 Clock Output to the TCLO0 Pin
Output external TCL0 clock pulse to the TCLO0 pin (divided by four):
External (TCL0) Clock Pulse
TCLO0 Output Pulse
BITS SMB LD LD LD LD LD LD BITR BITS
NOTE:
EMB 15 EA,#01H TREF0,EA EA,#0CH TMOD0,EA A,#1H PMG2,A P4.1 TOE0
; P4.1 output mode ; P4.1 clear
The Port 4.0 must be a open-drain pin for external TC0 clock input to the TCL0 pin, when the Port 4 is set to output mode.
11-16
S3C72Q5/P72Q5
TIMERS and TIMER/COUNTERS
TC0 MODE REGISTER (TMOD0) TMOD0 is the 8-bit mode control register for timer/counter 0. It is addressable by 8-bit write instructions. One bit, TMOD0.3, is also 1-bit writeable. RESET clears all TMOD0 bits to logic zero and disables TC0 operations. F90H F91H TMOD0.3 "0" TMOD0.2 TMOD0.6 "0" TMOD0.5 "0" TMOD0.4
TMOD0.2 is the enable/disable bit for timer/counter 0. When TMOD0.3 is set to "1", the contents of TCNT0, IRQT0, and TOL0 are cleared, counting starts from 00H, and TMOD0.3 is automatically reset to "0" for normal TC0 operation. When TC0 operation stops (TMOD0.2 = "0"), the contents of the TC0 counter register TCNT0 are retained until TC0 is re-enabled. The TMOD0.6, TMOD0.5, and TMOD0.4 bit settings are used together to select the TC0 clock source. This selection involves two variables: -- Synchronization of timer/counter operations with either the rising edge or the falling edge of the clock signal input at the TCL0 pin, and -- Selection of one of four frequencies, based on division of the incoming system clock frequency, for use in internal TC0 operation.
Table 11-6. TC0 Mode Register (TMOD0) Organization Bit Name TMOD0.7 TMOD0.6 TMOD0.5 TMOD0.4 TMOD0.3 1 Clear TCNT0, IRQT0, and TOL0 and resume counting immediately (This bit is automatically cleared to logic zero immediately after counting resumes.) Disable timer/counter 0; retain TCNT0 contents Enable timer/counter 0 Always logic zero Always logic zero F90H Setting 0 0,1 Always logic zero Specify input clock edge and internal frequency Resulting TC0 Function Address F91H
TMOD0.2
0 1
TMOD0.1 TMOD0.0
0 0
11-17
TIMERS and TIMER/COUNTERS
S3C72Q5/P72Q5
Table 11-7. TMOD0.6, TMOD0.5, and TMOD0.4 Bit Settings TMOD0.6 0 0 0 1 1 1 1 TMOD0.5 0 0 1 0 0 1 1 TMOD0.4 0 1 x 0 1 0 1 Resulting Counter Source and Clock Frequency External clock input (TCL0) on rising edges External clock input (TCL0) on falling edges fxt (Subsytem clock: 32.768 kHz) fxx/210 (4.09 kHz) fxx /26 (65.5 kHz) fxx/24 (262 kHz) fxx (4.19 MHz)
NOTE: 'fxx' = selected system clock of 4.19 MHz.
F PROGRAMMING TIP -- Restarting TC0 Counting Operation
1. Set TC0 timer interval to 4.09 kHz: BITS SMB LD LD EI BITS 2. EMB 15 EA,#4CH TMOD0,EA IET0
Clear TCNT0, IRQT0, and TOL0 and restart TC0 counting operation: BITS SMB BITS EMB 15 TMOD0.3
11-18
S3C72Q5/P72Q5
TIMERS and TIMER/COUNTERS
TC0 COUNTER REGISTER (TCNT0) The 8-bit counter register for timer/counter 0, TCNT0, is read-only and can be addressed by 8-bit RAM control instructions. RESET sets all TCNT0 register values to logic zero (00H). Whenever TMOD0.3 is enabled, TCNT0 is cleared to logic zero and counting resumes. The TCNT0 register value is incremented each time an incoming clock signal is detected that matches the signal edge and frequency setting of the TMOD0 register (specifically, TMOD0.6, TMOD0.5, and TMOD0.4). Each time TCNT0 is incremented, the new value is compared to the reference value stored in the TC0 reference buffer, TREF0. When TCNT0 = TREF0, an overflow occurs in the TCNT0 register, the interrupt request flag, IRQT0, is set to logic one, and an interrupt request is generated to indicate that the specified timer/counter interval has elapsed.
~ ~
TREF0
Reference Value = n
~~
TCNT0
0
1
2
n-1
n
0 Match
1
2
~~
~ ~
n-1 n
Count Clock
0 Match
1
2
3
TOL0
~
Interval Time IRQT0 Set IRQT0 Set
Timer Start Instruction (TMOD0.3 is set)
Figure 11-3. TC0 Timing Diagram
~
11-19
TIMERS and TIMER/COUNTERS
S3C72Q5/P72Q5
TC0 REFERENCE REGISTER (TREF0) The TC0 reference register TREF0 is an 8-bit write-only register. It is addressable by 8-bit RAM control instructions. RESET initializes the TREF0 value to 'FFH'. TREF0 is used to store a reference value to be compared to the incrementing TCNT0 register in order to identify an elapsed time interval. Reference values will differ depending upon the specific function that TC0 is being used to perform -- as a programmable timer/counter, event counter, clock signal divider, or arbitrary frequency output source. During timer/counter operation, the value loaded into the reference register is compared to the TCNT0 value. When TCNT0 = TREF0, the TC0 output latch (TOL0) is inverted and an interrupt request is generated to signal the interval or event. The TREF0 value, together with the TMOD0 clock frequency selection, determines the specific TC0 timer interval. Use the following formula to calculate the correct value to load to the TREF0 reference register:
TC0 timer interval = (TREF0 value + 1)
x
1 TMOD0 frequency setting
(TREF0 value 0)
TC0 OUTPUT ENABLE FLAG (TOE0) The 1-bit timer/counter 0 output enable flag TOE0 controls output from timer/counter 0 to the TCLO0 pin. TOE0 is addressable by 1-bit and 4-bit read/write instruction. (MSB) F92H "0" TOE0 "U" (LSB) "0"
NOTE: The "U" means a undefined register bit.
When you set the TOE0 flag to "1", the contents of TOL0 can be output to the TCLO0 pin. Whenever a RESET occurs, TOE0 is automatically set to logic zero, disabling all TC0 output. Even when the TOE0 flag is disabled, timer/counter 0 can continue to output an internally generated clock frequency, via TOL0. TC0 OUTPUT LATCH (TOL0) TOL0 is the output latch for timer/counter 0. When the 8-bit comparator detects a correspondence between the value of the counter register TCNT0 and the reference value stored in the TREF0 register, the TOL0 value is inverted -- the latch toggles high-to-low or low-to-high. Whenever the state of TOL0 is switched, the TC0 signal is output. TC0 output may be directed to the TCLO0 pin. Assuming TC0 is enabled, when bit 3 of the TMOD0 register is set to "1", the TOL0 latch is cleared to logic zero, along with the counter register TCNT0 and the interrupt request flag, IRQT0, and counting resumes immediately. When TC0 is disabled (TMOD0.2 = "0"), the contents of the TOL0 latch are retained and can be read, if necessary.
11-20
S3C72Q5/P72Q5
TIMERS and TIMER/COUNTERS
F PROGRAMMING TIP -- Setting a TC0 Timer Interval
To set a 30 ms timer interval for TC0, given fxx = 4.19 MHz, follow these steps. 1. Select the timer/counter 0 mode register with a maximum setup time of 62.5ms (assume the TC0 counter clock = fxx/210, and TREF0 is set to FFH): Calculate the TREF0 value: TREF0 value + 1 4.09 kHz 30 ms 244 s = 122.9 = 7AH
2.
30 ms =
TREF0 + 1 =
TREF0 value = 7AH - 1 = 79H 3. Load the value 79H to the TREF0 register: BITS SMB LD LD LD LD EMB 15 EA,#79H TREF0,EA EA,#4CH TMOD0,EA
11-21
TIMERS and TIMER/COUNTERS
S3C72Q5/P72Q5
8-BIT TIMER/COUNTER 1 (TC1)
OVERVIEW Timer/counter 1 (TC1) is used to count system 'events' by identifying the transition (high-to-low or low-to-high) of incoming square wave signals. To indicate that an event has occurred, or that a specified time interval has elapsed, TC1 generates an interrupt request. By counting signal transitions and comparing the current counter value with the reference register value, TC1 can be used to measure specific time intervals. TC1 has a reloadable counter that consists of two parts: an 8-bit reference register (TREF1) into which you write the counter reference value, and an 8-bit counter register (TCNT1) whose value is automatically incremented by counter logic. An 8-bit mode register, TMOD1, is used to activate the timer/counter and to select the basic clock frequency to be used for timer/counter operations. To dynamically modify the basic frequency, new values can be loaded into the TMOD1 register during program execution. TC1 FUNCTION SUMMARY 8-bit programmable timer Generates interrupts at specific time intervals based on the selected clock frequency.
11-22
S3C72Q5/P72Q5
TIMERS and TIMER/COUNTERS
TC1 COMPONENT SUMMARY Mode register (TMOD1) Reference register (TREF1) Counter register (TCNT1) Clock selector circuit 8-bit comparator Activates the timer/counter and selects the internal clock frequency. Stores the reference value for the desired number of clock pulses between interrupt requests. Counts internal or external clock pulses based on the bit settings in TMOD1 and TREF1. Together with the mode register (TMOD1), lets you select one of four internal clock frequencies or an external clock. Determines when to generate an interrupt by comparing the current value of the counter register (TCNT1) with the reference value previously programmed into the reference register (TREF1). Cleared when TC1 operation starts and the TC1 interrupt service routine is executed and enabled whenever the counter value and reference value coincide. Must be set to logic one before the interrupt requests generated by timer/counter 1 can be processed. Table 11-8. TC1 Register Overview Register Name TMOD1 Type Control Description Controls TC1 enable/disable (bit 2); clears and resumes counting operation (bit 3); sets input clock and clock frequency (bits 6-4) Counts clock pulses matching the TMOD1 frequency setting Stores reference value for the timer/counter 1 interval setting Size 8-bit RAM Address FA6H-FA7H Addressing Mode 8-bit writeonly; (TMOD1.3 is also 1-bit writeable) 8-bit read-only 8-bit write-only Reset Value "0"
Interrupt request flag (IRQT1) Interrupt enable flag (IET1)
TCNT1 TREF1
Counter Reference
8-bit 8-bit
FA8H-FA9H FAAH-FABH
"0" FFH
11-23
TIMERS and TIMER/COUNTERS
S3C72Q5/P72Q5
Clocks (fxx/2 10 , fxx/2 8, fxx/2 6 , fxx 4) fxt TMOD1.7 TMOD1.6 TMOD1.5 8 TMOD1.4 TMOD1.3 TMOD1.2 TMOD1.1 TMOD1.0 Clear IRQT1 Set Clock Selector Clear 8 TCNT1 8-Bit Comparator 8 TREF1
Figure 11-4. TC1 Circuit Diagram
TC1 ENABLE/DISABLE PROCEDURE Enable Timer/Counter 1 -- Set TMOD1.2 to logic one -- Set the TC1 interrupt enable flag IET1 to logic one -- Set TMOD1.3 to logic one TCNT1, IRQT1, and TOL1 are cleared to logic zero, and timer/counter operation starts.
Disable Timer/Counter 1 -- Set TMOD1.2 to logic zero Clock signal input to the counter register TCNT1 is halted. The current TCNT1 value is retained and can be read if necessary.
11-24
S3C72Q5/P72Q5
TIMERS and TIMER/COUNTERS
TC1 PROGRAMMABLE TIMER/COUNTER FUNCTION Timer/counter 1 can be programmed to generate interrupt requests at various intervals based on the selected system clock frequency. Its 8-bit TC1 mode register TMOD1 is used to activate the timer/counter and to select the clock frequency. The reference register TREF1 stores the value for the number of clock pulses to be generated between interrupt requests. The counter register, TCNT1, counts the incoming clock pulses, which are compared to the TREF1 value as TCNT1 is incremented. When there is a match (TREF1 = TCNT1), an interrupt request is generated. To program timer/counter 1 to generate interrupt requests at specific intervals, choose one of five internal clock frequencies (divisions of the system clock, fxx, fxt) and load a counter reference value into the TREF1 register. TCNT1 is incremented each time an internal counter pulse is detected with the reference clock frequency specified by TMOD1.4-TMOD1.6 settings. To generate an interrupt request, the TC1 interrupt request flag (IRQT1) is set to logic one, and the interrupt is generated. The content of TCNT1 is then cleared to 00H and TC1 continues counting. The interrupt request mechanism for TC1 includes an interrupt enable flag (IET1) and an interrupt request flag (IRQT1). TC1 OPERATION SEQUENCE The general sequence of operations for using TC1 can be summarized as follows: 1. 2. 3. 4. 5. 6. 7. 8. 9. Set TMOD1.2 to "1" to enable TC1 Set TMOD1.6 to "1" to enable the system clock (fxx) input. Set TMOD1.5 and TMOD1.4 bits to desired internal frequency (fxx/2n) or TMOD1.6 and TMOD1.5 to "1" to enable the system clock fxt input. Load a value to TREF1 to specify the interval between interrupt requests Set the TC1 interrupt enable flag (IET1) to "1" Set TMOD1.3 bit to "1" to clear TCNT1, IRQT1, and TOL1 and start counting TCNT1 increments with each internal clock pulse When the comparator shows TCNT1 = TREF1, the IRQT1 flag is set to "1", and an interrupt request is generated. TCNT1 is cleared to 00H and counting resumes
10. Programmable timer/counter operation continues until TMOD1.2 is cleared to "0".
11-25
TIMERS and TIMER/COUNTERS
S3C72Q5/P72Q5
TC1 MODE REGISTER (TMOD1) TMOD1 is the 8-bit mode control register for timer/counter 1. It is addressable by 8-bit write instructions. One bit, TMOD1.3, is also 1-bit writeable. RESET clears all TMOD1 bits to logic zero and disables TC1 operations. FA6H FA7H TMOD1.3 "0" TMOD1.2 TMOD1.6 "0" TMOD1.5 "0" TMOD1.4
TMOD1.2 is the enable/disable bit for timer/counter 1. When TMOD1.3 is set to "1", the contents of TCNT1, and IRQT1, are cleared, counting starts from 00H, and TMOD1.3 is automatically reset to "0" for normal TC1 operation. When TC1 operation stops (TMOD1.2 = "0"), the contents of the TC1 counter register TCNT1 are retained until TC1 is re-enabled. The TMOD1.6, TMOD1.5, and TMOD1.4 bit settings are used together to select the TC1 clock source. This selection involves: -- Selection of one of five frequencies, based on division of the incoming system clock frequency, or subsytem clock frequency, for use in internal TC1 operation.
Table 11-9. TC1 Mode Register (TMOD1) Organization Bit Name TMOD1.7 TMOD1.6 TMOD1.5 TMOD1.4 TMOD1.3 1 Clear TCNT1, and IRQT1, and resume counting immediately (This bit is automatically cleared to logic zero immediately after counting resumes.) Disable timer/counter 1; retain TCNT1 contents Enable timer/counter 1 Always logic zero Always logic zero FA6H Setting 0 0,1 Always logic zero Specify input clock edge and internal frequency Resulting TC1 Function Address FA7H
TMOD1.2
0 1
TMOD1.1 TMOD1.1
0 0
11-26
S3C72Q5/P72Q5
TIMERS and TIMER/COUNTERS
Table 11-10. TMOD1.6, TMOD1.5, and TMOD1.4 Bit Settings TMOD1.6 0 1 1 1 1 TMOD1.5 1 0 0 1 1 TMOD1.4 x 0 1 0 1 Resulting Counter Source and Clock Frequency fxt (Subsytem clock: 32.768 kHz) fxx/210 (4.09 kHz) fxx /26 (65.5 kHz) fxx/24 (262 kHz) fxx (4.19 MHz)
NOTE: 'fxx' = selected system clock of 4.19 MHz.
F PROGRAMMING TIP -- Restarting TC1 Counting Operation
1. Set TC1 timer interval to 4.09 kHz: BITS SMB LD LD EI BITS 2. EMB 15 EA,#4CH TMOD1,EA IET1
Clear TCNT1, and IRQT1, and restart TC1 counting operation: BITS SMB BITS EMB 15 TMOD1.3
11-27
TIMERS and TIMER/COUNTERS
S3C72Q5/P72Q5
TC1 COUNTER REGISTER (TCNT1) The 8-bit counter register for timer/counter 1, TCNT1, is read-only and can be addressed by 8-bit RAM control instructions. RESET sets all TCNT1 register values to logic zero (00H). Whenever TMOD1.3 is enabled, TCNT1 is cleared to logic zero and counting resumes. The TCNT1 register value is incremented each time an incoming clock signal is detected that matches the signal edge and frequency setting of the TMOD1 register (specifically, TMOD1.6, TMOD1.5, and TMOD1.4). Each time TCNT1 is incremented, the new value is compared to the reference value stored in the TC1 reference buffer, TREF1. When TCNT1 = TREF1, an overflow occurs in the TCNT1 register, the interrupt request flag, IRQT1, is set to logic one, and an interrupt request is generated to indicate that the specified timer/counter interval has elapsed.
~ ~
TREF1
Reference Value = n
~~
TCNT1
0
1
2
n-1
n
0
1
2
~~
~ ~
n-1 n
Count Clock
0
1
2
3
Timer Start Instruction (TMOD1.3 is set)
IRQT1 Set
IRQT1 Set
Figure 11-5. TC1 Timing Diagram
11-28
S3C72Q5/P72Q5
TIMERS and TIMER/COUNTERS
TC1 REFERENCE REGISTER (TREF1) The TC1 reference register TREF1 is an 8-bit write-only register. It is addressable by 8-bit RAM control instructions. RESET initializes the TREF1 value to 'FFH'. TREF1 is used to store a reference value to be compared to the incrementing TCNT1 register in order to identify an elapsed time interval. Reference values will differ depending upon the specific function that TC1 is being used to perform -- as a programmable timer/counter. During timer/counter operation, the value loaded into the reference register is compared to the TCNT1 value. When TCNT1 = TREF1 an interrupt request is generated to signal the interval. The TREF1 value, together with the TMOD1 clock frequency selection, determines the specific TC1 timer interval. Use the following formula to calculate the correct value to load to the TREF1 reference register:
TC1 timer interval = (TREF1 value + 1)
x
1 TMOD1 frequency setting
(TREF1 value 1)
F PROGRAMMING TIP -- Setting a TC1 Timer Interval
To set a 30 ms timer interval for TC1, given fxx = 4.19 MHz, follow these steps. 1. Select the timer/counter 1 mode register with a maximum setup time of 62.5ms (assume the TC1 counter clock = fxx/210, and TREF1 is set to FFH): Calculate the TREF0 value: TREF1 value + 1 4.09 kHz 30 ms 244 s = 122.9 = 7AH
2.
30 ms =
TREF1 + 1 =
TREF1 value = 7AH - 1 = 79H 3. Load the value 79H to the TREF1 register: BITS SMB LD LD LD LD EMB 15 EA,#79H TREF1,EA EA,#4CH TMOD1,EA
11-29
TIMERS and TIMER/COUNTERS
S3C72Q5/P72Q5
WATCH TIMER
OVERVIEW The watch timer is a multi-purpose timer which consists of three basic components: -- 8-bit watch timer mode register (WMOD) -- Clock selector -- Frequency divider circuit Watch timer functions include real-time and watch-time measurement and interval timing for the main and subsystem clock. It is also used as a clock source for the LCD controller and for generating buzzer (BUZ) output. Real-Time and Watch-Time Measurement To start watch timer operation, set bit 2 of the watch timer mode register (WMOD.2) to logic one. The watch timer starts, the interrupt request flag IRQW is automatically set to logic one, and interrupt requests commence in 0.5second intervals. Since the watch timer functions as a quasi-interrupt instead of a vectored interrupt, the IRQW flag should be cleared to logic zero by program software as soon as a requested interrupt service routine has been executed. Using a Main System or Subsystem Clock Source The watch timer can generate interrupts based on the main system clock frequency or on the subsystem clock. When the zero bit of the WMOD register is set to "1", the watch timer uses the subsystem clock signal (fxt) as its source; if WMOD.0 = "0", the main system clock (fx) is used as the signal source, according to the following formula: Main system clock (fx) 128 (MHz)
Watch timer clock (fw)
=
= 32.768 kHz (fx = 4.19
This feature is useful for controlling timer-related operations during stop mode. When stop mode is engaged, the main system clock (fx) is halted, but the subsystem clock continues to oscillate. By using the subsystem clock as the oscillation source during stop mode, the watch timer can set the interrupt request flag IRQW to "1", thereby releasing stop mode. Buzzer Output Frequency Generator The watch timer can generate a steady 2 kHz, 4 kHz, 8 kHz, or 16 kHz signal to the BUZ pin at selected clock for watch timer. To select the desired BUZ frequency , load the appropriate value to the WMOD register. This output can then be used to actuate an external buzzer sound. To generate a BUZ signal, three conditions must be met: -- The WMOD.7 register bit is set to "1" -- The output latch for I/O port 5.2 is cleared to "0" -- The port 5.2 output mode flag (PM5.2) set to 'output' mode
11-30
S3C72Q5/P72Q5
TIMERS and TIMER/COUNTERS
Timing Tests in High-Speed Mode By setting WMOD.1 to "1", the watch timer will operate in high-speed mode, generating an interrupt every 3.91 ms at oscillation clock of 4.19 MHz. At its normal speed (WMOD.1 = '0'), the watch timer generates an interrupt request every 0.5 seconds. High-speed mode is useful for timing events for program debugging sequences. Check Subsystem Clock Level Feature The watch timer can also check the input level of the subsystem clock by testing WMOD.3. If WMOD.3 is "1", the input level at the XTin pin is high; if WMOD.3 is "0", the input level at the XT in pin is low.
P5.2 Latch WMOD.7 WMOD.6 WMOD.5 WMOD.4 8 WMOD.3 WMOD.2 WMOD.1 WMOD.0 ENABLE/DISABLE MUX
PM5.2
BUZ
fw/16 fw/8 fw/4 fw/2 Selector Circuit IRQW
To LCD Controller
Clock Selector
fw (32.768 kHz) (note)
Frequency Dividing Circuit
fw/2 7
fw/2 14
fxt
M U X
fx/16 fx/32 fx/64 fx/128
fx = Main-system Clock fxt = Sub-system Clock fw = Watch Timer Frequency
LMOD.3-.2
NOTE:
fw = 32.768 kHz, when fx is 4.19 MHz and fx/128 is selected.
Figure 11-6. Watch Timer Circuit Diagram
11-31
TIMERS and TIMER/COUNTERS
S3C72Q5/P72Q5
WATCH TIMER MODE REGISTER (WMOD) The watch timer mode register WMOD is used to select specific watch timer operations. It is 8-bit write-only addressable. An exception is WMOD bit 3 (the XT IN input level control bit) which is 1-bit read-only addressable. A RESET automatically sets WMOD.3 to the current input level of the subsystem clock, XT IN (high, if logic one; low, if logic zero), and all other WMOD bits to logic zero. F88H F89H WMOD.3 WMOD.7 WMOD.2 "0" WMOD.1 WMOD.5 WMOD.0 WMOD.4
In summary, WMOD settings control the following watch timer functions: -- Watch timer clock and LCD clock selection -- Watch timer speed control -- Enable/disable watch timer -- XTIN input level control -- Buzzer frequency selection -- Enable/disable buzzer output (WMOD.0) (WMOD.1) (WMOD.2) (WMOD.3) (WMOD.4 and WMOD.5) (WMOD.7)
Table 11-11. Watch Timer Mode Register (WMOD) Organization Bit Name WMOD.7 Values 0 1 WMOD.6 WMOD.5 - .4 0 0 1 1 WMOD.3 0 1 WMOD.2 0 1 WMOD.1 0 1 WMOD.0 0 1
NOTE:
Function Disable buzzer (BUZ) signal output at the BUZ pin Enable buzzer (BUZ) signal output at the BUZ pin Always logic zero
Address F89H
0 0 1 0 1
2 kHz buzzer (BUZ) signal output 4 kHz buzzer (BUZ) signal output 8 kHz buzzer (BUZ) signal output 16 kHz buzzer (BUZ) signal output Input level to XT in pin is low Input level to XT in pin is high Disable watch timer; clear frequency dividing circuits Enable watch timer Normal mode; sets IRQW to 0.5 second High-speed mode; sets IRQW to 3.91 ms Select (fx/128) as the watch timer clock (fw) Select a LCD clock source as main system clock Select subsystem clock as watch timer clock (fw) Select a LCD clock source as sub system clock F88H
Main system clock frequency (fx) is assumed to be 4.19 MHz; subsystem clock (fxx) is assumed to be 32.768 kHz.
11-32
S3C72Q5/P72Q5
TIMERS and TIMER/COUNTERS
F PROGRAMMING TIP -- Using the Watch Timer
1. Select a subsystem clock as the LCD display clock, a 0.5 second interrupt, and 2 kHz buzzer enable: BITS SMB LD LD BITR LD LD BITS 2. EMB 15 EA,#40H PMG1,EA P5.2 EA,#85H WMOD,EA IEW
; P5.2? output mode
Sample real-time clock processing method: BTSTZ RET * * * IRQW ; 0.5 second check ; No, return ; Yes, 0.5 second interrupt generation ; Increment HOUR, MINUTE, SECOND
CLOCK
11-33
S3C72Q5/P72Q5
LCD CONTROLLER/DRIVER
12
OVERVIEW
-- LCD controller/driver
LCD CONTROLLER/DRIVER
The S3C72Q5 microcontroller can directly drive an up-to-12-characters (5 x 12 dots) LCD panel. Its LCD block has the following components:
-- Display RAM (100H-1BBH) for storing display data (13H page) -- 60 segment output pins (SEG0-SEG59) -- 12 common output pins (COM0-COM11) -- LCD contrast control circuit by software (16 steps) The frame frequency, LCD divide resistors, key strobe signal output key, and check signal output are determined by bit settings in the LCD mode register, LMOD. The LCD duty and normal LCD display are determined by bit settings in the LCD control registers, LCON0 and LCON1. When a subsystem clock is selected as the LCD clock source, the LCD display is enabled even during main stop and idle modes.
12-1
LCD CONTROLLER/DRIVER
S3C72Q5/P72Q5
LCD CIRCUIT DIAGRAM
SEG59 SEG58 Display RAM Memory Bank1 (Page 13H) M U X SEG0/P8.0 SEG44/DW Segment
8
SEG16/D0 SEG15/P8.15 SEG14/P8.14
Driver VLC1 VLC2 VLC3 VLC4 COM11 COM10
4
KSR0-3
Voltage Divider
8 4 4
LMOD LCON0 LCON1 fxt or divided main-system clock(fx) LCD Controller COM Control
COM0
4
LCNST
Figure 12-1. LCD Circuit Diagram
fxt fx/16 fx/32 fx/64 fx/128 Clock Selector To LCD Controller
M U X
WMOD.0 LMOD
Figure 12-2. LCD Clock Circuit Diagram
12-2
S3C72Q5/P72Q5
LCD CONTROLLER/DRIVER
LCD RAM ADDRESS AREA RAM addresses 100H-1BBH of bank1 page 13H are used as LCD data memory. These locations can be addressed by 8-bit instructions only. However, the upper 3 bits of each address must be written to zero. When the bit value of a display segment is "1", the LCD display is turned on; when the bit value is "0", the display is turned off. Display RAM data are sent out through segment pins SEG0-SEG59 using a direct memory access (DMA) method that is synchronized with the fLCD signal. RAM addresses in this location that are not used for LCD display can be allocated to general-purpose use.
SSSSS EEEEE GGGGG 01234 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH LSB MSB 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH
SSSSS EEEEE GGGGG 56789 A0H A1H A2H A3H A4H A5H A6H A7H A8H A9H AAH ABH LSB MSB
SSSSS EEEEE GGGGG 55555 01234 B0H B1H B2H B3H B4H B5H B6H B7H B8H B9H BAH BBH LSB MSB
SSSSS EEEEE GGGGG 55555 56789 COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 LSB MSB
Figure 12-3. Display RAM Organization
12-3
LCD CONTROLLER/DRIVER
S3C72Q5/P72Q5
LCD CONTRAST CONTROL REGISTER (LCNST) The LCD contrast control register (LCNST) is used to control the LCD contrast up to 16 step contrast level. Following a RESET, all LCNST values are cleared to "0". This disable the LCD contrast control. F8AH F8BH LCNST.3 LCNST.7 LCNST.2 0 LCNST.1 0 LCNST.0 0
Table 12-1. LCD Contrast Control Register (LCNST) Organization LCD Contrast Control Enable/Disable Bit LCNST.7 0 1 Bits 6-4 Bits 6-4 Always logic zero Enable/Disable LCD Contrast Control Disable LCD contrast control Enable LCD contrast control
Segment/Port Output Selection Bits LCNST.3 0 0 0 0 0 * * * * 1
NOTE:
LCNST.2 0 0 0 0 1 * * * * 1
LCNST.1 0 0 1 1 0 * * * * 1
LCNST.0 0 1 0 1 0 * * * * 1
16 Step Contrast Level 1/16 step (The dimmest level) 2/16 step 3/16 step 4/16 step 4/16 step * * * * 16/16 step (The brightest level)
VLCD = VDD x (1-(16-n)/48), when n = 0-15 (At normal LCD dividing Resistors)
12-4
S3C72Q5/P72Q5
LCD CONTROLLER/DRIVER
LCD OUTPUT CONTROL REGISTER 0 (LCON0) The LCD output control register 0, LCON0 can be manipulated using 4-bit write instructions. F8EH LCON0.3 LCON0.2 "0" "0"
LCON0 can select LCD duty. Table 12-2. LCD Output Control Register (LCON0) Organization LCON0.3 0 0 1 1 LCON0.2 0 1 0 1 Duty 1/9 duty (COM0-COM8 select) 1/10 duty (COM0-COM9 select) 1/11 duty (COM0-COM10 select) 1/12 duty (COM0-COM11 select)
NOTES: 1. COM has priority over normal port in P7.3/COM9-P7.1/COM11. This means these port are assigned to COM pins regardless of the value of PMG2, when duty is selected to 1/10, 1/11, or 1/12 at LCON0 register. 2. The port used COM must be set to output to prevent LCD display distortion.
LCD OUTPUT CONTROL REGISTER 1 (LCON1) The LCD output control register 1, LCON1 can be manipulated using 4-bit write instructions. F8FH LCON1.3 LCON1.2 LCON1.1 LCON1.0
LCON1 control the following LCD functions. -- LCD display on/off LCON1.2 -- Key check signal output with LCD display off (LCON1.3) -- Dimming mode (LCON1.0)
Table 12-3. LCD Output Control Register (LCON1) Organization LCON1.3 0 0 1 LCON1.2 1 1 0 LCON1.1 0 0 0 LCON1.0 0 1 1 Bias Selection for LCD Display LCD display on Dimming mode Key check signal output with LCD display off
NOTES: 1. To turn off LCD display, you must set LCON1 to 9 not 0. 2. P8 can be used to normal output port, when LCD display off. The value of P8 is determined by KSR0-KSR3 regardless of LMOD.0. (refer to P12-17)
12-5
LCD CONTROLLER/DRIVER
S3C72Q5/P72Q5
LCD MODE REGISTER (LMOD) The LCD mode register LMOD can be manipulated using 8-bit write instructions. F8DH F8CH "0" LMOD.3 LMOD.6 LMOD.2 LMOD.5 LMOD.1 LMOD.4 LMOD.0
LMOD controls the following LCD functions: -- External interrupt INTP0 enable/disable selection bits (LMOD.6, LMOD.5, and LMOD.4) -- External interrupt INTP0 detection pins can be select (LMOD.6, LMOD.5, and LMOD.4) -- When main system clock is selected as watch timer clock by WMOD.0, watch timer clock selection bits (LMOD.3 and LMOD.2) -- LCD dividing resistors selection (LMOD.1) -- Key strobe signal disable/enable selection (LMOD.0)
12-6
S3C72Q5/P72Q5
LCD CONTROLLER/DRIVER
Table 12-4. LCD Mode Control Register (LMOD) Organization External Interrupt (INTP0) Pins Selection Bits (1) LMOD.6 0 0 0 0 1 1 1 1 LMOD.5 0 0 1 1 0 0 1 1 LMOD.4 0 1 0 1 0 1 0 1 External Interrupt (INTP0) Pins Selection Bits (1) Interrupt request at K0 triggered by falling edge Interrupt request at K0-K1 triggered by falling edge Interrupt request at K0-K2 triggered by falling edge Interrupt request at K0-K3 triggered by falling edge Interrupt request at K0-K4 triggered by falling edge Interrupt request at K0-K5 triggered by falling edge Interrupt request at K0-K6 triggered by falling edge Interrupt request flag (IRQP0) cannot be set to logic one
Watch Timer Clock Selection Bits (2) LMOD.3 0 0 1 1 LMOD.2 0 1 0 1 When main system clock is selected as watch timer clock by WMOD.0 fx/128 fx/64 fx/32 fx/16
LCD Dividing Resistor Selection Bits LMOD.1 0 1 Normal LCD dividing resistors Diminish LCD dividing resistors to strength LCD drive LCD Dividing Resistor
Key Strobe Signal Output Control Bits (SEG0/P8.0-SEG15/P8.15) LMOD.0 0 1 Key Strobe Signal Output Control (SEG0/P8.0-SEG15/P8.15) Enable key strobe signal output (3) Disable key strobe signal output (4)
NOTES: 1. The pins which are not selected as external interrupt (K0-K6) can be used to normal I/O. To use external interrupts, corresponding pins must be set to input mode. 2. LCD clock can be selected only when main clock(fx) is used as clock source of watch timer. When sub clock(fxt) is used as clock source of watch timer, LCD clock is always fw/48 (1/9 duty), fw/44 (1/10 duty), fw/40 (1/11duty), or fw/36 (1/12 duty). 3. In this case, pull-up resistors of port0,1 are disabled if the value of PUR0 is "0", when the value of PUR0 is "1", the pull-up resistors of selected pins as interrupt input are enabled or disabled by key strobe signal, and that of nonselected pins are disabled. 4. In this case, pull-up resistors of port 0,1 are disabled or enabled by the value of PUR0 flag.
12-7
LCD CONTROLLER/DRIVER
S3C72Q5/P72Q5
Application Without Internal Contrast Control S3C72Q5 VDD VLC1 R1 VLC2 R2 VLC3 R3 VLC4 R4 VLC5 LCNST.7 = 0 "0" LCD "1" Controller Contrast LCON1 (ON) VSS VLCD Fixed VLCD = VDD
Application With Internal Contrast Control S3C72Q5 VDD VLC1 R1 VLC2 R2 VLC3 R3 VLC4 R4 VLC5 LCNST.7 = 1 "0" LCD "1" Controller Contrast LCON1 (ON) VSS VLCD Fixed VLCD = RLCD x VDD RLCD + RCN
NOTES: 1. When the LCD module is turned off, load LCON1 to "9" to reduce power consumption. 2. When LCNST.7 is logic one, LCD contrast can be controlled by writing data to LCNST.3-.0. 3. Where R CN is LCD contrast controller's resistor.
Figure 12-4. LCD Voltage Dividing Resistors Connection
12-8
S3C72Q5/P72Q5
LCD CONTROLLER/DRIVER
When LCON1 is 4 or 5, LMOD.0 are set to "0" and pull-up enable by PUMOD0, RE and LE signal are generated as below: tCOM = 1.46 ms (t XT = 32.768 kHz) COM COM0 1 2 3 4 5 tF = 13.18 ms 6 7 8 0
Resistor Enable : RE tSmax = 2.93 ms tSmin = 1.46 ms
tRE = 1.5 t XT = 45.8 s
~ ~
tE Input Latch Enable : LE
tD tLE = t XT/2 = t E = t D = 15.3 s
~ ~
Valid Input Signals: P0.0-P1.2 Latch Data
> tSmax
Figure 12-5. RE, LE and Inputs Signal Waveform (1/9 Duty)
~ ~ ~ ~
12-9
LCD CONTROLLER/DRIVER
S3C72Q5/P72Q5
fF = 75.85 Hz tAST = 45.8 s VLC1 VLC2 VLC3 VLC4 VSS VLC1 VLC2 VLC3 VLC4 VSS VLC1 VLC2 VLC3 VLC4 VSS VLC1 VLC2 VLC3 VLC4 VSS On Off On Off Off Off Off On Off On VLCD 3/4VLCD 2/4VLCD 1/4VLCD VSS -1/4VLCD -2/4VLCD -3/4VLCD -VLCD
COM0
COM1
COM8
SEG0
COM0 -SEG0
NOTE:
The upper figure is COM and SEG signal waveform when LMOD.0 is set to logic "0" and fw is 32.768 kHz.
Figure 12-6. LCD Signal Waveform for 1/9 Duty and 1/4 Bias
12-10
S3C72Q5/P72Q5
LCD CONTROLLER/DRIVER
When LCON1 is 4 or 5, LMOD.0 are set to "0" and pull-up enable by PUMOD0, RE and LE signal are generated as below: tCOM = 1.46 ms (tXT = 32.768 kHz) COM COM0 1 2 3 4 5 tF = 14.64 ms 6 7 8 9 0
Resistor Enable : RE tS = 2.93 ms tRE = 1.5 t XT = 45.8 s
~
tE Input Latch Enable : LE
tD tLE = t XT/2 = tE = t D = 15.3 s
~
Valid Input Signals: P0.0-P1.2 Latch Data
> tSmax
Figure 12-7. RE, LE and Inputs Signal Waveform (1/10 Duty)
~ ~ ~ ~
12-11
LCD CONTROLLER/DRIVER
S3C72Q5/P72Q5
fF = 68.3Hz tAST = 45.8 s VLC1 VLC2 VLC3 VLC4 VSS VLC1 VLC2 VLC3 VLC4 VSS VLC1 VLC2 VLC3 VLC4 VSS VLC1 VLC2 VLC3 VLC4 VSS Off On Off Off On On Off VLCD 3/4VLCD 2/4VLCD 1/4VLCD VSS -1/4VLCD -2/4VLCD -3/4VLCD -VLCD
COM0
COM1
COM9
SEG0
COM0 -SEG0
NOTE:
The upper figure is COM and SEG signal waveform when LMOD.0 is set to logic "0" and fw is 32.768 kHz.
Figure 12-8. LCD Signal Waveform for 1/10 Duty and 1/4 Bias
12-12
S3C72Q5/P72Q5
LCD CONTROLLER/DRIVER
When LCON1 is 4 or 5, LMOD.0 are set to "0" and pull-up enable by PUMOD0, RE and LE signal are generated as below: tCOM = 1.46 ms (t XT = 32.768 kHz) COM COM0 1 2 3 4 5 6 tF = 16.1 ms 7 8 9 10 0
Resistor Enable : RE tSmax = 2.93 ms tSmin = 1.46 ms
tRE = 1.5 t XT = 45.8 s
~ ~
tE Input Latch Enable : LE
tD tLE = t XT/2 = tE = t D = 15.3 s
~ ~
Valid Input Signals: P0.0-P1.2 Latch Data
> tSmax
Figure 12-9. RE, LE and Inputs Signal Waveform (1/11 Duty)
~ ~ ~ ~
12-13
LCD CONTROLLER/DRIVER
S3C72Q5/P72Q5
fF = 62.11 Hz tAST = 45.8 s VLC1 VLC2 VLC3 VLC4 VSS VLC1 VLC2 VLC3 VLC4 VSS VLC1 VLC2 VLC3 VLC4 VSS VLC1 VLC2 VLC3 VLC4 VSS Off On Off Off On Off Off Off On On Off VLCD 3/4VLCD 2/4VLCD 1/4VLCD VSS -1/4VLCD -2/4VLCD -3/4VLCD -VLCD
COM0
COM1
COM10
SEG0
COM0 -SEG0
NOTE:
The upper figure is COM and SEG signal waveform when LMOD.0 is set to logic "0" and fw is 32.768 kHz.
Figure 12-10. LCD Signal Waveform for 1/11 Duty and 1/4 Bias
12-14
S3C72Q5/P72Q5
LCD CONTROLLER/DRIVER
When LCON1 is 4 or 5, LMOD.0 are set to "0" and pull-up enable by PUMOD0, RE and LE signal are generated as below: tCOM = 1.46 ms (tXT = 32.768 kHz) COM COM0 1 2 3 4 5 6 7 tF = 17.56 ms 8 9 10 11 0
Resistor Enable : RE tS = 2.93 ms
tRE = 1.5 t XT = 45.8 s
~
tE Input Latch Enable : LE
tD tLE = t XT/2 = tE = t D = 15.3 s
~
Valid Input Signals: P0.0-P1.2 Latch Data
> tSmax
Figure 12-11. RE, LE and Inputs Signal Waveform (1/12 Duty)
~ ~ ~ ~
12-15
LCD CONTROLLER/DRIVER
S3C72Q5/P72Q5
fF = 56.95 Hz tAST = 45.8 s VLC1 VLC2 VLC3 VLC4 VSS VLC1 VLC2 VLC3 VLC4 VSS VLC1 VLC2 VLC3 VLC4 VSS VLC1 VLC2 VLC3 VLC4 VSS Off On Off Off On Off Off Off On On Off VLCD 3/4VLCD 2/4VLCD 1/4VLCD VSS -1/4VLCD -2/4VLCD -3/4VLCD -VLCD
COM0
COM1
COM11
SEG0
COM0 -SEG0
NOTE:
The upper figure is COM and SEG signal waveform when LMOD.0 is set to logic "0" and fw is 32.768 kHz.
Figure 12-12. LCD Signal Waveform for 1/12 Duty and 1/4 Bias
12-16
S3C72Q5/P72Q5
LCD CONTROLLER/DRIVER
KEY SCAN REGISTER (KSR) The 16 output pins (P8.0-P8.15) of 60 segments can be used for key check signal output. KSR0-KSR3 are mapped to the RAM address FA2H-FA5H, and the reset value is "0". KSR is the write-only register that can be manipulated by 4-bits RAM write instruction only. Table 12-5. KSR Organization KSR0 KSR1 KSR2 KSR3 KSR0.3 KSR1.3 KSR2.3 KSR3.3 KSR0.2 KSR1.2 KSR2.2 KSR3.2 KSR0.1 KSR1.1 KSR2.1 KSR3.1 KSR0.0 KSR1.0 KSR2.0 KSR3.0 FA2H FA3H FA4H FA5H
When LCON1 is 9, the values of KSR0-KSR3 are output to segment pins for key check regardless of LMOD.0. At this time, only one of 16 bits (KSR0.0-KSR3.3) must be set to logic "1", and the contents of KSR must be changed 16 times one by one for 16 key check by software. When a bit value of KSR is "1", the corresponding segment pin becomes the low level. Figure 12-14 shows its segment pin output.
SEG i
SEG i + 1 KSRx.0 = 1 KSRx.0 = 0
SEG i + 2 KSRx.1 = 1 KSRx.1 = 0
Non-overlap KSRx.2 = 1 NOTE: "x" means 0, 1, 2 and 3. KSRx.2 = 0
Figure 12-13. Segment Pin Output Signal When LCON1.3 = 1
12-17
S3C72Q5/P72Q5
EXTERNAL MEMORY INTERFACE
13
OVERVIEW
EXTERNAL MEMORY INTERFACE
The S3C72Q5 microcontroller can directly interface the external memory up to 6 x 4 M-bit. It external memory interface block has the following components. -- 8-bit external memory control register (EMCON) -- External memory address register 0, 1, 2 (EMAR0-EMAR2) -- 8-bit external memory data register 0 (EMDR0) -- External memory interface clock selector -- Six external memory selection pins (DM0-DM5) -- Eight data and nineteen address pins (D0-D7, A0-A18) It should be taken care to the LCD contrast due to an external memory interface, since all external memory interface lines except DM0-DM5 are shared with segment driver pins of LCD driver/controller. EXTERNAL MEMORY CONTROL REGISTER (EMCON) The external memory control register (EMCON) is used to read data from or write data in a external memory, to select external memory interface clock frequency, to increase automatically the address (a value of EMAR2-EMAR0) or not, and to select data memory pin (one of DM0-DM5). The EMCON can be manipulated using 8-bit write. FD2H FD3H EMCON.3 EMCON.7 EMCON.2 EMCON.6 EMCON.1 EMCON.5 EMCON.0 EMCON.4
The memory access clock frequency, fM, determines the read and write time for external memory. The fM should be selected appropriately because a memory has read and write time specified and the external memory interface lines except DM0-DM5 are shared with segment driver pins of LCD driver/controller.
13-1
EXTERNAL MEMORY INTERFACE
S3C72Q5/P72Q5
Table 13-1. External Memory Control Register (EMCON) Organization Memory Read/Write Control Bit EMCON.7 0 1 Memory read signal output Memory write signal output
Memory Access Clock Selection Bits EMCON.6 0 0 1 1 EMCON.5 0 1 0 1 fxx/8 fxx/4 fxx/2 fxx/1 Memory Access Clock Frequency (fM )
Address Increment Control Bit EMCON.4 0 1 Memory Selection Bits EMCON.3 0 0 0 0 1 1 EMCON.2 0 0 1 1 0 0 EMCON.1 0 1 0 1 0 1 External Data Memory Selection Data memory 0(DM0 active) Data memory 1(DM1 active) Data memory 2(DM2 active) Data memory 3(DM3 active) Data memory 4(DM4 active) Data memory 5(DM5 active) The address(a value of EMAR2 - EMAR0) is not increased automatically after memory access. The address(a value of EMAR2 - EMAR0) is increased automatically after memory access.
Memory Access Start Bit (This bit is cleared automatically when memory access is finished) EMCON.0 0 1 Not busy (read) Start a memory access (write) busy (read)
NOTES: 1. When it reads data from a external memory, the data are written to the register EMDR0. 2. When it writes data to a external memory, the data to the register EMDR0 are written to a external memory. 3. The external memory selection pins of P6.0/DM0 - P7.1/DM5 should be set to push-pull output and the latches should be set to logic "1".
13-2
S3C72Q5/P72Q5
EXTERNAL MEMORY INTERFACE
HOW TO ACCESS THE EXTERNAL MEMORY The pin which are selected for external memory interface of DM0-DM5 should be set to push-pull output and the latches should be set to logic "1". The procedure for external memory interface may be summarized as follows. 1. To read data form external memory -- Load the address of external memory to EMAR2-EMAR0 in bank 15. -- Clear EMCON.7 to logic 0, load appropriate values to EMCON.6-.1 -- Wait for memory access set-up time -- Set EMCON.0 to logic 1. -- Check EMCON.0 until for not busy ("0") -- Read a value of EMDR0 in bank 15 if EMCON.0 is "0". 2. To write data to external memory -- Load the address of external memory to EMAR2-EMAR0 in bank 15. -- Load data to EMDR0 in bank 15 -- Set EMCON.7 to logic 1, load appropriate values to EMCON.6-.1 -- Wait for memory access set-up time -- Set EMCON.0 to logic 1. -- Check EMCON.0 until not busy (0) before writing other data to external memory.
13-3
EXTERNAL MEMORY INTERFACE
S3C72Q5/P72Q5
F PROGRAMMING TIP -- External Memory Interface
The external memory selection pins of P6.0/DM0-P7.1/DM5 should be set to push-pull output and the latches should be set to logic "1". 1. To read data form external memory when DM0 and DM1 are used to control CS pins external memories respectively. BITS SMB LD LD LD LD LD LD : : : BITS SMB LD LD LD LD LD LD LD ; DELAY LD AND DECS JPS LD SMB LD EMB 15 EA,#03H PMG2,EA EA,#03H P6,EA EA,#00010000B EMCON,EA ; need set-up time ; Initial part ; DM0 and DM1 output ; DM0(P6.0) and DM1 (P6.1) latches "1" ; Read mode, increase address automatically, ; select DM0, fM = fxx/8
EMB 15 EA,#00H EMAR0,EA EMAR1,EA A,#4H EMAR2,A EA,#00010001B EMCON,EA EA,EMCON A,#0001B A DELAY EA,EMDR0 0 ADATR_B,EA
; External memory address 40000H ; Start a memory reading
NEXT
; Data
A0-A18 D0-D7 DW (2) DR DM0 ( Active) DM1 [S3C72Q5] SRAM (1)
13-4
S3C72Q5/P72Q5
EXTERNAL MEMORY INTERFACE
F PROGRAMMING TIP -- External Memory Interface (Continued)
2. To write data to external memory when DM0 and DM1 are used to control CS pins of external memory, respectively. BITS SMB LD LD LD LD LD LD : : : BITS SMB LD LD LD LD LD LD LD LD LD ; DELAY EMB 15 EA,#03H PMG2,EA EA,#03H P6,EA EA,#10010010B EMCON,EA ; need set-up time ; Initial part ; DM0 and DM1 output ; DM0(P6.0) and DM1 (P6.1) latches "1" ; Write mode, increase address automatically, ; select DM1, fM = fxx/8
EMB 15 EA,#00H EMAR0,EA EMAR1,EA A,#4H EMAR2,A EA,#38H EMDR0,EA EA,#10010011B EMCON,EA
; External memory address 40000H ; Data ; Write mode, increase address automatically, ; select DM1, fM = fxx/8
NEXT
LD AND DECS JPS SMB LD SMB LD
EA,EMCON A,#0001B A DELAY 0 EA,ADATR_B 15 EMDR0,EA
; Data
A0-A18 D0-D7 DW (1) DR DM0 DM1 ( Active) [S3C72Q5] SRAM (0)
13-5
EXTERNAL MEMORY INTERFACE
S3C72Q5/P72Q5
EXTERNAL MEMORY WRITE CYCLE TIMING DIAGRAM
Memory Access Clock: fM EMCON.0 "1" SEG Signal D0-D7, A0-A18 SEG Signal
SEG16/D0-SEG23/D7 SEG24/A0-SEG42/A18 SEG43/DR
SEG Signal
SEG Signal
SEG44/DW
SEG Signal
SEG Signal
DM 2/fM
Figure 13-1. External Memory Write Cycle Timing Diagram
EXTERNAL MEMORY READ CYCLE TIMING DIAGRAM
Memory Access Clock: fM
SEG16/D0-SEG23/D7 SEG24/A0-SEG42/A18 SEG43/DR
SEG Signal
D0-D7, A0-A18
SEG Signal
SEG Signal
SEG Signal
SEG44/DW
SEG Signal
SEG Signal
DM 2/fM
Figure 13-2. External Memory Read Cycle Timing Diagram
13-6
S3C72Q5/P72Q5
EXTERNAL MEMORY INTERFACE
LCD Pannel
A0-A18 D0-D7 DR DW S3C72Q5X DM0 DM1 DM2 DM3 DM4 DM5
A0-A18 D0-D7 DE WE CS CS 4 CS 5 CS CS CS SRAM0 (4 M bit) 1 2 3
Figure 13-3. External Interface Function Diagram (S3C72Q5, SRAM, EPROM, EEPROM)
13-7
S3C72Q5/P72Q5
ELECTRICAL DATA
14
OVERVIEW
ELECTRICAL DATA
In this section, information on S3C72Q5 electrical characteristics is presented as tables and graphics. The information is arranged in the following order: Standard Electrical Characteristics -- Absolute maximum ratings -- D.C electrical characteristics -- Main-system clock oscillator characteristics -- Sub-system clock oscillator characteristics -- I/O capacitance -- A.C electrical characteristics -- Operating voltage range Miscellaneous Timing Waveforms -- A.C timing measurement point -- Clock timing measurement at XIN -- Clock timing measurement at XT IN -- TCL0 timing -- Input timing for RESET -- Input timing for external interrupts Stop Mode Characteristics and Timing Waveforms -- RAM data retention supply voltage in stop mode -- Stop mode release timing when initiated by RESET -- Stop mode release timing when initiated by an interrupt request
14-1
ELECTRICAL DATA
S3C72Q5/P72Q5
Table 14-1. Absolute Maximum Ratings (TA = 25 C) Parameter Supply Voltage Input Voltage Output Voltage Output Current High Symbol VDD VI VO IOH IOL One I/O pin active All I/O pins active Output Current Low One I/O pin active Total for ports 0, 1, 4 - 7, 8 Operating Temperature Storage Temperature
NOTE:
Conditions - Ports 0, 1, 4 - 7 -
Rating - 0.3 to + 6.5 - 0.3 to VDD + 0.3 - 0.3 to VDD + 0.3 - 15 - 30 + 30 (Peak value) + 15 (note) + 100 (Peak value) + 60 (note) - 25 to + 85 - 65 to + 150
Duty .
Units V V V mA
mA
TA Tstg
- -
C C
The values for Output Current Low ( IOL ) are calculated as Peak Value x
Table 14-2. D.C Electrical Characteristics (TA = - 25 C to + 85 C, VDD = 1.8 V to 5.5 V) Parameter Operating Voltage Input High Voltage Symbol VDD VIH1 VIH2 VIH3 Input Low Voltage VIL1 VIL2 VIL3 Output High Voltage Output Low Voltage VOH Conditions fx = 0.4 - 3MHz, fxt = 32.8kHz fx = 0.4 - 6MHz Ports 0, 1, 4 - 7 and D0 - D7 RESET XIN, XOUT, XTIN, and XTOUT Ports 0, 1, 4 - 7 and D0 - D7 RESET XIN, XOUT, XTIN, and XTOUT VDD = 4.5 V to 5.5 V IOH = - 1 mA VOL Ports 0,1,4-7, Memory access pins VDD = 4.5 V to 5.5 V IOL = 15 mA Ports 0,1,4-7, Memory access pins VDD = 1.8 V to 5.5 V IOL = 1.6 mA 0.4 - 2.0 VDD - 1.0 Min 1.8 2.7 0.8V DD 0.7V DD VDD - 0.1 - Typ - - - Max 5.5 5.5 VDD VDD VDD 0.2V DD 0.3V DD 0.1 - Units V
14-2
S3C72Q5/P72Q5
ELECTRICAL DATA
Table 14-2. D.C Characteristics (Continued) (TA = - 25 C to + 85 C, VDD = 1.8 V to 5.5 V) Parameter Input High Leakage Current Symbol ILIH1 Conditions VI = VDD All input pins except those specified below for ILIH2 VI = VDD XIN, XOUT, XTIN, XTOUT Input Low Leakage Current ILIL1 VI = 0 V All input pins except RESET, XIN, XOUT, XTIN, and XTOUT ILIL2 Output High Leakage Current Output Low Leakage Current Pull-Up Resistor ILOH ILOL RL1 VI = 0 V XIN, XOUT, XTIN, XTOUT VO = VDD All output pins VO = 0 V All output pins VI = 0 V; VDD = 5V; TA = 25 C Ports 0, 1, 4 - 7 VDD = 3V RL2 VI = 0 V; VDD = 5V; RESET TA = 25 C VDD = 3V LCD Voltage Dividing Resistor RLCD1 RLCD2 VLC1-COMi Voltage Drop (i = 0-11) VLC1-SEGx Voltage Drop (x = 0-59) Middle Output Voltage (1) VDC TA = 25 C When LMOD.1 = "0" TA = 25 C When LMOD.1 = "1" - 15 A per common pin - - 120 mV 23 33 43 250 46 500 66 750 86 50 100 100 200 150 300 25 50 75 k 3 -3 - 20 -3 Min - Typ - Max 3 Units A
ILIH2
20
VDS
- 15 A per common pin
-
-
120
VLC2 VLC3 VLC4
VDD = 2.4V to 5.5V, 1/4 bias LCD clock = 0Hz
0.75V DD - 0.2 0.5V DD - 0.2 0.25V DD - 0.2
0.75V DD 0.5V DD 0.25V DD
0.75V DD + 0.2 0.5V DD + 0.2 0.25V DD + 0.2
V
NOTES: 1. It is middle output voltage when LCD controller/driver is 1/12 duty and 1/4 bias. 2. Low leakage current is absolute value.
14-3
ELECTRICAL DATA
S3C72Q5/P72Q5
Table 14-2. D.C Characteristics (continued) (TA = - 25 C to + 85 C, VDD = 1.8 V to 5.5 V) Parameter Supply Current (1) Symbol IDD1 (2) Conditions Run mode VDD = 5 V 10% Crystal oscillator C1 = C2 = 22pF VDD = 3 V 10% IDD2 (2) Idle mode VDD = 5 V 10% Crystal oscillator C1 = C2 = 22pF VDD = 3 V 10% IDD3 (3) IDD4 (3) IDD5 6 MHz 4.19 MHz 0.5 0.4 20 5.0 2.5 1.5 1.0 35 15 5 A 6 MHz 4.19 MHz 6 MHz 4.19 MHz 2.0 1.5 1.3 1.0 4.0 3.0 2.5 1.8 6 MHz 4.19 MHz Min - Typ 4.5 3.2 Max 8.0 5.5 Units mA
Run mode; VDD = 3 V 10% 32 kHz crystal oscillator Idle mode; VDD = 3 V 10% 32 kHz crystal oscillator Stop mode; TA = 25 C VDD = 5 V 10% Stop mode; TA = 25 C VDD = 3 V 10% Stop mode; TA = 25 C VDD = 5 V 10% Stop mode; TA = 25 C VDD = 3 V 10% SCMOD = 0100B SCMOD = 0000B XTIN = 0V
0.5
3
0.2
3
0.1
2
NOTES: 1. Currents in the following circuits are not included; on-chip pull-up resistors, internal LCD voltage dividing resistors, output port drive currents. 2. Data includes power consumption for subsystem clock oscillation. 3. When the system clock control register, SCMOD, is set to 1001B, main system clock oscillation stops and the subsystem clock is used. When the LCD display is on, LCD module current may be about 100uA. 4. Every values in this table is measured when the power control register (PCON) is set to "0011B".
14-4
S3C72Q5/P72Q5
ELECTRICAL DATA
Table 14-3. Main System Clock Oscillator Characteristics (TA = - 25 C to + 85 C, VDD = 1.8 V to 5.5 V) Oscillator Ceramic Oscillator
XIN XOUT
Clock Configuration
Parameter Oscillation frequency(fx) (1) Stabilization time (2)
Test Condition 2.7V - 5.5V 1.8V - 5.5V After VDD reaches the minimum level of its variable range; VDD = 2.0 V to 5.5 V
Min 0.4 0.4 -
Typ - - -
Max 6 3 4
Units MHz
ms
C1
C2
Crystal Oscillator
XIN XOUT
Oscillation frequency(fx) (1) Stabilization time (2)
2.7V - 5.5V 1.8V - 5.5V VDD = 4.5 V to 5.5 V
0.4 0.4 -
- - -
6 3 10
MHz
ms
C1
C2
VDD = 2.0 V to 5.5 V External Clock
XIN XOUT
- 0.4 0.4 83.3
- - - -
30 6 3
1250
XIN input frequency(fx) (1) XIN input high and low level width (t XH, tXL)
2.7V - 5.5V 1.8V - 5.5V -
MHz
ns
RC Oscillator
XIN R
XOUT
Frequency
VDD = 5 V
0.4
-
2
MHz
VDD = 3 V
0.4
-
1
NOTES: 1. Oscillation frequency and input frequency data are for oscillator characteristics only. 2. Stabilization time is the interval required for oscillator stabilization after a power-on or release of STOP mode.
14-5
ELECTRICAL DATA
S3C72Q5/P72Q5
Table 14-4. Recommended Oscillator Constants (TA = - 25 C to + 85 C, VDD = 1.8 V to 5.5 V) Manufacturer Series Number (1) Frequency Range Load Cap (pF) C1 TDK FCR-M5 FCR-MC5 CCR-MC3 3.58 MHz-6.0 MHz 3.58 MHz-6.0 MHz 3.58 MHz-6.0 MHz 33
(2)
Oscillator Voltage Range (V) MIN 2.0 2.0 2.0 MAX 5.5 5.5 5.5
Remarks
C2 33
(2)
Leaded Type On-chip C Leaded Type On-chip C SMD Type
(3)
(3)
NOTES: 1. Please specify normal oscillator frequency. 2. On-chip C: 30pF built in. 3. On-chip C: 38pF built in.
14-6
S3C72Q5/P72Q5
ELECTRICAL DATA
Table 14-5. Subsystem Clock Oscillator Characteristics (TA = - 25 C to + 85 C, VDD = 1.8 V to 5.5 V) Oscillator Crystal Oscillator
XTIN XTOUT
Clock Configuration
Parameter Oscillation frequency (1) Stabilization time (2)
Test Condition - VDD = 4.5 V to 5.5 V
Min 32 -
Typ 32.768 1.0
Max 35 2
Units kHz s
C1
C2
VDD = 2.0 V to 5.5 V External Clock
XTIN XTOUT
- 32 5
- - -
10 100 15 kHz uS
XTIN input frequency (1) XTIN input high and low level width (t XTL, tXTH)
-
NOTES: 1. Oscillation frequency and XT IN input frequency data are for oscillator characteristics only. 2. Stabilization time is the interval required for oscillating stabilization after a power-on occurs or release of sub clock stop
Table 14-6. Input/Output Capacitance (TA = 25 C, VDD = 0 V ) Parameter Input Capacitance Output Capacitance I/O Capacitance Symbol CIN COUT CIO Condition f = 1 MHz; Unmeasured pins are returned to VSS Min - Typ - Max 15 Units pF
14-7
ELECTRICAL DATA
S3C72Q5/P72Q5
Table 14-7. A.C. Electrical Characteristics (TA = - 25 C to + 85 C, VDD = 1.8 V to 5.5 V) Parameter Instruction Cycle Time (note) Symbol tCY Conditions VDD = 2.7 V to 5.5 V VDD = 1.8 V to 5.5 V With subsystem clock (fxt) TCL0 Input Frequency fTI VDD = 2.7 V to 5.5 V VDD = 1.8 V to 5.5 V TCL0 Input High, Low Width Interrupt Input High, Low Width tTIH tTIL fINTH, fINTL K0 - K6 RESET Input Low Width
NOTE:
Min 0.67 1.33 114 0
Typ -
Max 64 64
Units uS
122 -
125 1.5 1 MHz kHz uS
VDD = 2.7 V to 5.5 V VDD = 1.8 V to 5.5 V INT0, INT1, KS0 - KS7
0.48 1.8 10
-
-
tRSL
Input
10
Unless otherwise specified, Instruction Cycle Time condition values assume a main system clock ( fx ) source.
14-8
S3C72Q5/P72Q5
ELECTRICAL DATA
CPU Clock 1.5 MHz
Main Oscillator Frequency 6 MHz
0.75 MHz
3 MHz
15.625 kHz 1 2 1.8 V 3 2.7 V Supply Voltage (V) CPU clock = 1/n x oscillator frequency (n = 4, 8 or 64) 4 5 5.5 V 6 7
Figure 14-1. Standard Operating Voltage Range
Table 14-8. RAM Data Retention Supply Voltage in Stop Mode (TA = - 25 C to + 85 C) Parameter Data retention supply voltage Data retention supply current Release signal set time Oscillator stabilization wait time (1) Symbol VDDDR IDDDR tSREL tWAIT Conditions - VDDDR = 1.8 V - Released by RESET Released by interrupt Min 1.8 - 0 - - Typ - 0.1 - 217/fx
(2)
Max 5.5 10 - - -
Unit V uA uS ms
NOTES: 1. During oscillator stabilization wait time, all CPU operations must be stopped to avoid instability during oscillator startup. 2. Use the basic timer mode register (BMOD) interval timer to delay execution of CPU instructions during the wait time.
14-9
ELECTRICAL DATA
S3C72Q5/P72Q5
TIMING WAVEFORMS
Internal RESET Operation Stop Mode Data Retention Mode Idle Mode Operating Mode
~ ~ ~ ~
VDD
VDDDR Execution of STOP Instruction RESET tWAIT tSREL
Figure 14-2. Stop Mode Release Timing When Initiated By RESET
Idle Mode
~ ~ ~ ~
Stop Mode Data Retention
Normal Operating Mode
VDD
VDDDR Execution of STOP Instruction
tSREL
tWAIT Power-down Mode Terminating Signal (Interrupt Request)
Figure 14-3. Stop Mode Release Timing When Initiated By Interrupt Request
14-10
S3C72Q5/P72Q5
ELECTRICAL DATA
0.8 VDD Measurement Points 0.2 VDD
0.8 VDD
0.2 VDD
Figure 14-4. A.C. Timing Measurement Points (Except for XIN and XTIN)
tINTL
tINTH
INT0, 1 INTP0 (K0-K6) KS0 to KS2
0.8 VDD 0.2 VDD
Figure 14-5. Input Timing for External Interrupts and Quasi -Interrupts
14-11
ELECTRICAL DATA
S3C72Q5/P72Q5
1/fx tXL tXH
XIN
VDD - 0.1 V 0.1 V
Figure 14-6. Clock Timing Measurement at XIN
1/fxt tXTL tXTH
XT IN
VDD - 0.1 V 0.1 V
Figure 14-7. Clock Timing Measurement at XTIN
14-12
S3C72Q5/P72Q5
ELECTRICAL DATA
1/fTI tTIL tTIH
TCL0
0.8 VDD 0.2 VDD
Figure 14-6. TCL0 Timing
tRSL
RESET 0.3 VDD
Figure 14-7. Input Timing for RESET Signal
14-13
S3C72Q5/P72Q5
MECHANICAL DATA
15
OVERVIEW
MECHANICAL DATA
The S3C72Q5 microcontroller is currently available in a 100-pin QFP package.
23.90 0.3 0-8 20.00 0.2 0.15
+0.10 -0.05
17.90 0.3
14.00 0.2
100-QFP-1420C
0.80 0.20
0.10 MAX
#100 (0.83) 0.3 0.1 0.10 MAX 0.65 (0.58)
#1
0.05 MIN 2.65 0.10 3.00 MAX
0.80 0.20 NOTE : Dimensions are in millimeters.
Figure 15-1. 100-QFP-1420 Package Dimensions
15-1
S3C72Q5/P72Q5
S3P72Q5 OTP
16
OVERVIEW
S3P72Q5 OTP
The S3P72Q5 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the S3C72Q5 microcontroller. It has an on-chip OTP ROM instead of masked ROM. The EPROM is accessed by serial data format. The S3P72Q5 is fully compatible with the S3C72Q5, both in function and in pin configuration. Because of its simple programming requirements, the S3P72Q5 is ideal for use as an evaluation chip for the S3C72Q5.
16-1
S3P72Q5 OTP
S3C72Q5/P72Q5
SEG39/A15 SEG40/A16 SEG41/A17 SEG42/A18 SEG43/DR SEG44/DW SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 SEG38/A14 SEG37/A13 SEG36/A12 SEG35/A11 SEG34/A10 SEG33/A9 SEG32/A8 SEG31/A7 SEG30/A6 SEG29/A5 SEG28/A4 SEG27/A3 SEG26/A2 SEG25/A1 SEG24/A0 SEG23/D7 SEG22/D6 SEG21/D5 SEG20/D4 SEG19/D3 SEG18/D2 SEG17/D1 SEG16/D0 SEG15/P8.15 SEG14/P8.14 SEG13/P8.13 SEG12/P8.12 SEG11/P8.11 SEG10/P8.10 SEG9/P8.9
SEG59 COM4 COM5 COM6 COM7 COM8 P7.3/KS7/COM9 P7.2/KS6/COM10 P7.1/KS5/DM5/COM11 P7.0/KS4/DM4 P6.3/KS3/DM3 P6.2/KS2/DM2 SDAT/P6.1/KS1/DM1 SCLK/P6.0/KS0/DM0 VDD VSS XOUT XIN VPP/TEST XTIN XTOUT RESET P5.0 P5.1 P5.2/BUZ P5.3/CLO P4.0/TCL0 P4.1/TCLO0 P4.2/INT0 P4.3/INT1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
S3P72Q5
(100-QFP-1420C)
Figure 16-1. S3P72Q5 Pin Assignments (100-QFP Package)
50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 SEG8/P8.8 SEG7/P8.7 SEG6/P8.6 SEG5/P8.5 SEG4/P8.4 SEG3/P8.3 SEG2/P8.2 SEG1/P8.1 SEG0/P8.0 COM3 COM2 COM1 COM0 P0.0/K0 P0.1/K1 P0.2/K2 P0.3/K3 P1.0/K4 P1.1/K5 P1.2/K6
16-2
S3C72Q5/P72Q5
S3P72Q5 OTP
Table 16-1. Descriptions of Pins Used to Read/Write the EPROM Main Chip Pin Name P3.1 Pin Name SDAT Pin No. 13 I/O I/O During Programming Function Serial data pin. Output port when reading and input port when writing. Can be assigned as a Input / push-pull output port. Serial clock pin. Input only pin. Power supply pin for EPROM cell writing (indicates that OTP enters into the writing mode). When 12.5 V is applied, OTP is in writing mode and when 5 V is applied, OTP is in reading mode. (Option) Chip initialization Logic power supply pin. VDD should be tied to +5 V during programming.
P3.0 TEST
SCLK VPP(TEST)
14 19
I/O I
RESET VDD / VSS
RESET VDD / VSS
22 15/16
I I
Table 16-2. Comparison of S3P72Q5 and S3C72Q5 Features Characteristic Program Memory Operating Voltage (V DD) OTP Programming Mode Pin Configuration EPROM Programmability S3P72Q5 16 Kbyte EPROM 1.8 V to 5.5 V VDD = 5 V, VPP(TEST)=12.5V 100 QFP User Program 1 time 100 QFP Programmed at the factory S3C72Q5 16 Kbyte mask ROM 1.8 V to 5.5V
OPERATING MODE CHARACTERISTICS When 12.5 V is supplied to the VPP(TEST) pin of the S3P72Q5, the EPROM programming mode is entered. The operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in Table 16-3 below. Table 16-3. Operating Mode Selection Criteria VDD 5V VPP(TEST) 5V 12.5 V 12.5 V 12.5 V
NOTE:
REG/MEM 0 0 0 1
Address (A15-A0) 0000H 0000H 0000H 0E3FH
R/W 1 0 1 0 EPROM read
Mode
EPROM program EPROM verify EPROM read protection
"0" means Low level; "1" means High level.
16-3
S3P72Q5 OTP
S3C72Q5/P72Q5
Table 16-4. D.C Characteristics (TA = - 25 C to + 85 C, VDD = 1.8 V to 5.5 V) Parameter Supply Current (1) Symbol IDD1 (2) Conditions Run mode VDD = 5 V 10% Crystal oscillator C1 = C2 = 22pF VDD = 3 V 10% IDD2 (2) Idle mode VDD = 5 V 10% Crystal oscillator C1 = C2 = 22pF VDD = 3 V 10% IDD3 (3) IDD4 (3) IDD5 6 MHz 4.19 MHz 0.5 0.4 20 5.0 2.5 1.5 1.0 35 15 5 A 6 MHz 4.19 MHz 6 MHz 4.19 MHz 2.0 1.5 1.3 1.0 4.0 3.0 2.5 1.8 6 MHz 4.19 MHz Min - Typ 4.5 3.2 Max 8.0 5.5 Units mA
Run mode; VDD = 3 V 10% 32 kHz crystal oscillator Idle mode; VDD = 3 V 10% 32 kHz crystal oscillator Stop mode; TA = 25 C VDD = 5 V 10% Stop mode; TA = 25 C VDD = 3 V 10% Stop mode; TA = 25 C VDD = 5 V 10% Stop mode; TA = 25 C VDD = 3 V 10% SCMOD = 0100B SCMOD = 0000B XTIN = 0V
0.5
3
0.2
3
0.1
2
NOTES: 1. Currents in the following circuits are not included; on-chip pull-up resistors, internal LCD voltage dividing resistors, output port drive currents. 2. Data includes power consumption for subsystem clock oscillation. 3. When the system clock control register, SCMOD, is set to 1001B, main system clock oscillation stops and the subsystem clock is used. When the LCD display is on, LCD module current may be about 100uA. 4. Every values in this table is measured when the power control register (PCON) is set to "0011B".
16-4
S3C72Q5/P72Q5
S3P72Q5 OTP
CPU Clock 1.5 MHz
Main Oscillator Frequency 6 MHz
0.75 MHz
3 MHz
15.625 kHz 1 2 1.8 V 3 2.7 V Supply Voltage (V) CPU clock = 1/n x oscillator frequency (n = 4, 8 or 64) 4 5 5.5 V 6 7
Figure 16-2. Standard Operating Voltage Range
16-5
S3C72Q5/P72Q5
DEVELOPMENT TOOLS
17
OVERVIEW
SHINE
DEVELOPMENT TOOLS
Samsung provides a powerful and easy-to-use development support system in turnkey form. The development support system is configured with a host system, debugging tools, and support software. For the host system, any standard computer that operates with MS-DOS as its operating system can be used. One type of debugging tool including hardware and software is provided: the sophisticated and powerful in-circuit emulator, SMDS2+, for S3C7, S3C9, S3C8 families of microcontrollers. The SMDS2+ is a new and improved version of SMDS2. Samsung also offers support software that includes debugger, assembler, and a program for setting options.
Samsung Host Interface for In-Circuit Emulator, SHINE, is a multi-window based debugger for SMDS2+. SHINE provides pull-down and pop-up menus, mouse support, function/hot keys, and context-sensitive hyper-linked help. It has an advanced, multiple-windowed user interface that emphasizes ease of use. Each window can be sized, moved, scrolled, highlighted, added, or removed completely. SAMA ASSEMBLER The Samsung Arrangeable Microcontroller (SAM) Assembler, SAMA, is a universal assembler, and generates object code in standard hexadecimal format. Assembled program code includes the object code that is used for ROM data and required SMDS program control data. To assemble programs, SAMA requires a source file and an auxiliary definition (DEF) file with device specific information. SASM57 The SASM57 is an relocatable assembler for Samsung's S3C7-series microcontrollers. The SASM57 takes a source file containing assembly language statements and translates into a corresponding source code, object code and comments. The SASM57 supports macros and conditional assembly. It runs on the MS-DOS operating system. It produces the relocatable object code only, so the user should link object file. Object files can be linked with other object files and loaded into memory. HEX2ROM HEX2ROM file generates ROM code from HEX file which has been produced by assembler. ROM code must be needed to fabricate a microcontroller which has a mask ROM. When generating the ROM code (.OBJ file) by HEX2ROM, the value 'FF' is filled into the unused ROM area upto the maximum ROM size of the target device automatically. TARGET BOARDS Target boards are available for all S3C7-series microcontrollers. All required target system cables and adapters are included with the device-specific target board. OTPs One time programmable microcontroller (OTP) for the S3C72Q5 microcontroller and OTP programmer (Gang) are now available.
17-1
DEVELOPMENT TOOLS
S3C72Q5/P72Q5
IBM-PC AT or Compatible
RS-232C
SMDS2+
PROM/OTP Writer Unit
Target Application System
RAM Break/Display Unit Probe Adapter Bus Trace/Timer Unit
SAM4 Base Unit
POD
TB72Q5 Target Board Eva Chip
Power Supply Unit
Figure 17-1. SMDS Product Configuration (SMDS2+)
17-2
S3C72Q5/P72Q5
DEVELOPMENT TOOLS
TB72Q5 TARGET BOARD The TB72Q5 target board is used for the S3C72Q5 microcontroller. It is supported by the SMDS2+ development system.
TB72Q5
To User_VCC Off RESET On U2 74HC11 Stop Idle
+
+
XTI XTAL
25 100-Pin Connector
MDS J101 1 2 51 J102 52
50-Pin Connector
1
160 QFP S3E7200 EVA Chip
External Triggers Ch1 Ch2
XI XTAL 49 50 99 100
MDS
SM1271A
Figure 17-2. TB72Q5 Target Board Configuration
50-Pin Connector
17-3
DEVELOPMENT TOOLS
S3C72Q5/P72Q5
Table 17-1. Power Selection Settings for TB72Q5 'To User_Vcc' Settings
To User_VCC Off On
Operating Mode
Comments The SMDS2/SMDS2+ supplies VCC to the target board (evaluation chip) and the target system.
TB72Q5
VCC VSS
Target System
VCC SMDS2/SMDS2+
To User_VCC Off On
TB72Q5
External VCC VSS
Target System
The SMDS2/SMDS2+ supplies VCC only to the target board (evaluation chip). The target system must have its own power supply.
VCC SMDS2+
Table 17-2. Main-clock Selection Settings for TB72Q5 Sub Clock Setting
XI XTAL MDS
Operating Mode
EVA Chip S3E72Q0 XOUT No Connection 100 Pin Connector SMDS2/SMDS2+
Comments Set the XI switch to "MDS" when the target board is connected to the SMDS2/SMDS2+.
XIN
XI XTAL MDS
EVA Chip S3E72Q0 XOUT XTAL Target Board
Set the XI switch to "XTAL" when the target board is used as a standalone unit, and is not connected to the SMDS2/SMDS2+.
XIN
17-4
S3C72Q5/P72Q5
DEVELOPMENT TOOLS
Table 17-3. Sub-clock Selection Settings for TB72Q5 Sub Clock Setting
XTI XTAL MDS
Operating Mode
EVA Chip S3E72Q0 XT OUT No Connection 100 Pin Connector SMDS2/SMDS2+
Comments Set the XTI switch to "MDS" when the target board is connected to the SMDS2/SMDS2+.
XTIN
XTI XTAL MDS
EVA Chip S3E72Q0 XT OUT XTAL Target Board
Set the XTI switch to "XTAL" when the target board is used as a standalone unit, and is not connected to the SMDS2/SMDS2+.
XTIN
IDLE LED This LED is ON when the evaluation chip (S3E72Q0) is in idle mode. STOP LED This LED is ON when the evaluation chip (S3E72Q0) is in stop mode.
17-5
DEVELOPMENT TOOLS
S3C72Q5/P72Q5
J101 SEG59 COM5 COM7 P7.3/KS7/COM9 P7.1/KS5/DM5/COM11 P6.3/KS3/DM3 P6.1/KS1/DM1 VDD XOUT TEST XTOUT P5.0 P5.2/BUZ P4.0/TCL0 P4.2/INT0 P1.2/K6 P1.0/K4 P0.2/K2 P0.0/K0 COM1 COM3 SEG1/P8.1 SEG3/P8.3 SEG5/P8.5 SEG7/P8.7 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 COM4 COM6 COM8 P7.2/KS6/COM10 P7.0/KS4/DM4 P6.2/KS2/DM2 P6.0/KS0/DM0 VSS XIN XTIN RESET P5.1 P5.3/CLO P4.1/TCLO0 P4.3/INT1 P1.1/K5 P0.3/K3 P0.1/K1 COM0 COM2 SEG0/P8.0 SEG2/P8.2 SEG4/P8.4 SEG6/P8.5 SEG8/P8.8 SEG9/P8.9 SEG11/P8.11 SEG13/P8.13 SEG15/P8.15 SEG17/D1 SEG19/D3 SEG21/D5 SEG23/D7 SEG25/A1 SEG27/A3 SEG29/A5 SEG31/A7 SEG33/A9 SEG35/A11 SEG37/A13 SEG39/A15 SEG41/A17 SEG43/DR SEG45 SEG47 SEG49 SEG51 SEG53 SEG55 SEG57 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99
J102 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 SEG10/P8.10 SEG12/P8.12 SEG14/P8.14 SEG16/D0 SEG18/D2 SEG20/D4 SEG22/D6 SEG24/A0 SEG26/A2 SEG28/A4 SEG30/A6 SEG32/A8 SEG34/A10 SEG36/A12 SEG38/A14 SEG40/A16 SEG42/A18 SEG44/DW SEG46 SEG48 SEG50 SEG52 SEG54 SEG56 SEG58
Target Board J101 50-Pin DIP Connector 1 2 J102 51 52 Target Cable for 50-Pin Connector Part Name: (AS50D-A) Order Cods: SM6305 49 50 99 100 51
Figure 17-4. TB72Q5 Adapter Cable for 100-QFP Package (S3C72Q5/P72Q5)
50-Pin DIP Connector
50-Pin DIP Connector
Figure 17-3. 50-Pin Connectors for TB72Q5
Target System J102 52 1 J101 50-Pin DIP Connector 2
99 100
49
50
17-6
S3C7 SERIES MASK ROM ORDER FORM
Product description: Device Number: S3C7__________- ___________(write down the ROM code number) Package Pellet Wafer Package Type: __________
Product Order Form:
Package Marking (Check One): Standard Custom A (Max 10 chars) Custom B (Max 10 chars each line)
SEC
@ YWW Device Name
@ YWW Device Name
@ YWW
@ : Assembly site code, Y : Last number of assembly year, WW : Week of assembly
Delivery Dates and Quantities: Deliverable ROM code Customer sample Risk order Please answer the following questions: See Risk Order Sheet Required Delivery Date - Quantity Not applicable Comments See ROM Selection Form
F
For what kind of product will you be using this order? New product Replacement of an existing product Upgrade of an existing product Other
If you are replacing an existing product, please indicate the former product name ( )
F
What are the main reasons you decided to use a Samsung microcontroller in your product? Please check all that apply. Price Development system Used same micom before Product quality Technical support Quality of documentation Features and functions Delivery on time Samsung reputation
Mask Charge (US$ / Won): Customer Information: Company Name: Signatures:
____________________________
___________________ ________________________ (Person placing the order)
Telephone number
_________________________
__________________________________ (Technical Manager)
(For duplicate copies of this form, and for additional ordering information, please contact your local Samsung sales representative. Samsung sales offices are listed on the back cover of this book.)
S3C7 SERIES REQUEST FOR PRODUCTION AT CUSTOMER RISK
Customer Information: Company Name: Department: Telephone Number: Date: Risk Order Information: Device Number: Package: Intended Application: Product Model Number: S3C7________- ________ (write down the ROM code number) Number of Pins: ____________ Package Type: _____________________ ________________________________________________________________ ________________________________________________________________ __________________________ __________________________ Fax: _____________________________
________________________________________________________________ ________________________________________________________________
Customer Risk Order Agreement: We hereby request SEC to produce the above named product in the quantity stated below. We believe our risk order product to be in full compliance with all SEC production specifications and, to this extent, agree to assume responsibility for any and all production risks involved.
Order Quantity and Delivery Schedule: Risk Order Quantity: Delivery Schedule: Delivery Date (s) Quantity Comments _____________________ PCS
Signatures:
_______________________________ (Person Placing the Risk Order)
______________________________________ (SEC Sales Representative)
(For duplicate copies of this form, and for additional ordering information, please contact your local Samsung sales representative. Samsung sales offices are listed on the back cover of this book.)
S3C72Q5 MASK OPTION SELECTION FORM
Device Number: S3C72Q5-_________ (write down the ROM code number)
Attachment (Check one):
Diskette
PROM
Customer Checksum:
________________________________________________________________
Company Name:
________________________________________________________________
Signature (Engineer):
________________________________________________________________
Please answer the following questions:
F
Application (Product Model ID:
_______________________)
Audio LCD Databank Industrials Remocon
Video Caller ID Home Appliance Other
Telecom LCD Game Office Automation
Please describe in detail its application
__________________________________________________________________________ _
S3P7 SERIES OTP FACTORY WRITING ORDER FORM (1/2)
Product Description: Device Number: S3P ________-________(write down the ROM code number) Package Package Type: Pellet _____________________ Wafer
Product Order Form: If the product order form is package: Package Marking (Check One): Standard
Custom A (Max 10 chars)
Custom B (Max 10 chars each line)
SEC
@ YWW Device Name
@ YWW Device Name
@ YWW
@ : Assembly site code, Y : Last number of assembly year, WW : Week of assembly
Delivery Dates and Quantity: ROM Code Release Date Required Delivery Date of Device Quantity
Please answer the following questions:
F
What is the purpose of this order? New product development Replacement of an existing microcontroller Upgrade of an existing product Other
If you are replacing an existing microcontroller, please indicate the former microcontroller name ( )
F
What are the main reasons you decided to use a Samsung microcontroller in your product? Please check all that apply. Price Development system Used same micom before Product quality Technical support Quality of documentation Features and functions Delivery on time Samsung reputation
Customer Information: Company Name: Signatures: ___________________ ________________________ (Person placing the order) Telephone number _________________________
__________________________________ (Technical Manager)
S3P72Q5 OTP FACTORY WRITING ORDER FORM (2/2)
Device Number: S3P ___-__________ (write down the ROM code number)
Customer Checksums:
_______________________________________________________________
Company Name:
________________________________________________________________
Signature (Engineer):
________________________________________________________________
Read Protection (1):
Yes
No
Please answer the following questions:
F
Are you going to continue ordering this device? Yes If so, how much will you be ordering? No _________________pcs
F
Application (Product Model ID: _______________________)
Audio LCD Databank Industrials Remocon
Video Caller ID Home Appliance Other
Telecom LCD Game Office Automation
Please describe in detail its application
__________________________________________________________________________
NOTES: 1. Once you choose a read protection, you cannot read again the programming code from the EPROM. 2. FLASH MCU Writing will be executed in our manufacturing site. 3. The writing program is completely verified by a customer. Samsung does not take on any responsibility for errors occurred from the writing program.
(For duplicate copies of this form, and for additional ordering information, please contact your local Samsung sales representative. Samsung sales offices are listed on the back cover of this book.)

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