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54ACT16861, 74ACT16861 20-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
SCAS197B - JUNE 1990 - REVISED NOVEMBER 1996
D D D D D D D D
Members of the Texas Instruments Widebus TM Family Inputs Are TTL-Voltage Compatible 3-State Outputs Drive Bus Lines Directly Flow-Through Architecture Optimizes PCB Layout Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise EPICTM (Enhanced-Performance Implanted CMOS) 1-m Process 500-mA Typical Latch-Up Immunity at 125C Package Options Include Shrink Plastic Small-Outline 300-mil (DL) Packages Using 25-mil Center-to-Center Pin Spacings and 380-mil Fine-Pitch Ceramic Flat (WD) Packages Using 25-mil Center-to-Center Pin Spacings
54ACT16861 . . . WD PACKAGE 74ACT16861 . . . DL PACKAGE (TOP VIEW)
description
The 'ACT16861 are noninverting 20-bit transceivers designed for asynchronous communication between data buses. The control-function implementation minimizes external timing requirements. The 'ACT16861 can be used as two 10-bit transceivers or one 20-bit transceiver. They allow data transmission from the A bus to the B bus or from the B bus to the A bus, depending upon the logic level at the output-enable (OEAB or OEBA) inputs. The output-enable inputs can be used to disable the device so that the buses are effectively isolated.
1OEAB 1B1 1B2 GND 1B3 1B4 VCC 1B5 1B6 1B7 GND 1B8 1B9 1B10 2B1 2B2 2B3 GND 2B4 2B5 2B6 VCC 2B7 2B8 GND 2B9 2B10 2OEAB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
1OEBA 1A1 1A2 GND 1A3 1A4 VCC 1A5 1A6 1A7 GND 1A8 1A9 1A10 2A1 2A2 2A3 GND 2A4 2A5 2A6 VCC 2A7 2A8 GND 2A9 2A10 2OEBA
The 74ACT16861 is packaged in TI's shrink small-outline package, which provides twice the I/O pin count and functionality of standard small-outline packages in the same printed-circuit-board area. The 54ACT16861 is characterized for operation over the full military temperature range of -55C to 125C. The 74ACT16861 is characterized for operation from -40C to 85C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC and Widebus are trademarks of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303
Copyright (c) 1996, Texas Instruments Incorporated
* DALLAS, TEXAS 75265
1
54ACT16861, 74ACT16861 20-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
SCAS197B - JUNE 1990 - REVISED NOVEMBER 1996
FUNCTION TABLE (each 10-bit section) INPUTS OEAB L L H H OEBA L H L H OPERATION Latch A and B (A = B) A to B B to A Isolation
logic symbol
56 1OEBA 1OEAB 2OEBA 2OEAB 1A1 28 55 1 29 EN1 EN2 EN3 EN4 1 1 1 1A2 1A3 1A4 1A5 1A6 1A7 1A8 1A9 1A10 2A1 54 52 51 49 48 47 45 44 43 42 3 1 1 2A2 2A3 2A4 2A5 2A6 2A7 2A8 2A9 2A10 41 40 38 37 36 34 33 31 30 4 16 17 19 20 21 23 24 26 27 2B2 2B3 2B4 2B5 2B6 2B7 2B8 2B9 2B10 2 3 5 6 8 9 10 12 13 14 15 1B2 1B3 1B4 1B5 1B6 1B7 1B8 1B9 1B10 2B1 2 1B1
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
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POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
54ACT16861, 74ACT16861 20-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
SCAS197B - JUNE 1990 - REVISED NOVEMBER 1996
logic diagram (positive logic)
1OEBA 56 2OEBA 29
1OEAB
1
2OEAB
28
1A1
55
2
1B1
2A1
42
15
2B1
To Nine Other Channels
To Nine Other Channels
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to VCC + 0.5 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 mA Maximum power package dissipation at TA = 55C (in still air) (see Note 2): DL package . . . . . . . . . . . 1.4 W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The maximum package power dissipation is calculated using a junction temperature of 150C and a board trace length of 750 mils.
recommended operating conditions (see Note 3)
54ACT16861 MIN VCC VIH VIL VI VO IOH IOL t/v Supply voltage High-level input voltage Low-level input voltage Input voltage Output voltage High-level output current Low-level output current Input transition rise or fall rate 0 -55 0 0 4.5 2 0.8 VCC VCC -24 24 10 125 0 -40 0 0 NOM 5 MAX 5.5 74ACT16861 MIN 4.5 2 0.8 VCC VCC -24 24 10 85 NOM 5 MAX 5.5 UNIT V V V V V mA mA ns/V C
TA Operating free-air temperature NOTE 3: Unused inputs must be held high or low to prevent them from floating.
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
3
54ACT16861, 74ACT16861 20-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
SCAS197B - JUNE 1990 - REVISED NOVEMBER 1996
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS IOH = -50 A 50 VOH IOH = -24 mA 24 IOH = -75 mA IOL = 50 A VOL IOL = 24 mA IOL = 75 mA VI = VCC or GND VO = VCC or GND VI = VCC or GND, IO = 0 VCC 4.5 V 5.5 V 4.5 V 5.5 V 5.5 V 4.5 V 5.5 V 4.5 V 5.5 V 5.5 V 5.5 V 5.5 V 5.5 V 5.5 V 5V 4.5 0.1 0.5 8 0.9 0.1 0.1 0.36 0.36 MIN 4.4 5.4 3.94 4.94 TA = 25C TYP MAX 54ACT16861 MIN 4.4 5.4 3.8 4.8 3.85 0.1 0.1 0.44 0.44 1.65 1 5 80 1 MAX 74ACT16861 MIN 4.4 5.4 3.8 4.8 3.85 0.1 0.1 0.44 0.44 1.65 1 5 80 1 A A A mA pF pF V V MAX UNIT
II IOZ ICC ICC Ci
Control inputs A or B ports
One input at 3.4 V, Other inputs at VCC or GND Control inputs VI = VCC or GND VO = VCC or GND
Cio A or B ports 5V 17 Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms. For I/O ports, the parameter IOZ includes the input leakage current. This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC.
switching characteristics over recommended operating free-air temperature range, VCC = 5 V 0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER tPLH tPHL tPZH tPZL tPHZ tPLZ FROM (INPUT) A or B TO (OUTPUT) B or A A or B A or B MIN 3.1 2.9 2.4 3.7 4.9 4.5 TA = 25C TYP MAX 6.5 7.5 6.6 8.5 7.4 6.9 9.2 10 9 11.5 9.8 9.3 54ACT16861 MIN 3.1 2.9 2.4 3.7 4.9 4.5 MAX 10.4 11.1 10 12.7 10.7 10 74ACT16861 MIN 3.1 2.9 2.4 3.7 4.9 4.5 MAX 10.4 11.1 10 12.7 10.7 10 UNIT ns ns ns
OEBA or OEAB OEBA or OEAB
operating characteristics, VCC = 5 V, TA = 25C
PARAMETER Cpd d Power dissipation capacitance per transceiver Outputs enabled Outputs disabled TEST CONDITIONS CL = 50 pF pF, f = 1 MHz TYP 64 14 UNIT pF
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
4
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
54ACT16861, 74ACT16861 20-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
SCAS197B - JUNE 1990 - REVISED NOVEMBER 1996
PARAMETER MEASUREMENT INFORMATION
2 x VCC From Output Under Test CL = 50 pF (see Note A) 500 S1 Open GND 500 TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH S1 Open 2 x VCC GND
LOAD CIRCUIT Timing Input tw 3V Input 1.5 V 1.5 V 0V VOLTAGE WAVEFORMS Output Control (low-level enabling) Output Waveform 1 S1 at 2 x VCC (see Note B) Output Waveform 2 S1 at GND (see Note B) tPZH VOLTAGE WAVEFORMS Data Input tsu 1.5 V 3V 1.5 V 0V th 3V 1.5 V 0V
3V Input 1.5 V tPLH In-Phase Output tPHL Out-of-Phase Output 50% VCC 50% VCC 1.5 V 0V tPHL VOH 50% VCC VOL tPLH VOH 50% VCC VOL
3V 1.5 V tPZL tPLZ 50% VCC tPHZ 80% VCC VOH 20% VCC 1.5 V 0V
[ VCC
VOL
50% VCC
[0V
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO = 50 , tr = 3 ns, tf = 3 ns. D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
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IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof.
Copyright (c) 1998, Texas Instruments Incorporated

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