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SN74ALVC16820 3.3-V 10-BIT FLIP-FLOP WITH DUAL OUTPUTS
SCAS268 - MARCH 1993 - REVISED MARCH 1994
* * * * * * *
Member of the Texas Instruments Widebus TM Family EPIC TM (Enhanced-Performance Implanted CMOS) Submicron Process Supports Unregulated Battery Operation Down to 2.7 V Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25C Typical VOHV (Output VOH Undershoot) > 2 V at VCC = 3.3 V, TA = 25C Bus-Hold On Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors Package Options Include Plastic 300-mil Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages
DGG OR DL PACKAGE (TOP VIEW)
This 10-bit flip-flop is designed specifically for low-voltage 3.3-V VCC operation. The flip-flops of the SN74ALVC16820 are edge-triggered D-type flip-flops. On the positive transition of the clock (CLK) input, the device provides true data at the Q outputs. A buffered output-enable (OE) input can be used to place the ten outputs in either a normal logic state (high or low level) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components.
17 18 19 20 21 22 23 24 25 26 27 28
40 39 38 37 36 35 34 33 32 31 30 29
The output-enable (OE) input does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. The SN74ALVC16820 is available in TI's shrink small-outline (DL) and thin shrink small-outline (DGG) packages, which provide twice the I/O pin count and functionality of standard small-outline packages in the same printed-circuit-board area. The SN74ALVC16820 is characterized for operation from - 40C to 85C.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
Copyright (c) 1994, Texas Instruments Incorporated
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
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PRODUCT PREVIEW
description
1OE 1Q1 1Q2 GND 2Q1 2Q2 VCC 3Q1 3Q2 4Q1 GND 4Q2 5Q1 5Q2 6Q1 6Q2 7Q1 GND 7Q2 8Q1 8Q2 VCC 9Q1 9Q2 GND 10Q1 10Q2 2OE
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
CLK D1 NC GND D2 NC VCC D3 NC D4 GND NC D5 NC D6 NC D7 GND NC D8 NC VCC D9 NC GND D10 NC NC
SN74ALVC16820 3.3-V 10-BIT FLIP-FLOP WITH DUAL OUTPUTS
SCAS268 - MARCH 1993 - REVISED MARCH 1994
FUNCTION TABLE (each flip-flop) INPUTS OEn L L L H n = 1, 2 CLK L X D H L X X OUTPUT Qn H L Q0 Z
logic diagram (positive logic)
1OE 1
2OE
28
CLK
56 2 1Q1
PRODUCT PREVIEW
C1 D1 55 1D
3
1Q2
To Nine Other Channels
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to VCC + 0.5 V Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 50 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA Maximum power dissipation at TA = 55C (in still air) (see Note 3): DGG package . . . . . . . . . . . . . . . . . . 1 W DL package . . . . . . . . . . . . . . . . . . 1.4 W Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65C to 150C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. This value is limited to 4.6 V maximum. 3. The maximum package power dissipation is calculated using a junction temperature of 150C and a board trace length of 750 mils. For more information, refer to the Package Thermal Considerations application note.
9-2
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
SN74ALVC16820 3.3-V 10-BIT FLIP-FLOP WITH DUAL OUTPUTS
SCAS268 - MARCH 1993 - REVISED MARCH 1994
recommended operating conditions
MIN VCC VIH VIL VI VO IOH IOL t /v TA Supply voltage High-level input voltage Low-level input voltage Input voltage Output voltage High-level High level output current Low level output current Low-level Input transition rise or fall rate Operating free-air temperature VCC = 2.7 V VCC = 3 V VCC = 2.7 V VCC = 3 V 0 - 40 VCC = 2.7 V to 3.6 V VCC = 2.7 V to 3.6 V 2.7 2 0.8 0 0 VCC VCC - 12 - 24 12 24 10 85 MAX 3.6 UNIT V V V V V mA mA ns / V C
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
IOH = - 100 A VOH IOH = - 12 mA IOH = - 24 mA IOL = 100 A VOL II II(hold) I(h ld) IOZ ICC IOL = 12 mA IOL = 24 mA VI = VCC or GND VI = 0.8 V VI = 2 V VO = VCC or GND VI = VCC or GND, IO = 0 VCC = 3 V to 3.6 V, One input at VCC - 0.6 V, Other inputs at VCC or GND VI = VCC or GND VO = VCC or GND VCC - 0.2 2.2 2.4 2 0.2 0.4 0.55 5 75 -75 10 40 750 3.3 V 3.3 V 4 6 A A A A A pF pF V
2.7 V 3V 3V MIN to MAX 2.7 V 3V 3.6 V 3V 3.6 V 3.6 V
V
nICC
Ci Co
For conditions shown as MIN or MAX, use the appropriate values under recommended operating conditions.
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
9-3
PRODUCT PREVIEW
PARAMETER
TEST CONDITIONS
VCC MIN to MAX
MIN
TYP
MAX
UNIT
SN74ALVC16820 3.3-V 10-BIT FLIP-FLOP WITH DUAL OUTPUTS
SCAS268 - MARCH 1993 - REVISED MARCH 1994
timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
VCC = 3.3 V 0.15 V MIN fclock tw tsu th Clock frequency Pulse duration, CLK high or low Setup time, data before CLK Hold time, data after CLK High or low High or low 0.8 2 1 2 0 MAX 150 VCC = 3.3 V 0.3 V MIN 0 MAX 150 VCC = 2.7 V MIN 0 MAX 150 MHz ns ns ns UNIT
switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Note 4)
PARAMETER fmax tPLH FROM (INPUT) TO (OUTPUT) VCC = 3.3 V 0.15 V MIN 150 CLK Q Q Q 4 4 5 5 4.5 4.5 MAX VCC = 3.3 V 0.3 V MIN 150 4.5 4.5 5.7 5.7 4.5 4.5 MAX VCC = 2.7 V MIN 150 MAX MHz ns ns ns UNIT
PRODUCT PREVIEW
tPHL tPZH tPZL tPHZ
OE OE
tPLZ NOTE 4: Load circuit and voltage waveforms are shown in Section 1.
9-4
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
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Copyright (c) 1998, Texas Instruments Incorporated

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