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SN74LVCH16543A 16-BIT REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS
SCAS317F - NOVEMBER 1993 - REVISED JUNE 1998
D D D D D D D D D D
Member of the Texas Instruments Widebus TM Family EPICTM (Enhanced-Performance Implanted CMOS) Submicron Process Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25C Typical VOHV (Output VOH Undershoot) > 2 V at VCC = 3.3 V, TA = 25C Power Off Disables Outputs, Permitting Live Insertion Supports Mixed-Mode Signal Operation on All Ports (5-V Input/Output Voltage With 3.3-V VCC) ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 250 mA Per JESD 17 Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors Package Options Include Plastic 300-mil Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages
DGG OR DL PACKAGE (TOP VIEW)
description
This 16-bit registered transceiver is designed for 1.65-V to 3.6-V VCC operation. The SN74LVCH16543A can be used as two 8-bit transceivers or one 16-bit transceiver. Separate latch-enable (LEAB or LEBA) and output-enable (OEAB or OEBA) inputs are provided for each register to permit independent control in either direction of data flow.
1OEAB 1LEAB 1CEAB GND 1A1 1A2 VCC 1A3 1A4 1A5 GND 1A6 1A7 1A8 2A1 2A2 2A3 GND 2A4 2A5 2A6 VCC 2A7 2A8 GND 2CEAB 2LEAB 2OEAB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
1OEBA 1LEBA 1CEBA GND 1B1 1B2 VCC 1B3 1B4 1B5 GND 1B6 1B7 1B8 2B1 2B2 2B3 GND 2B4 2B5 2B6 VCC 2B7 2B8 GND 2CEBA 2LEBA 2OEBA
The A-to-B enable (CEAB) input must be low to enter data from A or to output data from B. If CEAB is low and LEAB is low, the A-to-B latches are transparent; a subsequent low-to-high transition of LEAB puts the A latches in the storage mode. With CEAB and OEAB both low, the 3-state B outputs are active and reflect the data present at the output of the A latches. Data flow from B to A is similar, but requires using the CEBA, LEBA, and OEBA inputs. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC and Widebus are trademarks of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright (c) 1998, Texas Instruments Incorporated
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SN74LVCH16543A 16-BIT REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS
SCAS317F - NOVEMBER 1993 - REVISED JUNE 1998
description (continued)
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. The SN74LVCH16543A is characterized for operation from -40C to 85C.
FUNCTION TABLE (each 8-bit section) INPUTS CEAB H X L L LEAB X X H L OEAB X H L L A X X X L OUTPUT B Z Z B0 L
L L L H H A-to-B data flow is shown; B-to-A flow control is the same except that it uses CEBA, LEBA, and OEBA. Output level before the indicated steady-state input conditions were established
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SN74LVCH16543A 16-BIT REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS
SCAS317F - NOVEMBER 1993 - REVISED JUNE 1998
logic symbol
1OEBA 1CEBA 1LEBA 1OEAB 1CEAB 1LEAB 2OEBA 2CEBA 2LEBA 2OEAB 2CEAB 2LEAB 1A1 5 3 6D 1A2 1A3 1A4 1A5 1A6 1A7 1A8 2A1 6 8 9 10 12 13 14 15 9 12D 2A2 2A3 2A4 2A5 2A6 2A7 2A8 16 17 19 20 21 23 24 11D 10 56 54 55 1 3 2 29 31 30 28 26 27 1EN3 G1 1C5 2EN4 G2 2C6 7EN9 G7 7C11 8EN10 G8 8C12 5D 4 52 1B1
51 49 48 47 45 44 43 42
1B2 1B3 1B4 1B5 1B6 1B7 1B8 2B1
41 40 38 37 36 34 33
2B2 2B3 2B4 2B5 2B6 2B7 2B8
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
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SN74LVCH16543A 16-BIT REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS
SCAS317F - NOVEMBER 1993 - REVISED JUNE 1998
logic diagram (positive logic)
1OEBA 1CEBA 1LEBA 1OEAB 1CEAB 1LEAB 1A1 56 54 55 1 3 2 5 C1 1D 52 1B1
C1 1D
To Seven Other Channels 29 31 30 28 26 27 15 C1 1D 42 2B1
2OEBA 2CEBA 2LEBA 2OEAB 2CEAB 2LEAB 2A1
C1 1D
To Seven Other Channels
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SN74LVCH16543A 16-BIT REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS
SCAS317F - NOVEMBER 1993 - REVISED JUNE 1998
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 6.5 V Input voltage range, VI: (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 6.5 V Voltage range applied to any output in the high-impedance or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 6.5 V Voltage range applied to any output in the high or low state, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 mA Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Continuous current through each VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA Package thermal impedance, JA (see Note 3): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81C/W DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The value of VCC is provided in the recommended operating conditions table. 3. The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions (see Note 4)
MIN VCC Supply voltage Operating Data retention only VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VCC = 1.65 V to 1.95 V VIL VI VO Low-level input voltage Input voltage Output voltage High or low state 3 state VCC = 1.65 V VCC = 2.3 V VCC = 2.7 V VCC = 3 V VCC = 1.65 V VCC = 2.3 V VCC = 2.7 V VCC = 3 V 0 VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V 0 0 0 1.65 1.5 0.65 x VCC 1.7 2 0.35 x VCC 0.7 0.8 5.5 VCC 5.5 -4 -8 -12 -24 4 8 12 24 10 ns/V mA mA V V V V MAX 3.6 UNIT V
VIH
High-level input voltage
IOH
High-level High level output current
IOL
Low-level Low level output current
t/v
Input transition rise or fall rate
TA Operating free-air temperature -40 85 C NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
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SN74LVCH16543A 16-BIT REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS
SCAS317F - NOVEMBER 1993 - REVISED JUNE 1998
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER IOH = -100 A IOH = -4 mA VOH IOH = -8 mA IOH = -12 mA 12 IOH = -24 mA IOL = 100 A VOL IOL = 4 mA IOL = 8 mA IOL = 12 mA IOL = 24 mA II Ioff Control inputs VI = 0 to 5.5 V VI or VO = 5.5 V VI = 0.58 V VI = 1.07 V VI = 0.7 V II(hold) ( ) A or B ports VI = 1.7 V VI = 0.8 V VI = 2 V VI = 0 to 3.6 V IOZ ICC ICC Ci Cio Control inputs A or B ports VO = 0 to 5.5 V VI = VCC or GND 3.6 V VI 5.5 V# IO = 0 TEST CONDITIONS VCC 1.65 V to 3.6 V 1.65 V 2.3 V 2.7 V 3V 3V 1.65 V to 3.6 V 1.65 V 2.3 V 2.7 V 3V 3.6 V 0 1.65 1 65 V 2.3 23V 3V 3..6 V 3.6 V 3.6 36V 45 -45 75 -75 500 10 20 20 500 5 8 A A A pF pF A MIN VCC-0.2 1.2 1.7 2.2 2.4 2.2 0.2 0.45 0.7 0.4 0.55 5 10 A A V V TYP MAX UNIT
One input at VCC - 0.6 V, Other inputs at VCC or GND VI = VCC or GND
2.7 V to 3.6 V 3.3 V
VO = VCC or GND 3.3 V All typical values are at VCC = 3.3 V, TA = 25C. This information was not available at the time of publication. This is the bus-hold maximum dynamic current required to switch the input from one state to another. For I/O ports, the parameter IOZ includes the input leakage current, but not II(hold). # This applies in the disabled state only.
timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figures 1 through 3)
VCC = 1.8 V 0.15 V MIN tw tsu Pulse duration, LE or CE low Setup time, data before LE or CE MAX VCC = 2.5 V 0.2 V MIN MAX VCC = 2.7 V MIN 3.3 1.1 1.9 MAX VCC = 3.3 V 0.3 V MIN 3.3 1.1 1.9 MAX ns ns ns UNIT
th Hold time, data after LE or CE This information was not available at the time of publication.
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SN74LVCH16543A 16-BIT REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS
SCAS317F - NOVEMBER 1993 - REVISED JUNE 1998
switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figures 1 through 3)
PARAMETER FROM (INPUT) A or B LE CE OE TO (OUTPUT) B or A A or B A or B A or B VCC = 1.8 V 0.15 V MIN MAX VCC = 2.5 V 0.2 V MIN MAX VCC = 2.7 V MIN MAX 6.1 7.4 7.9 7.1 7.6 6.9 VCC = 3.3 V 0.3 V MIN 1.2 1.5 1.2 1.5 1 1.5 MAX 5.4 6.1 6.6 6.6 6.3 6.3 ns ns ns UNIT
tpd d ten tdis ten tdis
This information was not available at the time of publication.
operating characteristics, TA = 25C
PARAMETER Outputs enabled Outputs disabled f = 10 MHz TEST CONDITIONS VCC = 1.8 V 0.15 V TYP VCC = 2.5 V 0.2 V TYP VCC = 3.3 V 0.3 V TYP 44 4 pF UNIT
Cpd
Power dissipation capacitance per transceiver
This information was not available at the time of publication.
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SN74LVCH16543A 16-BIT REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS
SCAS317F - NOVEMBER 1993 - REVISED JUNE 1998
PARAMETER MEASUREMENT INFORMATION VCC = 1.8 V 0.15 V
2 x VCC From Output Under Test CL = 30 pF (see Note A) 1k S1 Open GND 1k TEST tpd tPLZ/tPZL tPHZ/tPZH S1 Open 2 x VCC Open
LOAD CIRCUIT tw Timing Input tsu Data Input VCC/2 VCC VCC/2 0V th VCC VCC/2 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Output Control (low-level enabling) tPZL VCC Input VCC/2 tPLH VCC/2 0V tPHL VOH Output VCC/2 VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VCC/2 VOL Output Waveform 2 S1 at Open (see Note B) Output Waveform 1 S1 at 2 x VCC (see Note B) tPZH VCC Input VCC/2 VOLTAGE WAVEFORMS PULSE DURATION VCC/2 0V
VCC VCC/2 VCC/2 0V tPLZ VCC VCC/2 VOL + 0.15 V VOL tPHZ VOH VOH - 0.15 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES
VCC/2
NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2 ns, tf 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
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SN74LVCH16543A 16-BIT REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS
SCAS317F - NOVEMBER 1993 - REVISED JUNE 1998
PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V 0.2 V
2 x VCC From Output Under Test CL = 30 pF (see Note A) 500 S1 Open GND 500 TEST tpd tPLZ/tPZL tPHZ/tPZH S1 Open 2 x VCC GND
LOAD CIRCUIT tw Timing Input tsu Data Input VCC/2 VCC VCC/2 0V th VCC VCC/2 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Output Control (low-level enabling) tPZL VCC Input VCC/2 tPLH VCC/2 0V tPHL VOH Output VCC/2 VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VCC/2 VOL Output Waveform 2 S1 at GND (see Note B) Output Waveform 1 S1 at 2 x VCC (see Note B) tPZH VCC Input VCC/2 VOLTAGE WAVEFORMS PULSE DURATION VCC/2 0V
VCC VCC/2 VCC/2 0V tPLZ VCC VCC/2 VOL + 0.15 V VOL tPHZ VOH VOH - 0.15 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES
VCC/2
NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2 ns, tf 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd.
Figure 2. Load Circuit and Voltage Waveforms
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SN74LVCH16543A 16-BIT REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS
SCAS317F - NOVEMBER 1993 - REVISED JUNE 1998
PARAMETER MEASUREMENT INFORMATION VCC = 2.7 V AND 3.3 V 0.3 V
6V From Output Under Test CL = 50 pF (see Note A) 500 S1 Open GND 500 TEST tpd tPLZ/tPZL tPHZ/tPZH S1 Open 6V GND
LOAD CIRCUIT
tw 2.7 V
Timing Input tsu Data Input 1.5 V
2.7 V 1.5 V 0V th 2.7 V 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES
Input
1.5 V
1.5 V 0V
VOLTAGE WAVEFORMS PULSE DURATION
Output Control (low-level enabling) tPZL Output Waveform 1 S1 at 6 V (see Note B) Output Waveform 2 S1 at GND (see Note B) tPZH
2.7 V 1.5 V 1.5 V 0V tPLZ 3V 1.5 V tPHZ VOH - 0.3 V VOH 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES VOL + 0.3 V VOL
2.7 V Input tPLH 1.5 V 1.5 V 0V tPHL VOH Output 1.5 V VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES 1.5 V VOL
1.5 V
NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2.5 ns, tf 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd.
Figure 3. Load Circuit and Voltage Waveforms
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Copyright (c) 1998, Texas Instruments Incorporated

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