View SCBS137D_1000150.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

SN54LVT543, SN74LVT543 3.3-V ABT OCTAL REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS
SCBS137D - MAY 1992 - REVISED JULY 1995
D D D D D D D D D
State-of-the-Art Advanced BiCMOS Technology (ABT) Design for 3.3-V Operation and Low Static Power Dissipation Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC ) Support Unregulated Battery Operation Down to 2.7 V Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25C ESD Protection Exceeds 2000 V Per MIL-STD-883C, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Bus-Hold Data Inputs Eliminate the Need for External Pullup Resistors Support Live Insertion Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), and Thin Shrink Small-Outline (PW) Packages, Ceramic Chip Carriers (FK), and Ceramic (JT) DIPs
SN54LVT543 . . . JT PACKAGE SN74LVT543 . . . DB, DW, OR PW PACKAGE (TOP VIEW)
LEBA OEBA A1 A2 A3 A4 A5 A6 A7 A8 CEAB GND
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13
VCC CEBA B1 B2 B3 B4 B5 B6 B7 B8 LEAB OEAB
SN54LVT543 . . . FK PACKAGE (TOP VIEW)
A1 OEBA LEBA NC VCC
4
description
These octal transceivers are designed specifically for low-voltage (3.3-V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment. The 'LVT543 contain two sets of D-type latches for temporary storage of data flowing in either direction. Separate latch-enable (LEAB or LEBA) and output-enable (OEAB or OEBA) inputs are provided for each register to permit independent control in either direction of data flow.
A2 A3 A4 NC A5 A6 A7
5 6 7 8 9 10
3 2 1 28 27 26 25 24 23 22 21 20
CEBA B1 B2 B3 B4 NC B5 B6 B7
19 11 12 13 14 15 16 17 18
NC - No internal connection
The A-to-B enable (CEAB) input must be low in order to enter data from A or to output data from B. If CEAB is low and LEAB is low, the A-to-B latches are transparent; a subsequent low-to-high transition of LEAB puts the A latches in the storage mode. With CEAB and OEAB both low, the 3-state B outputs are active and reflect the data present at the output of the A latches. Data flow from B to A is similar but requires using the CEBA, LEBA, and OEBA inputs. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
A8 CEAB GND NC OEAB LEAB B8
Copyright (c) 1995, Texas Instruments Incorporated
1
SN54LVT543, SN74LVT543 3.3-V ABT OCTAL REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS
SCBS137D - MAY 1992 - REVISED JULY 1995
description (continued)
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The SN74LVT543 is available in TI's shrink small-outline package (DB), which provides the same I/O pin count and functionality of standard small-outline packages in less than half the printed-circuit-board area. The SN54LVT543 is characterized for operation over the full military temperature range of - 55C to 125C. The SN74LVT543 is characterized for operation from - 40C to 85C.
FUNCTION TABLE INPUTS CEAB H X L L L LEAB X X H L L OEAB X H L L L A X X X L H OUTPUT B Z Z B0 L
H A-to-B data flow is shown; B-to-A flow control is the same except that it uses CEBA, LEBA, and OEBA. Output level before the indicated steady-state input conditions were established
logic symbol
2 OEBA 23 CEBA 1 LEBA 13 OEAB 11 CEAB 14 LEAB A1 3 3 4 5 6 7 8 9 10 6D 1 1 1EN3 G1 1C5 2EN4 G2 2C6 5D 4 22 B1
A2 A3 A4 A5 A6 A7 A8
21 20 19 18 17 16 15
B2 B3 B4 B5 B6 B7 B8
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the DB, DW, JT, and PW packages.
2
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
SN54LVT543, SN74LVT543 3.3-V ABT OCTAL REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS
SCBS137D - MAY 1992 - REVISED JULY 1995
logic diagram (positive logic)
OEBA CEBA LEBA OEAB CEAB LEAB A1 2 23 1 13 11 14 3 C1 1D 22 B1
C1 1D
To Seven Other Channels Pin numbers shown are for the DB, DW, JT, and PW packages.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to 7 V Voltage range applied to any output in the high state or power-off state, VO (see Note 1) . . . . - 0.5 V to 7 V Current into any output in the low state, IO: SN54LVT543 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA SN74LVT543 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Current into any output in the high state, IO (see Note 2): SN54LVT543 . . . . . . . . . . . . . . . . . . . . . . . . . 48 mA SN74LVT543 . . . . . . . . . . . . . . . . . . . . . . . . . 64 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 50 mA Maximum power dissipation at TA = 55C (in still air) (see Note 3): DB package . . . . . . . . . . . . . . . . . . . 0.65 W DW package . . . . . . . . . . . . . . . . . . . 1.7 W PW package . . . . . . . . . . . . . . . . . . . 0.7 W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65C to 150C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. This current flows only when the output is in the high state and VO > VCC. 3. The maximum package power dissipation is calculated using a junction temperature of 150C and a board trace length of 750 mils. For more information, refer to the Package Thermal Considerations application note in the 1994 ABT Advanced BiCMOS Technology Data Book, literature number SCBD002B.
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
3
SN54LVT543, SN74LVT543 3.3-V ABT OCTAL REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS
SCBS137D - MAY 1992 - REVISED JULY 1995
recommended operating conditions (see Note 4)
SN54LVT543 MIN VCC VIH VIL VI IOH IOL t /v Supply voltage High-level input voltage Low-level input voltage Input voltage High-level output current Low-level output current Input transition rise or fall rate Outputs enabled - 55 2.7 2 0.8 5.5 - 24 48 10 125 - 40 MAX 3.6 SN74LVT543 MIN 2.7 2 0.8 5.5 - 32 64 10 85 MAX 3.6 UNIT V V V V mA mA ns / V C
TA Operating free-air temperature NOTE 4: Unused control inputs must be held high or low to prevent them from floating.
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
4
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
SN54LVT543, SN74LVT543 3.3-V ABT OCTAL REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS
SCBS137D - MAY 1992 - REVISED JULY 1995
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER VIK TEST CONDITIONS VCC = 2.7 V, VCC = MIN to MAX, VCC = 2.7 V, VCC = 3 V VCC = 2 7 V 2.7 VOL VCC = 3 V II = -18 mA IOH = -100 A IOH = - 8 mA IOH = - 24 mA IOH = - 32 mA IOL = 100 A IOL = 24 mA IOL = 16 mA IOL = 32 mA IOL = 48 mA IOL = 64 mA VI = VCC or GND VI = 5.5 V VI = 5.5 V VI = VCC VI = 0 VI or VO = 0 to 4.5 V VI = 0.8 V VI = 2 V VO = 3 V VO = 0.5 V Outputs high ICC VCC = 3.6 V, VI = VCC or GND IO = 0, Outputs low Outputs disabled 0.13 8.8 0.13 Control inputs A or B ports MIN SN54LVT543 TYP MAX -1.2 VCC - 0.2 2.4 2 2 0.2 0.5 0.4 0.5 0.55 0.55 1 10 20 5 -10 75 -75 1 -1 0.19 12 0.19 0.2 4.5 11 4.5 11 0.13 8.8 0.13 75 -75 1 -1 0.19 12 0.19 0.2 mA pF pF mA 1 10 20 5 -10 100 A or B ports A A A A A 0.2 0.5 0.4 0.5 V VCC - 0.2 2.4 MIN SN74LVT543 TYP MAX -1.2 UNIT V
VOH
V
VCC = 3.6 V, VCC = 0 or MAX, II VCC = 3.6 V Ioff II(hold) I(h ld) IOZH IOZL VCC = 0, VCC = 3 V VCC = 3.6 V, VCC = 3.6 V,
ICC Ci Cio
VCC = 3 V to 3.6 V, One input at VCC - 0.6 V, Other inputs at VCC or GND VI = 3 V or 0 VO = 3 V or 0
All typical values are at VCC = 3.3 V, TA = 25C. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. Unused terminals at VCC or GND This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
5
SN54LVT543, SN74LVT543 3.3-V ABT OCTAL REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS
SCBS137D - MAY 1992 - REVISED JULY 1995
timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
SN54LVT543 VCC = 3.3 V 0.3 V MIN tw Pulse duration, LEAB or LEBA low A or B before LEAB or LEBA tsu Setup time A or B before CEAB or CEBA Hold time Data high Data low Data high Data low 3.3 0 0.8 0 0.9 1.7 1.8 MAX VCC = 2.7 V MIN 3.3 0 1.1 0 1.2 1.7 1.8 MAX SN74LVT543 VCC = 3.3 V 0.3 V MIN 3.3 0 0.8 0 0.9 1.7 1.8 MAX VCC = 2.7 V MIN 3.3 0 1.1 0 1.2 1.7 1.8 ns ns MAX ns UNIT
th
A or B after LEAB or LEBA A or B after CEAB or CEBA
switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1)
SN54LVT543 PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 3.3 V 0.3 V MIN tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ tPZH tPZL tPHZ tPLZ A or B B or A A or B A or B A or B A or B A or B 1 1 1 1 1 1.1 2.4 2 1 1.4 2.3 2 MAX 4.9 4.8 6.1 5.9 6 6.6 6.7 6 6.2 6.9 6.6 5.6 VCC = 2.7 V MIN MAX 5.7 6 7.5 7.5 7.8 8.4 7.3 6.1 7.8 8.5 7.3 5.8 SN74LVT543 VCC = 3.3 V 0.3 V MIN TYP MAX 1 1 1 1 1 1.1 2.4 2 1 1.4 2.3 2 2.9 3.3 4 4.1 4.1 4.5 4.8 4 4.2 4.7 4.7 3.8 4.7 4.6 5.9 5.7 5.8 6.4 6.5 5.8 6 6.7 6.4 5.4 VCC = 2.7 V MIN MAX 5.5 5.8 7.3 7.3 7.6 8.2 7.1 5.9 7.6 8.3 7.1 5.6 ns ns ns ns ns ns UNIT
LE OE OE CE CE
All typical values are at VCC = 3.3 V, TA = 25C.
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
6
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
SN54LVT543, SN74LVT543 3.3-V ABT OCTAL REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS
SCBS137D - MAY 1992 - REVISED JULY 1995
PARAMETER MEASUREMENT INFORMATION
6V From Output Under Test CL = 50 pF (see Note A) 500 S1 Open GND 500 TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH S1 Open 6V GND
LOAD CIRCUIT FOR OUTPUTS
2.7 V Timing Input 1.5 V 0V
tw 2.7 V Input 1.5 V 1.5 V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 2.7 V 1.5 V tPZL Output Waveform 1 S1 at 6 V (see Note B) Output Waveform 2 S1 at GND (see Note B) tPZH tPLZ 1.5 V tPHZ VOH - 0.3 V VOH 3V VOL + 0.3 V VOL 1.5 V 0V Data Input tsu 1.5 V th 2.7 V 1.5 V 0V
2.7 V Input 1.5 V tPLH Output 1.5 V 1.5 V 0V tPHL VOH 1.5 V VOL tPHL Output 1.5 V tPLH VOH 1.5 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS
Output Control
1.5 V
[0V
VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2.5 ns, tf 2.5 ns. D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
7
IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof.
Copyright (c) 1998, Texas Instruments Incorporated

▲Up To Search▲

Price & Availability of SCBS137D

	To Download SCBS137D Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .