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SN54LVT652, SN74LVT652 3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SCBS141E - MAY 1992 - REVISED JULY 1995
D D D D D D D D D
State-of-the-Art Advanced BiCMOS Technology (ABT) Design for 3.3-V Operation and Low-Static Power Dissipation Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC ) Support Unregulated Battery Operation Down to 2.7 V Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25C ESD Protection Exceeds 2000 V Per MIL-STD-883C, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Bus-Hold Data Inputs Eliminate the Need for External Pullup Resistors Support Live Insertion Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), and Thin Shrink Small-Outline (PW) Packages, Ceramic Chip Carriers (FK), and Ceramic (JT) DIPs
SN54LVT652 . . . JT PACKAGE SN74LVT652 . . . DB, DW, OR PW PACKAGE (TOP VIEW)
CLKAB SAB OEAB A1 A2 A3 A4 A5 A6 A7 A8 GND
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13
VCC CLKBA SBA OEBA B1 B2 B3 B4 B5 B6 B7 B8
SN54LVT652 . . . FK PACKAGE (TOP VIEW)
OEAB SAB CLKAB NC VCC CLKBA SBA
4 3 2 1 28 27 26
description
These bus transceivers and registers are designed specifically for low-voltage (3.3-V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment. The 'LVT652 consist of bus transceiver circuits, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the data bus or from the internal storage registers.
A1 A2 A3 NC A4 A5 A6
5 6 7 8 9 10
25 24 23 22 21 20
19 11 12 13 14 15 16 17 18
OEBA B1 B2 NC B3 B4 B5
NC - No internal connection
Output-enable (OEAB and OEBA) inputs are provided to control the transceiver functions. Select-control (SAB and SBA) inputs are provided to select whether real-time or stored data is transferred. The circuitry used for select control eliminates the typical decoding glitch that occurs in a multiplexer during the transition between real-time and stored data. A low input selects real-time data and a high input selects stored data. Figure 1 illustrates the four fundamental bus-management functions that can be performed with the LVT652.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
A7 A8 GND NC B8 B7 B6
Copyright (c) 1995, Texas Instruments Incorporated
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SN54LVT652, SN74LVT652 3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SCBS141E - MAY 1992 - REVISED JULY 1995
description (continued)
Data on the A or B data bus, or both, can be stored in the internal D-type flip-flops by low-to-high transitions at the appropriate clock (CLKAB or CLKBA) inputs regardless of the select- or enable-control pins. When SAB and SBA are in the real-time transfer mode, it is possible to store data without using the internal D-type flip-flops by simultaneously enabling OEAB and OEBA. In this configuration, each output reinforces its input; therefore, when all other data sources to the two sets of bus lines are at high impedance, each set of bus lines remains at its last state. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver. The SN74LVT652 is available in TI's shrink small-outline package (DB), which provides the same I/O pin count and functionality of standard small-outline packages in less than half the printed-circuit-board area. The SN54LVT652 is characterized for operation over the full military temperature range of - 55C to 125C. The SN74LVT652 is characterized for operation from - 40C to 85C.
FUNCTION TABLE INPUTS OEAB L L X H L L L L H H H OEBA H H H H X L L L H H L CLKAB H or L H or L X X X H or L H or L CLKBA H or L H or L X H or L X X H or L SAB X X X X X X X X L H H SBA X X X X X X L H X X H A1- A8 Input Input Input Input Unspecified Output Output Output Input Input Output DATA I/O B1- B8 Input Input Unspecified Output Input Input Input Input Output Output Output OPERATION OR FUNCTION Isolation Store A and B data Store A, hold B Store A in both registers Hold A, store B Store B in both registers Real-time B data to A bus Stored B data to A bus Real-time A data to B bus Stored A data to B bus Stored A data to B bus and stored B data to A bus
The data output functions may be enabled or disabled by a variety of level combinations at the OEAB or OEBA inputs. Data input functions are always enabled; i.e., data at the bus pins is stored on every low-to-high transition of the clock inputs. Select control = L; clocks can occur simultaneously Select control = H; clocks must be staggered in order to load both registers
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POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
SN54LVT652, SN74LVT652 3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SCBS141E - MAY 1992 - REVISED JULY 1995
BUS B
3 21 OEAB OEBA L L
1 23 2 CLKAB CLKBA SAB X X X
22 SBA L
3 21 OEAB OEBA H H
1 CLKAB X
23 CLKBA X
2 SAB L
BUS B 22 SBA X REAL-TIME TRANSFER BUS A TO BUS B 1 CLKAB H or L 23 CLKBA H or L 2 SAB H BUS B 22 SBA H TRANSFER STORED DATA TO A AND/OR B
BUS A
REAL-TIME TRANSFER BUS B TO BUS A
BUS B
BUS A
3 OEAB X L L
21 OEBA H X H
1 23 2 CLKAB CLKBA SAB X X X X X
22 SBA X X X
3 OEAB H
21 OEBA L
STORAGE FROM A, B, OR A AND B
Figure 1. Bus-Management Functions
Pin numbers shown are for the DB, DW, JT, and PW packages.
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
BUS A
BUS A
3
SN54LVT652, SN74LVT652 3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SCBS141E - MAY 1992 - REVISED JULY 1995
logic symbol
OEBA OEAB CLKBA SBA CLKAB SAB 21 3 23 22 1 2 EN1 [BA] EN2 [AB] C4 G5 C6 G7 1 1 6D 1 A2 A3 A4 A5 A6 A7 A8 5 6 7 8 9 10 11 7 7 19 18 17 16 15 14 13 B2 B3 B4 B5 B6 B7 B8 5 51 1 2 4D 20 B1
A1
4
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the DB, DW, JT, and PW packages.
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POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
SN54LVT652, SN74LVT652 3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SCBS141E - MAY 1992 - REVISED JULY 1995
logic diagram (positive logic)
OEBA 21
OEAB CLKBA SBA CLKAB SAB
3 23 22 1 2
One of Eight Channels
1D C1
A1
4 20 1D C1 B1
To Seven Other Channels Pin numbers shown are for the DB, DW, JT, and PW packages.
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
5
SN54LVT652, SN74LVT652 3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SCBS141E - MAY 1992 - REVISED JULY 1995
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to 7 V Voltage range applied to any output in the high state or power-off state, VO (see Note 1) . . . . - 0.5 V to 7 V Current into any output in the low state, IO: SN54LVT652 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA SN74LVT652 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Current into any output in the high state, IO (see Note 2): SN54LVT652 . . . . . . . . . . . . . . . . . . . . . . . . . 48 mA SN74LVT652 . . . . . . . . . . . . . . . . . . . . . . . . . 64 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 50 mA Maximum power dissipation at TA = 55C (in still air) (see Note 3): DB package . . . . . . . . . . . . . . . . . . . 0.65 W DW package . . . . . . . . . . . . . . . . . . . 1.7 W PW package . . . . . . . . . . . . . . . . . . . 0.7 W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65C to 150C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. This current flows only when the output is in the high state and VO > VCC. 3. The maximum package power dissipation is calculated using a junction temperature of 150C and a board trace length of 750 mils. For more information, refer to the Package Thermal Considerations application note in the 1994 ABT Advanced BiCMOS Technology Data Book, literature number SCBD002B.
recommended operating conditions (see Note 4)
SN54LVT652 MIN VCC VIH VIL VI IOH IOL t /v Supply voltage High-level input voltage Low-level input voltage Input voltage High-level output current Low-level output current Input transition rise or fall rate Outputs enabled - 55 2.7 2 0.8 5.5 - 24 48 10 125 - 40 MAX 3.6 SN74LVT652 MIN 2.7 2 0.8 5.5 - 32 64 10 85 MAX 3.6 UNIT V V V V mA mA ns / V C
TA Operating free-air temperature NOTE 4: Unused control inputs must be held high or low to prevent them from floating.
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
6
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
SN54LVT652, SN74LVT652 3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SCBS141E - MAY 1992 - REVISED JULY 1995
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER VIK TEST CONDITIONS VCC = 2.7 V, VCC = MIN to MAX, VCC = 2.7 V, VCC = 3 V VCC = 2 7 V 2.7 VOL VCC = 3 V II = -18 mA IOH = -100 A IOH = - 8 mA IOH = - 24 mA IOH = - 32 mA IOL = 100 A IOL = 24 mA IOL = 16 mA IOL = 32 mA IOL = 48 mA IOL = 64 mA VI = VCC or GND VI = 5.5 V VI = 5.5 V VI = VCC VI = 0 MIN SN54LVT652 TYP MAX - 1.2 VCC - 0.2 2.4 2 2 0.2 0.5 0.4 0.5 0.55 0.55 Control inputs 1 10 20 A or B ports 5 - 10 75 - 75 1 -1 Outputs high ICC VCC = 3.6 V, VI = VCC or GND IO = 0, Outputs low Outputs disabled 0.13 8.8 0.13 0.19 12 0.19 0.2 4.5 11 4.5 11 0.13 8.8 0.13 75 - 75 1 -1 0.19 12 0.19 0.2 mA pF pF mA 1 10 20 5 - 10 100 A A A A A 0.2 0.5 0.4 0.5 V VCC - 0.2 2.4 MIN SN74LVT652 TYP MAX - 1.2 UNIT V
VOH
V
VCC = 3.6 V, VCC = 0 or MAX, II VCC = 3.6 V Ioff II(hold) I(h ld) IOZH IOZL VCC = 0, VCC = 3 V VCC = 3.6 V, VCC = 3.6 V,
VI or VO = 0 to 4.5 V VI = 0.8 V A or B ports VI = 2 V VO = 3 V VO = 0.5 V
ICC Ci Cio
VCC = 3 V to 3.6 V, One input at VCC - 0.6 V, Other inputs at VCC or GND VI = 3 V or 0 VO = 3 V or 0
All typical values are at VCC = 3.3 V, TA = 25C. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. Unused terminals at VCC or GND This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
7
SN54LVT652, SN74LVT652 3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SCBS141E - MAY 1992 - REVISED JULY 1995
timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figure 2)
SN54LVT652 VCC = 3.3 V 0.3 V MIN fclock tw tsu th Clock frequency Pulse duration, CLK high or low Setup time, A or B before , CLKAB or CLKBA Data high Data low 0 MAX 150 VCC = 2.7 V MIN 0 MAX 150 SN74LVT652 VCC = 3.3 V 0.3 V MIN 0 3.3 1.2 2 0.5 MAX 150 VCC = 2.7 V MIN 0 3.3 1.2 2.5 0.5 MAX 150 MHz ns ns ns UNIT
Hold time, A or B after CLKAB or CLKBA
switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 2)
SN54LVT652 PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 3.3 V 0.3 V MIN fmax tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ tPZH tPZL tPHZ MAX VCC = 2.7 V MIN MAX SN74LVT652 VCC = 3.3 V 0.3 V MIN TYP MAX 150 CLKBA or CLKAB A or B SBA or SAB OEBA OEBA OEAB OEAB A or B B or A A or B A A B B 1.8 2 1.2 1 1.4 1.4 1 1 2.2 1.8 1 1.2 1.7 3.7 3.7 2.8 2.6 3.7 4 2.9 3 3.9 3.2 3.3 3.4 4.5 6 5.7 4.7 4.6 6.4 6.2 5.8 6 6.5 5.8 6.5 6.3 7.2 VCC = 2.7 V MIN 150 6.9 6.4 5.5 5.3 7.6 6.8 7.2 7.3 6.9 5.9 7.5 7.1 8.1 6.3 MAX MHz ns ns ns ns ns ns ns UNIT
tPLZ 1.5 3.8 5.8 All typical values are at VCC = 3.3 V, TA = 25C. These parameters are measured with the internal output state of the storage register opposite to that of the bus input.
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
8
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
SN54LVT652, SN74LVT652 3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SCBS141E - MAY 1992 - REVISED JULY 1995
PARAMETER MEASUREMENT INFORMATION
6V From Output Under Test CL = 50 pF (see Note A) 500 S1 Open GND 500 TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH S1 Open 6V GND
2.7 V LOAD CIRCUIT FOR OUTPUTS tw 2.7 V Input 1.5 V 1.5 V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 2.7 V 1.5 V tPZL Output Waveform 1 S1 at 6 V (see Note B) Output Waveform 2 S1 at GND (see Note B) tPZH tPLZ 1.5 V tPHZ VOH - 0.3 V VOH 3V VOL + 0.3 V VOL 1.5 V 0V Data Input tsu 1.5 V th 2.7 V 1.5 V 0V Timing Input 1.5 V 0V
2.7 V Input tPLH Output 1.5 V 1.5 V 1.5 V 0V tPHL VOH 1.5 V VOL tPHL Output 1.5 V tPLH VOH 1.5 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS
Output Control
1.5 V
[0V
VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2.5 ns, tf 2.5 ns. D. The outputs are measured one at a time with one transition per measurement.
Figure 2. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
9
SN54LVT652, SN74LVT652 3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SCBS141E - MAY 1992 - REVISED JULY 1995
10
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof.
Copyright (c) 1998, Texas Instruments Incorporated

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