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SN54ABT821, SN74ABT821 10-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS
SCBS193A - FEBRUARY 1991 - REVISED JULY 1994
* * * * * *
State-of-the-Art EPIC-BTM BiCMOS Design Significantly Reduces Power Dissipation ESD Protection Exceeds 2000 V Per MIL-STD-883C, Method 3015 Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Typical VOLP (Output Ground Bounce) < 1 V at VCC = 5 V, TA = 25C High-Drive Outputs (- 32-mA IOH, 64-mA IOL ) Package Options Include Plastic Small-Outline (DW) and Shrink Small-Outline (DB) Packages, Ceramic Chip Carriers (FK), and Plastic (NT) and Ceramic (JT) DIPs
SN54ABT821 . . . JT PACKAGE SN74ABT821 . . . DB, DW, OR NT PACKAGE (TOP VIEW)
OE 1D 2D 3D 4D 5D 6D 7D 8D 9D 10D GND
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13
VCC 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q 9Q 10Q CLK
description
These 10-bit flip-flops feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing wider buffer registers, I/O ports, bidirectional bus drivers with parity, and working registers. The ten flip-flops are edge-triggered D-type flip-flops. On the positive transition of the clock (CLK) input, the device provides true data at the Q outputs. A buffered output-enable (OE) input can be used to place the ten outputs in either a normal logic state (high or low level) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components.
SN54ABT821 . . . FK PACKAGE (TOP VIEW)
3D 4D 5D NC 6D 7D 8D
2D 1D OE NC VCC 1Q 2Q
4 5 6 7 8 9 10 3 2 1 28 27 26 25 24 23 22 21 20 19 11 12 13 14 15 16 17 18
3Q 4Q 5Q NC 6Q 7Q 8Q
NC - No internal connection
OE does not affect the internal operations of the latch. Previously stored data can be retained or new data can be entered while the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The SN74ABT821 is available in TI's shrink small-outline package (DB), which provides the same I/O pin count and functionality of standard small-outline packages in less than half the printed-circuit-board area. The SN54ABT821 is characterized for operation over the full military temperature range of - 55C to 125C. The SN74ABT821 is characterized for operation from - 40C to 85C.
EPIC-B is a trademark of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
9D 10D GND NC CLK 10Q 9Q
Copyright (c) 1994, Texas Instruments Incorporated
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SN54ABT821, SN74ABT821 10-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS
SCBS193A - FEBRUARY 1991 - REVISED JULY 1994
FUNCTION TABLE (each flip-flop) INPUTS OE L L L H CLK H or L X D H L X X OUTPUT Q H L Q0 Z
logic symbol
OE CLK 1D 2D 3D 4D 5D 6D 7D 8D 9D 10D
1 13 2 3 4 5 6 7 8 9 10 11
EN C2 2D 23 22 21 20 19 18 17 16 15 14 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q 9Q 10Q
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
OE 1
CLK
13
C1 1D 2 1D
23
1Q
To Nine Other Channels Pin numbers shown are for the DB, DW, JT, and NT packages.
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POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
SN54ABT821, SN74ABT821 10-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS
SCBS193A - FEBRUARY 1991 - REVISED JULY 1994
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to 7 V Voltage range applied to any output in the high state or power-off state, VO . . . . . . . . . . . . . - 0.5 V to 5.5 V Current into any output in the low state, IO: SN54ABT821 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA SN74ABT821 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -18 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 50 mA Maximum power dissipation at TA = 55C (in still air) (see Note 2): DB package . . . . . . . . . . . . . . . . . . . 0.65 W DW package . . . . . . . . . . . . . . . . . . . 1.7 W NT package . . . . . . . . . . . . . . . . . . . . 1.3 W Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65C to 150C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions beyond those indicated in the "recommended operating conditions" section of this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The maximum package power dissipation is calculated using a junction temperature of 150C and a board trace length of 750 mils, except for the NT package, which has a trace length of zero. For more information, refer to the Package Thermal Considerations application note in the 1994 ABT Advanced BiCMOS Technology Data Book, literature number SCBD002B.
recommended operating conditions (see Note 3)
SN54ABT821 MIN VCC VIH VIL VI IOH IOL t /v t /VCC Supply voltage High-level input voltage Low-level input voltage Input voltage High-level output current Low-level output current Input transition rise or fall rate Power-up ramp rate 200 - 55 125 0 4.5 2 0.8 VCC - 24 48 10 200 - 40 85 0 MAX 5.5 SN74ABT821 MIN 4.5 2 0.8 VCC - 32 64 10 MAX 5.5 UNIT V V V V mA mA ns / V s / V C
TA Operating free-air temperature NOTE 3: Unused or floating inputs must be held high or low.
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
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SN54ABT821, SN74ABT821 10-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS
SCBS193A - FEBRUARY 1991 - REVISED JULY 1994
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER VIK VCC = 4.5 V, VCC = 4.5 V, VCC = 5 V, VCC = 4 5 V 4.5 VOL II IOZPU IOZPD IOZH IOZL Ioff ICEX IO ICC VCC = 4 5 V 4.5 VCC = 5.5 V, VCC = 0 to 2.1 V, VCC = 2.1 V to 0, VCC = 2.1 V to 5.5 V, VCC = 2.1 V to 5.5 V, VCC = 0, VCC = 5.5 V, VCC = 5.5 V, VCC = 5.5 V, 55V VI = VCC or GND TEST CONDITIONS II = -18 mA IOH = - 3 mA IOH = - 3 mA IOH = - 24 mA IOH = - 32 mA IOL = 48 mA IOL = 64 mA VI = VCC or GND VO = 0.5 to 2.7 V, VO = 0.5 to 2.7 V, VO = 2.7 V, VO = 0.5 V, OE = X OE = X OE 2 V OE 2 V MIN 2.5 3 2 2* 0.55 0.55* 1 50 50 10 - 10 100 50 - 50 Outputs high IO = 0, 0 Outputs low Outputs disabled -140 1 24 0.5 -180 250 38 250 1.5 4 - 50 50 -180 250 38 250 1.5 - 50 1 50 50 10 - 10 0.55 0.55 1 50 50 10 - 10 100 50 -180 250 38 250 1.5 TA = 25C TYP MAX -1.2 2.5 3 2 2 V A A A A A A A mA A mA A mA pF pF SN54ABT821 MIN MAX -1.2 2.5 3 V SN74ABT821 MIN MAX -1.2 UNIT V
VOH
VI or VO 4.5 V VO = 5.5 V Outputs high VO = 2.5 V
ICC Ci
VCC = 5.5 V, One input at 3.4 V, Other inputs at VCC or GND VI = 2.5 V or 0.5 V VO = 2.5 V or 0.5 V
Co 7 * On products compliant to MIL-STD-883, Class B, this parameter does not apply. All typical values are at VCC = 5 V. Not more than one output should be tested at a time, and the duration of the test should not exceed one second. This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 1)
VCC = 5 V, TA = 25C MIN fclock tw tsu th Clock frequency Pulse duration CLK high or low duration, Setup time, data before CLK Hold time, data after CLK High Low 0 2.9 3.8 2.1 1.3 MAX 125 SN54ABT821 MIN 0 2.9 3.8 2.1 1.3 MAX 125 SN74ABT821 MIN 0 2.9 3.8 2.1 1.3 MAX 125 MHz ns ns ns UNIT
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
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POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
SN54ABT821, SN74ABT821 10-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS
SCBS193A - FEBRUARY 1991 - REVISED JULY 1994
switching characteristics over recommended ranges of supply voltage and operating free-air temperature, CL = 50 pF (unless otherwise noted) (see Figure 1)
PARAMETER fmax tPLH tPHL tPZH tPZL tPHZ FROM (INPUT) TO (OUTPUT) VCC = 5 V, TA = 25C MIN 125 1.6 2.1 1 2.2 2.7 1.7 TYP 4.1 4.6 3 4.1 4.7 4.6 MAX 5.6 6.2 4.5 5.6 6.2 6.1 SN54ABT821 MIN 125 1.6 2.1 1 2.2 2.7 1.7 MAX 6.9 6.9 6 6.5 7 7 SN74ABT821 MIN 125 1.6 2.1 1 2.2 2.7 1.7 MAX MHz 6.2 6.7 5.3 6.3 6.7 6.5 ns ns ns UNIT
CLK
Q Q Q
OE
OE tPLZ This data sheet limit may vary among suppliers.
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
2-5
SN54ABT821, SN74ABT821 10-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS
SCBS193A - FEBRUARY 1991 - REVISED JULY 1994
PARAMETER MEASUREMENT INFORMATION
7V From Output Under Test CL = 50 pF (see Note A) 500 S1 Open GND 500 TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH S1 Open 7V Open
LOAD CIRCUIT FOR OUTPUTS 3V Timing Input tw 3V Input 1.5 V 1.5 V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Data Input tsu 1.5 V th 3V 1.5 V 0V 1.5 V 0V
Input (see Note B) tPLH Output
3V 1.5 V 1.5 V 0V tPHL VOH 1.5 V 1.5 V VOL tPHL tPLH VOH 1.5 V 1.5 V VOL
Output Control tPZL Output Waveform 1 S1 at 7 V (see Note C) Output Waveform 2 S1 at Open (see Note C) tPZH
3V 1.5 V 1.5 V 0V tPLZ 1.5 V tPHZ VOH - 0.3 V VOH
3.5 V VOL + 0.3 V VOL
Output
1.5 V
[0V
VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2.5 ns, tf 2.5 ns. C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
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* DALLAS, TEXAS 75265
IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof.
Copyright (c) 1998, Texas Instruments Incorporated

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