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SN54LVTH125, SN74LVTH125 3.3-V ABT QUADRUPLE BUS BUFFERS WITH 3-STATE OUTPUTS
SCBS703F - AUGUST 1997 - REVISED JUNE 2000
D D D D D D D D D
State-of-the-Art Advanced BiCMOS Technology (ABT) Design for 3.3-V Operation and Low Static-Power Dissipation Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC) Support Unregulated Battery Operation Down to 2.7 V Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25C Ioff and Power-Up 3-State Support Hot Insertion Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors Latch-Up Performance Exceeds 500 mA Per JESD 17 ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Package Options Include Plastic Small-Outline (D), Shrink Small-Outline (DB), Thin Very Small-Outline (DGV), and Thin Shrink Small-Outline (PW) Packages, Ceramic Chip Carriers (FK), and Ceramic (J) DIPs
SN54LVTH125 . . . J PACKAGE SN74LVTH125 . . . D, DB, DGV, OR PW PACKAGE (TOP VIEW)
1OE 1A 1Y 2OE 2A 2Y GND
1 2 3 4 5 6 7
14 13 12 11 10 9 8
VCC 4OE 4A 4Y 3OE 3A 3Y
SN54LVTH125 . . . FK PACKAGE (TOP VIEW)
1Y NC 2OE NC 2A
4 5 6 7 8
3 2 1 20 19 18 17 16 15 14 9 10 11 12 13
1A 1OE NC VCC 4OE 4A NC 4Y NC 3OE
NC - No internal connection
Copyright (c) 2000, Texas Instruments Incorporated
description
These bus buffers are designed specifically for low-voltage (3.3-V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment. The 'LVTH125 devices feature independent line drivers with 3-state outputs. Each output is in the high-impedance state when the associated output-enable (OE) input is high. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. When VCC is between 0 and 1.5 V, the devices are in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. These devices are fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict. The SN54LVTH125 is characterized for operation over the full military temperature range of -55C to 125C. The SN74LVTH125 is characterized for operation from -40C to 85C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
2Y GND NC 3Y 3A
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SN54LVTH125, SN74LVTH125 3.3-V ABT QUADRUPLE BUS BUFFERS WITH 3-STATE OUTPUTS
SCBS703F - AUGUST 1997 - REVISED JUNE 2000
FUNCTION TABLE (each buffer) INPUTS OE L L H A H L X OUTPUT Y H L Z
logic symbol
1OE 1A 2OE 2A 3OE 3A 4OE 4A 1 2 4 5 10 9 13 12 8 3Y EN 1 3 6 1Y 2Y
11
4Y
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the D, DB, DGV, J, and PW packages.
logic diagram (positive logic)
1OE 1A 1 2 3 3OE 1Y 3A 10 9 8
3Y
2OE 2A
4 5 6
4OE 2Y 4A
13 12 11
4Y
Pin numbers shown are for the D, DB, DGV, J, and PW packages.
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POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
SN54LVTH125, SN74LVTH125 3.3-V ABT QUADRUPLE BUS BUFFERS WITH 3-STATE OUTPUTS
SCBS703F - AUGUST 1997 - REVISED JUNE 2000
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V Voltage range applied to any output in the high-impedance or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V Voltage range applied to any output in the high state, VO (see Note 1) . . . . . . . . . . . . . -0.5 V to VCC + 0.5 V Current into any output in the low state, IO: SN54LVTH125 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA SN74LVTH125 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Current into any output in the high state, IO (see Note 2): SN54LVTH125 . . . . . . . . . . . . . . . . . . . . . . . 48 mA SN74LVTH125 . . . . . . . . . . . . . . . . . . . . . . . 64 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 mA Package thermal impedance, JA (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86C/W DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96C/W DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. This current flows only when the output is in the high state and VO > VCC. 3. The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions (see Note 4)
SN54LVTH125 MIN VCC VIH VIL VI IOH IOL t/v t/VCC TA Supply voltage High-level input voltage Low-level input voltage Input voltage High-level output current Low-level output current Input transition rise or fall rate Power-up ramp rate Operating free-air temperature Outputs enabled 200 -55 125 2.7 2 0.8 5.5 -24 48 10 200 -40 85 MAX 3.6 SN74LVTH125 MIN 2.7 2 0.8 5.5 -32 64 10 MAX 3.6 UNIT V V V V mA mA ns/V s/V C
NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
3
SN54LVTH125, SN74LVTH125 3.3-V ABT QUADRUPLE BUS BUFFERS WITH 3-STATE OUTPUTS
SCBS703F - AUGUST 1997 - REVISED JUNE 2000
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER VIK TEST CONDITIONS VCC = 2.7 V, VCC = 2.7 V to 3.6 V, VCC = 2.7 V, VCC = 3 V VCC = 2 7 V 2.7 VOL VCC = 3 V II = -18 mA IOH = -100 A IOH = -8 mA IOH = -24 mA IOH = -32 mA IOL = 100 A IOL = 24 mA IOL = 16 mA IOL = 32 mA IOL = 48 mA IOL = 64 mA VI = 5.5 V VI = VCC or GND VI = VCC VI = 0 VI or VO = 0 to 4.5 V VI = 0.8 V VI = 2 V VI = 0 to 3.6 V VO = 3 V VO = 0.5 V 75 -75 5 -5 50 50 0.12 4.5 0.12 0.19 7 0.19 0.3 4 6.5 4 6.5 0.12 4.5 0.12 MIN SN54LVTH125 TYP MAX -1.2 VCC-0.2 2.4 2 2 0.2 0.5 0.4 0.5 0.55 0.55 10 1 1 -5 75 -75 500 5 -5 50 50 0.19 7 0.19 0.2 mA pF pF mA A A A A A 10 1 1 -5 100 A A 0.2 0.5 0.4 0.5 V VCC-0.2 2.4 MIN SN74LVTH125 TYP MAX -1.2 UNIT V
VOH
V
VCC = 0 or 3.6 V, II Control inputs Data inputs Ioff II(hold) ( ) IOZH IOZL IOZPU IOZPD Data inputs VCC = 3.6 V, VCC = 3 6 V 3.6 VCC = 0, VCC = 3 V VCC = 3.6 V, VCC = 3.6 V, VCC = 3.6 V,
VCC = 0 to 1.5 V, VO = 0.5 V to 3 V, OE = don't care VCC = 1.5 V to 0, VO = 0.5 V to 3 V, OE = don't care VCC = 3.6 V, IO = 0, VI = VCC or GND Outputs high Outputs low Outputs disabled
ICC
ICC Ci Co
VCC = 3 V to 3.6 V, One input at VCC - 0.6 V, Other inputs at VCC or GND VI = 3 V or 0 VO = 3 V or 0
On products compliant to MIL-PRF-38535, this parameter is not production tested. All typical values are at VCC = 3.3 V, TA = 25C. This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another. This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
4
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
SN54LVTH125, SN74LVTH125 3.3-V ABT QUADRUPLE BUS BUFFERS WITH 3-STATE OUTPUTS
SCBS703F - AUGUST 1997 - REVISED JUNE 2000
switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1)
SN54LVTH125 PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 3.3 V 0.3 V MIN tPLH tPHL tPZH tPZL tPHZ tPLZ A Y Y Y 1 1 1 1.1 1.5 1.3 MAX 4.2 4.1 4.9 4.9 5.3 4.7 VCC = 2.7 V MIN MAX 4.7 5.1 5.6 5.6 5.9 4.2 SN74LVTH125 VCC = 3.3 V 0.3 V MIN 1 1 1 1.1 1.5 1.3 TYP 2 2.1 2 2.1 2.3 2.8 MAX 3.5 3.9 4 4 4.5 4.5 VCC = 2.7 V MIN MAX 4.5 4.9 5.5 5.4 5.7 4 ns ns ns UNIT
OE OE
All typical values are at VCC = 3.3 V, TA = 25C.
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
5
SN54LVTH125, SN74LVTH125 3.3-V ABT QUADRUPLE BUS BUFFERS WITH 3-STATE OUTPUTS
SCBS703F - AUGUST 1997 - REVISED JUNE 2000
PARAMETER MEASUREMENT INFORMATION
6V From Output Under Test CL = 50 pF (see Note A) 500 S1 Open GND 500 TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH S1 Open 6V GND
2.7 V LOAD CIRCUIT tw 2.7 V Input 1.5 V 1.5 V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 2.7 V Output Control Output Waveform 1 S1 at 6 V (see Note B) Output Waveform 2 S1 at GND (see Note B) tPZL 1.5 V 1.5 V 1.5 V 0V tPLZ 3V VOL + 0.3 V VOL tPHZ 1.5 V VOH - 0.3 V VOH 0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING Data Input Timing Input 1.5 V 0V tsu 1.5 V th 2.7 V 1.5 V 0V
2.7 V Input tPLH Output tPHL 1.5 V 1.5 V 1.5 V 1.5 V 0V tPHL 1.5 V VOH VOL tPLH VOH Output 1.5 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS
tPZH
NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2.5 ns, tf 2.5 ns. D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
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POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Customers are responsible for their applications using TI components. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof.
Copyright (c) 2000, Texas Instruments Incorporated

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