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SN74CBTR16245 16-BIT FET BUS SWITCH
SCDS077A - JULY 1998 - REVISED MAY 2000
D D D D
Standard '16245-Type Pinout 25- Switch Connection Between Two Ports TTL-Compatible Input Levels Package Options Include Plastic Thin Shrink Small-Outline (DGG), Thin Very Small-Outline (DGV), and Shrink Small-Outline (DL) Packages
DGG, DGV, OR DL PACKAGE (TOP VIEW)
description
The SN74CBTR16245 provides 16 bits of high-speed TTL-compatible bus switching in a standard '16245 device pinout. The low on-state resistance of the switch allows connections to be made with minimal propagation delay. The device is organized as two 8-bit low-impedance switches with separate output-enable (OE) inputs. When OE is low, the switch is on, and data can flow from port A to port B, or vice versa. When OE is high, the switch is open, and a high-impedance state exists between the two ports. The device has equivalent 25- series resistors to reduce signal-reflection noise. This eliminates the need for external terminating resistors. The SN74CBTR16245 is characterized for operation from -40C to 85C.
17 18 19 20 21 22 23 24
32 31 30 29 28 27 26 25
NC - No internal connection
FUNCTION TABLE (each 8-bit bus switch) INPUT OE L H FUNCTION A port = B port Disconnect
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
Copyright (c) 2000, Texas Instruments Incorporated
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PRODUCT PREVIEW
NC 1B1 1B2 GND 1B3 1B4 VCC 1B5 1B6 GND 1B7 1B8 2B1 2B2 GND 2B3 2B4 VCC 2B5 2B6 GND 2B7 2B8 NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
1OE 1A1 1A2 GND 1A3 1A4 VCC 1A5 1A6 GND 1A7 1A8 2A1 2A2 GND 2A3 2A4 VCC 2A5 2A6 GND 2A7 2A8 2OE
SN74CBTR16245 16-BIT FET BUS SWITCH
SCDS077A - JULY 1998 - REVISED MAY 2000
logic diagram (positive logic)
1A1 47 2 1B1
37 1A8 48 1OE
12 1B8
2A1
36
13
2B1
26 2A8 25 2OE
23 2B8
PRODUCT PREVIEW
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V Continuous channel current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Input clamp current, IIK (VI/O < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 mA Package thermal impedance, JA (see Note 2): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70C/W DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58C/W DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions (see Note 3)
MIN VCC VIH VIL TA Supply voltage High-level control input voltage Low-level control input voltage Operating free-air temperature -40 4.5 2 0.8 85 MAX 5.5 UNIT V V V C
NOTE 3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
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SN74CBTR16245 16-BIT FET BUS SWITCH
SCDS077A - JULY 1998 - REVISED MAY 2000
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER VIK II ICC ICC Ci VCC = 4.5 V, VCC = 0 VCC = 5.5 V VCC = 5.5 V, Control inputs Control inputs VCC = 5.5 V, VI = 3 V or 0 VO = 3 V or 0, VCC = 4.5 V TEST CONDITIONS II = -18 mA VI = 5.5 V VI = 5.5 V or GND IO = 0, One input at 3.4 V, OE = VCC VI = 0 II = 64 mA II = 30 mA VI = VCC or GND Other inputs at VCC or GND MIN TYP MAX -1.2 10 1 3 2.5 UNIT V A A mA pF pF
Cio(OFF) ron
VI = 2.4 V, II = 15 mA All typical values are at VCC = 5 V, TA = 25C. This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND. Measured by the voltage drop between the A and B terminals at the indicated current through the switch. On-state resistance is determined by the lower of the voltages of the two (A or B) terminals.
switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1)
PARAMETER tpd ten FROM (INPUT) A or B OE TO (OUTPUT) B or A A or B MIN MAX UNIT ns ns
tdis A or B ns OE The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance).
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3
PRODUCT PREVIEW
SN74CBTR16245 16-BIT FET BUS SWITCH
SCDS077A - JULY 1998 - REVISED MAY 2000
PARAMETER MEASUREMENT INFORMATION
7V From Output Under Test CL = 50 pF (see Note A) 500 S1 Open GND 500 Output Control (low-level enabling) tPZL Output Waveform 1 S1 at 7 V (see Note B) tPZH VOH Output 1.5 V VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES 1.5 V VOL Output Waveform 2 S1 at Open (see Note B) TEST tpd tPLZ/tPZL tPHZ/tPZH S1 Open 7V Open
3V 1.5 V 1.5 V 0V tPLZ 3.5 V 1.5 V tPHZ VOH VOH - 0.3 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES VOL + 0.3 V VOL
LOAD CIRCUIT
3V Input 1.5 V 1.5 V 0V tPLH tPHL
PRODUCT PREVIEW
1.5 V
NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2.5 ns, tf 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
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Copyright (c) 2000, Texas Instruments Incorporated

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