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SN74ALVC16834 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS
SCES140B - JULY 1998 - REVISED FEBRUARY 1999
D D D D D
Member of the Texas Instruments Widebus TM Family EPIC TM (Enhanced-Performance Implanted CMOS) Submicron Process Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Package Options Include Plastic Shrink Small-Outline (DL), Thin Shrink Small-Outline (DGG), and Thin Very Small-Outline (DGV) Packages
DGG, DGV, OR DL PACKAGE (TOP VIEW)
description
This 18-bit universal bus driver is designed for 1.65-V to 3.6-V VCC operation. Data flow from A to Y is controlled by the output-enable (OE) input. The device operates in the transparent mode when the latch-enable (LE) input is low. The A data is latched if the clock (CLK) input is held at a high or low logic level. If LE is high, the A data is stored in the latch/flip-flop on the low-to-high transition of CLK. When OE is high, the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The SN74ALVC16834 is characterized operation from -40C to 85C. for
NC NC Y1 GND Y2 Y3 VCC Y4 Y5 Y6 GND Y7 Y8 Y9 Y10 Y11 Y12 GND Y13 Y14 Y15 VCC Y16 Y17 GND Y18 OE LE
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
GND NC A1 GND A2 A3 VCC A4 A5 A6 GND A7 A8 A9 A10 A11 A12 GND A13 A14 A15 VCC A16 A17 GND A18 CLK GND
NC - No internal connection
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC and Widebus are trademarks of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright (c) 1999, Texas Instruments Incorporated
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SN74ALVC16834 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS
SCES140B - JULY 1998 - REVISED FEBRUARY 1999
FUNCTION TABLE INPUTS OE H L L L L L L LE X L L H H H H CLK X X X H L A X L H L H X X OUTPUT Y Z L H L H Y0
Y0 Output level before the indicated steady-state input conditions were established, provided that CLK is high before LE goes high Output level before the indicated steady-state input conditions were established
logic symbol
OE CLK LE 27 30 2C3 28 C3 G2 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 3 5 6 8 9 10 12 13 14 15 16 17 19 20 21 23 24 26 1 1 3D 54 52 51 49 48 47 45 44 43 42 41 40 38 37 36 34 33 31 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 EN1
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
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SN74ALVC16834 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS
SCES140B - JULY 1998 - REVISED FEBRUARY 1999
logic diagram (positive logic)
OE 27
CLK
30
LE
28
A1
54
1D C1 CLK 3 Y1
To 17 Other Channels
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 4.6 V Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 mA Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Continuous current through each VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA Package thermal impedance, JA (see Note 3): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81C/W DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86C/W DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. This value is limited to 4.6 V maximum. 3. The package thermal impedance is calculated in accordance with JESD 51.
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SN74ALVC16834 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS
SCES140B - JULY 1998 - REVISED FEBRUARY 1999
recommended operating conditions (see Note 4)
MIN VCC VIH Supply voltage High-level input voltage VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VI VO Input voltage Output voltage VCC = 1.65 V VCC = 2.3 V VCC = 2.7 V VCC = 3 V VCC = 1.65 V VCC = 2.3 V VCC = 2.7 V VCC = 3 V 0 0 1.65 0.65 x VCC 1.7 2 0.35 x VCC 0.7 0.8 VCC VCC -4 -12 -12 -24 4 12 12 24 10 ns/V mA mA V V V V MAX 3.6 UNIT V
VIL
Low-level input voltage
IOH
High-level High level output current
IOL
Low-level Low level output current
t/v
Input transition rise or fall rate
TA Operating free-air temperature -40 85 C NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
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SN74ALVC16834 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS
SCES140B - JULY 1998 - REVISED FEBRUARY 1999
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER IOH = -100 A IOH = -4 mA IOH = -6 mA VOH IOH = -12 mA IOH = -24 mA IOL = 100 A IOL = 4 mA IOL = 6 mA IOL = 12 mA IOL = 24 mA VI = VCC or GND VO = VCC or GND VI = VCC or GND, One input at VCC - 0.6 V, Control inputs Data inputs VI = VCC or GND IO = 0 Other inputs at VCC or GND TEST CONDITIONS VCC 1.65 V to 3.6 V 1.65 V 2.3 V 2.3 V 2.7 V 3V 3V 1.65 V to 3.6 V 1.65 V 2.3 V 2.3 V 2.7 V 3V 3.6 V 3.6 V 3.6 V 3 V to 3.6 V 3.3 33V 3.3 V 4 5.5 7 MIN TYP MAX UNIT VCC-0.2 1.2 2 1.7 2.2 2.4 2 0.2 0.45 0.4 0.7 0.4 0.55 5 10 40 750 A A A A pF pF V V
VOL
II IOZ ICC ICC Ci
Co Outputs VO = VCC or GND All typical values are at VCC = 3.3 V, TA = 25C.
timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figures 1 through 3)
VCC = 1.8 V MIN fclock tw Clock frequency Pulse duration LE low CLK high or low Data before CLK tsu Setup time Data before LE Data after CLK th Hold time Data after LE CLK high or low CLK high CLK low MAX VCC = 2.5 V 0.2 V MIN 3.3 3.3 2.1 2.2 1.5 0.6 0.8 MAX 150 3.3 3.3 2.1 2.3 1.9 0.6 0.8 VCC = 2.7 V MIN MAX 150 3.3 3.3 1.7 1.9 1.5 0.7 0.9 ns ns VCC = 3.3 V 0.3 V MIN MAX 150 MHz ns UNIT
This information was not available at the time of publication.
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SN74ALVC16834 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS
SCES140B - JULY 1998 - REVISED FEBRUARY 1999
switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figures 1 through 3)
PARAMETER fmax A tpd ten tdis LE CLK OE OE Y Y Y FROM (INPUT) TO (OUTPUT) VCC = 1.8 V MIN TYP VCC = 2.5 V 0.2 V MIN 150 1 1.3 1.2 1.4 1 4.4 6 6 5.6 4 MAX VCC = 2.7 V MIN 150 4.2 5.9 5.3 5.6 4.7 MAX VCC = 3.3 V 0.3 V MIN 150 1 1.5 1.5 1.5 1.8 3.6 4.9 4.6 5 4.5 ns ns ns MAX MHz UNIT
This information was not available at the time of publication.
switching characteristics from 0C to 65C, CL = 50 pF
PARAMETER tpd FROM (INPUT) CLK TO (OUTPUT) Y VCC = 3.3 V 0.15 V MIN 1.7 MAX 4.3 ns UNIT
operating characteristics, TA = 25C
PARAMETER Cpd d Power dissipation capacitance Outputs enabled Outputs disabled TEST CONDITIONS CL = 0 0, f = 10 MHz VCC = 1.8 V TYP VCC = 2.5 V TYP 38 13 VCC = 3.3 V TYP 41 15 UNIT pF
This information was not available at the time of publication.
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SN74ALVC16834 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS
SCES140B - JULY 1998 - REVISED FEBRUARY 1999
PARAMETER MEASUREMENT INFORMATION VCC = 1.8 V
2 x VCC From Output Under Test CL = 30 pF (see Note A) 1 k S1 Open GND 1 k TEST tpd tPLZ/tPZL tPHZ/tPZH S1 Open 2 x VCC GND
LOAD CIRCUIT tw Timing Input tsu Data Input VCC/2 VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC VCC/2 0V th VCC VCC/2 0V Output Control (low-level enabling) tPZL VCC Input VCC/2 tPLH VCC/2 0V tPHL VOH Output VCC/2 VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VCC/2 VOL Output Waveform 2 S1 at GND (see Note B) Output Waveform 1 S1 at 2 x VCC (see Note B) tPZH VCC Input VCC/2 VOLTAGE WAVEFORMS PULSE DURATION VCC/2 0V
VCC VCC/2 VCC/2 0V tPLZ VCC VCC/2 VOL + 0.15 V VOL tPHZ VOH VOH - 0.15 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES
VCC/2
NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2 ns, tf 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
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SN74ALVC16834 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS
SCES140B - JULY 1998 - REVISED FEBRUARY 1999
PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V 0.2 V
2 x VCC From Output Under Test CL = 30 pF (see Note A) 500 S1 Open GND 500 TEST tpd tPLZ/tPZL tPHZ/tPZH S1 Open 2 x VCC GND
LOAD CIRCUIT tw Timing Input tsu Data Input VCC/2 VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC VCC/2 0V th VCC VCC/2 0V Output Control (low-level enabling) tPZL VCC Input VCC/2 tPLH VCC/2 0V tPHL VOH Output VCC/2 VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VCC/2 VOL Output Waveform 2 S1 at GND (see Note B) Output Waveform 1 S1 at 2 x VCC (see Note B) tPZH VCC Input VCC/2 VOLTAGE WAVEFORMS PULSE DURATION VCC/2 0V
VCC VCC/2 VCC/2 0V tPLZ VCC VCC/2 VOL + 0.15 V VOL tPHZ VOH VOH - 0.15 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES
VCC/2
NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2 ns, tf 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd.
Figure 2. Load Circuit and Voltage Waveforms
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POST OFFICE BOX 655303
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SN74ALVC16834 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS
SCES140B - JULY 1998 - REVISED FEBRUARY 1999
PARAMETER MEASUREMENT INFORMATION VCC = 2.7 V AND 3.3 V 0.3 V
6V From Output Under Test CL = 50 pF (see Note A) 500 S1 Open GND 500 TEST tpd tPLZ/tPZL tPHZ/tPZH S1 Open 6V GND
LOAD CIRCUIT
tw 2.7 V
Timing Input
2.7 V 1.5 V 0V tsu th 2.7 V 1.5 V 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES
Input
1.5 V
1.5 V 0V
VOLTAGE WAVEFORMS PULSE DURATION
Data Input
Output Control (low-level enabling) tPZL
2.7 V 1.5 V 1.5 V 0V tPLZ 3V 1.5 V VOL + 0.3 V VOL tPHZ VOH VOH - 0.3 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES
2.7 V Input 1.5 V 1.5 V 0V tPLH Output 1.5 V VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES tPHL VOH 1.5 V VOL
Output Waveform 1 S1 at 6 V (see Note B) tPZH Output Waveform 2 S1 at GND (see Note B)
1.5 V
NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2.5 ns, tf 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd.
Figure 3. Load Circuit and Voltage Waveforms
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Copyright (c) 1999, Texas Instruments Incorporated

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