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| CD54/74AC153, CD54/74ACT153 Data sheet acquired from Harris Semiconductor SCHS237A September 1998 - Revised May 2000 Dual 4-Input Multiplexer Description The 'AC153 and 'ACT153 are dual 4-input multiplexers that utilize Advanced CMOS Logic technology. One of the four sources for each section is selected by the common Select inputs, S0 and S1. When the Enable inputs (1E, 2E) are HIGH, the outputs are in the low state. Features * Buffered Inputs * Typical Propagation Delay - 6.3ns at VCC = 5V, TA = 25oC, CL = 50pF * Exceeds 2kV ESD Protection MIL-STD-883, Method 3015 * SCR-Latchup-Resistant CMOS Process and Circuit Design * Speed of Bipolar FASTTM/AS/S with Significantly Reduced Power Consumption * Balanced Propagation Delays * AC Types Feature 1.5V to 5.5V Operation and Balanced Noise Immunity at 30% of the Supply * 24mA Output Drive Current - Fanout to 15 FASTTM ICs - Drives 50 Transmission Lines Ordering Information PART NUMBER CD54AC153F3A CD74AC153E CD74AC153M96 CD54ACT153F3A CD74ACT153E CD74ACT153M NOTES: 1. When ordering, use the entire part number. Add the suffix 96 to obtain the variant in the tape and reel. 2. Wafer and die for this part number is available which meets all electrical specifications. Please contact your local TI sales office or customer service for ordering information. TEMP. RANGE (oC) -55 to 125 0 to 70oC, -40 to 85, -55 to 125 0 to 70oC, -40 to 85, -55 to 125 -55 to 125 0 to 70oC, -40 to 85, -55 to 125 0 to 70oC, -40 to 85, -55 to 125 16 Ld SOIC PACKAGE 16 Ld CERDIP 16 Ld PDIP 16 Ld SOIC 16 Ld CERDIP 16 Ld PDIP [ /Title (CD74 AC153 , CD74 ACT15 3) /Subject (Dual 4-Input Multiplexer) /Autho r () /Keywords (Harris Semiconductor, Advan ced CMOS ) /Creator () /DOCI NFO pdfmark Pinout CD54AC153, CD54ACT153 (CERDIP) CD74AC153, CD74ACT153 (PDIP, SOIC) TOP VIEW 1E 1 S1 2 1I3 3 1I2 4 1I1 5 1I0 6 1Y 7 GND 8 16 VCC 15 2E 14 S0 13 2I3 12 2I2 11 2I1 10 2I0 9 2Y CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. FASTTM is a Trademark of Fairchild Semiconductor. Copyright (c) 2000, Texas Instruments Incorporated. 1 CD54/74AC153, CD54/74ACT153 Functional Diagram 1 1E 6 1I0 5 1I1 4 1I2 3 1I3 S0 S1 2I0 2I1 2I2 2I3 2E 14 2 10 11 12 13 15 GND = 8 VCC = 16 SEL/MUX 9 2Y SEL/MUX 7 1Y TRUTH TABLE SELECT INPUTS S1 X L L L L H H H H S0 X L L H H L L H H nI0 X L H X X X X X X DATA INPUTS nI1 X X X L H X X X X nI2 X X X X X L H X X nI3 X X X X X X X L H ENABLE INPUTS nE H L L L L L L L L OUTPUT nY L L H L H L H L H Select inputs S1 and S0 are common to both sections. H = High Level, L = Low Level, X = Don't Care, Z = High Impedance. 2 CD54/74AC153, CD54/74ACT153 Absolute Maximum Ratings DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 6V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .20mA DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .50mA DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .50mA DC VCC or Ground Current, ICC or IGND (Note 3) . . . . . . . . .100mA Thermal Information Thermal Resistance (Typical, Note 5) JA (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 Maximum Junction Temperature (Plastic Package) . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC Operating Conditions Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC (Note 4) AC Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.5V to 5.5V ACT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Slew Rate, dt/dv AC Types, 1.5V to 3V . . . . . . . . . . . . . . . . . . . . . . . . . 50ns (Max) AC Types, 3.6V to 5.5V . . . . . . . . . . . . . . . . . . . . . . . . 20ns (Max) ACT Types, 4.5V to 5.5V. . . . . . . . . . . . . . . . . . . . . . . 10ns (Max) CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 3. For up to 4 outputs per device, add 25mA for each additional output. 4. Unless otherwise specified, all voltages are referenced to ground. 5. JA is measured with the component mounted on an evaluation PC board in free air. DC Electrical Specifications TEST CONDITIONS PARAMETER AC TYPES High Level Input Voltage VIH 1.5 3 5.5 Low Level Input Voltage VIL 1.5 3 5.5 High Level Output Voltage VOH VIH or VIL -0.05 -0.05 -0.05 -4 -24 -75 (Note 6, 7) -50 (Note 6, 7) 1.5 3 4.5 3 4.5 5.5 5.5 1.2 2.1 3.85 1.4 2.9 4.4 2.58 3.94 0.3 0.9 1.65 1.2 2.1 3.85 1.4 2.9 4.4 2.48 3.8 3.85 0.3 0.9 1.65 1.2 2.1 3.85 1.4 2.9 4.4 2.4 3.7 3.85 0.3 0.9 1.65 V V V V V V V V V V V V V SYMBOL VI (V) IO (mA) VCC (V) 25oC MIN MAX -40oC TO 85oC MIN MAX -55oC TO 125oC MIN MAX UNITS 3 CD54/74AC153, CD54/74ACT153 DC Electrical Specifications (Continued) TEST CONDITIONS PARAMETER Low Level Output Voltage SYMBOL VOL VI (V) VIH or VIL IO (mA) 0.05 0.05 0.05 12 24 75 (Note 6, 7) 50 (Note 6, 7) Input Leakage Current Quiescent Supply Current MSI ACT TYPES High Level Input Voltage Low Level Input Voltage High Level Output Voltage VIH VIL VOH VIH or VIL -0.05 -24 -75 (Note 6, 7) -50 (Note 6, 7) Low Level Output Voltage VOL VIH or VIL 0.05 24 75 (Note 6, 7) 50 (Note 6, 7) Input Leakage Current Quiescent Supply Current MSI Additional Supply Current per Input Pin TTL Inputs High 1 Unit Load NOTES: 6. Test one output at a time for a 1-second maximum duration. Measurement is made by forcing current and measuring voltage to minimize power dissipation. 7. Test verifies a minimum 50 transmission-line-drive capability at 85oC, 75 at 125oC. II ICC ICC VCC or GND VCC or GND VCC -2.1 0 4.5 to 5.5 4.5 to 5.5 4.5 4.5 5.5 5.5 4.5 4.5 5.5 5.5 5.5 5.5 4.5 to 5.5 2 4.4 3.94 0.8 0.1 0.36 0.1 8 2.4 2 4.4 3.8 3.85 0.8 0.1 0.44 1.65 1 80 2.8 2 4.4 3.7 3.85 0.8 0.1 0.5 1.65 1 160 3 V V V V V V V V V V A A mA II ICC VCC or GND VCC or GND 0 25oC MIN MAX 0.1 0.1 0.1 0.36 0.36 0.1 8 -40oC TO 85oC MIN MAX 0.1 0.1 0.1 0.44 0.44 1.65 1 80 -55oC TO 125oC MIN MAX 0.1 0.1 0.1 0.5 0.5 1.65 1 160 UNITS V V V V V V V A A VCC (V) 1.5 3 4.5 3 4.5 5.5 5.5 5.5 5.5 ACT Input Load Table INPUT S0, S1, nI0, nI1 nE UNIT LOAD 1 0.47 NOTE: Unit load is ICC limit specified in DC Electrical Specifications Table, e.g., 2.4mA max at 25oC. 4 CD54/74AC153, CD54/74ACT153 Switching Specifications Input tr, tf = 3ns, CL = 50pF (Worst Case) -40oC TO 85oC PARAMETER AC TYPES Propagation Delay, S0, S1, to Y tPLH, tPHL 1.5 3.3 (Note 9) 5 (Note 10) Propagation Delay, nI to Y tPLH, tPHL 1.5 3.3 5 Propagation Delay, nE to Y tPLH, tPHL 1.5 3.3 5 Input Capacitance Power Dissipation Capacitance ACT TYPES Propagation Delay, S0, S1, to Y Propagation Delay, nI to Y Propagation Delay, nE to Y Input Capacitance Power Dissipation Capacitance NOTES: 8. Limits tested at 100%. 9. 3.3V Min at 3.6V, Max at 3V. 10. 5V Min at 5.5V, Max at 4.5V. 11. CPD is used to determine the dynamic power consumption per multiplexer. AC: PD = VCC2 fi (CPD + CL) ACT: PD = VCC2 fi (CPD + CL) + VCC ICC where fi = input frequency, CL = output load capacitance, VCC = supply voltage. tPLH, tPHL tPLH, tPHL tPLH, tPHL CI CPD (Note 11) 5 (Note 10) 5 5 5.7 4.6 3.2 93 20 16.4 11.5 10 5.5 4.5 3.2 93 22 18 12.6 10 ns ns ns pF pF CI CPD (Note 11) 7.2 5.2 4.8 3.4 4.3 3.1 93 227 25.5 18.2 151 16.9 12.1 134 15 10.7 10 7 5 4.7 3.3 4.1 3 93 250 28 20 166 18.6 13.3 148 16.5 11.8 10 ns ns ns ns ns ns ns ns ns pF pF SYMBOL VCC (V) MIN TYP MAX -55oC TO 125oC MIN TYP MAX UNITS 5 CD54/74AC153, CD54/74ACT153 tr = 3ns OUTPUT DISABLE tf = 3ns INPUT LEVEL 90% VS 10% GND tPLZ OUTPUT: LOW TO OFF TO LOW tPHZ OUTPUT: HIGH TO OFF TO HIGH OUTPUTS ENABLED tPZL VS 0.2VCC tPZH VOL ( GND) VOH ( VCC) 0.8 VCC VS OUTPUTS ENABLED GND (tPHZ, tPZH) OPEN (tPHL, tPLH) 2 VCC (tPLZ, tPZL) (OPEN DRAIN) OUTPUTS DISABLED OTHER INPUTS (TIED HIGH OR LOW) OUTPUT DISABLE DUT WITH THREESTATE OUTPUT 500 RL CL 50pF OUT 500 RL FOR AC SERIES ONLY: WHEN VCC = 1.5V, RL = 1k FIGURE 1. THREE-STATE PROPAGATION DELAY WAVEFORMS AND TEST CIRCUIT tr = 3ns E tf = 3ns 90% VS 10% I OR S OUTPUT Y tPLH tPHL VS FIGURE 2. PROPAGATION DELAY TIMES AND TEST CIRCUIT OUTPUT RL (NOTE) 500 DUT OUTPUT LOAD CL 50pF NOTE: For AC Series Only: When VCC = 1.5V, RL = 1k. AC Input Level Input Switching Voltage, VS Output Switching Voltage, VS VCC 0.5 VCC 0.5 VCC ACT 3V 1.5V 0.5 VCC FIGURE 3. PROPAGATION DELAY TIMES 6 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Customers are responsible for their applications using TI components. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof. Copyright (c) 2000, Texas Instruments Incorporated |
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