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SN54AHC573, SN74AHC573 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
SCLS242I - OCTOBER 1995 - REVISED JANUARY 2000
D D D D D
EPICTM (Enhanced-Performance Implanted CMOS) Process Operating Range 2-V to 5.5-V VCC
3-State Outputs Directly Drive Bus Lines Latch-Up Performance Exceeds 250 mA Per JESD 17 Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), Thin Very Small-Outline (DGV), Thin Shrink Small-Outline (PW), and Ceramic Flat (W) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) DIPs
SN54AHC573 . . . J OR W PACKAGE SN74AHC573 . . . DB, DGV, DW, N, OR PW PACKAGE (TOP VIEW)
OE 1D 2D 3D 4D 5D 6D 7D 8D GND
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
VCC 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q LE
description
The 'AHC573 devices are octal transparent D-type latches designed for 2-V to 5.5-V VCC operation. When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is low, the Q outputs are latched at the logic levels of the D inputs. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components.
SN54AHC573 . . . FK PACKAGE (TOP VIEW)
2D 1D OE VCC
3D 4D 5D 6D 7D
4 5 6 7 8
3 2 1 20 19 18 17 16 15 14 9 10 11 12 13
1Q 2Q 3Q 4Q 5Q 6Q
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The SN54AHC573 is characterized for operation over the full military temperature range of -55C to 125C. The SN74AHC573 is characterized for operation from -40C to 85C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright (c) 2000, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.
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8D GND LE 8Q 7Q
1
SN54AHC573, SN74AHC573 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
SCLS242I - OCTOBER 1995 - REVISED JANUARY 2000
FUNCTION TABLE (each latch) INPUTS OE L L L H LE H H L X D H L X X OUTPUT Q H L Q0 Z
logic symbol
OE LE 1D 2D 3D 4D 5D 6D 7D 8D 1 11 2 3 4 5 6 7 8 9 EN C1 1D 19 18 17 16 15 14 13 12 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
OE 1
LE
11 C1 19
1D
2
1D
1Q
To Seven Other Channels
2
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SN54AHC573, SN74AHC573 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
SCLS242I - OCTOBER 1995 - REVISED JANUARY 2000
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 mA Package thermal impedance, JA (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70C/W DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92C/W DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions (see Note 3)
SN54AHC573 MIN VCC VIH Supply voltage High-level input voltage VCC = 2 V VCC = 3 V VCC = 5.5 V VCC = 2 V VIL VI VO IOH Low-level input voltage Input voltage Output voltage High-level output current VCC = 2 V VCC = 3.3 V 0.3 V VCC = 5 V 0.5 V VCC = 2 V IOL Low-level output current VCC = 3.3 V 0.3 V VCC = 5 V 0.5 V VCC = 3.3 V 0.3 V VCC = 5 V 0.5 V VCC = 3 V VCC = 5.5 V 0 0 2 1.5 2.1 3.85 0.5 0.9 1.65 5.5 VCC -50 -4 -8 50 4 8 100 20 0 0 MAX 5.5 SN74AHC573 MIN 2 1.5 2.1 3.85 0.5 0.9 1.65 5.5 VCC -50 -4 -8 50 4 8 100 20 V V V V MAX 5.5 UNIT V
mA
mA
mA
mA ns/V
t/v
Input transition rise or fall rate
TA Operating free-air temperature -55 125 -40 85 C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
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SN54AHC573, SN74AHC573 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
SCLS242I - OCTOBER 1995 - REVISED JANUARY 2000
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC 2V IOH = -50 mA VOH IOH = -4 mA IOH = -8 mA IOL = 50 mA VOL IOL = 4 mA II IOZ ICC Ci IOL = 8 mA VI = VCC or GND VI = VIL or VIH, VO = VCC or GND VI = VCC or GND, IO = 0 VI = VCC or GND VO = VCC or GND 3V 4.5 V 3V 4.5 V 2V 3V 4.5 V 3V 4.5 V 0 V to 5.5 V 5.5 V 5.5 V 5V 2.5 MIN 1.9 2.9 4.4 2.58 3.94 0.1 0.1 0.1 0.36 0.36 0.1 0.25 4 10 TA = 25C TYP MAX 2 3 4.5 SN54AHC573 MIN 1.9 2.9 4.4 2.48 3.8 0.1 0.1 0.1 0.5 0.5 1* 2.5 40 MAX SN74AHC573 MIN 1.9 2.9 4.4 2.48 3.8 0.1 0.1 0.1 0.44 0.44 1 2.5 40 10 V V MAX UNIT
mA mA mA
pF pF
Co 5V 3.5 * On products compliant to MIL-PRF-38535, this parameter is not production tested at VCC = 0 V.
timing requirements over recommended operating free-air temperature range, VCC = 3.3 V 0.3 V (unless otherwise noted) (see Figure 1)
TA = 25C MIN MAX tw tsu th Pulse duration, LE high Setup time, data before LE Hold time, data after LE 5 3.5 1.5 SN54AHC573 MIN 5 3.5 1.5 MAX SN74AHC573 MIN 5 3.5 1.5 MAX UNIT ns ns ns
timing requirements over recommended operating free-air temperature range, VCC = 5 V 0.5 V (unless otherwise noted) (see Figure 1)
TA = 25C MIN MAX tw tsu th Pulse duration, LE high Setup time, data before LE Hold time, data after LE 5 3.5 1.5 SN54AHC573 MIN 5 3.5 1.5 MAX SN74AHC573 MIN 5 3.5 1.5 MAX UNIT ns ns ns
4
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SN54AHC573, SN74AHC573 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
SCLS242I - OCTOBER 1995 - REVISED JANUARY 2000
switching characteristics over recommended operating free-air temperature range, VCC = 3.3 V 0.3 V (unless otherwise noted) (see Figure 1)
PARAMETER tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ FROM (INPUT) D LE TO (OUTPUT) Q Q Q Q Q Q Q Q LOAD CAPACITANCE CL = 15 pF CL = 15 pF CL = 15 pF CL = 15 pF CL = 50 pF CL = 50 pF CL = 50 pF CL = 50 pF MIN TA = 25C TYP MAX 7* 7* 7.6* 7.6* 7.3* 7.3* 8.3* 8.3* 9.5 9.5 10.1 10.1 9.8 9.8 10.7 10.7 11* 11* 11.9* 11.9* 11.5* 11.5* 11* 11* 14.5 14.5 15.4 15.4 15 15 14.5 14.5 1.5** SN54AHC573 MIN 1* 1* 1* 1* 1* 1* 1* 1* 1 1 1 1 1 1 1 1 MAX 13* 13* 14* 14* 13.5* 13.5* 13* 13* 16.5 16.5 17.5 17.5 17 17 16.5 16.5 SN74AHC573 MIN 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 MAX 13 13 14 14 13.5 13.5 13 13 16.5 16.5 17.5 17.5 17 17 16.5 16.5 1.5 UNIT ns ns ns ns ns ns ns ns ns
OE OE D LE
OE OE
tsk(o) CL = 50 pF On products compliant to MIL-PRF-38535, this parameter is not production tested. On products compliant to MIL-PRF-38535, this parameter does not apply.
switching characteristics over recommended operating free-air temperature range, VCC = 5 V 0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ FROM (INPUT) D LE TO (OUTPUT) Q Q Q Q Q Q Q Q LOAD CAPACITANCE CL = 15 pF CL = 15 pF CL = 15 pF CL = 15 pF CL = 50 pF CL = 50 pF CL = 50 pF CL = 50 pF TA = 25C MIN TYP MAX 4.5* 4.5* 5* 5* 5.2* 5.2* 5.2* 5.2* 6 6 6.5 6.5 6.7 6.7 6.7 6.7 6.8* 6.8* 7.7* 7.7* 7.7* 7.7* 7.7* 7.7* 8.8 8.8 9.7 9.7 9.7 9.7 9.7 9.7 1** SN54AHC573 MIN 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 MAX 8* 8* 9* 9* 9* 9* 9* 9* 10 10 11 11 11 11 11 11 SN74AHC573 MIN 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 MAX 8 8 9 9 9 9 9 9 10 10 11 11 11 11 11 11 1 UNIT ns ns ns ns ns ns ns ns ns
OE OE D LE
OE OE
tsk(o) CL = 50 pF On products compliant to MIL-PRF-38535, this parameter is not production tested. On products compliant to MIL-PRF-38535, this parameter does not apply.
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SN54AHC573, SN74AHC573 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
SCLS242I - OCTOBER 1995 - REVISED JANUARY 2000
noise characteristics, VCC = 5 V, CL = 50 pF, TA = 25C (see Note 4)
PARAMETER VOL(P) VOL(V) VOH(V) VIH(D) Quiet output, maximum dynamic VOL Quiet output, minimum dynamic VOL Quiet output, minimum dynamic VOH High-level dynamic input voltage 4 3.5 1.5 SN74AHC573 MIN MAX 1 -0.8 UNIT V V V V V
VIL(D) Low-level dynamic input voltage NOTE 4: Characteristics are for surface-mount packages only.
operating characteristics, VCC = 5 V, TA = 25C
PARAMETER Cpd Power dissipation capacitance TEST CONDITIONS No load, f = 1 MHz TYP 16 UNIT pF
6
POST OFFICE BOX 655303
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SN54AHC573, SN74AHC573 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
SCLS242I - OCTOBER 1995 - REVISED JANUARY 2000
PARAMETER MEASUREMENT INFORMATION
RL = 1 k S1 VCC Open GND
From Output Under Test CL (see Note A)
Test Point
From Output Under Test CL (see Note A)
TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Drain
S1 Open VCC GND VCC
LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS
LOAD CIRCUIT FOR 3-STATE AND OPEN-DRAIN OUTPUTS VCC Timing Input tw VCC tsu Data Input 0V 50% VCC 50% VCC th 0V VCC 50% VCC 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC VCC 50% VCC tPZL 50% VCC tPZH Output Waveform 2 S1 at GND (see Note B) 50% VCC 50% VCC 0V tPLZ VCC VOL + 0.3 V tPHZ VOH - 0.3 V VOH 0 V VOL
Input
50% VCC
50% VCC
VOLTAGE WAVEFORMS PULSE DURATION
Input tPLH In-Phase Output tPHL Out-of-Phase Output
50% VCC
50% VCC 0V tPHL
Output Control
50% VCC
VOH 50% VCC VOL tPLH
Output Waveform 1 S1 at VCC (see Note B)
50% VCC
VOH 50% VCC VOL
VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO = 50 , tr 3 ns, tf 3 ns. D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
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Copyright (c) 2000, Texas Instruments Incorporated

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