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SN54AHCT595, SN74AHCT595 8-BIT SHIFT REGISTERS WITH 3-STATE OUTPUT REGISTERS
SCLS374G - MAY 1997 - REVISED JUNE 2000
D D D D D D D
EPICTM (Enhanced-Performance Implanted CMOS) Process Inputs Are TTL-Voltage Compatible 8-Bit Serial-In, Parallel-Out Shift Shift Register Has Direct Clear Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 - 2000-V Human-Body Model (A114-A) - 200-V Machine Model (A115-A) - 1000-V Charged-Device Model (C101) Package Options Include Plastic Small-Outline (D), Shrink Small-Outline (DB), Thin Shrink Small-Outline (PW), and Ceramic Flat (W) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) DIPs
SN54AHCT595 . . . J OR W PACKAGE SN74AHCT595 . . . D, DB, N, OR PW PACKAGE (TOP VIEW)
QB QC QD QE QF QG QH GND
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
VCC QA SER OE RCLK SRCLK SRCLR QH
SN54AHCT595 . . . FK PACKAGE (TOP VIEW)
QC QB NC VCC QA QD QE NC QF QG
4 5 6 7 8 3 2 1 20 19 18 17 16 15 14 9 10 11 12 13
description
The 'AHCT595 devices contain an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. The storage register has parallel 3-state outputs. Separate clocks are provided for the shift and storage registers. The shift register has a direct overriding clear (SRCLR) input, serial (SER) input, and serial outputs for cascading. When the output-enable (OE) input is high, the outputs are in the high-impedance state.
SER OE NC RCLK SRCLK
QH
GND NC Q H
NC - No internal connection
Both the shift register clock (SRCLK) and storage register clock (RCLK) are positive-edge triggered. If both clocks are connected together, the shift register always is one clock pulse ahead of the storage register. The SN54AHCT595 is characterized for operation over the full military temperature range of -55C to 125C. The SN74AHCT595 is characterized for operation from -40C to 85C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC is a trademark of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303
Copyright (c) 2000, Texas Instruments Incorporated
* DALLAS, TEXAS 75265
SRCLR
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SN54AHCT595, SN74AHCT595 8-BIT SHIFT REGISTERS WITH 3-STATE OUTPUT REGISTERS
SCLS374G - MAY 1997 - REVISED JUNE 2000
FUNCTION TABLE INPUTS SER X X X L H X X X SRCLK X X X X X SRCLR X X L H H H X X RCLK X X X X X X OE H L X X X X X X FUNCTION Outputs QA-QH are disabled. Outputs QA-QH are enabled. Shift register is cleared. First stage of the shift register goes low. Other stages store the data of previous stage, respectively. First stage of the shift register goes high. Other stages store the data of previous stage, respectively. Shift-register state is not changed. Shift-register data is stored in the storage register. Storage-register state is not changed.
logic symbol
OE RCLK 13 12 EN3 C2 SRG8 R C1/ 14 15 1D 2D 3 1 2 3 4 5 6 2D 3 7 9
10 SRCLR SRCLK 11
SER
QA QB QC QD QE QF QG QH QH
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the D, DB, J, N, PW, and W packages.
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POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
SN54AHCT595, SN74AHCT595 8-BIT SHIFT REGISTERS WITH 3-STATE OUTPUT REGISTERS
SCLS374G - MAY 1997 - REVISED JUNE 2000
logic diagram (positive logic)
OE RCLK SRCLR SRCLK SER 13 12 10 11 14 1D Q C1 R 3D C3 Q
15
QA
2D Q C2 R
3D C3 Q
1
QB
2D Q C2 R
3D C3 Q
2
QC
2D Q C2 R
3D C3 Q
3
QD
2D Q C2 R
3D C3 Q
4
QE
2D Q C2 R
3D C3 Q
5
QF
2D Q C2 R
3D C3 Q
6
QG
2D Q C2 R
3D C3 Q
7
QH QH
9
Pin numbers shown are for the D, DB, J, N, PW, and W packages.
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
3
SN54AHCT595, SN74AHCT595 8-BIT SHIFT REGISTERS WITH 3-STATE OUTPUT REGISTERS
SCLS374G - MAY 1997 - REVISED JUNE 2000
timing diagram
SRCLK
SER
RCLK
SRCLR
OE
QA
QB
QC
QD
QE
QF
QG
QH
QH'
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POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
IIIII IIIII IIIII IIIII IIIII IIIII IIIII IIIII IIIII IIIII IIIII IIIII IIIII IIIII IIIII IIIII
SN54AHCT595, SN74AHCT595 8-BIT SHIFT REGISTERS WITH 3-STATE OUTPUT REGISTERS
SCLS374G - MAY 1997 - REVISED JUNE 2000
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Package thermal impedance, JA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73C/W DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions (see Note 3)
SN54AHCT595 MIN VCC VIH VIL VI VO IOH IOL t/v Supply voltage High-level input voltage Low-level input voltage Input voltage Output voltage High-level output current Low-level output current Input transition rise or fall rate 0 0 4.5 2 0.8 5.5 VCC -8 8 20 0 0 MAX 5.5 SN74AHCT595 MIN 4.5 2 0.8 5.5 VCC -8 8 20 MAX 5.5 UNIT V V V V V mA mA ns/V
TA Operating free-air temperature -55 125 -40 85 C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
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SN54AHCT595, SN74AHCT595 8-BIT SHIFT REGISTERS WITH 3-STATE OUTPUT REGISTERS
SCLS374G - MAY 1997 - REVISED JUNE 2000
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER VOH VOL II IOZ ICC ICC Ci TEST CONDITIONS IOH = -50 mA IOH = -8 mA IOL = 50 mA IOL = 8 mA VI = VCC or GND VO = VCC or GND VI = VCC or GND, IO = 0 One input at 3.4 V, Other inputs at VCC or GND VI = VCC or GND VCC 4.5 45V 45V 4.5 0 V to 5.5 V 5.5 V 5.5 V 5.5 V 5V 3 MIN 4.4 3.94 0.1 0.36 0.1 0.25 4 1.35 10 TA = 25C TYP MAX 4.5 SN54AHCT595 MIN 4.4 3.8 0.1 0.44 1* 2.5 40 1.5 MAX SN74AHCT595 MIN 4.4 3.8 0.1 0.44 1 2.5 40 1.5 10 MAX UNIT V V
mA mA mA
mA pF pF
Co VO = VCC or GND 5V 5.5 * On products compliant to MIL-PRF-38535, this parameter is not production tested at VCC = 0 V. This is the increase in supply current for each input at one of the specified TTL voltage levels rather than 0 V or VCC.
timing requirements over recommended operating free-air temperature range, VCC = 5 V 0.5 V (unless otherwise noted) (see Figure 1)
TA = 25C MIN MAX SRCLK high or low tw Pulse duration RCLK high or low SRCLR low SER before SRCLK tsu SRCLK before RCLK Setup time SRCLR low before RCLK SRCLR high (inactive) before SRCLK 5 5 5 3 5 5 3.4 SN54AHCT595 MIN 5.5 5.5 5 3 5 5 3.8 MAX SN74AHCT595 MIN 5.5 5.5 5 3 5 5 3.8 ns ns MAX UNIT
th Hold time SER after SRCLK 2 2 2 ns This setup time allows the storage register to receive stable data from the shift register. The clocks can be tied together, in which case the shift register is one clock pulse ahead of the storage register.
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
6
POST OFFICE BOX 655303
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SN54AHCT595, SN74AHCT595 8-BIT SHIFT REGISTERS WITH 3-STATE OUTPUT REGISTERS
SCLS374G - MAY 1997 - REVISED JUNE 2000
switching characteristics over recommended operating free-air temperature range, VCC = 5 V 0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER fmax tPLH tPHL tPLH tPHL tPHL tPZH tPZL tPLH tPHL tPLH tPHL tPHL tPZH tPZL tPHZ tPLZ RCLK SRCLK SRCLR OE RCLK SRCLK SRCLR OE OE QA-QH Q QH QH QA-QH Q QA-QH Q QH QH QA-QH Q QA-QH Q FROM (INPUT) TO (OUTPUT) LOAD CAPACITANCE CL = 15 pF CL = 50 pF CL = 15 pF CL = 15 pF CL = 15 pF CL = 15 pF CL = 50 pF CL = 50 pF CL = 50 pF CL = 50 pF CL = 50 pF MIN 135* 95 TA = 25C TYP MAX 170* 140 4.3* 4.3* 4.5* 4.5* 4.5* 4.3* 5.4* 5.6 5.6 6.4 6.4 6.4 5.7 6.8 3.5 3.4 7.4* 7.4* 8.2* 8.2* 8* 8.6* 8.6* 9.4 9.4 10.2 10.2 10 10.6 10.6 10.3 10.3 SN54AHCT595 MIN 115* 85 1* 1* 1* 1* 1* 1* 1* 1 1 1 1 1 1 1 1 1 8.5* 8.5* 9.4* 9.4* 9.1* 10* 10* 10.5 10.5 11.4 11.4 11.1 12 12 11 11 MAX SN74AHCT595 MIN 115 85 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 8.5 8.5 9.4 9.4 9.1 10 10 10.5 10.5 11.4 11.4 11.1 12 12 11 11 MAX UNIT MHz ns ns ns ns ns ns ns ns ns
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
noise characteristics, VCC = 5 V, CL = 50 pF, TA = 25C (see Note 4)
PARAMETER VOL(P) VOL(V) VOH(V) VIH(D) Quiet output, maximum dynamic VOL Quiet output, minimum dynamic VOL Quiet output, minimum dynamic VOH High-level dynamic input voltage 2 0.8 SN74AHCT595 MIN TYP 1 -0.6 3.8 MAX UNIT V V V V V
VIL(D) Low-level dynamic input voltage NOTE 4: Characteristics are for surface-mount packages only.
operating characteristics, VCC = 5 V, TA = 25C
PARAMETER Cpd Power dissipation capacitance TEST CONDITIONS No load, f = 1 MHz TYP 112 UNIT pF
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
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SN54AHCT595, SN74AHCT595 8-BIT SHIFT REGISTERS WITH 3-STATE OUTPUT REGISTERS
SCLS374G - MAY 1997 - REVISED JUNE 2000
PARAMETER MEASUREMENT INFORMATION
RL = 1 k S1 VCC Open GND
From Output Under Test CL (see Note A)
Test Point
From Output Under Test CL (see Note A)
TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Drain
S1 Open VCC GND VCC
LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS
LOAD CIRCUIT FOR 3-STATE AND OPEN-DRAIN OUTPUTS 3V Timing Input tw 3V tsu Data Input 0V 1.5 V 1.5 V 0V th 3V 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 3V 3V 1.5 V tPZL 50% VCC tPZH Output Waveform 2 S1 at GND (see Note B) 50% VCC 1.5 V 0V tPLZ VCC VOL + 0.3 V VOL tPHZ VOH - 0.3 V VOH 0 V
Input
1.5 V
1.5 V
VOLTAGE WAVEFORMS PULSE DURATION
Input tPLH In-Phase Output tPHL Out-of-Phase Output
1.5 V
1.5 V 0V tPHL 50% VCC VOH 50% VCC VOL tPLH 50% VCC VOH 50% VCC VOL
Output Control
Output Waveform 1 S1 at VCC (see Note B)
VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO = 50 , tr 3 ns, tf 3 ns. D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
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IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Customers are responsible for their applications using TI components. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof.
Copyright (c) 2000, Texas Instruments Incorporated

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