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SN54LV175A, SN74LV175A QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR
SCLS400C - APRIL 1998 - REVISED MAY 2000
D D D D D D D D D D
EPIC TM (Enhanced-Performance Implanted CMOS) Process Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25C Typical VOHV (Output VOH Undershoot) >2.3 V at VCC = 3.3 V, TA = 25C 2-V to 5.5-V VCC Operation Support Mixed-Mode Voltage Operation on All Ports Contain Four Flip-Flops With Double-Rail Outputs Applications Include: - Buffer/Storage Registers - Shift Registers - Pattern Generators Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Package Options Include Plastic Small-Outline (D, NS), Shrink Small-Outline (DB), Thin Very Small-Outline (DGV), and Thin Shrink Small-Outline (PW) Packages, Ceramic Flat (W) Packages, Chip Carriers (FK), and DIPs (J)
SN54LV175A . . . J OR W PACKAGE SN74LV175A . . . D, DB, DGV, NS, OR PW PACKAGE (TOP VIEW)
CLR 1Q 1Q 1D 2D 2Q 2Q GND
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
VCC 4Q 4Q 4D 3D 3Q 3Q CLK
SN54LV175A . . . FK PACKAGE (TOP VIEW)
1Q 1D NC 2D 2Q
1Q CLR NC VCC 4Q
4 5 6 7 8 3 2 1 20 19 18 17 16 15 14 9 10 11 12 13
4Q 4D NC 3D 3Q
NC - No internal connection
description
The 'LV175A devices are quadruple D-type flip-flops designed for 2-V to 5.5-V VCC operation. These devices have a direct clear (CLR) input and feature complementary outputs from each flip-flop. Information at the data (D) inputs meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going edge of CLK. When CLK is at either the high or low level, the D input has no effect at the output. The SN54LV175A is characterized for operation over the full military temperature range of -55C to 125C. The SN74LV175A is characterized for operation from -40C to 85C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC is a trademark of Texas Instruments.
UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303
Copyright (c) 2000, Texas Instruments Incorporated
* DALLAS, TEXAS 75265
2Q GND NC CLK 3Q
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SN54LV175A, SN74LV175A QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR
SCLS400C - APRIL 1998 - REVISED MAY 2000
FUNCTION TABLE (each flip-flop) INPUTS CLR L H H H CLK X L D X H L X OUTPUTS Q L H L Q0 Q H L H Q0
logic symbol
CLR CLK 1 9 R C1 2 1D 4 1D 3 7 2D 5 6 10 3D 12 11 15 4D 13 14 3Q 4Q 4Q 1Q 1Q 2Q 2Q 3Q
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the D, DB, DGV, J, NS, PW, and W packages.
logic diagram (positive logic)
CLR 1
CLK 1D
9 4 2
1D C1 R
1Q
3
1Q
To Three Other Channels Pin numbers shown are for the D, DB, DGV, J, NS, PW, and W packages.
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POST OFFICE BOX 655303
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SN54LV175A, SN74LV175A QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR
SCLS400C - APRIL 1998 - REVISED MAY 2000
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V Voltage range applied to any output in the high-impedance or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Package thermal impedance, JA (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73C/W DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82C/W DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. This value is limited to 5.5 V maximum. 3. The package thermal impedance is calculated in accordance with JESD 51.
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SN54LV175A, SN74LV175A QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR
SCLS400C - APRIL 1998 - REVISED MAY 2000
recommended operating conditions (see Note 4)
SN54LV175A MIN VCC Supply voltage VCC = 2 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V VCC = 2 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V 0 0 VCC = 2 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V VCC = 2 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V 0 0 0 2 1.5 VCC x 0.7 VCC x 0.7 VCC x 0.7 0.5 VCC x 0.3 VCC x 0.3 VCC x 0.3 5.5 VCC -50 -2 -6 -12 50 2 6 12 200 100 20 0 0 0 0 0 MAX 5.5 SN74LV175A MIN 2 1.5 VCC x 0.7 VCC x 0.7 VCC x 0.7 0.5 VCC x 0.3 VCC x 0.3 VCC x 0.3 5.5 VCC -50 -2 -6 -12 50 2 6 12 200 100 20 ns/V mA A mA V V MAX 5.5 UNIT V
VIH
High-level High level input voltage
VIL
Low-level Low level input voltage
VI VO
Input voltage Output voltage
V V A
IOH
High-level High level output current
IOL
Low-level Low level output current
t/v
Input transition rise or fall rate
TA Operating free-air temperature -55 125 -40 85 C NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
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POST OFFICE BOX 655303
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SN54LV175A, SN74LV175A QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR
SCLS400C - APRIL 1998 - REVISED MAY 2000
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS IOH = -50 A IOH = -2 mA IOH = -6 mA IOH = -12 mA IOL = 50 A IOL = 2 mA IOL = 6 mA IOL = 12 mA VI = VCC or GND VI = VCC or GND, VI or VO = 0 to 5.5 V VI = VCC or GND IO = 0 SN54LV175A VCC 2 V to 5.5 V 2.3 V 3V 4.5 V 2 V to 5.5 V 2.3 V 3V 4.5 V 0 V to 5.5 V 5.5 V 0V 3.3 V 1.4 MIN VCC-0.1 2 2.48 3.8 0.1 0.4 0.44 0.55 1 20 5 1.4 TYP MAX SN74LV175A MIN VCC-0.1 2 2.48 3.8 0.1 0.4 0.44 0.55 1 20 5 A A A pF V TYP MAX UNIT
VOH
V
VOL
II ICC Ioff Ci
timing requirements over recommended operating free-air temperature range, VCC = 2.5 V 0.2 V (unless otherwise noted) (see Figure 1)
TA = 25C MIN MAX tw tsu th Pulse duration CLR low CLK high or low Data Set p time before CLK Setup Hold time, data after CLK CLR inactive 6 6.5 7 7 0.5 SN54LV175A MIN 6 7 7.5 7.5 1 MAX SN74LV175A MIN 6 7 7.5 7.5 1 MAX UNIT ns ns ns
timing requirements over recommended operating free-air temperature range, VCC = 3.3 V 0.3 V (unless otherwise noted) (see Figure 1)
TA = 25C MIN MAX tw tsu th Pulse duration CLR low CLK high or low Data Setup Set p time before CLK Hold time, data after CLK CLR inactive 5 5 5 5 1 SN54LV175A MIN 5 5 5 5 1 MAX SN74LV175A MIN 5 5 5 5 1 MAX UNIT ns ns ns
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
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SN54LV175A, SN74LV175A QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR
SCLS400C - APRIL 1998 - REVISED MAY 2000
timing requirements over recommended operating free-air temperature range, VCC = 5 V 0.5 V (unless otherwise noted) (see Figure 1)
TA = 25C MIN MAX tw tsu th Pulse duration CLR low CLK high or low Data Set p time before CLK Setup Hold time, data after CLK CLR inactive 5 5 4 5 1 SN54LV175A MIN 5 5 4 5 1 MAX SN74LV175A MIN 5 5 4 5 1 MAX UNIT ns ns ns
switching characteristics over recommended operating free-air temperature range, VCC = 2.5 V 0.2 V (unless otherwise noted) (see Figure 1)
PARAMETER fmax tpd d tpd d CLR CLK CLR CLK Any Any Any Any FROM (INPUT) TO (OUTPUT) LOAD CAPACITANCE CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF MIN 50* 40 TA = 25C TYP MAX 105* 80 7.9* 9.3* 10.4 12 16.6* 18.8* 21.6 23.3 2 SN54LV175A MIN 45* 35 1* 1* 1 1 20* 22* 25.5 27 MAX SN74LV175A MIN 45 35 1 1 1 1 20 22 25.5 27 2 MAX UNIT MHz ns ns ns
tsk(o) CL = 50 pF * On products compliant to MIL-PRF-38535, this parameter is not production tested.
switching characteristics over recommended operating free-air temperature range, VCC = 3.3 V 0.3 V (unless otherwise noted) (see Figure 1)
PARAMETER fmax tpd d tpd d tsk(o) CLR CLK CLR CLK Any Any Any Any FROM (INPUT) TO (OUTPUT) LOAD CAPACITANCE CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 50 pF TA = 25C MIN TYP MAX 90* 50 155* 120 5.5* 6.5* 7.4 8.4 10.1* 11.5* 13.6 15 1.5 SN54LV175A MIN 75* 45 1* 1* 1 1 12* 13.5* 15.5 17 MAX SN74LV175A MIN 75 45 1 1 1 1 12 13.5 15.5 17 1.5 MAX UNIT MHz ns ns ns
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
6
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
SN54LV175A, SN74LV175A QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR
SCLS400C - APRIL 1998 - REVISED MAY 2000
switching characteristics over recommended operating free-air temperature range, VCC = 5 V 0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER fmax tpd d tpd d CLR CLK CLR CLK Any Any Any Any FROM (INPUT) TO (OUTPUT) LOAD CAPACITANCE CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF MIN 150* 85 TA = 25C TYP MAX 215* 165 3.7* 4.6* 5.3 6 6.4* 7.3* 8.4 9.3 1 SN54LV175A MIN 125* 75 1* 1* 1 1 7.5* 8.5* 9.5 10.5 MAX SN74LV175A MIN 125 75 1 1 1 1 7.5 8.5 9.5 10.5 1 MAX UNIT MHz ns ns ns
tsk(o) CL = 50 pF * On products compliant to MIL-PRF-38535, this parameter is not production tested.
noise characteristics, VCC = 3.3 V, CL = 50 pF, TA = 25C (see Note 5)
PARAMETER VOL(P) VOL(V) VOH(V) VIH(D) Quiet output, maximum dynamic VOL Quiet output, minimum dynamic VOL Quiet output, minimum dynamic VOH High-level dynamic input voltage 2.31 0.99 SN74LV175A MIN TYP 0.3 -0.3 3 MAX 0.8 -0.8 UNIT V V V V V
VIL(D) Low-level dynamic input voltage NOTE 5: Characteristics are for surface-mount packages only.
operating characteristics, TA = 25C
PARAMETER Cpd Power dissi ation ca acitance dissipation capacitance TEST CONDITIONS CL = 50 pF F, f = 10 MHz VCC 3.3 V 5V TYP 13.6 14.5 UNIT pF F
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SN54LV175A, SN74LV175A QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR
SCLS400C - APRIL 1998 - REVISED MAY 2000
PARAMETER MEASUREMENT INFORMATION
RL = 1 k S1 VCC Open GND
From Output Under Test CL (see Note A)
Test Point
From Output Under Test CL (see Note A)
TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Drain
S1 Open VCC GND VCC
LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS
LOAD CIRCUIT FOR 3-STATE AND OPEN-DRAIN OUTPUTS VCC 50% VCC 0V VCC tsu Data Input 0V 50% VCC th VCC 50% VCC 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC VCC 50% VCC tPZL Output Waveform 1 S1 at VCC (see Note B) Output Waveform 2 S1 at GND (see Note B) tPZH tPLZ 50% VCC tPHZ VOH - 0.3 V VOH 0V 50% VCC 0V VCC VOL + 0.3 V VOL
Timing Input tw
Input
50% VCC
50% VCC
VOLTAGE WAVEFORMS PULSE DURATION
Input tPLH In-Phase Output tPHL Out-of-Phase Output
50% VCC
50% VCC tPHL
0V
Output Control
50% VCC
VOH 50% VCC VOL tPLH
50% VCC
VOH 50% VCC VOL
50% VCC
VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO = 50 , tr 3 ns, tf 3 ns. D. The outputs are measured one at a time with one input transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPHL and tPLH are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
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IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Customers are responsible for their applications using TI components. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof.
Copyright (c) 2000, Texas Instruments Incorporated

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