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| 8-Bit Microcontroller with OSD SDA 20Cxx50 Preliminary Data CMOS IC 1 Features q SAB 8051 Architecture - - - - - On-chip oscillator and clock circuits Binary or decimal arithmetic Signed-overflow detection and parity computation Integrated Boolean processor for control applications Full depth stack for subroutine return linkage and data storage - Two priority level, nested interrupt structure q On-Screen Display Unit P-DIP-40 - Up to six lines of 18 characters without software multiplexing - More than six lines when using software multiplexing - Interrupt generation by the OSD logic - 12 x 16 dot character matrix - 96 user defined characters (mask-programmable) - Two character sizes selectable individually for each line - Boxed or non-boxed mode selectable for each line - Character frame mode software selectable - One of eight colors selectable for each character - One of eight background colors selectable - LC oscillator for dot clock generation - Dot clock synchronization by sandcastle pulse - R/G/B/BLANK-outputs for colored text or symbols q On-Chip RAM - Direct byte and bit addressability - Four register banks - Data memory with power down mode operation, including 128 user-defined software flags: 128 bytes for SDA 20C0850 256 bytes for SDA 20C1650 256 bytes for SDA 20C2450 256 bytes for SDA 20C3250 Semiconductor Group 5 01.94 SDA 20Cxx50 - Data memory accessible with MOVX-instructions (XRAM): 0 bytes for SDA 20C0850 0 bytes for SDA 20C1650 128 bytes for SDA 20C2450 256 bytes for SDA 20C3250 q On-Chip ROM - Mask-programmable program memory: 8192 bytes for SDA 20C0850 16384 bytes for SDA 20C1650 24576 bytes for SDA 20C2450 32768 bytes for SDA 20C3250 q 26 Bidirectional I/O Lines - - - - - One 8-bit port comprising up to eight programmable D/A outputs One 8-bit multifunction port One 8-bit port with open drain output for LED-driving One 2-bit port with open drain output Two additional input lines q Pulse Width Modulation Unit - Up to eight programmable PWM-output channels for low cost Digital-to-analog conversion (8-bit resolution) q Timers - Two 16-bit general purpose timers/event counters - One 16-bit multi mode-timer with 2-bit prescaler and selectable watchdog, interrupt or capture function (not for SDA 20C0850). q Serial Interface - Full duplex UART Interface Type SDA 20C0850 SDA 20C1850 SDA 20C2450 SDA 20C3250 Ordering Code Q Q Q Q Package P-DIP-40 P-DIP-40 P-DIP-40 P-DIP-40 Semiconductor Group 6 SDA 20Cxx50 Pin Configuration (top view) Semiconductor Group 7 SDA 20Cxx50 1.1 Pin Definitions and Functions Symbol Input (I) Output (O) Supply (S) I I/O I/O I/O I/O I/O I/O I/O I/O S S I O Function Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 P5.4 P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0 P5.4 is an input port only Port 0 is an 8-bit open drain bidirectional l/O-port. Port 0 pins that have 1 s written to them float; in this state they can be used as high-impedance inputs. VSS VDD XTAL1 XTAL2 Ground (0 V) Power supply voltage Input to the inverting oscillator amplifier. Output of the inverting oscillator amplifier. To drive the device from an external clock source, XTAL1 should be driven, while XTAL2 is left open. A low level on this pin resets the processor. Port 1 is an 8-bit bidirectional l/O-port with internal pullup resistors. Port 1 pins that have 1 s written to them are pulled high by the internal pullup resistors, and in that state can be used as inputs. These eight bits also contain the output channels of the pulse width modulation unit. The secondary functions are assigned to the pins of port 1 as follows: PWMi (P1.i): output of PWM-channel i (i = 0,...,7) 14 15 16 17 18 19 20 21 22 RST P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 I I/O I/O I/O I/O I/O I/O I/O I/O Semiconductor Group 8 SDA 20Cxx50 Pin Definitions and Functions (cont'd) Pin No. Symbol Input (I) Output (O) Supply (S) I/O I/O I/O I/O I/O I/O I/O I/O Function 23 24 25 26 27 28 29 30 P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 Port 3 is an 8-bit bidirectional l/O port with internal pullup resistors. Port 3 pins that have l s written to them are pulled high by the internal pullup resistors, and in that state can be used as inputs. It also contains the interrupt, timer, serial port and capture input pins. The output latch corresponding to a secondary function must be programmed to a one (1) for that function to operate. The secondary functions are assigned to the pins of port 3, as follows: - CAP (P3.1) : input for timer capture mode - INT0 (P3.2) : interrupt 0 input/timer 0 gate control input - INT1 (P3.3) : interrupt 1 input/timer 1 gate control input - T0 (P3.4) : counter 0 input - T1 (P3.5) : counter 1 input - RXD (P3.6) : serial port receive line - TXD (P3.7) : serial port transmit line Port 4 is a 2-bit bidirectional l/O port with no internal pullup. Port 4 pins that have 1 s written to them must be pulled high by an external pullup resistor, and in that state can be used as inputs. Sandcastle synchronization input P5.3 is an input port only Red color signal output Green color signal output Blue color signal output Blanking output LCIN and LCOUT are used to connect the external dot clock frequency reference. 31 32 P4.0 P4.1 I/O I/O 33 34 35 36 37 38 39 40 SC P5.3 R G B BLANK LCIN LCOUT I I O O O O Semiconductor Group 9 SDA 20Cxx50 1.2 Block Diagram Figure 1 Block Diagram RAM 128 x 8 256 x 8 256 x 8 256 x 8 XRAM - - 128 x 8 256 x 8 ROM 8Kx8 16 K x 8 24 K x 8 32 K x 8 Chip SDA 20C0850 SDA 20C1650 SDA 20C2450 SDA 20C3250 Semiconductor Group 10 SDA 20Cxx50 2 2.1 Functional Description Architecture The CPU manipulates operands in two memory spaces. These are the internal program memory and the internal data memory and extended data memory spaces. (No internal extended data memory in SDA 20C0850 and SDA 20C1650). The internal data memory address space is divided into the 256-byte internal data RAM (128 byte for SDA 20C0850) and the 128-byte Special Function Register (SFR) address spaces. Four register banks (each bank has eight registers), 128 addressable bits, and the stack reside in the internal data RAM. The stack depth is limited only by the available internal data RAM. Its location is determined by the 8-bit Stack Pointer (SP). All registers except the four 8-register banks reside in the special function register address space. These memory mapped registers include arithmetic registers, pointers, I/O ports, registers for the interrupt system, timer, pulse width modulator, serial channel and OSD circuit. 128-bit locations in the SFR address space are addressable as bits. The extended data Memory is addressed by MOVX-instructions and addressed by the data pointer register DPTR. (No internal extended data memory in SDA 20C0850 and SDA 20C1650). Conditional branches are performed relative to the 16-bit program counter. The register-indirect jump permits branching relative to a 16-bit base register with an offset provided by an 8-bit index register. Sixteen-bit jumps and calls permit branching to any location in the internal memory address space. The processor has five methods for addressing source operands: register, direct, register-indirect, immediate, and base-register plus index-register indirect addressing. The first three methods can be used for addressing destination operands. Most instructions have a "destination, source" field that specifies the data type, addressing methods and operands involved. For operations other than moves, the destination operand is also a source operand. Registers in the four 8 register banks can be accessed through register, direct, or register-indirect addressing; the lower 128 bytes of internal data RAM through direct or register-indirect addressing, the upper 128 bytes of internal data RAM through register-indirect addressing and the special function registers through direct addressing. Look-up tables resident in program memory can be accessed through base-register plus index-register indirect addressing. 2.1.1 CPU Hardware The functional block diagram displayed in figure 2 shows the hardware architecture of the CPU in detail. Instruction Decoder Each program instruction is decoded by the instruction decoder. This unit generates the internal signals that control the functions of each unit within the CPU section. These signals control the sources and destination of data, as well as the function of the Arithmetic/Logic Unit (ALU). Semiconductor Group 11 SDA 20Cxx50 Program Control Section The program control section controls the sequence in which the instructions stored in program memory are executed. The conditional branch logic enables conditions internal and external to the processor to cause a change in the sequence of program execution. The 16-bit program counter holds the address of the instruction to be executed. It is manipulated with the control transfer instructions listed in chapter "Instruction Set". Internal Program Memory The controller contains 8/16/24/32 Kbyte of internal program memory for SDA 20C08/16/24/32 resident on-chip. The memory is mask-programmable. Internal Data RAM The internal data RAM provides a 256-byte scratch pad memory (128 byte for SDA 20C0850), which includes four register banks and 128 direct addressable software flags. Each register bank contains registers R0-R7. The addressable flags are located in the 16-byte locations starting at byte address 32 and ending with byte location 47 of the RAM address space. Arithmetic/Logic Unit (ALU) The arithmetic section of the processor performs many data manipulation functions and includes the Arithmetic/Logic Unit (ALU) and the A-, B- and PSW registers. The ALU accepts 8-bit data words from one or two sources and generates an 8-bit result under the control of the instruction decoder. The ALU performs the arithmetic operations of add, subtract, multiply, divide, increment, decrement, BCD decimal-add-adjust and compare, and the logic operations of and, or, exclusive-or, complement and rotate (right, left, or nibble swap). The A register is the accumulator, the B register is dedicated during multiply and divide and serves as both a source and a destination. During all other operations the B register is simply another location of the special function register space and may be used for any purpose. Semiconductor Group 12 SDA 20Cxx50 Boolean Processor The Boolean processor is an integral part of the processor architecture. It is an independent bit processor with its own instruction set, its own accumulator (the carry flag) and its own bit-addressable RAM and l/O. The bit manipulation instructions allow the direct addressing of 128 bits within the internal data RAM and several bits within the special function registers. The special function registers which have addresses exactly divisible by eight contain directly addressable bits. The Boolean processor can perform, on any addressable bit, the bit operations of set, clear, complement, jump-if-set, jump-if-not-set, jump-if set then-clear and move to/from carry. Between any addressable bit (or its complement) and the carry flag it can perform the bit operation of logical AND or logical OR with the result returned to the carry flag. Program Status Word Register (PSW) The PSW flags record processor status information and controls the operation of the processor. The carry (CY), auxiliary carry (AC), two user flags (F0 and F1), register bank select (RS0 and RS1), overflow (OV) and parity (P) flags reside in the program status word register. These flags are bitmemory-mapped within the byte-memory-mapped PSW. The CY-, AC-, and OV flags generally reflect the status of the latest arithmetic operations. The CY flag is also the Boolean accumulator for bit operations. The P flag always reflects the parity of the A register. F0 and F1 are general purpose flags which are pushed onto the stack as part of a PSW save. The two register bank select bits (RS1 and RS0) determine which one of the four register banks is selected as follows: RS1 0 0 1 1 RS0 0 1 0 1 Register Bank 0 1 2 3 Register Location 00H - 07H 08H - 0FH 10H - 17H 18H - 1FH MSB CY AC F0 SFR Address: D0H PSW: Program Status Word RS1 RS0 OV F1 LSB P Stack Pointer (SP) The 8-bit stack pointer contains the address at which the last byte was pushed onto the stack. This is also the address of the next byte that will be popped. The SP is incremented during a push. SP can be read from or written to under software control. The stack may be located anywhere within the internal data RAM address space and may be as large as 256 bytes. (128 bytes for SDA 20C0850). Semiconductor Group 13 SDA 20Cxx50 Data Pointer Register (DPTR) The 16-bit data pointer register DPTR is the concatenation of registers DPH (high-order byte) and DPL (low-order byte). The DPTR is used in register-indirect addressing to move program memory constants and to access the extended data memory. DPTR may be manipulated as one 16-bit register or as two independent 8-bit registers DPL and DPH. Port 0, Port 1, Port 3, Port 4, Port 5 These four ports provide 26 I/O lines to interface to the external world. These ports are both byte and bit addressable. Port 0 is used for binary l/O and offers eight open drain output lines. Port 1 provides up to eight PWM output channels as alternate functions while port 3 contains special control signals. Port 4 is a two bit open drain l/O port. P5 contains two additional input lines. Interrupt Logic Controlled by five special function registers (TCON, IE, IP, IFR, SCON) the interrupt logic provides six interrupt vectors. Each of them may be assigned to high or low priority (see chapter "Interrupt System"). Timer/Counter 0/1 Two general purpose 16-bit timers/counters are controlled by the special function registers TMOD and TCON (see chapter "General Purpose Timers/ Counters"). Multi Mode Timer (not for SDA 20C0850) A 16-bit timer with a programmable 2-bit prescaler may be used as watchdog, capture or general purpose timer. It is controlled by the special function registers WDMOD, WDTC, WDCL, WDCH, WDRL, WDRH, CAPL and CAPH (see chapter "Multi Mode Timer"). Pulse Width Modulation Unit Up to eight lines of port 1 may be used as 8-bit PWM-outputs. The PWM logic is controlled by registers PWME, PWMC, PWCOUNT, PWCOMP0...7 (see chapter "Pulse Width Modulation Unit"). On Screen Display Unit Text and graphics to be inserted into a video picture are generated by the on-screen display unit. Control registers DER, DHR, DVR0...5, DSCR, DDR, DAR, DCPR are described in chapter "OnScreen Display". Serial Interface To communicate with other UART (universal asynchronous receiver/transmitter) devices and for I/O-expansion, a full duplex serial interface has been provided. It consists of a serial port receive line RxD and a serial port transmit line TxD and can be programmed to function in different operating modes (see chapter "Serial Interface"). Semiconductor Group 14 SDA 20Cxx50 Figure 2 Functional Block Diagram Semiconductor Group 15 SDA 20Cxx50 2.1.2 CPU Timing The timing generation is completely self-contained, except for the frequency reference which can be a crystal or external clock source. 2.1.3 Addressing Modes There are five general addressing modes operating on bytes. One of these five addressing modes, however, operates on both bytes and bits: - - - - - Register Direct (both bytes and bits) Register Indirect Immediate Base-Register plus Index-Register Indirect The following table summarizes, which memory spaces may be accessed by each of the addressing modes: Register Addressing R0-R7 ACC, B, CY (bit), DPTR Direct Addressing RAM (Low Part) Special Function Registers Register Indirect Addressing RAM (@R1, @R0, SP) Immediate Addressing Program Memory Base-Register plus Index-Register Indirect Addressing Program Memory (@DPTR + A, @ PC + A) Register Addressing Register addressing accesses the eight working registers (R0-R7) of the selected register bank. The PSW register flags RS1 and RS0 determine which register bank is enabled. The least significant three bits of the instruction opcode indicate which register is to be used. ACC, B, DPTR and CY, the Boolean processor accumulator, can also be addressed as registers. Direct Addressing Direct byte addressing specifies an on-chip RAM location (only low part) or a special function register. Direct addressing is the only method of accessing the special function registers. An additional byte is appended to the instruction opcode to provide the memory location address. The highest-order bit of this byte selects one of two groups of addresses: values between 0 and 127 (00H-7FH) access internal RAM locations, while values between 128 and 255 (80H-0FFH) access one of the special function registers. Semiconductor Group 16 SDA 20Cxx50 Register-lndirect Addressing Register-indirect addressing uses the contents of either R0 or R1 (in the selected register bank) as a pointer to locations in the 256 bytes of internal RAM. Note that the special function registers are not accessable by this method. Execution of PUSH and POP instructions also use register-indirect addressing. The stack pointer may reside anywhere in internal RAM. Immediate Addressing Immediate addressing allows constants to be part of the opcode instruction in program memory. An additional byte is appended to the instruction to hold the source variable. In the assembly language and instruction set, a number sign (#) precedes the value to be used, which may refer to a constant, an expression, or a symbolic name. Base-Register plus Index Register-lndirect Addressing Base-register plus index register-indirect addressing allows a byte to be accessed from program memory via an indirect move from the location whose address is the sum of a base register (DPTR or PC) and index register, ACC. This mode facilitates accessing to look-up-table resident in program memory. 2.2 Memory Organization The processor memory is organized into two address spaces. The memory spaces are: - Internal program memory space (8/16/24/32 Kbyte for SDA 20C08/16/24/32) - 256 byte (only 128 byte for SDA 20C08) plus 128 byte internal data memory address space - Additional internal data memory (128 byte for SDA 20C2450, 256 byte for SDA 20C3250). A 16-bit program counter provides the processor with its 64-Kbyte addressing capabilities. The program counter allows the user to execute calls and branches to any location within the program memory space. There are no instructions that permit program execution to move from the program memory space to any of the data memory space. 2.2.1 Internal Program ROM Certain locations in program memory are reserved for specific programs. Locations 0000 through 0002 are reserved for the initialization program. Following reset, the CPU always begins execution at location 0000. Locations 0003 through 0043 are reserved for the six interrupt-request service programs as indicated in the following table: Source External Interrupt 0 Timer 0 Overflow External Interrupt 1 or On-Screen Display Timer 1 Overflow Serial Interface Pulse Width Modulator or Multi Mode Timer Address 03 (03H) 11 (0BH) 19 (13H) 27 (1BH) 35 (23H) 43 (2BH) Semiconductor Group 17 SDA 20Cxx50 2.2.2 Internal Data RAM The internal data memory is divided into four blocks: the lower 128 byte of RAM, the upper 128 byte of RAM (not for SDA 20C0850), the 128-byte Special Function Register (SFR) area and for SDA 20C2450/20C3250 the 128/256 byte additional RAM (figure 3). Because the upper RAM area and the SFR area share the same address locations, they are accessed through different addressing modes. The internal data RAM address space is 0 to 255. Four banks of eight registers each occupy locations 0 through 31. Only one of these banks may be enabled at a time through a two-bit field in the PSW. In addition, 128-bit locations of the on-chip RAM are accessible through direct addressing. These bits reside in internal data RAM at byte locations 32 through 47, as shown in figure 4. The lower 128 bytes of internal data RAM can be accessed through direct or registerindirect addressing, the upper 128 bytes of internal data RAM through register-indirect addressing and the special function registers through direct addressing. The stack can be located anywhere in the internal data RAM address space. The stack depth is limited only by the available internal data RAM, thanks to an 8-bit reloadable stack pointer. The stack is used for storing the program counter during subroutine calls and may also be used for passing parameters. Any byte of internal data RAM or special function registers accessible through direct addressing can be pushed/popped. 2.2.3 Special Function Registers The special function register address space resides between addresses 128 and 255. All registers except the program counter and the four banks of eight working registers reside here. Memory mapping the special function registers allows them to be accessed as easily as the internal RAM. As such, they can be operated on by most instructions. A complete list of the special function registers is given in table 1. In addition, many bit locations within the special function register address space can be accessed using direct addressing. These direct addressable bits are located at byte addresses divisible by eight as shown in figure 5. Semiconductor Group 18 SDA 20Cxx50 Figure 3 Internal Data Memory Address Space Semiconductor Group 19 SDA 20Cxx50 RAM BYTE 256 (MSB) (LSB) 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 Bank 3 24 23 Bank 2 16 15 Bank 1 8 7 Bank 0 0 7F 77 6F 67 5F 57 4F 47 3F 37 2F 27 1F 17 0F 07 7E 76 6E 66 5E 56 4E 46 3E 36 2E 26 1E 16 0E 06 7D 75 6D 65 5D 55 4D 45 3D 35 2D 25 1D 15 0D 05 7C 74 6C 64 5C 54 4C 44 3C 34 2C 24 1C 14 0C 04 7B 73 6B 63 5B 53 4B 43 3B 33 2B 23 1B 13 0B 03 7A 72 6A 62 5A 52 4A 42 3A 32 2A 22 1A 12 0A 02 79 71 69 61 59 51 49 41 39 31 29 21 19 11 09 01 78 70 68 60 58 50 48 40 38 30 28 20 18 10 08 00 FFH 2FH 2EH 2DH 2CH 2BH 2AH 29H 28H 27H 26H 25H 24H 23H 22H 21H 20H 1FH 18H 17H 10H 0FH 08H 07H 00H Figure 4 Internal RAM-Bit Addresses Semiconductor Group 20 SDA 20Cxx50 Direct Byte Address (decimal) 248 240 232 224 216 208 200 192 184 176 168 152 144 136 128 P3.7 EA SM0 P1.7 TF1 P0.7 SM1 P1.6 TR1 P0.6 P3.6 A.7 1 CY S E7 A.6 HSY AC M1 E6 P7 B.7 P6 B.6 P5 Addressable SFR Bits P4 B.4 P3 B.3 P2 B.2 P1 B.1 P4.1 P0 B.0 P4.0 A.0 B P C0 E0 PX0 P3.0 EX0 RI P1.0 IT0 P0.0 PWCOMP7 B P4 ACC DSCR PSW PWMC PWME IP P3 IE SCON P1 TCON P0 B.5 A.5 VSY F0 M0 E5 PPW P3.5 EPW SM2 P1.5 TF0 P0.5 A.4 EMU* RS1 R E4 PS P3.4 ES REN P1.4 TR0 P0.4 A.3 PRE RS0 IR E3 PT1 P3.3 ET1 TB8 P1.3 IE1 P0.3 A.2 R OV C2 E2 PX1 P3.2 EX1 RB8 P1.2 IT1 P0.2 A.1 G F1 C1 E1 PT0 P3.1 ET0 TI P1.1 IE0 P0.1 * EMU bit is 0 for SDA 20Cxx50 and 1 for SDA 30C0050 Figure 5 Special Function Register Bit Addresses Semiconductor Group 21 SDA 20Cxx50 Table 1 Special Function Register Overview Special Function Register Description Symbolic Address Name Location (hex.) Address Location (dec.) Bit Initial Value Address after Reset MSB...LSB (hex.) (hex.) E7 - E0 F7 - F0 D7 - D0 - - - - 87 - 80 97 - 90 B7 - B0 E9 - E8 BF - B8 AF - A8 - - 8F - 88 - - - - 00 00 00 07 00 00 00 FF FF FF FF XX000000 (bin.) 0X000000 (bin.) 00 00 00 00 00 00 00 Arithmetic Registers Accumulator B Register Program Status Word Pointer Registers Stack Pointer Data Pointer (high byte) Data Pointer (low byte) Power Control Register I/O Port Registers Port 0 Port 1 Port 3 Port 4 ACC, A B PSW SP DPH DPL PCON P0 P1 P3 P4 E0 F0 D0 81 83 82 87 80 90 B0 E8 B8 A8 FA 89 88 8D 8C 8B 8A 224 240 208 129 131 130 135 128 144 176 232 184 168 250 137 136 141 140 139 138 Interrupt Control Registers Interrupt Priority Flags IP Interrupt Enable Flags IE Interrupt Flag Register IFR Timer 0/1 Registers Timer 0/1 Mode Register Timer 0/1 Control Register Timer 1 (high byte) Timer 0 (high byte) Timer 1 (low byte) Timer 0 (low byte) Multi-Mode Timer Registers *) Timer Status Register Timer Clear Register Counter Register (low byte) Counter Register (high byte) Reload Register (low byte) Reload Register (high byte) Capture Register (low byte) Capture Register (high byte) TMOD TCON TH1 TH0 TL1 TL0 WDMOD WDTC WDCL WDCH WDRL WDRH CAPL CAPH 86 97 84 85 8E 8F 91 92 134 135 132 133 142 143 145 146 - - - - - - - - 01 FF FF FF FF FF 00 00 X: undefined bit value *) not for SDA 20C0850 Semiconductor Group 22 SDA 20Cxx50 Special Function Register Overview (cont'd) Special Function Register Description Symbolic Name Address Location (hex.) Address Location (dec.) Bit Initial Value Address after Reset MSB...LSB (hex.) (hex.) 9F - 98 - 00 00 Serial Interface Serial Control Register Serial Interface Buffer Register Pulse Width Modulator Registers Control Register Enable Register PWM8-Counter Register Compare Register 0 Compare Register 1 Compare Register 2 Compare Register 3 Compare Register 4 Compare Register 5 Compare Register 6 Compare Register 7 On-Screen Display Registers Enable Register Vertical Position of Row 0 Vertical Position of Row 1 Vertical Position of Row 2 Vertical Position of Row 3 Vertical Position of Row 4 Vertical Position of Row 5 Status and Control Address Register Data Register Horizontal Position Color and Polarity Register Accumulator Extension Register SCON SBUF 98 99 152 153 PWMC PWME PWCOUNT PWCOMP0 PWCOMP1 PWCOMP2 PWCOMP3 PWCOMP4 PWCOMP5 PWCOMP6 PWCOMP7 C8 C0 F9 F1 F2 F3 F4 F5 F6 F7 F8 200 192 249 241 242 243 244 245 246 247 248 CF - C8 C7 - C0 - - - - - - - - FF - F8 80 00 00 FF FF FF FF FF FF FF FF DER DVR0 DVR1 DVR2 DVR3 DVR4 DVR5 DSCR DAR DDR DHR DCPR ACEXT D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC E1 209 210 211 212 213 214 215 216 217 218 219 220 225 - - - - - - - DF - D8 - - - - - 00 XX XX XX XX XX XX XX XX XX XX 00 XX X: undefined bit value 2.3 Interrupt System External events and the real-time on-chip peripherals require CPU service asynchronous to the execution of any particular section of code. To couple the asynchronous activities of these functions to normal program execution, a sophisticated multiple-source, two-priority-level, nested interrupt system is provided. Semiconductor Group 23 SDA 20Cxx50 2.3.1 Interrupt Sources The processor acknowledges interrupt requests from eight sources, which are mapped on six vectors. One vector for external interrupt 0, one vector for external interrupt 1 or OSD interrupt, two vectors for timer 0 and timer 1, one vector for the serial interface and one vector for the multi-mode timer and PWM interrupts. Each of the six vectors can be assigned to either of two priority levels and can independently be enabled or disabled. Additionally, all enabled interrupts may be globally enabled or disabled. Interrupts result in a transfer of control to a new program location. An interrupt vectors to a special location in program memory for its service program. The program servicing the request begins at this address. The starting address (interrupt vector) of the interrupt service program for each interrupt source is shown in the following table: Interrupt Source External Request 0 Internal Timer/Counter 0 External Request 1 or On-Screen Display Internal Timer/Counter 1 Serial Interface Pulse Width Modulator or Multi-Mode Timer Starting Address 03 11 19 27 35 43 (03H) (0BH) (13H) (1BH) (23H) (2BH) 2.3.2 Interrupt Control The information flags, which control the entire interrupt system, are stored in five special function registers: TCON IE IP IFR SCON Timer/Counter Control Register Interrupt Enable Register Interrupt Priority Register Interrupt Flag Register Serial Control Register 88H A8H B8H FAH 98H All these registers except for IFR contain direct addressable bits. The interrupt system is shown diagrammatically in figure 6. A source requests an interrupt by setting its associated interrupt request flag in the TCON, SCON or IFR- register, as detailed in the following table: Interrupt Source External Request 0 Internal Timer/Counter 0 External Request 1 or On-Screen Display Internal Timer/Counter 1 Serial Interface Receive Serial Interface Transmit Pulse Width Modulator or Multi-Mode Timer *) Request Flag IE0 TF0 IE1 TF1 RI TI IPWM IWDT Bit Location TCON.1 TCON.5 TCON.3 TCON.7 SCON.0 SCON.1 IFR.0 IFR.1 The timer 0 and timer 1 interrupts are generated by TF0 and TF1, which are set by a rollover in their respective timer/counter register, except for timer 0 in mode 3. *) not for SDA 20C0850 Semiconductor Group 24 SDA 20Cxx50 Figure 6 Interrupt System q q q q q q q Six interrupt vectors Each interrupt can be individually enabled/disabled Enabled interrupts can be globally enabled/disabled Each interrupt can be assigned to either of two priority levels Each interrupt vectors to a separate location in program memory Interrupt nesting to two levels External interrupt requests can be programmed to be level- or transition-activated Semiconductor Group 25 SDA 20Cxx50 The PWM/multi-mode timer interrupt is generated by the logical OR of IPWM and IWDT. To decide, which source (PWM or multi-mode timer) has requested the interrupt, the interrupt service routine located at address 02BH has to check the bits IPWM (IFR.0) and IWDT (IFR.1). These bits are usually set by hardware but they can also be set by software. If a PWM/multi-mode timer interrupt is generated, the flags IPWM and IWDT will not be cleared by hardware, they will have to be cleared by software.The interrupt request will be acknowledged, if its interrupt enable bit in the Interrupt Enable register (IE) is set, and will be serviced according to the selected priority level in the Interrupt Priority register (IP). Within the IE register there are seven addressable flags. Six flags enable/disable the six interrupt sources when set/cleared. Setting/clearing the seventh flag permits a global enable/disable of all enabled interrupt requests. MSB P5.3 P5.4 00H IPWM = 1 Interrupt request was generated by the PWM unit IWDT = 1 Interrupt request was generated by the multi-mode-timer Input Line P5.3 Input Line P5.4 Reserved - SFR Address: FAH IFR: Interrupt Flag Register - - - IWDT IPWM LSB Default after reset: IPWM IWDT *) P5.3 P5.4 IFR.2 ... IFR.5: - - Figure 7 Interrupt Flag Register IFR All the bits that generate interrupts can be set or cleared by software, with the same result as though they had been set or cleared by hardware. That is, interrupts can be generated or pending interrupt requests can be cancelled by software. *) not for SDA 20C0850 Semiconductor Group 26 SDA 20Cxx50 MSB EA - EPW 0X00 0000B SFR Address: A8H IE: Interrupt Enable Register ES ET1 EX1 ET0 LSB EX0 Default after reset: EA X: undefined bit value Enables or disables all interrupts. If EA = 0, no interrupt will be acknowledged. If EA = 1, each interrupt source is individually enabled or disabled by setting or clearing its enable bit. Reserved Enables or disables the interrupt from the pulse width modulation unit and from the multi-mode-timer. If EPW = 0, this interrupt is disabled. Enables or disables the serial interface interrupt. If ES = 0, the serial interface interrupt is disabled. Enables or disables the timer 1 overflow interrupt. If ET1 = 0, the timer 1 interrupt is disabled. Enables or disables external interrupt 1 or OSD interrupt. If EX1 = 0, external interrupt 1/OSD interrupt is disabled. Enables or disables the timer 0 overflow interrupt. If ET0 = 0, the timer 0 interrupt is disabled. Enables or disables external interrupt 0. If EX0 = 0, external interrupt 0 is disabled. IE.6 EPW ES ET1 EX1 ET0 EX0 Figure 8 Interrupt Enable Register IE Setting/clearing a bit in the IP register establishes its associated interrupt request as a high/low priority. If a low-priority level interrupt is being serviced, a high-priority level interrupt will interrupt it. However, an interrupt source cannot interrupt a service program of the same or higher priority level. Semiconductor Group 27 SDA 20Cxx50 MSB - - PPW XX00 0000 Reserved Reserved SFR Address: B8H IP: Interrupt Priority Register PS PT1 PX1 PT0 LSB PX0 Default after reset: IP.7 IP.6 PPW PS PT1 PX1 PT0 PX0 X: undefined bit value Defines the interrupt from the pulse width modulation unit or the multimode-timer. PPW = 1 programs it to the higher priority level. Defines the serial interface interrupt priority level. PS = 1 programs it to the higher priority level. Defines the timer 1 interrupt priority level. PT1 = 1 programs it to the higher priority level. Defines the external interrupt 1/OSD interrupt priority level. PX1 = 1 programs it to the higher priority level. Defines the timer 0 interrupt priority level. PT0 = 1 programs it to the higher priority level. Defines the external interrupt 0 priority level. PX0 = 1 programs it to the higher priority level. Figure 9 Interrupt Enable Register IP If two requests of different priority levels are received simultaneously, the request of higher priority level will be serviced. If requests of the same priority level are received simultaneously, an internal polling sequence determines which request is serviced. Thus within each priority level there is a second priority structure determined by the polling sequence, as follows: Source 1. 2. 3. 4. 5. 6. IE0 TF0 IE1/OSD TF1 RI/TI IPWM/IWDT Priority within Level (highest) (lowest) Note that the "priority within level" structure is only used to resolve simultaneous requests of the same priority level. 2.3.3 Interrupt Nesting The process whereby a high-level interrupt request interrupts a low-level interrupt service program is called nesting. In this case the address of the next instruction in the low-priority service program is pushed onto the stack, the stack pointer is incremented by two and processor control is transferred to the program memory location of the first instruction of the high-level service program. The last instruction of the high-priority interrupt service program must be a RETI instruction. This Semiconductor Group 28 SDA 20Cxx50 instruction clears the higher "priority-level-active" flip-flop. RETI also returns processor control to the next instruction of the low-level interrupt service program. Since the lower "priority-level-active" flipflop has remained set, high priority interrupts are reenabled while further low-priority interrupts remain disabled. 2.3.4 External Interrupts The external interrupt request inputs (INT0 and INT1) can be programmed for either transitionactivated or level-activated operation. Control of the external interrupts is provided by the four loworder bits of TCON as shown in figure 10. When IT0 and IT1 are set to one, interrupt requests on INT0 and INT1 are transition-activated (highto-low), else they are low-level activated. IE0 and IE1 are the interrupt request flags. These flags are set when their corresponding interrupt request inputs at INT0 and INT1, respectively, are low when sampled by the processor and the transition-activated scheme is selected by IT0 and IT1. MSB TF1 TR1 TF0 SFR Address: 88H TCON: Timer and Interrupt Control Register TR0 IE1 IT1 IE0 IT0 LSB Default after reset: TCON.4 - TCON.7 IE1 IT1 IE0 IT0 00H See chapter "General Purpose Timers/Counters" Interrupt 1 edge flag. Set by hardware when external interrupt edge detected. Cleared when interrupt processed. Interrupt 1 type control bit. Set/cleared by software to specify falling edge/low level triggered external interrupts. Interrupt 0 edge flag. Set by hardware when external interrupt edge detected. Cleared when interrupt processed. Interrupt 0 type control bit. Set/cleared by software to specify falling edge/low level triggered external interrupts. Figure 10 Function of Lower Nibble Bits in TCON - Transition-Activated Interrupts (IT0 = 1, IT1 = 1) The IE0, IE1 flags are set by a high-to-low transition at INT0, INT1, respectively; they are cleared during entering the corresponding interrupt service routine. For transition-activated operation, the input must remain low for more than twelve oscillator periods, but needs not to be synchronous with the oscillator. The upward transition of a transition-activated input may occur at any time after the twelve oscillator period latching time, but the input must remain high for twelve oscillator periods before reactivation. - Level-Activated Interrupts (IT = 0, IT1 = 0) The IE0, IE1 flags are set whenever INT0, INT1 are respectively sampled at low level. Sampling INT0, INT1 at high level clears IE0, IE1, respectively. Semiconductor Group 29 SDA 20Cxx50 For level-activated operation, if the input is low during the sampling that occurs fourteen oscillator periods before the end of the instruction in progress, an interrupt subroutine call is made. The levelactivated input needs to be low only during the sampling that occurs fourteen oscillator periods before the end of the instruction in progress and may remain low during the entire execution of the service program. However, the input must be deactivated before the service routine is completed to avoid invoking a second interrupt, or else another interrupt will be generated. 2.3.5 Interrupt Task Function The processor records the active priority level(s) by setting internal flip-flop(s). One of these nonaddressable flip-flops is set while a low-level interrupt is being serviced. The other flip-flop is set while the high-level interrupt is being serviced. The appropriate flip-flop is set when the processor transfers control to the service program. The flip-flop corresponding to the interrupt level being serviced is reset when the processor executes a RETl instruction. The sequence of events for an interrupt is: - A source provokes an interrupt by setting its associated interrupt request bit to let the processor know an interrupt condition has occurred. - The CPU's internal hardware latches the internal request in the tenth, twenty-second, thirtyfourth and forty-sixth oscillator period of the instruction in progress. - The interrupt request is conditioned by bits in the interrupt enable and interrupt priority register. - The processor acknowledges the interrupt by setting one of the two internal "priority-level active" flip-flops and performing a hardware subroutine call. This call pushes the PC (but not the PSW) onto the stack and, for most sources, clears the interrupt request flag. - The service program is executed. - Control is returned to the main program when the RETI instruction is executed. The RETI instruction also clears one of the internal "priority-level active" flip-flops. Most interrupt request flags (IE0, IE1, TF0 and TF1) are cleared when the processor transfers control to the first instruction of the interrupt service program. The RI, TI, IPWM and IWDT interrupt request flags are exceptions and must be cleared as part of the respective interrupt service program. This is also the case for IE0, IE1, if INT0, INT1 are level activated. 2.3.6 Response Time The highest-priority interrupt request gets serviced at the end of the instruction in progress unless the request is made in the last fourteen oscillator periods of the instruction in progress. Under this circumstance, the next instruction will also execute before the interrupt's subroutine call is made. If a request is active and conditions are right for it to be acknowledged, a hardware subroutine call to the requested service routine will be the next instruction to be executed. The call itself takes two cycles. Thus, a minimum of three complete machine cycles elapse between activation of an external interrupt request and the beginning of execution of the first instruction of the service routine. lf the instruction in progress is not in its final cycle, the additional wait time cannot be more than 3 cycles, since the longest instructions (MUL and DIV) are only 4 cycles long, and if the instruction in progress is RETI or an access to IE or IP, the additional wait time cannot be more than 5 cycles (a maximum of one more cycle to complete the instruction in progress, plus 4 cycles to Semiconductor Group 30 SDA 20Cxx50 complete the next instruction if the instruction is MUL or DIV). Thus, in a single-interrupt system, the response time is always more than 3 cycles and less than 8 cycles (approximately 7 s at 12-MHz operation). Examples of the best and worst case conditions are illustrated in the following table. Instruction Time (Oscillator Periods) Best Case External interrupt generated immediately before (best) / after (worst) the pin is sampled (Time until end of bus cycle) Current or next instruction finishes in 12 oscillator periods Next instruction is MUL or DIV Internal latency for hardware subroutine call 2+ Worst Case 2- 12 12 don't care 24 38 48 24 86 If an interrupt of equal or higher priority level is already in progress, the additional wait time obviously depends on the nature of the other interrupt's service routine. 2.4 Processor Reset and Initialization Processor initialization is accomplished with activation of the RST pin, which is the input to a Schmitt Trigger. To reset the processor, this pin should be held low for at least four s, while the oscillator is running. Upon powering up, RST should be held low for at least 10 ms after the power supply stabilizes to allow the oscillator to stabilize. Normal operation commences with the instruction at absolute location 0000H (program memory locations 0000H through 0002H are reserved for the initialization routine of the microcomputer). Table 1 (in chapter "Memory Organization") shows the values to be read after the end of the initialization sequence. After the processor is reset, all port latches are written with ones. Outputs are undefined until the reset period is complete. Power-Down Operations The controller provides two modes in which power consumption can be significantly reduced. - Idle mode. The CPU is gated off from the oscillator. All peripherals are still provided with the clock and are able to work. - Power-down mode. Operation of the controller is turned off. This mode is used to save the contents of internal RAM with a very low standby current. Both modes are entered by software. Special function register PCON is used to enter one of these modes. Semiconductor Group 31 SDA 20Cxx50 The idle mode can be terminated by activation of any enabled interrupt (or a hardware reset). The CPU operation is resumed, the interrupt will be serviced and the next instruction to be executed after RETI instruction will be the one following the instruction that set the bit IDLS. The port state and the contents of SFRs are held during idle mode. The only exit from power-down mode is a hardware reset. The reset will redefine all SFRs, but will not change the contents of internal RAM. MSB SMOD PDS IDLS 000xxx00 Power-down start bit. The instruction that sets the PDS flag is the last instruction before entering the power-down mode. IDLE start bit. The instruction that sets the PDS flag is the last instruction before entering the idle mode. Power-down enable bit. When set, starting the power-down mode is enabled. Idle enable bit. When set, starting the idle mode is enabled. Baud rate control for serial interface; if set, the baud rate is doubled. SFR Address: 87H PCON: Power Control Register - - - PDE IDLE LSB Default after reset: PDS IDLS PDE IDLE SMOD 2.5 Ports and I/O Pins There are 26 I/O pins configured as three 8-bit ports and one 2-bit port. Each pin can be individually and independently programmed as input or output and each can be configured dynamically (i.e., on-the-fly) under software control. Moreover, two input-only lines are provided. An instruction that uses a port's bit/byte as a source operand reads a value that is the logical AND of the last value written to the bit/byte and the polarity being applied to the pin/pins by an external device (this assumes that none of the processor's electrical specifications are being violated). An instruction that reads a bit/byte, operates on the content, and writes the result back to the bit/byte, reads the last value written to the bit/byte instead of the logic level at the pin/pins. Pins comprising a single port can be made a mixed collection of inputs and outputs by writing a "one" to each pin that is to be an input. Each time an instruction uses a port as the destination, the operation must write "ones" to those bits that correspond to the input pins. An input to a port pin needs not to be synchronized to the oscillator. All the port latches have "ones" written to them by the reset function. If a "zero" is subsequently written to a port latch, it can be reconfigured as an input by writing a "one" to it. The instructions that perform a read of, operation on, and write to a port's bit/byte are INC, DEC, CPL, JBC, SETB, CLR, MOV P.X, CJNE, DJNZ, ANL, ORL, and XRL. The source read by these operations is the last value that was written to the port, without regard to the levels being applied at the pins. This insures that bits written to a "one" (for use as inputs) are not inadvertently cleared. Semiconductor Group 32 SDA 20Cxx50 Port 0 has an open-drain output. Writing a "one" to the bit latch leaves the output transistor off, so the pin floats (figure 11). In that condition it can be used as a high impedance input. Port 0 is considered "true bidirectional", because when configured as an input it floats. Port 4.0 and 4.1 have also an open-drain configuration (see figure 12) and have to be pulled up by external resistors. Ports 1 and 3 have "quasi-bidirectional" output drivers which comprise an internal pullup resistor of 10 k to 40 k as shown in figure 13. When configured as inputs they pull high and will source current when externally pulled low. In ports 1 and 3 the output drivers provide source current for two oscillator periods if, and only if, software updates the bit in the output latch from a "zero" to an "one". Sourcing current only on "zero to one" transition prevents a pin programmed as an input, from sourcing current into the external device that is driving the input pin. The port output drivers can sink or source the following TTL loads: Port 0 1 3 4 LS TTL load 8 (only sink) 4 4 4 (only sink) Secondary functions can be selected individually and independently for the pins of port 1 and 3. Further information on port 1's secondary functions is given in chapter "Pulse Width Modulation Unit". P3 generates the secondary control signals automatically as long as the pin corresponding to the appropriate signal is programmed as an input, i.e. if the corresponding bit latch in the P3 special function register contains a "one". The following alternate functions can be selected when using the corresponding P3 pins: P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 CAP INT0 INT1 T0 T1 RXD TXD (multi-mode timer capture input) (external Interrupt 0) (external Interrupt 1) (timer/counter 0 external input) (timer/counter 1 external input) (serial interface receive line) (serial interface transmit line) Two read-only input lines P5.3 and P5.4 are available, the input status is read through special function register bits IFR.7 and IFR.6 (not bit-addressable). Semiconductor Group 33 SDA 20Cxx50 Read Modify-Write Feature "Read-modify-write" commands are instructions that read a value, possibly change it, and then rewrite it to the latch. When the destination operand is a port or a port bit, these instructions read the latch rather than the pin. The read-modify-write instructions are listed in table 2. The read-modify-write instructions are directed to the latch rather than the pin in order to avoid a possible misinterpretation of the voltage level at the pin. For example, a port bit might be used to drive the base of a transistor. When a "one" is written to the bit, the transistor is turned on. If the CPU then reads the same port bit at the pin rather than the latch, it will read the base voltage of the transistor and interpret it as a 0. Reading the latch rather than the pin will return the correct value of "one". Table 2 Read-Modify-Write Instructions Mnemonic ANL ORL XRL JBC CPL INC DEC DJNZ MOV PX.Y, C* CLR PX.Y* SET PX.Y* Description logical AND logical OR logical EX-OR jump if bit = 1 and clear bit complement bit increment decrement decrement and jump if not zero move carry bit to bit Y of port X clear bit Y of port X set bit Y of port X Example ANL P1, A ORL P2, A XRL P3, A JBC P1.1, LABEL CPL P3.0 INC P1 DEC P1 DJNZ P3, LABEL MOV P1.7, C CLR P2.6 SET P3.5 *) The instruction reads the port byte (all 8 bits), modifies the addressed bit, then writes the new byte back to the latch. Semiconductor Group 34 SDA 20Cxx50 Figure 11 Port 0: Bidirectional Open Drain Bus Configuration Semiconductor Group 35 SDA 20Cxx50 Figure 12 Port 4: Open Drain Configuration Semiconductor Group 36 SDA 20Cxx50 Figure 13 Ports 1 and 3: "Quasi-Bidirectional" Port Structure Semiconductor Group 37 SDA 20Cxx50 2.6 General Purpose Timers/Counters Two independent general purpose 16-bit timers/ counters are integrated for use in measuring time intervals, measuring pulse widths, counting events, and causing periodic (repetitive) interrupts. Either can be configured to operate as timer or event counter. In the "timer" function, the registers TLx and/or THx (x = 0, 1) are incremented every machine cycle. Thus, one can think of it as counting machine cycles. Since a machine cycle consists of 12 oscillator periods, the count rate is 1/12 of the oscillator frequency. In the "counter" function, the registers TLx and/or THx (x = 0, 1) are incremented in response to a 1-to-0 transition at its corresponding external input pin, T0 or T1. In this function, the external input is sampled during every machine cycle. When the samples show a high in one cycle and a low in the next cycle, the count is incremented. The new count value appears in the register during the cycle following the one in which the transition was detected. Since it takes 2 machine cycles (24 oscillator periods) to recognize a 1-to-0 transition, the maximum count rate is 1/24 of the oscillator frequency. There are no restrictions on the duty cycle of the external input signal, but to ensure that a given level is sampled at least once before it changes, it should be held for at least one full machine cycle. Timer/Counter 0: Mode Selection Timer/counter 0 can be configured in one of four operating modes, which are selected by bit-pairs (M 1, M0) in TMOD register (figure 14). - Mode 0 Putting timer/counter 0 into mode 0 makes it look like an 8048 timer, which is an 8-bit counter with a divide-by-32 prescaler. Figure 16 shows the mode 0 operation as it applies to timer 0. In this mode, the timer register is configured as a 13-bit register. As the count rolls over from all 1s to all 0s, it sets the timer interrupt flag TF0. The counted input is enabled to the Timer when TR0 = 1 and either GATE = 0 or INT0 = 1. (Setting GATE = 1 allows the Timer to be controlled by external input INT0, to facilitate pulse width measurements.) TR0 is a control bit in the special function register TCON (figure 15). GATE is contained in register TMOD (figure 14). The 13-bit register consists of all 8 bits of TH0 and the lower 5 bits of TL0. The upper 3 bits of TL0 are indeterminate and should be ignored. Setting the run flag (TR0) does not clear the registers. - Mode 1 Mode 1 is the same as mode 0, except that the timer/counter 0 register is being run with all 16 bits. - Mode 2 Mode 2 configures the timer/counter 0 register as an 8-bit counter (TL0) with automatic reload, as shown in (figure 17). Overflow from TL0 not only sets TF0, but also reloads TL0 with the contents of TH0, which is preset by software. The reload leaves TH0 unchanged. - Mode 3 Timer/counter 0 in mode 3 establishes TL0 and TH0 as two separate counters. The logic for mode 3 on timer 0 is shown in (figure 18). TL0 uses the timer 0 control bits: C/T, GATE, TR0, INT0 and TF0. TH0 is locked into a timer function (counting machine cycles) and takes over the use of TR1 and TF1 from timer 1. Thus, TH0 now controls the "Timer 1" interrupt. Semiconductor Group 38 SDA 20Cxx50 Mode 3 is provided for applications requiring an extra 8-bit timer or counter. With timer 0 in mode 3, the processor can operate as if it has three timers/counters. When timer 0 is in mode 3, timer 1 can be turned on and off by switching it out of and into its own mode 3, or can still be used in any application not requiring an interrupt. Timer/Counter 1: Mode Selection Timer/counter 1 can also be configured in one of four modes, which are selected by its own bitpairs (M 1, M0) in TM0D register. The serial port receives a pulse each time that timer/counter 1 overflows. This pulse rate is divided to generate the transmission rate of the serial port. Modes 0 and 1 are the same as for counter 0. - Mode 2 The "reload" mode is reserved to determine the frequency of the serial clock signal (not implemented). - Mode 3 When counter 1's mode is reprogrammed to mode 3 (from mode 0, 1 or 2), it disables the increment counter. This mode is provided as an alternative to using the TR1 bit (in TCON-register) to start and stop timer/counter 1. Configuring the Timer/Counter Input The use of the timer/counter is determined by two 8-bit registers, TMOD (timer mode) and TCON (timer control), as shown in figure 14 and figure 15. The input to the counter circuitry is from an external reference (for use as a counter), or from the on-chip oscillator (for use as a timer), depending on whether TMOD's C/T bit is set or cleared, respectively. When used as a time base, the on-chip oscillator frequency is divided by twelve (12) before being used as the counter input. When TMOD's gate bit is set (1), the external reference input (T1, T0) or the oscillator input is gated to the counter conditional upon a second external input (INT0), (INT1) being high. When the gate bit is zero (0), the external reference, or oscillator input, is unconditionally enabled. In either case, the normal interrupt function of INT0 and INT1 is not affected by the counter's operation. If enabled, an interrupt will occur when the input at INT0 or INT1 is low. The counters are enabled for incrementing when TCON's TR1- and TR0 bits are set. When the counters overflow, the TF1-and TF0 bits in TCON get set, and interrupt requests are generated. The counter circuitry counts up to all 1's and then overflows to either 0's or the reload value. Upon overflow, TF1 or TF0 is set. When an instruction changes the timer's mode or alters its control bits, the actual change occurs at the end of the instruction's execution. The T1 and T0 inputs are sampled near the falling-edge of ALE in the tenth, twenty-second, thirtyfourth and forty-sixth oscillator periods of the instruction-in-progress. Thus, an external reference's high and low times must each be a minimum of twelve oscillator periods in duration. There is a twelve oscillator period delay from the time when a toggled input (transition from high to low) is sampled to the time when the counter is incremented. Semiconductor Group 39 SDA 20Cxx50 MSB SFR Address: 89H TMOD: Timer 0/1 Mode Register LSB GATE C/T M1 M0 GATE C/T M1 M0 Timer 1 GATE Timer 0 Gating control when set. Time/counter "x" is enabled only while "INTx" pin is high and "TRx" control pin is set. When cleared, Timer "x" is enabled, whenever "TRx" control bit is set. Timer or counter selector. Cleared for timer operation (input from internal system clock). Set for counter operation (input from "Tx" input pin). C/T M0 M1 0 0 1 1 0 1 0 1 Operating Mode SAB 8048 timer: "TLx" serves as five-bit prescaler. 16-bit timer/counter: "THx" and "TLx" are cascaded, there is no prescaler. 8-bit auto-reload timer/counter: "THx" holds a value which is to be reloaded into "TLx" each time it overflows. (Timer 0) TL0 is an eight-bit timer/counter controlled by the standard timer 0 control bits; TH0 is an eight-bit timer only controlled by timer 1 control bits. (Timer 1) Timer/counter 1 is stopped. Default after reset: 00H Figure 14 Timer/Counter Mode Register Semiconductor Group 40 SDA 20Cxx50 MSB SFR Address: 88H TCON: Timer 0/1 Control Register LSB TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 TF1 Timer 1 overflow flag. Set by hardware on timer/counter owerflow. Cleared by hardware when processor vectors to interrupt routine. Timer 1 run control bit. Set/cleared by software to turn timer/counter ON/OFF. Timer 0 overflow flag. Set by hardware on timer/counter owerflow. Cleared by hardware when processor vectors to interrupt routine. Timer 0 run control bit. Set/cleared by software to turn timer/counter ON/OFF. Interrupt 1 edge flag. Set by hardware when external interrupt edge detected. Cleared when interrupt processed. Interrupt 1 type control bit. Set/cleared by software to specify falling edge/low level triggered external interrupts. Interrupt 0 edge flag. Set by hardware when external interrupt edge detected. Cleared when interrupt processed. Interrupt 0 type control bit. Set/cleared by software to specify falling edge/low level triggered external interrupts. TR1 TF0 TR0 IE 1 IT1 IE0 IT0 Default after reset: 00H Figure 15 Timer/Counter Control Register Semiconductor Group 41 SDA 20Cxx50 Figure 16 Timer/Counter 0 Mode 0: 13-Bit Counter Figure 17 Timer/Counter 0 Mode 2: 8-Bit Auto-Reload Semiconductor Group 42 SDA 20Cxx50 Figure 18 Timer/Counter 0 Mode 3: Two 8-Bit Counters Semiconductor Group 43 SDA 20Cxx50 2.7 Multi-Mode Timer (not for SDA C0850) The multi-mode timer is a 16-bit reloadable counter with a two-bit prescaler, which provides several functions. One of five different modes may be selected: - Watchdog Mode for recovery from software or hardware upset - Timer Interrupt Mode to generate an interrupt request at counter underflow - Timer Polling Mode provides a 16-bit downward counter - Capture Mode 0 (no interrupt) to determine time difference between subsequent 1-to-0 transitions at pin P3.1 /CAP - Capture Mode 1 (with interrupt) to determine time difference between subsequent 1-to-0 transitions at pin P3.1/CAP and to generate an interrupt at every capture event or timer overflow There is a variable prescaler (factor 1, 2 or 4) integrated, which enables the counter to be strobed by a timer clock that is 1/48,1/24 or 1/12 of the external oscillator frequency. Independent of the chosen mode, the timer can be started, but cannot be stopped by software means. Only a clearing operation, which reloads and restarts the timer, can be done. To ensure reliability (specially in watchdog mode), the clearing operation (i.e. reloading the counter) must be done by two subsequent MOV operations to different special function registers. In watchdog, interrupt and polling mode, the timer decrements every timer clock cycle. The default reload value is 0FFFFH. The reload value might be changed by writing to the reload registers and is taken over by the counter, when a starting or clearing operation is performed. In capture mode, the timer increments and the default start value is 0000H. The cycle time of the multi-mode timer depends on the clock frequency, the prescaler factor and the reload value. It can be computed as: TCYCLE = (48/fOSC) x (WDRH x 256 + WDRL + 1) / PRESC (PRESC = 1, 2 or 4) Using an oscillator frequency of 12 MHz, a maximum timer cycle of 262.2 ms can be selected. The prescale factor selection will be described in detail in the following. Semiconductor Group 44 SDA 20Cxx50 Figure 19 Block Diagram of the Multi-Mode Timer Semiconductor Group 45 SDA 20Cxx50 Special Function Registers MSB SFR Address: 86H WDMOD: MMT Status Register WDTZ PRS1 PRS0 M2 M1 M0 WDTS SWDT LSB SWDT Start Multi-Mode Timer. Setting SWDT = 1 will start the timer. This bit will be reset automatically; setting SWDT = 0 will not stop the timer! SWDT is a write-only bit. A read operation will always show a 1. Multi-Mode Timer Status WDTS = 1 flags that the timer has been started. This bit position can not be written to. The reset routine has to check this flag to differentiate between external and internal reset. This flag is not affected by an internal reset: WDTS = 1. External reset changes the flag: WDTS = 0. Timer Mode Selection Timer Mode Watchdog Mode Timer Interrupt Mode Timer Polling Mode Capture Mode 0 Capture Mode 1 Prescaler Selection Timer Input WDTS M0/1/2 M2 M1 M0 0 0 0 1 1 0 0 1 1 0 0 1 1 1 1 PRS0/1 PRS1 PRS0 0 0 1 WDTZ 0 1 X fosc/48 fosc/24 fosc/12 MMT Zero Flag. WDTZ is a read-only bit and indicates that the timer reached zero since the last read or write access to register WDTS. With every read or write access to register WDMOD the WDTZ flag is cleared automatically. Note: When using watchdog mode, M0, M1 and M2 have to be set simultaneously with starting the timer and can not be altered afterwards! Default after reset: 01H Semiconductor Group 46 SDA 20Cxx50 MSB SFR Address: 97H WDTC: MMT Clear Register LSB -- CWDT -- -- -- -- -- -- CWDT Clear Multi-Mode Timer To clear the timer, bit CWDT has to be set to 1 immediately before setting SWDT. Like SWDT, CWDT will be cleared automatically. FFH Default after reset: Multi-Mode Timer Counter Register (WDCL, WDCH) The low and the high byte of the 16-bit counter can be examined using the registers WDCL and WDCH. Only read access is possible. Address Location Default Value WDCL, WDCH: 84H, 85H WDCL, WDCH: FFH, FFH Multi-Mode Timer Reload Register (WDRL, WDRH) Using WDRL and WDRH, a 16-bit reload value may be written into the multi-mode timer reload register. Address Location Default Value WDRL, WDRH: 8EH, 8FH WDRL, WDRH: FFH, FFH After starting the timer in watchdog mode, registers WDRL and WDRH can not be altered any more. Multi-Mode Timer Capture Registers (CAPL, CAPH) The 16-bit capture value will be stored in the two capture registers. These registers can be read from or written to. Address Location Default Value CAPL, CAPH: CAPL, CAPH: 91H, 92H 00H, 00H Semiconductor Group 47 SDA 20Cxx50 Timer Modes The five different timer modes are selected by the three control bits M0, M1 and M2 in status register WDMOD. Except for watchdog mode, modes can be changed by switching the control bits. Only the described mode selections may be chosen. Other combinations of the mode control bits must not be used. Watchdog Mode In watchdog mode, the multi-mode timer serves for recovering the processor from software or hardware upset. The timer can be started and cleared (which means reloaded) by software but it cannot be stopped. If the timer is once started and the software fails to clear it at least every timer cycle, a counter underflow will cause an internal reset. The timer cycle is determined by the reload value, the prescaler and fOSC. The default reload value is FFFFH (the timer works decrementing). If a reload value different from FFFFH is to be used, the reload registers have to be written before entering watchdog mode; WDRL and WDRH will be set to a read-only state after the timer is started. The reload values are taken over to the timer at start time and with every clearing operation. In case of a reset, the reset routine can examine the reset cause (external of internal) by checking bit WDTS (WDMOD.1). Internal reset released by the multi-mode timer does not affect the registers WDMOD, WDRL and WDRH. Bit WDTS in register WDMOD is set and bit WDTZ in register WDMOD is left undefined. The counter starts again from FFFFH. So the reset routine will have time to run the application specific initialization. An external reset will clear and stop the counter; registers WDRL, WDRH and WDMOD will be set to their default values and so bit WDTS in register WDMOD will be cleared. Watchdog mode is entered by setting WDMOD as described in the following PRS1 0 0 1 PRS0 0 1 0 Timer Clock WDMOD Value 01H 21H 41H fosc/48 fosc/24 fosc/12 Figure 20 shows a flow chart of a watchdog application. Semiconductor Group 48 SDA 20Cxx50 Timer Interrupt Mode The interrupt mode configures the multi-mode timer as an additional interrupt source. If the interrupt is enabled (bit EPW and bit EA in register IE must be set), an interrupt request will be generated by every timer underflow. The interrupt service routine starting at location 02BH will have to check the interrupt flag register IFR at SFR location 0FAH, whether the interrupt was initiated by the multi-mode timer or the PWM unit. If the multi-mode timer caused the interrupt, bit IFR.1 will be set. For detailed information about interrupt handling see chapter "Interrupt System". The timer itself shows the following features: - the timer starts at the reload value - it works decrementing - at underflow an interrupt is requested and the timer simultaneously restarts at the reload value - it is possible to modify the reload register while the timer is working - the clearing operation (restart with reload values) can be performed Timer interrupt mode is selected by setting WDMOD to one of the following values: PRS1 0 0 1 Polling Mode Using polling mode, neither reset nor interrupt are initiated when the timer reaches zero.The user program has to read the counter status and act accordingly. In polling mode the timer shows the following features: - the timer starts at the reload value - at underflow the timer restarts at the reload value - it is possible to modify the reload register while the timer is working - the clearing operation (restart with the reload value) can be performed Polling mode is started with one of the following values written to WDMOD: PRS1 0 0 1 PRS0 0 1 0 Timer Clock WDMOD Value 0DH 2DH 4DH PRS0 0 1 0 Timer Clock WDMOD Value 05H 25H 45H fosc/48 fosc/24 fosc/12 fosc/48 fosc/24 fosc/12 Semiconductor Group 49 SDA 20Cxx50 Figure 20 Watchdog Mode Semiconductor Group 50 SDA 20Cxx50 Figure 21 Timer Interrupt Mode (Main Program) Semiconductor Group 51 SDA 20Cxx50 Figure 22 Timer Interrupt (Service Routine) Semiconductor Group 52 SDA 20Cxx50 Figure 23 Timer Polling Mode Semiconductor Group 53 SDA 20Cxx50 Capture Mode 0 In capture mode 0, the time difference between two subsequent falling edges at the capture input pin (P3.1/CAP) can be determined. The first falling edge after enabling capture mode and starting the counter resets the counter to the start value (e.g. 0000H). The second and following edges will latch the counter value into the 16-bit capture register (CAPL, CAPH) and will restart the counter again (see figure 24). Capture mode can be terminated by changing mode or by an external reset. In capture mode, the default start value might be changed; the counter will start from this value at the next 1-to-0 transition. For this purpose, the complemented start value has to be written into reload registers WDRL and WDRH. The default start value is 0000H (WDRL, WDRH = FFH). When capture mode is terminated, the last capture value will remain in CAPL and CAPH registers. The time between two subsequent falling edges at P3.1/CAP is to be computed as: TC = (256 x CAPH + CAPL + 1) x PRESC x 12 (PRESC = 1,2 or 4) fOSC Capture mode 0 is entered by setting WDMOD as described in the following: PRS1 0 0 1 PRS0 0 1 0 Timer Clock WDMOD Value 1DH 3DH 5DH fosc/48 fosc/24 fosc/12 A flow chart of capture mode 0 is shown in figure 25. If capture mode is not selected, the two capture registers can be used as additional scratch registers without disturbing any other multi-mode timer function. Capture Mode 1 In addition to capture mode 0, every capture event or timer overflow causes a branch to the interrupt service routine at location 2BH, if bits EPW and EA in register IE are set. Using control bit WDTZ in register WDMOD, the interrupt routine will be able to distinguish between these two cases: WDTZ = 0 after interrupt: capture event WDTZ = 1 after interrupt: timer overflow WDTZ is to be cleared after starting capture mode by reading control register WDMOD once. To start capture mode 1, WDMOD is to be set as follows: PRS1 0 0 1 PRS0 0 1 0 Timer Clock WDMOD Value 15H 35H 55H fosc/48 fosc/24 fosc/12 A flow chart of capture mode 1 is shown in figure 26. Semiconductor Group 54 SDA 20Cxx50 Figure 24 Capture Mode Timing Diagram Semiconductor Group 55 SDA 20Cxx50 Figure 25 Capture Mode 0 Semiconductor Group 56 SDA 20Cxx50 Figure 26 Capture Mode 1 Semiconductor Group 57 SDA 20Cxx50 Figure 27 Capture Mode 1 (Interrupt Routine) Semiconductor Group 58 SDA 20Cxx50 2.8 Pulse Width Modulation Unit The PWM unit provides eight independent digital to analog conversion channels, with helpful time resolution flexibility. Controlled via special function registers, each channel can be enabled individually. Due to the modulator's flexibility the output frequency can be switched to 23.4 kHz, 46.9 kHz and 93.8 kHz by reducing time resolution (fOSC = 12 MHz). This is done by decreasing the timer width from 8 to 7 or 6 bits. General Considerations The PWM output channels are placed as alternate functions to the eight lines of port 1 (P1.0...P1.7). Each PWM channel can be individually switched between PWM function and port function. The PWM unit is controlled by the special function register PWMC located at address 0C8H. This register determines the counter's resolution (6, 7 or 8 bit) and starts or stops the counter. A counter status bit can be read and an interrupt enable flag can be set. Except for the status bit, read and write accesses are possible for this register. The PWMC register's lowest 3 bits are not employed and can be used as extra software flags (C0, C1, C2). The eight 8-bit compare registers PWCOMP0 - PWCOMP7 located at SFR addresses 0F1H - 0F8H contain the modulation ratios of the output signals which are related to the maximum defined by the counter's resolution. These compare registers are double buffered and a new compare value will only be taken into the main register, if the PWM timer is stopped or after the next timer overflow. To avoid overwriting the desired compare value, the counter status bit should be checked before a new write operation to a compare register is done. The PWM timer register located at SFR address 0F9H contains the actual value of the PWM counter and can only be read by the CPU. Every compare register, which is not employed for the PWM output can be used as an additional register. This is not allowed for register PWME. If the PWM function is not activated, the PWM timer is available for any other timing purpose. PWM Control Register PWMC MSB SFR Address: C8H PWMC: PWM Control Register S M1 M0 R IR C2 C1 C0 LSB Default after reset: 80H Semiconductor Group 59 SDA 20Cxx50 Function of the control bits: R = = M1, M0 C0, C1, C2 M1 0 0 1 S 0 1 The PWM timer is stopped and reset to 00H. All output latches (OL0 ... OL7) are set to 1. The PWM timer is set to RUN. At timer overflow, all output latches OL0...OL7 are set to 1. If the timer value meets the compare value of channel i, OLi is reset to 0. Control the output frequency and resolution of the PWM unit. General purpose software flags. M0 0 1 0 Output Frequency Resolution 8 bit 7 bit 6 bit fosc/2 x 256 fosc/2 x 128 fosc/2 x 64 Shows the actual state of the PWM timer. S is set by PWM timer overflow and has to be reset by software. This bit may be used to control whether a value selected for a compare channel was already written into the compare latch by a PWM timer overflow. IR = = 0 1 A PWM interrupt will not be requested. At every timer overflow bit IPWM in register IFR will be set to "one". This may initiate an interrupt request, if bit IE.5 in the interrupt enable register IE is set. PWM Enable Register PWME MSB SFR Address: C0H PWME: PWM Enable Register E7 E6 E5 E4 E3 E2 E1 E0 LSB Default after reset: 00H Ei = 0 The corresponding PWM channel is disabled. P1.i functions as normal bidirectional l/O port. The corresponding PWM channel is enabled. P1.i is automatically set to logic 1 and is connected to the output latch of the corresponding PWM channel (OLi). (i = 0 ... 7) =1 Semiconductor Group 60 SDA 20Cxx50 PWM Compare Registers PWCOMPx Each of the eight compare channels consists of - an 8-bit register with read and write access from the CPU. The SFR addresses are: PWCOMP 0: 0F1H PWCOMP 1: 0F2H PWCOMP 2: 0F3H PWCOMP 3: 0F4H PWCOMP 4: 0F5H PWCOMP 5: 0F6H PWCOMP 6: 0F7H PWCOMP 7: 0F8H After reset, the register contents are 0FFH. - an 8-bit compare latch, which is loaded with the value in the 8-bit Register, if the PWM timer overflows or stops. - a comparator, which compares the value of the compare latch with the timer value. If (M1, MO) (0,0), only the 7 (or the 6) least significant bits will be compared. - a one bit output latch, which is set on PWM timer overflow or stopped and reset on the compare event. The output latch controls the corresponding port pin, when the channel is enabled. RESET sets the output latch to 1. PWM Timer Register PWCOUNT (Address 0F9H, Reset value 00H) An 8-bit upwards counting binary counter (with an input frequency of fOSC/2) is provided as PWM timer. The counter registers can be read by software at SFR address 0F9H, but cannot be written to. If in PWMC register R = 0, the PWM timer will be held at 00H, i. e. at the reset value. If R = 1, the PWM timer will increment six times every CPU instruction cycle. M1 and M0 (in PWMC register) control the value, from which the PWM timer overflows to 00H: M1 0 0 1 M0 0 1 0 Overflow Value 0FFH (= 255) 07FH (= 127) 03FH (= 63) Semiconductor Group 61 SDA 20Cxx50 Figure 28 Block Diagram of Pulse Width Modulation Unit Semiconductor Group 62 SDA 20Cxx50 Figure 29 Block Diagram of One Pulse Width Modulation Channel (e.g. PWM0) Semiconductor Group 63 SDA 20Cxx50 2.9 On-Screen Display The OSD circuit generates video signals to display text or graphic symbols together with a video picture. The sandcastle signal (SC) is used to synchronize the circuit, which generates R-, G-, Band BLANK signals to be mixed with an incoming RGB video signal. Internal sync signals HS and VS are derived from SC. The dot clock is generated by an internal LC oscillator with external reference elements and synchronized by the rising edge of internal signal HS. Each of the six rows of text holds up to 18 characters and may be positioned and enabled individually. Using the OSD interrupt function, even more than six lines can be used. Boxed or non-boxed display mode and one of two text sizes may be selected for each row. One of eight background colors may be chosen globally and, additionally, full screen blanking is possible. In non-boxed mode, a colored frame may be activated to increase character readability. A set of 96 characters, each defined by a 12 x 16 pixel matrix, is contained in a mask-programmable character ROM in the SDA 20Cxx50 devices and may be user-defined according to the specific application. The SDA 30C0050 comprises an internal pixel RAM for emulation purpose. The OSD circuitry is designed to be used in a color TV application, where each character may be displayed in any of eight colors. Principle diagrams of the OSD circuit are shown in figure 30 to 32. Semiconductor Group 64 SDA 20Cxx50 Figure 30 Display of Six Rows of Text on a Video Screen (without using interrupt) Semiconductor Group 65 SDA 20Cxx50 Figure 31 Single and Double Size Character Display with Programmable Frame Mode Semiconductor Group 66 SDA 20Cxx50 Figure 32 OSD Block Diagram OSD Features and Programming This chapter gives a general description of the on-screen display circuit and the various programming features. Detailed informations for programming the device are found in chapter "OSD Special Function Registers". Dot Clock The OSD circuit contains an LC oscillator circuit for generation of a synchronized dot clock. The oscillator is synchronized by the active edge of internal signal HS, internal counters are reset with the falling edge of HS. HS is internally decoded from the synchronization input signal SC. The dot clock frequency defines the pixel width on the screen (figure 33). Semiconductor Group 67 SDA 20Cxx50 Figure 33 Pixel Width Definition The dot clock frequency is determined by the external reference elements. Horizontal Positioning The horizontal start position is common to all lines of text and is independent of the selected text size. The time between the rising edge of SC and the first pixel to be displayed may be calculated as follows: tHO = (DHR + C) x tDOT C 17 (depends on the dot clock frequency) Figure 34 Horizontal Offset Timing Diagram Semiconductor Group 68 SDA 20Cxx50 The value written to DHR may be set in steps of four, because DHR.0 and DHR.1 are always set to 0 internally. Time tHO must be greater than the HS high time tHSH. Vertical Positioning and Line Modes The vertical position of row i and the line mode may be chosen individually for each of the six rows of text. Each row is controlled by a vertical control register DVRi (i = 0,..., 5). Bit Si defines the text size to normal (Si = 0) or double size (Si = 1), bit Bi enables (Bi = 1) or disables (Bi = 0) boxed mode. Bits Vi0 ... Vi5 define the vertical start position in steps of 8 horizontal lines. The values of the vertical control registers DVRi are compared with the actual count value and a OSD output is started when the numbers match. If two or more lines are programmed to overlap, the line with the lowest index is displayed on top. Display Enable Each of the six display rows is enabled by one bit in OSD Enable Register DER. Additionally, a global enable bit in this register allows to enable or disable all individually enabled lines. Background Colors If boxed mode is selected, the respective rows of text are displayed on a colored background The background color is common to all rows and is defined in OSD Color and Polarity Register DCPR. Moreover, if bit FBG (full background) in this register is set, the whole screen will be blanked with the selected background color. Frame Mode For all lines not displayed in boxed mode, a color frame around the characters may be activated. This will increase the character contrast to the video background. OSD Interrupt The OSD circuitry is designed for a main use of six lines of text. In some applications, however, more than six lines are to be displayed. This is possible, if a cyclic reload of display lines and a vertical repositioning is done via the OSD interrupt. Using this way of time multiplexing, 12 lines or even more can be displayed (figure 35/36) and background color switching is possible. If enabled (by setting bit DER.6), every completion of a text row output will generate an interrupt, which is to be handled like the standard external interrupt 1. In this case, the state of pin P3.3/lNT1 is ignored (bits EA and EX1 in register IE must be set). Output Signal Polarity The signal polarity for BLANK may be selected by setting a control bit in DCPR. Sandcastle Operation The principle of sandcastle synchronization is shown in figure 37. Semiconductor Group 69 SDA 20Cxx50 Figure 35 Display of More than Six Rows of Text on a Video Screen (using OSD-interrupt) Semiconductor Group 70 SDA 20Cxx50 Figure 36 Flow Chart of OSD Interrupt Service Routine Semiconductor Group 71 SDA 20Cxx50 Figure 37 Sandcastle Synchronization Scheme Display RAM Access The information contained in the six display rows depends on the contents of the OSD display RAM. Each display position corresponds to one RAM location. Accesses to the display RAM are done in a two-step way. At first, the display RAM address is written to the OSD Address Register DAR, secondly the data and color information are written to or read from the OSD Registers DDR and DSCR, respectively. Note, that color information must be written first. Using registers DAR, DDR and DSCR in this way, character and color codes can be written to and read from any of the 6 x 18 = 108 locations of display RAM, each location representing a 10-bit word. Flow charts of read and write accesses are shown in the following figures. Semiconductor Group 72 SDA 20Cxx50 Figure 38 OSD RAM Read Access Semiconductor Group 73 SDA 20Cxx50 Figure 39 OSD RAM Write Access Semiconductor Group 74 SDA 20Cxx50 OSD Special Function Registers Bits notified "unused" in OSD special function registers may be used as additional software flags. Bits notified "reserved" must not be used. Display Enable Register DER MSB GE GE: DIE: DIE EN5 SFR Address: D1H DER: Display Enable Register EN4 EN3 EN2 EN1 EN0 LSB Global Enable; enables (1) or disables (0) all individually enabled rows of text Display Interrupt Enable; if set to "1", after every text row completion an interrupt will be generated and internally be switched to the "External Interrupt 1". This interrupt should be programmed to edge triggered mode (see chapter "Interrupt System"). Enable Display Row i; individual enable bit for row i OSD row i not displayed OSD row i displayed, if GE = 1 00H ENi: ENi = 0: ENi = 1: Default after reset: Display Vertical Control Registers DVRi MSB Vi5 Vi0 ... 5: Bi: Bi = 0: Bi = 1: Si: Si = 0: Si = 1: Vi4 Vi3 SFR Addresses: D2H...D7H DVR0 ... 5: Display Vertical Control Register Vi2 Vi1 Vi0 Bi Si LSB Vertical position of row i in binary (000000B ...100111B) Row i background flag No background (non boxed) Colored background (boxed) Character size of row i Normal size Double size undefined Default after reset: Semiconductor Group 75 SDA 20Cxx50 Display Status and Control Register DSCR This register is bit-addressable. MSB 1 DSCR.7: HSY: VSY: R: G: B: HSY VSY SFR Addresses: D8H DSCR: Display Status and Control Register - - R G B LSB A constant value of "1" is read (for SW compatibility to SDA 2056X devices) Horizontal synchronization status bit Vertical synchronization status bit Red color select Green color select Blue color select Bits R, G and B define the color of the next character to be written to the display RAM via display data register DDR. When reading display RAM information, R, G and B are valid after DRW = 1. The resulting color of any R-G-B combination is shown in table "OSD Color Definitions". DSCR.3: DSCR.4: reserved reserved undefined Default after reset: OSD Color Definitions R 0 0 0 0 1 1 1 1 G 0 0 1 1 0 0 1 1 B 0 1 0 1 0 1 0 1 Color black blue green cyan red magenta yellow white Semiconductor Group 76 SDA 20Cxx50 Display Address Register DAR MSB AV2 AV0 ... 2: AV1 AV0 SFR Address: D9H DAR: Display Address Register AH4 AH3 AH2 AH1 AH0 LSB Row address in display RAM to be accessed next AV2 0 0 0 0 1 1 AV1 0 0 1 1 0 0 AV0 0 1 0 1 0 1 Row 0 1 2 3 4 5 AH0 ... 4: Column address in display RAM to be accessed next AH4 0 0 0 1 AH3 0 0 0 0 undefined AH2 0 0 0 ... 0 AH1 0 0 1 0 AH0 0 1 0 1 Column 0 1 2 ... 17 Default after reset: Display Data Register DDR MSB FE FE: DB6 DB5 SFR Address: DAH DDR: Display Data Register DB4 DB3 DB2 DB1 DB0 LSB Frame Enable; if set to "1", text rows in non-boxed mode will be displayed with a black frame. DB0 ... 6: Character code to be written to or read from display RAM Default after reset: undefined Semiconductor Group 77 SDA 20Cxx50 Display Horizontal Control Register DHR MSB H5 HO ... 5: DHR.1: DHR.0: H4 H3 SFR Address: DBH DHR: Display Horizontal Control Register H2 H1 H0 - - LSB Horizontal offset; common for all rows of text Reserved for test purposes Reserved for test purposes Values written to DHR.0/1 are ignored. Default after reset: undefined Display Color and Polarity Register DCPR MSB FBG FBG: BCR BCG SFR Address: DCH DCPR: Display Color and Polarity Register BCB - BP - - LSB If set to 1, the selected background color will be displayed over the entire screen; if set to 0, the background color will only appear behind active rows of text if boxed mode is selected Background color red component Background color green component Background color blue component reserved BLANK polarity BLANK = 0 during RGB out BLANK = 1 during RGB out reserved reserved 00H BCR: BCG: BCB: DCPR.3: BP: BP = 0: BP = 1: DCPR.1: DCPR.0: Default after reset: Semiconductor Group 78 SDA 20Cxx50 Character Codes and ROM Definition The mask programmable devices SDA 20Cxx50 contain a character ROM for 96 user definable characters. The character codes are located in the range from 20H to 7FH. Character codes 00H to 1FH generate 'invisible' characters, which can be used to separate text in a single row. Leading blanks are to be filled with a user defined `blank' character. User Defined Character Sets For applications using the mask-programmable program memory and character ROM, an application specific character set has to be defined. For this purpose, a character definition file (standard ASCII format) has to be supplied to the manufacturer. From this file, the character ROM mask will be generated. The file format is: $CODE = aaH XXXXXXXXXXXX XXXXXXXXXXXX XXXXXXXXXXXX XXXXXXXXXXXX XXXXXXXXXXXX XXXXXXXXXXXX XXXXXXXXXXXX XXXXXXXXXXXX XXXXXXXXXXXX XXXXXXXXXXXX XXXXXXXXXXXX XXXXXXXXXXXX XXXXXXXXXXXX XXXXXXXXXXXX XXXXXXXXXXXX XXXXXXXXXXXX $CODE = ... ... $END (aa = 20 ... 7F; x = 0,1) Empty lines or lines beginning with '#', '/', ';' or '*' are ignored and may be used to insert comments. '$CODE = ' and '$END' are used as keywords to mark the beginning of a character definition and the end of all definitions. An example for one character is given in the following. Semiconductor Group 79 SDA 20Cxx50 Example of a Character Definition File Character to be coded: # -----------------------------------# Example character definition file # -----------------------------------$CODE = 20H ... $CODE = 53H 000000000000 000011110000 001111111100 011100001110 011000000110 011000000000 011100000000 001111100000 000011111000 000000111100 000000001110 000000000110 011000000110 011100001110 001111111100 000011110000 ... $CODE = 7FH ... $END Character Definition File (ASCII format) Semiconductor Group 80 SDA 20Cxx50 2.10 Serial Interface The serial port is full duplex, meaning it can transmit and receive simultaneously. It is also receivebuffered, meaning it can commence reception of a second byte before a previously received byte has been read from the receive register (however, if the first byte still hasn't been read by the time reception of the second byte is complete, one of the bytes will be lost). The serial port receive and transmit registers are both accessed at special function register SBUF. Writing to SBUF loads the transmit register, and reading SBUF accesses a physically separate receive register. The serial port can operate in 4 modes: Mode 0: Mode 1: Serial data enters and exits through RxD (P3.6). TxD (P3.7) outputs the shift clock at 1/12 of the oscillator frequency. 10 bits are transmitted (through TxD) or received (through RxD): a start bit (0), 8 data bits (LSB first), and a stop bit (1). On reception, the stop bit goes into RB8 in special function register SCON. The baud rate is variable. 11 bits are transmitted (through TxD) or received (through RxD): a start bit (0), 8 data bits (LSB first), a programmable 9th data bit, and a stop bit (1). On transmission, the 9th data bit (TB8 in SCON) can be assigned the value of 0 or 1. Or, for example, the parity bit (P, in the PSW) could be moved into TB8. On reception, the 9th data bit goes into RB8 in the special function register SCON, while the stop bit is ignored. The baud rate is programmable to either 1/32 or 1/64 the oscillator frequency. 11 bits are transmitted (through TxD) or received (through RxD): a start bit (0), 8 data bits (LSB first), a programmable 9th data bit and a stop bit (1). In fact, mode 3 is the same as mode 2 in all respects except the baud rate. The baud rate in mode 3 is variable. Mode 2: Mode 3: Semiconductor Group 81 SDA 20Cxx50 SM0 9FH Symbol SM0 SM1 SM2 SM1 9EH Position SCON.7 SCON.6 SCON.5 SM2 9DH REN 9CH TB8 9BH RB8 9AH TI 99H RI 98H Bit Address Function Serial port mode selection, see table 3. Enables the multiprocessor communication feature in modes 2 and 3. In mode 2 or 3, if SM2 is set to 1 then RI will not be activated if the received 9th data bit (RB8) is 0. In mode 1, if SM2 = 1 then RI will not be activated if a valid stop bit was not received. In mode 0, SM2 should be 0. Enables serial reception. Set by software to enable reception. Cleared by software to disable reception. Is the 9th data bit that will be transmitted in modes 2 and 3. Set or cleared by software as desired. In modes 2 and 3, is the 9th data bit that was received. In mode 1, if SM2 = 0, RB8 is the stop bit that was received. In mode 0, RB8 is not used. Is the transmit interrupt flag. Set by hardware at the end of the 8th bit time in mode 0, or at the beginning of the stop bit in the other modes, in any serial transmission. Must be cleared by software. Is the receive interrupt flag. Set by hardware at the end of the 8th bit time in mode 0, or halfway through stop bit time in the other modes, in any serial reception. Must be cleared by software. REN SCON.4 TB8 SCON.3 RB8 SCON.2 TI SCON.1 RI SCON.0 Figure 40 Serial Port Control Register SCON (98H) Semiconductor Group 82 SDA 20Cxx50 Table 3 Serial Port Mode Selection SM0 0 0 1 1 SM1 0 1 0 1 Mode 0 1 2 3 Description Shift reg. 8-bit UART 9-bit UART 9-bit UART Baud Rate fOSC/12 Variable fOSC/64 - fOSC/32 Variable In all four modes, transmission is initiated by any instruction that uses SBUF as a destination register. Reception is initiated in mode 0 by the condition RI = 0 and REN = 1. Reception is initiated in the other modes by the incoming start bit if REN = 1. The control, mode, and status bits of the serial port in special function register SCON are illustrated in figure 40. 2.10.1 Multiprocessor Communication Modes 2 and 3 of the serial interface of the controller have a special provision for multi-processor communication. In these modes, 9 data bits are received. The 9th one goes into RB8. Then comes a stop bit. The port can be programmed such that when the stop bit is received, the serial port interrupt will be activated only if RB8 = 1. This feature is enabled by setting bit SM2 in SCON. A way to use this feature in multiprocessor communications is as follows. When the master processor wants to transmit a block of data to one of the several slaves, it first sends out an address byte which identifies the target slave. An address byte differs from a data byte in that the 9th bit is 1 in an address byte and 0 in a data byte. With SM2 = 1, no slave will be interrupted by a data byte. An address byte however, will interrupt all slaves, so that each slave can examine the received byte and see if it is being addressed. The addressed slave will clear its SM2 bit and prepare to receive the data bytes that will be coming. The slaves that weren't addressed leave their SM2s set and go on about their business, ignoring the coming data bytes. SM2 has no effect in mode 0, and in mode 1 can be used to check the validity of the stop bit. In a mode 1 reception, if SM2 = 1, the receive interrupt will not be activated unless a valid stop bit is received. 2.10.2 Baud Rates The baud rate in mode 0 is fixed: Mode 0 baud rate = oscillator frequency 12 The baud rate in mode 2 depends on the value of bit SMOD in special function register PCON (bit 7). If SMOD = 0 (which is the value on reset), the baud rate is 1/64 of the oscillator frequency. If SMOD = 1, the baud rate is 1/32 of the oscillator frequency. Contrary to the SAB 8051 SMOD is placed on SFR address 97H. Mode 2 baud rate = 2SMOD 64 x osc. frequency Semiconductor Group 83 SDA 20Cxx50 The baud rates in modes 1 and 3 are determined by the timer 1 overflow rate or can be generated by the internal baud rate generator. When timer 1 is used as the baud rate generator, the baud rates in modes 1 and 3 are determined by the timer 1 overflow rate and the value of SMOD as follows: Modes 1, 3 baud rate = 2SMOD 32 x timer 1 overflow rate The timer 1 interrupt should be disabled in this application. The timer itself can be configured for either "timer" or "counter" operation, and in any of the 3 running modes. In the most typical applications, it is configured for "timer" operation, in the auto-reload mode (high nibble of TMOD = 0010B). In that case, the baud rate is given by the formula: Modes 1, 3 baud rate = 2SMOD 32 x oscillator frequency 12 x (256-TH1) One can achieve very low baud rates with timer 1 by leaving the timer 1 interrupt enabled, configuring the timer to run as a 16-bit timer (high nibble of TMOD = 0001B), and using the timer 1 interrupt to do a 16-bit software reload. Table 4 lists various commonly used baud rates and how they can be obtained from timer 1. Table 4 Generated Commonly Used Baud Rates Baud Rate fOSC MHz SMOD CT Timer 1 Mode X X 2 2 2 2 2 2 2 2 1 Reload Value X X FFH FDH FDH FAH F4H E8H 1DH 72H FEEBH Mode 0 max.: Mode 2 max.: Mode 1, 3: 1.33 MHz 500 Kbaud 62.5 Kbaud 19.2 Kbaud 9.6 Kbaud 4.8 Kbaud 2.4 Kbaud 1.2 Kbaud 137.5 Baud 110 Baud 110 Baud 16.0 16.0 12.0 11.059 11.059 11.059 11.059 11.059 11.986 6.0 12.0 X 1 1 1 0 0 0 0 0 0 0 X X 0 0 0 0 0 0 0 0 0 Semiconductor Group 84 SDA 20Cxx50 2.10.3 More about Mode 0 Serial data enters and exits through RxD. TxD outputs the shift clock. 8 bits are transmitted/ received: 8 data bits (LSB first). The baud rate is fixed at 1/12 the oscillator frequency. Figure 41 shows a simplified functional diagram of the serial port in mode 0, and associated timing. Transmission is initiated by any instruction that uses SBUF as a destination register. The "write-toSBUF" signal at S6P2 also loads a 1 into the 9th bit position of the transmit shift register and tells the TX control block to commence a transmission. The internal timing is such that one full machine cycle will elapse between "write-to-SBUF" and activation of SEND.SEND enables the output of the shift register to the alternate output function line of P3.6, and also enables SHIFT CLOCK to the alternate output function line of P3.7. SHIFT CLOCK is low during S3, S4 and S5 of every machine cycle, and high during S6, S1, and S2. At S6P2 of every machine cycle in which SEND is active, the contents of the transmit shift register is shifted one position to the right. As data bits shift out to the right, zeros come in from the left. When the MSB of the data byte is at the output position of the shift register, then the 1 that was initially loaded into the 9th position, is just left of the MSB, and all positions to the left of that contain zeros. This condition flags the TX control block to do one last shift and then deactivate SEND and set TI. Both of these actions occur at S1P1 in the 10th machine cycle after "write-to-SBUF". Reception is initiated by the condition REN = 1 and RI = 0. At S6P2 in the next machine cycle, the RX control unit writes the bits 1111 1110 to the receive shift register, and the next clock phase activates RECEIVE. RECEIVE enables SHIFT CLOCK to the alternate output function line of P3.7. SHIFT CLOCK makes transitions at S3P1 and S6P1 in every machine cycle. At S6P2 of every machine cycle in which RECEIVE is active, the contents of the receive shift register are shifted one position to the left. The value that comes in from the right is the value that was sampled at the P3.6 pin at S5P2 in the same machine cycle. As data bits come in from the right, 1s shift out to the left. When the 0 that was initially loaded into the farthest right position arrives at the farthest left position in the shift register, it flags the RX control block to do one last shift and load SBUF. At S1P1 in the 10th machine cycle after the write to SCON that cleared RI, RECEIVE is cleared and RI is set. 2.10.4 More about Mode 1 Ten bits are transmitted (through TxD), or received (through RxD): a start bit (0), 8 data bits (LSB first) and a stop bit (1). On reception, the stop bit goes into RB8 in SCON. The baud rate is determined by the timer 1 overflow rate. Figure 42 shows a simplified functional diagram of the serial port in mode 1, and associated timings for transmit and receive. Transmission is initiated by any instruction that uses SBUF as a destination register. The "write-toSBUF" signal also loads a 1 into the 9th bit position of the transmit shift register and flags the TX control block that a transmission is requested. Transmission actually commences at S1P1 of the machine cycle following the next rollover in the devide-by-16 counter (thus, the bit times are synchronized to the divide-by-16 counter, not to the "write-to-SBUF" signal). Semiconductor Group 85 SDA 20Cxx50 The transmission begins with activation of SEND, which puts the start bit to TxD. One bit time later, DATA is activated, which enables the output bit of the transmit shift register to TxD. The first shift pulse occurs one bit time after that. As data bits shift out to the right, zeros are clocked in from the left. When the MSB of the data byte is at the output position of the shift register, then the 1 that was initially loaded into the 9th position is just left of the MSB, and all positions to the left of that contain zeros. This condition flags the TX control unit to do one last shift and then deactivate SEND and set TI. This occurs at the 10th divideby-16 rollover after "write-to-SBUF". Reception is initiated by a detected 1-to-0 transition at RxD. For this purpose RxD is sampled at a rate of 16 times whatever baud rate has been established. When a transition is detected, the divideby-16 counter is immediately reset, and 1FFH is written into the input shift register. Resetting the divide-by-16 counter aligns its rollovers with the boundaries of the incoming bit times. The 16 states of the counter divide each bit time into 16ths. At the 7th, 8th and 9th counter states of each bit time, the bit detector samples the value of RxD. The value accepted is the value that was seen in at least 2 of the 3 samples. This is done for noise rejection. If the value accepted during the first bit time is not 0, the receive circuits are reset and the unit goes back looking for another 1-to-0 transition. This is to provide rejection of false start bits. If the start bit proves valid, it is shifted into the input shift register, and reception of the rest of the frame will proceed. As data bits come in from the right, 1s shift out to the left. When the start bit arrives at the farthest left position in the shift register (which in mode 1 is a 9-bit register), it flags the RX control block to do one last shift, load SBUF and RB8, and set RI. The signal to load SBUF and RB8, and to set RI, will be generated if, and only if, the following conditions are met at the time the final shift pulse is generated: 1) RI = 0, and 2) either SM2 = 0 or the received stop bit = 1 If either of these two conditions is not met, the received frame is irretrievably lost. If both conditions are met, the stop bit goes into RB8, the 8 data bits go into SBUF and RI is activated. At this time, no matter whether the above conditions are met or not, the unit goes back looking for a 1-to-0transition in RxD. 2.10.5 More about Modes 2 and 3 11 bits are transmitted (through TxD), or received (through RxD): a start bit (0), 8 data bits (LSB first), a programmable 9th data bit, and a stop bit (1). On transmission, the 9th data bit (TB8) can be assigned the value of 0 or 1. On reception, the 9th data bit goes into RB8 in SCON. The baud rate is programmable to either 1/32 or 1/64 of the oscillator frequency in mode 2. Mode 3 may have a variable baud rate generated from timer 1. Figures 43 and 44 show a functional diagram of the serial port in modes 2 and 3 and associated timings. The receive portion is exactly the same as in mode 1. The transmit portion differs from mode 1 only in the 9th bit of the transmit shift register. Transmission is initiated by any instruction that uses SBUF as a destination register. The "write-toSBUF" signal also loads TB8 into the 9th bit position of the transmit shift register and flags the TX control unit that a transmission is requested. Transmission commences at S1P1 of the machine Semiconductor Group 86 SDA 20Cxx50 cycle following the next rollover in the divide-by-16 counter (thus, the bit times are synchronized to the divide-by-16 counter, not to the "write-to-SBUF" signal). The transmission begins with activation of SEND, which puts the start bit to TxD. One bit time later, DATA is activated which enables the output bit of the transmit shift register to TxD. The first shift pulse occurs one bit time after that. The first shift clocks a 1 (the stop bit) into the 9th bit position of the shift register. Thereafter, only zeros are clocked in. Thus, as data bits shift out to the right, zeros are clocked in from the left. When TB8 is at the output position of the shift register, then the stop bit is just left of the TB8, and all positions to the left of that contain zeros. This condition flags the TX control unit to do one last shift and then deactive SEND and set TI. This occurs at the 11th divide-by-16 rollover after "write-to-SBUF". Reception is initiated by a detected 1-to-0 transition at RxD. For this purpose RxD is sampled at a rate of 16 times whatever baud rate has been established. When a transition is detected, the divideby-16 counter is immediately reset, and 1FFH is written to the input shift register. At the 7th, 8th, and 9th counter states of each bit time, the bit detector samples the value of RxD. The value accepted is the value that was seen in at least 2 of the 3 samples. If the value accepted during the first bit time is not 0, the receive circuits are reset and the unit goes back looking for another 1-to-0 transition. If the start bit proves valid, it is shifted into the input shift register, and reception of the rest of the frame will proceed. As data bits come in from the right, 1s shift out to the left. When the start bit arrives at the farthest left position in the shift register (which in modes 2 and 3 is a 9-bit register), it flags the RX control block to do one last shift, load SBUF and RB8, and set RI. The signal to load SBUF and RB8, and to set RI, will be generated if, and only if, the following conditions are met at the time the final shift pulse is generated: 1) RI = 0, and 2) either SM2 = 0 or the received 9th data bit = 1 If either of these two conditions is not met, the received frame is irretrievably lost, and RI is not set. If both conditions are met, the received 9th data bit goes into RB8, the first 8 data bits go into SBUF. One bit time later, no matter whether the above conditions are met or not, the unit goes back looking for a 1-to-0-transition at the RxD input. Note that the value of the received stop bit is irrelevant to SBUF, RB8 or RI. Semiconductor Group 87 SDA 20Cxx50 Figure 41a Serial Port Mode 0, Functional Diagram Semiconductor Group 88 SDA 20Cxx50 Figure 41b Serial Port Mode 0, Timing Semiconductor Group 89 SDA 20Cxx50 Figure 42a Serial Port Mode 1, Functional Diagram Semiconductor Group 90 SDA 20Cxx50 Figure 42b Serial Port Mode 1, Timing Semiconductor Group 91 SDA 20Cxx50 Figure 43a Serial Port Mode 2, Functional Diagram Semiconductor Group 92 SDA 20Cxx50 Figure 43b Serial Port Mode 2, Timing Semiconductor Group 93 SDA 20Cxx50 Figure 44a Serial Port Mode 3, Functional Diagram Semiconductor Group 94 SDA 20Cxx50 Figure 44b Serial Port Mode 3, Timing Semiconductor Group 95 SDA 20Cxx50 2.11 Advanced Function Register The on-chip clock generator of the SDA 20Cxx50 contains the same clock divider, found in every 8051 compatible design. The clock divider divides the external clock frequency (oscillator frequency) by 2. To enhance clock performance by either doubling the internal clock frequency or by keeping the internal frequency constant and halving the external quartz-frequency, the divider can be switched off by software. As software-switch for the divider a new Special-Function-Register (SFR) has been defined: Advanced Function Register AFR Default after reset: FFH (MSB) CDC CDC 1 1 1 1 1 1 1 SFR-Address A6H (LSB) Clock divider control bit. If set, the clock divider is on. The internal clock frequency is half the external oscillator frequency. If cleared, the clock divider is off. The internal clock frequency is equal to the external oscillator frequency. AFR.0 - AFR.6 Reserved, always to be written with `1'. Note: The current implementation allows a write access to the AFR-register only! Note: All time values given in this specification apply for CDC = 1 only (clock divider is on). Semiconductor Group 96 SDA 20Cxx50 2.12 Instruction Set The assembly language uses the same instruction set and the same instruction opcodes as the 8051 microcomputer family. 2.12.1 Notes on Data Addressing Modes Rn direct @Ri #data #data 16 bit - Working register R0-R7. - 128 internal RAM locations, any I/O port, control or status register. - Indirect internal RAM location addressed by register R0 or R1. - 8-bit constant included in instruction. - 16-bit constant included as bytes 2 & 3 of instruction. - 128 software flags, any l/O pin, control or status bit in special function registers. Operations working on external data memory (MOVX ...) are used to access the additional bytes of the extended internal data RAM (128/256 bytes for SDA 20C2450/SDA20C3250). 2.12.2 Notes on Program Addressing Modes addr 16 addr 11 rel - Destination address for LCALL & LJMP may be anywhere within the program memory address space. - Destination address for ACALL & AJMP will be within the same 2 Kbyte of the following instruction. - SJMP and all conditional jumps include an 8-bit offset byte. Range is + 127/- 128 bytes relative to first byte of the following instruction. Semiconductor Group 97 SDA 20Cxx50 2.12.3 Instruction Set Description Arithmetic Operations Mnemonic ADD ADD ADD ADD ADDC ADDC ADDC ADDC SUBB SUBB SUBB SUBB INC INC INC INC DEC DEC DEC DEC INC MUL DIV DA A, Rn A, direct A, @Ri A, #data A, Rn A, direct A, @Ri A, #data A, Rn A, direct A, @Ri A, #data A Rn direct @Ri A Rn direct @Ri DPTR AB AB A Description Add register to accumulator Add direct byte to accumulator Add indirect RAM to accumulator Add immediate data to accumulator Add register to accumulator with carry flag Add direct byte to A with carry flag Add indirect RAM to A with carry flag Add immediate data to A with carry flag Subtract register from A with borrow Subtract direct byte from A with borrow Subtract indirect RAM from A with borrow Subtract immediate data from A with borrow Increment accumulator Increment register Increment direct byte Increment indirect RAM Decrement accumulator Decrement register Decrement direct byte Decrement indirect RAM Increment data pointer Multiply A & B Divide A & B Decimal adjust accumulator Byte 1 2 1 2 1 2 1 2 1 2 1 2 1 1 2 1 1 1 2 1 1 1 1 1 Semiconductor Group 98 SDA 20Cxx50 Logical Operations Mnemonic ANL ANL ANL ANL ANL ANL ORL ORL ORL ORL ORL ORL XRL XRL XRL XRL XRL XRL CLR CPL RL RLC RR RRC SWAP A, Rn A, direct A, @Ri A, #data direct, A direct, #data A, Rn A, direct A, @Ri A, #data direct, A direct, #data A, Rn A, direct A, @Ri A, #data direct, A direct, #data A A A A A A A Description AND register to accumulator AND direct byte to accumulator AND indirect RAM to accumulator AND immediate data to accumulator AND accumulator to direct byte AND immediate data to direct byte OR register to accumulator OR direct byte to accumulator OR indirect RAM to accumulator OR immediate data to accumulator OR accumulator to direct byte OR immediate data to direct byte Exclusive-OR register to accumulator Exclusive-OR direct byte to accumulator Exclusive-OR indirect RAM to accumulator Exclusive-OR immediate data to accumulator Exclusive-OR accumulator to direct byte Exclusive-OR immediate data to direct Clear accumulator Complement accumulator Rotate accumulator left Rotate A left through the carry flag Rotate accumulator right Rotate A right through carry flag Swap nibbles within the accumulator Byte 1 2 1 2 2 3 1 2 1 2 2 3 1 2 1 2 2 3 1 1 1 1 1 1 1 Semiconductor Group 99 SDA 20Cxx50 Data Transfer Operations Mnemonic MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOVC MOVC MOVX MOVX MOVX MOVX PUSH POP XCH XCH XCH XCHD A, Rn A, direct A, @Ri A, #data Rn, A Rn, direct Rn, #data direct, A direct, Rn direct, direct direct, @Ri direct, #data @Ri, A @Ri, direct @Ri, #data A@A + DPTR A@A + PC A, @Ri A, @DPTR @Ri, A @DPTR, A direct direct A, Rn A, direct A, @Ri A, @Ri Description Move register to accumulator Move direct byte to accumulator Move indirect RAM to accumulator Move immediate data to accumulator Move accumulator to register Move direct byte to register Move immediate data to register Move accumulator to direct byte Move register to direct byte Move direct byte to direct Move indirect RAM to direct byte Move immediate data to direct byte Move accumulator to indirect RAM Move direct byte to indirect RAM Move immediate data to indirect RAM Move code byte relative to DPTR to accumulator Move code byte relative to PC to accumulator Move external RAM (8-bit addr) to accumulator Move external RAM (16-bit addr) to accumulator Move A to external RAM (8-bit addr) Move A to external RAM (16-bit addr) Push direct byte onto stack Push direct byte from stack Exchange register with accumulator Exchange direct byte with accumulator Exchange indirect RAM with accumulator Exchange low-order digital indirect RAM with A Byte 1 2 1 2 1 2 2 2 2 3 2 3 1 2 2 3 1 1 1 1 1 1 2 2 1 2 1 1 DPTR, #data16 Load data pointer with a 16-bit constant Semiconductor Group 100 SDA 20Cxx50 Boolean Variable Manipulation Mnemonic CLR CLR SETB SETB CPL CPL ANL ANL ORL ORL MOV MOV C bit C bit C bit C, bit C, /bit C, bit C, /bit C, bit bit, C Description Clear carry flag Clear direct bit Set carry flag Set direct bit Complement carry flag Complement direct bit AND direct bit to carry flag AND complement of direct bit to carry OR direct bit to carry flag OR complement of direct bit to carry Move direct bit to carry flag Move carry flag to direct bit Byte 1 2 1 2 2 2 2 2 2 2 2 2 Semiconductor Group 101 SDA 20Cxx50 Program and Machine Control Operations Mnemonic ACALL LCALL RET RETI AJMP LJMP SJMP JMP JZ JNZ JC JNC JB JNB JBC CJNE CJNE CJNE CJNE DJNZ DJNZ NOP addr 11 addr 16 rel @A + DPTR rel rel rel rel bit, rel bit, rel bit, rel A, direct, rel A, #data, rel Rn, #data, rel @Ri, #data, rel Rn, rel direct, rel addr11 addr16 Description Absolute subroutine call Long subroutine call Return from subroutine Return from interrupt Absolute jump Long jump Short jump (relative addr) Jump indirect relative to the DPTR Jump if accumulator is zero Jump if accumulator is not zero Jump if carry flag is set Jump if carry flag is not set Jump if direct bit set Jump if direct bit not set Jump if direct bit is set and clear bit Compare direct to A and jump if not equal Compare immediate to A and jump if not equal Byte 2 3 1 1 2 3 2 1 2 2 2 2 3 3 3 3 3 Compare immediate to register and jump if not equal 3 Compare immediate to indirect and jump if not equal 3 Decrement register and jump if not zero Decrement direct and jump if not zero No operation 2 3 1 Semiconductor Group 102 SDA 20Cxx50 2.12.4 Instruction Opcodes in Hexadecimal Order Hex Code 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28 29 2A 2B Number of Bytes 1 2 3 1 1 2 1 1 1 1 1 1 1 1 1 1 3 2 3 1 1 2 1 1 1 1 1 1 1 1 1 1 3 2 1 1 2 2 1 1 1 1 1 1 Mnemonic NOP AJMP LJMP RR INC INC INC INC INC INC INC INC INC INC INC INC JBC ACALL LCALL RRC DEC DEC DEC DEC DEC DEC DEC DEC DEC DEC DEC DEC JB AJMP RET RL ADD ADD ADD ADD ADD ADD ADD ADD Operands code addr code addr A A data addr @R0 @R1 R0 R1 R2 R3 R4 R5 R6 R7 bit addr, code addr code addr code addr A A data addr @R0 @R1 R0 R1 R2 R3 R4 R5 R6 R7 bit addr, code addr code addr A A, #data A, data addr A, @R0 A, @R1 A, R0 A, R1 A, R2 A, R3 Semiconductor Group 103 SDA 20Cxx50 Hex Code 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 Number of Bytes 1 1 1 1 3 2 1 1 2 2 1 1 1 1 1 1 1 1 1 1 2 2 2 3 2 2 1 1 1 1 1 1 1 1 1 1 2 2 2 3 2 2 1 1 1 Mnemonic ADD ADD ADD ADD JNB ACALL RETI RLC ADDC ADDC ADDC ADDC ADDC ADDC ADDC ADDC ADDC ADDC ADDC ADDC JC AJMP ORL ORL ORL ORL ORL ORL ORL ORL ORL ORL ORL ORL ORL ORL JNC ACALL ANL ANL ANL ANL ANL ANL ANL Operands A, R4 A, R5 A, R6 A, R7 bit addr, code addr code addr A A, #data A, data addr A, @R0 A, @R1 A, R0 A, R1 A, R2 A, R3 A, R4 A, R5 A, R7 A, R7 code addr code addr data addr, A data addr, #data A, #data A, data addr A, @R0 A, @R1 A, R0 A, R1 A, R2 A, R3 A, R4 A, R5 A, R6 A, R7 code addr code addr data addr, A data addr, #data A, #data A, data addr A, @R0 A, @R1 A, R0 Semiconductor Group 104 SDA 20Cxx50 Hex Code 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F 80 81 82 83 84 85 Number of Bytes 1 1 1 1 1 1 1 2 2 2 3 2 2 1 1 1 1 1 1 1 1 1 1 2 2 2 1 2 3 2 2 2 2 2 2 2 2 2 2 2 2 2 1 1 3 Mnemonic ANL ANL ANL ANL ANL ANL ANL JZ AJMP XRL XRL XRL XRL XRL XRL XRL XRL XRL XRL XRL XRL XRL XRL JNZ ACALL ORL JMP MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV SJMP AJMP ANL MOVC DIV MOV Operands A, R1 A, R2 A, R3 A, R4 A, R5 A, R6 A, R7 code addr code addr data addr, A data addr, #data A, #data A, data addr A, @R0 A, @R1 A, R0 A, R1 A, R2 A, R3 A, R4 A, R5 A, R6 A, R7 code addr code addr C, bit addr @A + DPTR A, #data data addr, #data @R0, #data @R1, #data R0, #data R1, #data R2, #data R3, #data R4, #data R5, #data R6, #data R7, #data code addr code addr C, bit addr A, @A + PC AB data addr, data addr Semiconductor Group 105 SDA 20Cxx50 Hex Code 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF B0 B1 B2 Number of Bytes 2 2 2 2 2 2 2 2 2 2 3 2 2 1 2 2 1 1 1 1 1 1 1 1 1 1 2 2 2 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 Mnemonic MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV ACALL MOV MOVC SUBB SUBB SUBB SUBB SUBB SUBB SUBB SUBB SUBB SUBB SUBB SUBB ORL AJMP MOV INC MUL reserved MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV ANL ACALL CPL Operands data addr, @R0 data addr, @R1 data addr, R0 data addr, R1 data addr, R2 data addr, R3 data addr, R4 data addr, R5 data addr, R6 data addr, R7 DPTR, #data 16 code addr bit addr, C A, @A + DPTR A, #data A, data addr A, @R0 A, @R1 A, R0 A, R1 A, R2 A, R3 A, R4 A, R5 A, R6 A, R7 C, /bit addr code addr C, /bit addr DPTR AB @R0, data addr @R1, data addr R0, data addr R1, data addr R2, data addr R3, data addr R4, data addr R5, data addr R6, data addr R7, data addr C, /bit addr code addr bit addr Semiconductor Group 106 SDA 20Cxx50 Hex Code B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF Number of Bytes 1 3 3 3 3 3 3 3 3 3 3 3 3 2 2 2 1 1 2 1 1 1 1 1 1 1 1 1 1 2 2 2 1 1 3 1 1 2 2 2 2 2 2 2 2 Mnemonic CPL CJNE CJNE CJNE CJNE CJNE CJNE CJNE CJNE CJNE CJNE CJNE CJNE PUSH AJMP CLR CLR SWAP XCH XCH XCH XCH XCH XCH XCH XCH XCH XCH XCH POP ACALL SETB SETB DA DJNZ XCHD XCHD DJNZ DJNZ DJNZ DJNZ DJNZ DJNZ DJNZ DJNZ Operands C A, #data, code addr A, data addr, code addr @R0, #data, code addr @R1, #data, code addr R0, #data, code addr R1, #data, code addr R2, #data, code addr R3, #data, code addr R4, #data, code addr R5, #data, code addr R6, #data, code addr R7, #data, code addr data addr code addr bit addr C A A, data addr A, @R0 A, @R1 A, R0 A, R1 A, R2 A, R3 A, R4 A, R5 A, R6 A, R7 data addr code addr bit addr C A data addr, code addr A, @R0 A, @R1 R0, code addr R1, code addr R2, code addr R3, code addr R4, code addr R5, code addr R6, code addr R7, code addr Semiconductor Group 107 SDA 20Cxx50 Hex Code E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF Number of Bytes 1 2 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 2 1 1 1 2 1 1 1 1 1 1 1 1 1 1 Mnemonic MOVX AJMP MOVX MOVX CLR MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOVX ACALL MOVX MOVX CPL MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV Operands A, @DPTR code addr A, @R0 A, @R1 A A, data addr A, @R0 A, @R1 A, R0 A, R1 A, R2 A, R3 A, R4 A, R5 A, R6 A, R7 @DPTR, A code addr @R0, A @R1, A A data addr, A @R0, A @R1, A R0, A R1, A R2, A R3, A R4, A R5, A R6, A R7, A Semiconductor Group 108 SDA 20Cxx50 3 Electrical Characteristics Absolute Maximum Ratings Parameter Voltage on any pin with respect to ground Power dissipation Ambient temperature under bias Storage temperature DC Characteristics TA = 0 to 85 C; VDD = 5 V 10 %, VSS = 0 V Parameter Power supply voltage Power supply current Power down current Input levels standard schmitt trigger Pins Symbol min. Limit Values max. 5.5 30 10 0.2 x VDD - 100 mV 0.2 x VDD 900 4.5 Unit Test Conditions V mA A mV Symbol Limit Values - 0.5 to 7 1 0 to 85 - 65 to 125 Unit V W C C VS Ptot TA Tstg VDD VDD VDD PORT 0 PORT 1 PORT 3 PORT 4 PORT 5 RST VDD IDD IPD VIL1 f = 12 MHz VDD = 5.5 V VDD = 5.5 V VIH1 mV Input levels clock pins Input levels sandcastle decoder XTAL1 LC1 SC VIL2 VIH2 VSCL VSCM VSCH 0.1 x VDD + 1V 0.7 x VDD - 10 0.7 x VDD 0.3 x VDD 0.1 x VDD 0.45 x VDD mV mV mV mV mV VDD = 4.5 V VDD = 4.5 V Leakage current at floating/input state PORT 0 PORT 4 XTAL2 LC1 LC2 SC ILeak 10 A VDD = 5.5 V VIL = 0 V VIH = 5.5 V Semiconductor Group 109 SDA 20Cxx50 DC Characteristics (cont'd) TA = 0 to 85 C; VDD = 5 V 10 %, VSS = 0 V Parameter Input current through standard pullup resistor Pins PORT 1 PORT 3 PORT 5 RST Low level output voltages PORT 0 of standard outputs PORT 1 PORT 3 PORT 4 OSD High level output voltages of standard outputs Output levels oscillators PORT 1 P 3.6 P 3.7 OSD XTAL2 LC2 Symbol min. Limit Values max. - 200 - 20 450 Unit Test Conditions A A mV IIL1 IIH1 VOL1 VDD = 5.5 V VIL = 0 V VDD = 4.5 V VIH = 1.8 V VDD = 4.5 V IOL = 3.2 mA VOH1 VDD - 1 V VDD = 4.5 V IOH = - 3.2 mA VOL2 VOH2 VDD - 1 V 1.0 V V VDD = 5.5 V IOL = 500 A VDD = 4.5 V IOH = - 500 A Semiconductor Group 110 SDA 20Cxx50 AC Characteristics External Clock Drive XTAL1 / Quartz Clock Drive XTAL1-XTAL2 Parameter Symbol Limit Values Variable Clock 1.2 MHz - 12MHz min. Oscillator cycle time High time Low time Rise time Fall time External quartz frequency max. 833 ns ns ns ns ns MHz 83.3 20 20 - - 1.2 Unit tCLCL tCHCX tCLCX tCLCH tCHCL fQ tCLCL - tCLCX tCLCL - tCHCX 20 20 12 Figure 45 External Clock Cycle Semiconductor Group 111 SDA 20Cxx50 OSD Input/Output Timing Characteristics Parameter Symbol Limit Values Variable DOT Clock fDOT = 6 MHz to 8 MHz min. L-sandcastle time H-sandcastle time Horizontal offset Pixel width Line width (= 216 x tDOT) max. s s s 166 36 ns s 15 3 Unit tSCL tSCH tHO tDOT tLINE tSCH 125 27 Figure 46 OSD Input/Output Timing Semiconductor Group 112 SDA 20Cxx50 Capture Input Timing Characteristics Parameter Symbol Limit Values Variable Clock Freq. up to 16 MHz min. L-capture input time H-capture input time max. - - ns ns 12 tCLCL 12 tCLCL Unit tCAPL tCAPH Figure 47 Capture Input Timing Semiconductor Group 113 SDA 20Cxx50 4 Application Example Recommended Capacitance Values Quartz Resonator Ceramic Resonator 40 10 40 10 Unit pF pF C1 C2 30 10 30 10 Figure 49 Color OSD Application Semiconductor Group 114 SDA 20Cxx50 5 Package Outlines Plastic Package, P-DIP-40 (Dual-in-Line) Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book "Package Information" Semiconductor Group 115 Dimensions in mm GPD05055 |
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