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PRELIMINARY DATA SHEET
SDA 5650/X VPS/PDC-Plus Decoder
Edition March 7, 2001 6251-563-1PD
SDA 5650/X Revision History: Previous Version: Page Page (in previous (in current Version) Version)
Current Version: 02.97
Subjects (major changes since last revision)
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SDA 5650/X
Preliminary Data Sheet
Table of Contents 1 1.1 1.2 1.3 2 2.1 2.2 2.2.1 2.2.2 2.2.3 2.2.4 2.3 2.4 2.5 3 4 5 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 6
Page 2 2 3 4
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
System Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 I2C Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 General Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Chip Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Write Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Order of Data Output on the I2C Bus and Bit Allocation of PDC/VPS Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Order of Data Output on the I2C Bus and Bit Allocation for the Header Time Mode (MAB = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Description of DAVN and EHB Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 PDC/VPS-Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Control Register Write (I2C-Bus Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Register Read (I2C-Bus Read) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DAVN and EHB Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Position of Teletext and VPS Data Lines within the Vertical Blanking Interval . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Definition of Voltage Levels for VPS Data Line . . . . . . . . . . . . . . . . . . . . . . BDSP 8/30 Format 1 Bit Allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Structure of the Teletext Data Packet 8/30 Format 2 . . . . . . . . . . . . . . . . . . BDSP 8/30 Format 2 Bit Allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Format of Programme Delivery Data in the Dedicated TV Line (VPS) 29 29 29 30 31 31 32 33 33 36
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Purchase of Micronas I2C components conveys the license under the Philips I2C patent to use the components in the I2C system provided the system conforms to the I2C specifications defined by Philips.
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Preliminary Data Sheet
CMOS 1 General Description
The PDC plus SDA 5650 decoder chip receives all VPS and 8/30 Format 1 and 2 data together with the teletext header information for easy identification of broadcast transmitter. The SDA 5650 includes a storage capacity of 16 bytes which can be used in different ways depending on selected modes.
P-DIP-14-1
1.1 Features * Single chip receiver for PDC data for Broadcast Data Service Packet (BDSP 8/30/2) according to CCIR teletext system B. VPS Data in dedicated line no. 16 of the vertical blanking interval (VBI) * Reception of BDSP packet 8/30/1 P-DSO-20-1 /-6 /-7 Unified Date and Time (UDT) Network indentification code (NIC) Short program label (SPL) * Reception of teletext header row Bytes no. 14 - 45 containing date, clock time and identification * On chip data slicer * Low external component count * I2C-Bus interface Communication with external microcontroller * PDC/VPS operation mode selectable via I2C-Bus register * Pin and software compatible to PDC/VPS decoder SDA 5649 * 5 V supply voltage * Video input signal level: 0.7 Vpp to 2.0 Vpp * Technology: CMOS * P-DIP-14-1 and P-DSO-20-1 package Type SDA 5650 SDA 5650X
Micronas
Ordering Code Q67100-H5164 Q67106-H5163
2
Package P-DIP-14-1 P-DSO-20-1 (SMD)
SDA 5650/X
Preliminary Data Sheet
1.2
Pin Configurations
P-DIP-14-1
P-DSO-20-1
Figure 1
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Preliminary Data Sheet
1.3
Pin Description Pin No. Symbol Function
P-DIP-14-1 P-DSO-20-1
1 1 2 2 3 4 4 5 6
VSS VSSA VSSD
SCL SDA CS0
Ground (0 V) Analog ground (0 V) Digital ground (0 V) Not connected Serial clock input of I2C Bus. Serial data input of I2C Bus. Chip select input determining the I2C-Bus addresses: 20H / 21H, when pulled low 22H / 23H, when pulled high. Video Composite Sync output from sync slicer used for PLL based clock generation. Data available output active low, when VPS data is received. Output signaling the presence of the first field active high. Test input; activates test mode when pulled high. Connect to ground for operating mode. Phase detector/charge pump output of data PLL (DAPLL). Connector of the loop filter for the SYSPLL. Input to the voltage controlled oscillator #1 of the DAPLL. Reference current input for the on-chip analog circuit. Composite video signal input. Positive supply voltage (+ 5 V nom.). Positive supply voltage for the digital circuits (+ 5 V nom.). Positive supply voltage for the analog circuits (+ 5 V nom.).
3, 8, 13, 18 N.C.
5 6 7 8 9 10 11 12 13 14
7 9 10 11 12 14 15 16 17 19 20
VCS DAVN EHB TI PD1 PD2/ VCO2 VCO1
IREF
CVBS
VDD VDDD VDDA
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Preliminary Data Sheet
Block Diagram
Figure 2
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Preliminary Data Sheet
2 2.1
System Description Functions
Referring to the functional block diagram of the PDC / VPS decoder, the composite video signal with negative going sync pulses is coupled to the pin CVBS through a capacitor which is used for clamping the bottom of the sync pulses to an internally fixed level. The signal is passed on to the slicer, an analogue circuitry separating the sync and the data parts of the CVBS signal, thus yielding the digital composite sync signal VCS and a digital data signal for further processing by comparing those signals to internally generated slicing levels. The output of the sync separator is forwarded, on one hand, to the output pin VCS, and on the other hand, to the clock generator and the timing block. The VCS signal represents a key signal that is used for deriving a system clock signal by means of a PLL and all other timing signal. The data slicer separates the data signal from the CVBS signal by comparing the video voltage to an internally generated slicing level which is found by averaging the data signal during TV line no. 16 in the VPS mode or by averaging the data signal during the clock run-in period of the teletext lines during the data entry window (DEW) in PDC mode. The clock generator delivers the system clock needed for the basic timing as well as for the regeneraton of the dataclock. It is based on two phase locked loops (PLL's) all parts of which are integrated on chip with the exception of the loop filter components. Each of the PLL's is composed of a voltage controlled relaxation oscillator (VCO), a phase/ frequency detector (PFD), and a charge pump which converts the digital output signals of the PFD to an analogue current. That current is transformed to a control voltage for the VCO by the off-chip loop filter. The generated VCO frequencies are 10 MHz and 13.875 MHz for VPS mode and PDC mode, respectively. All signals necessary for the control of sync and data slicing as well as for the data acquisition are generated by the Timing block. The SDA 5650 can be operated in three different modes: Depending on the selected operating mode, either teletext lines carrying 8/30 packages, the dedicated TV line no. 16 (VPS) or the teletext header bytes 38-45, 30-37, 22-29 and 14-21 are acquired. In PDC mode, only teletext rows 8/30 containing Broadcast Data Service Package (BDSP) information are acquired. The relevant bytes of 8/30 format 1 (8/30/1) and 8/30 format 2 (8/30/2) are extracted. The 8/30/1-bytes are stored in the acquisition register in a transparent way without any bit manipulation, whereas the Hamming coded bytes of packet 8/30/2 are Hamming-checked and bytes with one bit error are corrected. The storage of error free or corrected 8/30/2-data bytes in the transfer register to the I2C Bus is signalled by the DAVN output going low.
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Preliminary Data Sheet
In VPS mode, the extracted data bits of TV line no. 16 are checked for biphase errors. With no biphase errors encountered, the acquired bytes are stored in the transfer register to the I2C Bus. That transfer is signalled by a H/L transition of the DAVN output, as well. In TTX header mode A bytes 38-45 and 30-37 are accessed in this order. This assures software compatibility to the SDA 5649. In mode B bytes 22-29 and 14-21 are accessed in this order. In all three operating modes data are updated when a new data line has been received, provided that the chip is not accessed via the I2C Bus at the same time. A micro controller can read the stored bytes via the I2C-Bus interface at any time. However, one must be aware that the storage of new data from the acquisition interface is inhibited as long as the PDC decoder is being accessed via the I2C Bus. Note: In order to achieve maximum system performance it is recommended to start the SDA 5650 in VPS mode (state after power on) and read the register to check whether line 16 is received. After reception of VPS data inline 16 the SDA 5650 can be switched to 8/30 mode and waiting for packet 8/30 data. Since VPS data in line 16 is transmitted every frame and PDC data in packet 8/30 is transmitted nearly every second the recognition of both VPS and 8/30 packets can be done within PDC-system constraints (about 1 sec). 2.2 2.2.1 I2C Bus General Information
The I2C-Bus interface implemented on the PDC decoder is a slave transmitter/receiver, i. e., both reading from and writing to the PDC / VPS decoder is possible. The clock line SCL is controlled only by the bus master usually being a micro controller, whereas the SDA line is controlled either by the master or by the slave. A data transfer can only be initiated by the bus master when the bus is free, i. e., both SDA and SCL lines are in a high state. As a general rule for the I2C Bus, the SDA line changes state only when the SCL line is low. The only exception to that rule are the Start Condition and the Stop Condition. Further Details are given below. The following abbreviations are used: START: AS: AM: NAM: STOP: Start Condition generated by master Acknowledge by slave Acknowledge by master No Acknowledge by master Stop condition generated by master
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Preliminary Data Sheet
2.2.2
Chip Address
There are two pairs of chip addresses, which are selected by the CS0-input pin according to the following table: CS0 Input Low High 2.2.3 Write Mode Write Mode 20 (hex) 22 (hex) Read Mode 21 (hex) 23 (hex)
For writing to the PDC decoder, the following format has to be used: Start Chipaddress and Write Mode AS Byte to set Control Register AS Stop
Description of Data Transfer (Write Mode) Step1: Step 2: Step 3: Step 4: Step 5: Step 6: In order to start a data transfer the master generates a Start Condition on the bus by pulling the SDA line low while the SCL line is held high. The bus master puts the chip address on the SDA line during the next eight SCL pulses. The master releases the SDA line during the ninth clock pulse. Thus the slave can generate an acknowledge (AS) by pulling the SDA line to a low level. The controller transmits the data byte to set the Control register The slave acknowledges the reception of the byte. The master concludes the data communication by generating a Stop Condition.
The write mode is used to set the I2C-Bus control register which determines the operating mode:
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Preliminary Data Sheet
Control Register: Bit Number: 7 T4 6 T3 5 T2 4 T1 3 MAB 2 HDT 1 PDC/ VPS 0 FOR1/ FOR2
Default: All bits are set to 0 on power-up. Bits 4 through 7 are used for test purposes and must not be changed for normal operation by user software! Bit 0: determines, which kind of data is accessed via the I2C Bus when PDC mode is active: Value 0 BDSP 8/ 30/ 2 data accessible 1 BDSP 8/ 30/ 1 or header row data accessible (refer to description of Bit 2)
Bit 1:
determines the operating mode: Value
0 VPS mode active Bit 2:
1 PDC mode active determines whether BDSP 8/30/1-data or header row data is accessible: Value
0 BDSP 8/30/1 data accessible
1 Bytes of teletext header in mode A or B (see Bit 3)
Bit 3:
determines mode of teletext header access: Value
0 Mode A: header bytes in order 38-45, 30-37
1 Mode B: header bytes in order 22-29, 14-21
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Preliminary Data Sheet
2.2.4
Read Mode
For reading from the PDC decoder, the following format has to be used Start Chipaddress Read Mode AS 1st Byte AM ..... Last Byte NAM Stop
The contents of up to 16 registers (bytes) can be read starting with byte 1 bit 7 (refer to the table Order of Data Output on the I2C Bus and...) depending on the selected operating mode. Description of Data Transfer (Read Mode) Step1: To start a data transfer the master generates a Start Condition on the bus by pulling the SDA line low while the SCL line is held high. The byte address counter in the decoder is reset and points to the first byte to be output. The bus master puts the chip address on the SDA line during the next eight SCL pulses. The master releases the SDA line during the ninth clock pulse. Thus the slave can generate an acknowledge (AS) by pulling the SDA line to a low level. At this moment, the slave switches to transmitting mode. During the next eight clock pulses the slave puts the addressed data byte onto the SDA line. The reception of the byte is acknowledged by the master device which, in turn, pulls down the SDA line during the next SCL clock pulse. By acknowledging a byte, the master prompts the slave to increment its internal address counter and to provide the output of the next data byte. Steps no. 4 and no. 5 are repeated, until the desired amount of bytes have been read. The last byte is output by the slave since it will not be acknowledged by the master. To conclude the read operation, the master doesn't acknowledge the last byte to be received. A No Acknowledge by the master (NAM) causes the slave to switch from transmitting to receiving mode. Note that the master can prematurely cease any reading operation by not acknowledging a byte. The master gains control over the SDA line and concludes the data transfer by generating a Stop Condition on the bus, i. e., by producing a low/high transition on the SDA line while the SCL line is in a high state. With the SDA and the SCL lines being both in a high state, the I2C Bus is free and ready for another data transfer to be started.
Step 2: Step 3:
Step 4: Step 5:
Step 6: Step 7: Step 8:
Step 9:
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Preliminary Data Sheet
2.3
Order of Data Output on the I2C Bus and Bit Allocation of PDC/VPS Operating Modes I2C Bus Format 1 Byte 1 bit 7 6 5 4 3 2 1 0 bit 7 6 5 4 3 2 1 0 bit 7 6 5 4 3 2 1 0 bit 7 6 5 4 3 2 1 0 byte 15 PDC Packet 8/30 Format 2 bit 02) 1 2 3 4 5 6 7 bit 0 1 2 3 4 5 6 7 bit 0 1 2 3 4 5 6 7 bit 0 1 2 3 4 5 6 7 byte 16 bit 01) 1 2 3 bit 0 1 2 3 bit 0 1 2 3 bit 0 1 2 3 bit 0 1 2 3 bit 0 1 2 3 bit 0 1 2 3 bit 0 1 2 3 byte 11 bit 02) 1 2 3 4 5 6 7 bit 0 1 2 3 4 5 6 7 bit 0 1 2 3 4 5 6 7 bit 0 1 2 3 4 5 6 7 VPS Mode
t
byte 17
Byte 2
byte 16
byte 18
byte 12
byte 19
Byte 3
byte 17
byte 20
byte 13
byte 21
Byte 4
byte 18
byte 22
byte 14
byte 23
1) Message bit numbers according to EBU specification of PDC system. 2) Transmission bit number.
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Preliminary Data Sheet
2.3
Order of Data Output on the I2C Bus and Bit Allocation of PDC/VPS Operating Modes (cont'd) I2C Bus Format 1 Byte 5 bit 7 6 5 4 3 2 1 0 bit 7 6 5 4 3 2 1 0 bit 7 6 5 4 3 2 1 0 bit 7 6 5 4 3 2 1 0 byte 19 bit 0 1 2 3 4 5 6 7 bit 0 1 2 3 4 5 6 7 bit 0 1 2 3 4 5 6 7 bit 0 1 2 3 4 5 6 7 PDC Packet 8/30 Format 2 byte 14 bit 0 1 2 3 bit 0 1 2 3 bit 0 1 2 3 bit 0 1 2 3 byte 5 bit 0 1 2 3 4 5 6 7 bit 0 1 2 3 4 5 6 7 VPS Mode
byte 15
Byte 6
byte 20
byte 24
byte 15
byte 25
Byte 7
byte 21
byte 13
bit 0 1 2 3 - set to "1" - set to "1" - set to "1" - set to "1"
- set to "1" - set to "1" - set to "1" - set to "1" - set to "1" - set to "1" - set to "1" - set to "1"
Byte 8
byte 13
1) Message bit numbers according to EBU specification of PDC system. 2) Transmission bit number.
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Preliminary Data Sheet
2.3
Order of Data Output on the I2C Bus and Bit Allocation of PDC/VPS Operating Modes (cont'd) I2C Bus Format 1 Byte 9 bit 7 6 5 4 3 2 1 0 bit 7 6 5 4 3 2 1 0 bit 7 6 5 4 3 2 1 0 byte 14 bit 0 1 2 3 4 5 6 7 bit 0 1 2 3 4 5 6 7 bit 0 1 2 3 4 5 6 7 PDC Packet 8/30 Format 2 VPS Mode
Byte 10
byte 22
Byte 11
byte 23
1) Message bit numbers according to EBU specification of PDC system. 2) Transmission bit number.
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Preliminary Data Sheet
2.3
Order of Data Output on the I2C Bus and Bit Allocation of PDC/VPS Operating Modes (cont'd) I2C Bus Format 1 Byte 12 bit 7 6 5 4 3 2 1 0 bit7 6 5 4 3 2 1 0 byte 24 bit 0 1 2 3 4 5 6 7 bit 0 1 2 3 4 5 6 7 PDC Packet 8/30 Format 2 VPS Mode
Byte 13
byte 25
1) Message bit numbers according to EBU specification of PDC system. 2) Transmission bit number.
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Preliminary Data Sheet
2.4
Order of Data Output on the I2C Bus and Bit Allocation for the Header Time Mode (MAB = 0) I2C Bus Header Time Mode bit 7 6 5 4 3 2 1 0 bit 7 6 5 4 3 2 1 0 bit 7 6 5 4 3 2 1 0 bit 7 6 5 4 3 2 1 0 byte 38 bit 02) 1 2 3 4 5 6 7 bit 0 1 2 3 4 5 6 7 bit 0 1 2 3 4 5 6 7 bit 0 1 2 3 4 5 6 7
t
Byte 1
Byte 2
byte 39
Byte 3
byte 40
Byte 4
byte 41
1) Message bit numbers according to EBU specification of PDC system. 2) Transmission bit number.
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Preliminary Data Sheet
2.4
Order of Data Output on the I2C Bus and Bit Allocation for the Header Time Mode (MAB = 0) (cont'd) I2C Bus Header Time Mode bit 7 6 5 4 3 2 1 0 bit 7 6 5 4 3 2 1 0 bit 7 6 5 4 3 2 1 0 bit 7 6 5 4 3 2 1 0 byte 42 bit 02) 1 2 3 4 5 6 7 bit 0 1 2 3 4 5 6 7 bit 0 1 2 3 4 5 6 7 bit 0 1 2 3 4 5 6 7
t
Byte 5
Byte 6
byte 43
Byte 7
byte 44
Byte 8
byte 45
1) Message bit numbers according to EBU specification of PDC system. 2) Transmission bit number.
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Preliminary Data Sheet
2.4
Order of Data Output on the I2C Bus and Bit Allocation for the Header Time Mode (MAB = 0) (cont'd) I2C Bus Header Time Mode bit 7 6 5 4 3 2 1 0 bit 7 6 5 4 3 2 1 0 bit 7 6 5 4 3 2 1 0 bit 7 6 5 4 3 2 1 0 byte 30 bit 02) 1 2 3 4 5 6 7 bit 0 1 2 3 4 5 6 7 bit 0 1 2 3 4 5 6 7 bit 0 1 2 3 4 5 6 7
t
Byte 9
Byte 10
byte 31
Byte 11
byte 32
Byte 12
byte 33
1) Message bit numbers according to EBU specification of PDC system. 2) Transmission bit number.
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Preliminary Data Sheet
2.4
Order of Data Output on the I2C Bus and Bit Allocation for the Header Time Mode (MAB = 0) (cont'd) I2C Bus Header Time Mode bit 7 6 5 4 3 2 1 0 bit 7 6 5 4 3 2 1 0 bit 7 6 5 4 3 2 1 0 bit 7 6 5 4 3 2 1 0 byte 34 bit 02) 1 2 3 4 5 6 7 bit 0 1 2 3 4 5 6 7 bit 0 1 2 3 4 5 6 7 bit 0 1 2 3 4 5 6 7
t
Byte 13
Byte 14
byte 35
Byte 15
byte 36
Byte 16
byte 37
1) Message bit numbers according to EBU specification of PDC system. 2) Transmission bit number.
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Preliminary Data Sheet
2.4
Order of Data Output on the I2C Bus and Bit Allocation for the Header Time Mode (MAB = 0) (cont'd) I2C Bus Header Time Mode bit 7 6 5 4 3 2 1 0 bit 7 6 5 4 3 2 1 0 bit 7 6 5 4 3 2 1 0 bit 7 6 5 4 3 2 1 0 byte 22 bit 02) 1 2 3 4 5 6 7 bit 0 1 2 3 4 5 6 7 bit 0 1 2 3 4 5 6 7 bit 0 1 2 3 4 5 6 7
t
Byte 1
Byte 2
byte 23
Byte 3
byte 24
Byte 4
byte 25
1) Message bit numbers according to EBU specification of PDC system. 2) Transmission bit number.
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Preliminary Data Sheet
2.4
Order of Data Output on the I2C Bus and Bit Allocation for the Header Time Mode (MAB = 0) (cont'd) I2C Bus Header Time Mode bit 7 6 5 4 3 2 1 0 bit 7 6 5 4 3 2 1 0 bit 7 6 5 4 3 2 1 0 bit 7 6 5 4 3 2 1 0 byte 26 bit 02) 1 2 3 4 5 6 7 bit 0 1 2 3 4 5 6 7 bit 0 1 2 3 4 5 6 7 bit 0 1 2 3 4 5 6 7
t
Byte 5
Byte 6
byte 27
Byte 7
byte 28
Byte 8
byte 29
1) Message bit numbers according to EBU specification of PDC system. 2) Transmission bit number.
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Preliminary Data Sheet
2.4
Order of Data Output on the I2C Bus and Bit Allocation for the Header Time Mode (MAB = 0) (cont'd) I2C Bus Header Time Mode bit 7 6 5 4 3 2 1 0 bit 7 6 5 4 3 2 1 0 bit 7 6 5 4 3 2 1 0 bit 7 6 5 4 3 2 1 0 byte 14 bit 02) 1 2 3 4 5 6 7 bit 0 1 2 3 4 5 6 7 bit 0 1 2 3 4 5 6 7 bit 0 1 2 3 4 5 6 7
t
Byte 9
Byte 10
byte 15
Byte 11
byte 16
Byte 12
byte 17
1) Message bit numbers according to EBU specification of PDC system. 2) Transmission bit number.
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Preliminary Data Sheet
2.4
Order of Data Output on the I2C Bus and Bit Allocation for the Header Time Mode (MAB = 0) (cont'd) I2C Bus Header Time Mode bit 7 6 5 4 3 2 1 0 bit 7 6 5 4 3 2 1 0 bit 7 6 5 4 3 2 1 0 bit 7 6 5 4 3 2 1 0 byte 18 bit 02) 1 2 3 4 5 6 7 bit 0 1 2 3 4 5 6 7 bit 0 1 2 3 4 5 6 7 bit 0 1 2 3 4 5 6 7
t
Byte 13
Byte 14
byte 19
Byte 15
byte 20
Byte 16
byte 21
1) Message bit numbers according to EBU specification of PDC system. 2) Transmission bit number.
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Preliminary Data Sheet
2.5 DAVN EHB
Description of DAVN and EHB Outputs (Data Valid active low) (First Field active high)
Signal Output
VPS Mode 8/30/2 Mode
PDC Mode 8/30/1 Mode Header Time
DAVN H/L-transition (set low) in line 16 when in the line valid VPS data is carrying received valid 8/30/2 data at the start of line 16 in the line carrying valid 8/30/1 data in the line carrying valid header row X/0 data
L/H-transition (set high) always set high
at the beginning of the next field i.e., at the start of the next data entry window
on power-up or during I2C-Bus accesses when the bus master doesn't acknowledge in order to generate the stop condition
EHB L/H-transition H/L-transition at the beginning of the first field at the beginning of the second field
In test mode (i.e. TI = high), both DAVN and EHB are controlled by the CS0 pin and reproduce the state of the CS0 input.
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Preliminary Data Sheet
3
Electrical Characteristics
Absolute Maximum Ratings TA = 25 C Parameter Ambient temperature Storage temperature Total power dissipation Power dissipation per output Input voltage Supply voltage Thermal resistance Symbol min. Limit Values typ. max. 70 125 300 10 - 0.3 - 0.3 6 6 80 0 - 40 Unit Test Condition C C mW mW V V K/W in operation by storage
TA Tstg Ptot PDQ VIM VDD Rth SU
Note: Maximum ratings are absolute ratings; exceeding any one of these values may cause irreversible damage to the integrated circuit. Operating Range Supply voltage Supply current Ambient temperature range
VDD IDD TA
4.5 0
5 5
5.5 15 70
V mA C
Note: In the operating range the functions given in the circuit description are fulfilled.
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Preliminary Data Sheet
Electrical Characteristics TA = 25 C Parameter Symbol min. Input Signals SDA, SCL, CS0 H-input voltage L-input voltage Input capacitance Input current Input Signal TI H-input voltage L-input voltage Input capacitance Input current Limit Values typ. max. Unit Test Condition
VIH VIL CI IIM
0.7 x VDD 0
VDD
10 10
V pF A
0.3 x VDD V
VIH VIL CI IIM
0.9 x VDD 0
VDD
10 10
V pF A
0.1 x VDD V
Input Signals CVBS (pos. Video, neg. Sync) Video input signal level Synchron signal amplitude Data amplitude Coupling capacitor
VCVBS
0.7
1.0
2.0
V
2 Vpp with 0.8 V VSYNC and 1.2 V VDAT 1.0 V only related to VCS signal generation
VSYNC
0.15
0.3
0.8 (1.0)
V
VDAT
0.25 0.5 1.5 x VSYNC 33
1.2
V nF
CC H-input current IIH L-input current IIL Source impedance RS Leakage resistance RC
at coupling capacitor
10 - 1000 0.91 - 400 - 100 250 1 1.2
A A M
VI = 5 V VI = 0 V
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SDA 5650/X
Preliminary Data Sheet
Electrical Characteristics (cont'd) TA = 25 C Parameter Symbol min. Output Signals DAVN, EHB, VCS H-output voltage L-output voltage Limit Values typ. max. Unit Test Condition
VQH VQL
VDD - 0.5
0.4
V V
IQ = - 100 A IQ = 1.6 mA
Output Signals SDA (Open-Drain-Stage) L-output voltage Permissible output voltage
VQL
0.4 5.5
V V
IQ = 3.0 mA
PLL-Loop Filter Components (see application circuit) Resistance at PD2/ VCO2 Attenuation resistance Resistance at PD2/ VCO2
R1
6.8 1200 6.8 1200 2.2 33
k k k k nF nF
Resistance at VCO1 R2
R3 R5
Integration capacitor C1 Integration capacitor C3 VCO - Frequence Range Adjustment Resistance at IREF (for bias current adjustment)
R4
100
k
Note: The listed characteristics are ensured over the operating range of the integrated circuit. Typical characteristics specify mean values expected over the production spread. If not otherwise specified, typical characteristics apply at TA = 25 C and the given supply voltage.
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SDA 5650/X
Preliminary Data Sheet
t HD, STA
SDA t BUF SCL Stop Start t LOW t HD, DAT t HIGH t SU, DAT Stop t SU, STO
UET00130
t TLH
t THL
Figure 3 I2C-Bus Timing Parameter Clock frequency Inactive time prior to new transmission start-up Hold time during start condition Low-period of clock High-period of clock Set-up time for data Rise time for SDA and SCL signal Fall time for SDA and SCL signal Set-up time for SCL clock during stop condition All values referred to VIH and VIL levels. Symbol Limit Values min. max. 100 kHz s s s s ns 1 300 4.7 s ns s 0 4.7 4.0 4.7 4.0 250 Unit
fSCL tBUF tHD; STA tLOW tHIGH tSU;DAT tTLH tTHL tSU; STO
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SDA 5650/X
Preliminary Data Sheet
4
PDC/VPS-Receiver
Figure 4
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SDA 5650/X
Preliminary Data Sheet
5 5.1
Appendix Control Register Write (I2C-Bus Write)
Figure 5 5.2 Data Register Read (I2C-Bus Read)
Figure 6
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SDA 5650/X
Preliminary Data Sheet
5.3
DAVN and EHB Timing
Figure 7
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SDA 5650/X
Preliminary Data Sheet
5.4
Position of Teletext and VPS Data Lines within the Vertical Blanking Interval
Figure 8 5.5 Definition of Voltage Levels for VPS Data Line
Figure 9
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SDA 5650/X
Preliminary Data Sheet
5.6
BDSP 8/30 Format 1 Bit Allocation Bit No. 0 1 2 3 4 5 6 7 Network Identification Network Identification Weight 2-2 2 -1 20 21 Weight 22 1 23 1 Sign 0 1 1 1 Modified Julian Date (MJD) 1. Byte Modified Julian Date 2. Byte Modified Julian Date (MJD) 3. Byte Universal Time Coordinated (UTC) 1. Byte Universal Time Coordinated 2. Byte Universal Time Coordinated 3. Byte Short Programme Label 1. Byte Short Programme Label 2. Byte Short Programme Label 3. Byte Short Programme Label 4. Byte Time Offset Code 1. Byte 2. Byte Contents
Byte No. 13 14 15
16 17 18 19
MJD Digit Weight 104 MJD Digit Weight 102 MJD Digit Weight 100 UTC Hours Units UTC Minutes Units UTC Seconds Units
MJD Digit Weight 103 MJD Digit Weight 101 UTC Hours Tens UTC Minutes Tens UTC Seconds Tens
20 21 22 23 24 25
Note: This corresponds to the coding adopted in CCIR teletext system B BDSP 8/30 format 1. NB: The received bytes are output on the I2C Bus in a transparent way, i.e., on a bit-first-in-first-out basis. No bit manipulation is performed on the chip in this operating mode. Concerning bytes no. 16 through 21: When evaluating the numbers, note that each 4-bit-digit has been incremented by one prior to transmission, and the least significant bits are transmitted first.
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SDA 5650/X
Preliminary Data Sheet
5.7
Structure of the Teletext Data Packet 8/30 Format 2
Figure 10
:
5.8 byte 13
BDSP 8/30 Format 2 Bit Allocation bit 0 - LCI 1 - LCI 2 - LUF 3 - reserved but as yet undefined b1 b2 label update flag label channel identifier
The four message bits of byte 13 are used as follows
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SDA 5650/X
Preliminary Data Sheet
5.8
BDSP 8/30 Format 2 Bit Allocation (cont'd)
The message bits of bytes 14-25 are used in a way similar to the coding of the label in the dedicated television line as follows: byte 14 bit 0 PCS 1 PCS 2 3 byte 15 bit 0 CNI 1 CNI 2 CNI 3 CNI byte 16 bit 0 CNI 1 CNI 2 PIL 3 PIL byte 17 bit 0 PIL 1 PIL 2 PIL 3 PIL byte 18 bit 0 PIL 1 PIL 2 PIL 3 PIL byte 19 bit 0 PIL 1 PIL 2 PIL 3 PIL b1 b2 b3 b4 b9 b10 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 b14 hour month day network (or programme provider) b1 b2 reserved but yet undefined country status of analogue sound
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SDA 5650/X
Preliminary Data Sheet
5.8 byte 20
BDSP 8/30 Format 2 Bit Allocation (cont'd) bit 0 PIL 1 PIL 2 PIL 3 PIL b15 b16 b17 b18 b19 b20 b5 b6 b7 b8 b11 b12 b13 b14 b15 b16 b1 b2 b3 b4 b5 b6 b7 b8 programme type network (or programme provider) country minute
byte 21
bit 0 PIL 1 PIL 2 CNI 3 CNI
byte 22
bit 0 CNI 1 CNI 2 CNI 3 CNI
byte 23
bit 0 CNI 1 CNI 2 CNI 3 CNI
byte 24
bit 0 PTY 1 PTY 2 PTY 3 PTY
byte 25
bit 0 PTY 1 PTY 2 PTY 3 PTY
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SDA 5650/X
Preliminary Data Sheet
5.9
Data Format of Programme Delivery Data in the Dedicated TV Line (VPS)
Figure 11
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SDA 5650/X
Preliminary Data Sheet
Figure 12
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SDA 5650/X
Preliminary Data Sheet
6
Package Outlines P-DIP-14-1 (Plastic Dual In-line Package)
Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book "Package Information". Dimensions in mm Micronas 38
GPD05005
SDA 5650/X
Preliminary Data Sheet
P-DSO-20-1 (Plastic Dual Small Outline Package)
0.35 x 45
+0.09
2.65 max
2.45 -0.2
0.2 -0.1
7.6 -0.2 1)
1.27 0.35 +0.15 2) 20 0.2 24x 11 0.1
0.4 +0.8 10.3 0.3
GPS05094
1 12.8 1) 10 -0.2 Index Marking 1) Does not include plastic or metal protrusions of 0.15 max per side 2) Does not include dambar protrusion of 0.05 max per side
GPS05094
Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book "Package Information". SMD = Surface Mounted Device Micronas 39
0.23
8 ma x
Dimensions in mm
SDA 5650/X
PRELIMINARY DATA SHEET
Micronas GmbH Hans-Bunte-Strasse 19 D-79108 Freiburg (Germany) P.O. Box 840 D-79008 Freiburg (Germany) Tel. +49-761-517-0 Fax +49-761-517-2174 E-mail: docservice@micronas.com Internet: www.micronas.com Printed in Germany Order No. 6251-563-1PD
All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Any new issue of this data sheet invalidates previous issues. Product availability and delivery are exclusively subject to our respective order confirmation form; the same applies to orders based on development samples delivered. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Further, Micronas GmbH reserves the right to revise this publication and to make changes to its content, at any time, without obligation to notify any person or entity of such revisions or changes. No part of this publication may be reproduced, photocopied, stored on a retrieval system, or transmitted without the express written consent of Micronas GmbH.
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Micronas

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