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SN54ALS564A, SN74ALS564B OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS
SDAS164A - APRIL 1982 - REVISED JANUARY 1989
* * * * *
3-State Buffer-Type Inverting Outputs DriveBus-Lines Directly Bus-Structured Pinout Buffered Control Inputs Package Options Include Plastic Small Outline Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mil DIPs Dependable Texas Instruments Quality and Reliability
SN54ALS564A . . . J PACKAGE SN74ALS564B . . . DW OR N PACKAGE (TOP VIEW)
description
These 8-bit registers feature inverting 3-state outputs designed specifically for bus driving. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The 8-bit edge-triggered D-type flip-flops enter data on the low-to-high transition of the clock. The output control does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. The SN54ALS564A is characterized for operation over the full military temperature range of - 55C to 125C. The SN74ALS564B is characterized for operation from 0C to 70C.
OC 1D 2D 3D 4D 5D 6D 7D 8D GND
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
VCC 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q CLK
SN54ALS564A . . . FK PACKAGE (TOP VIEW)
3D 4D 5D 6D 7D
4 5 6 7 8
3 2 1 20 19 18 17 16 15 14 9 10 11 12 13
2D 1D OC VCC 1Q 2Q 3Q 4Q 5Q 6Q
logic symbol
FUNCTION TABLE (each flip-flop) INPUTS OC CLK D L L L H L X H L X X OUTPUT Q L H QO Z OC CLK 1D 2D 3D 4D 5D 6D 7D 8D 1 11 2 3 4 5 6 7 8 9 EN C1 1D 19 18 17 16 15 14 13 12 8Q 6Q 7Q 3Q 4Q 5Q 1Q 2Q
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for DW, J, and N packages.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright (c) 1989, Texas Instruments Incorporated
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
8D GND CLK 8Q 7Q
1
SN54ALS564A, SN74ALS564B OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS
SDAS164A - APRIL 1982 - REVISED JANUARY 1989
logic diagram (positive logic)
1 OC CLK 11
1D
2
C1 D1
19
1Q
2D
3
C1 D1
18 2Q
3D
4
C1 D1
17 3Q
4D
5
C1 D1
16 4Q
5D
6
C1 D1
15 5Q
6D
7
C1 D1
14
6Q
7D
8
C1 D1
13
7Q
8D
9
C1 D1
12
8Q
Pin numbers shown are for DW, J, and N packages.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Voltage applied to a disabled 3-state output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Operating free-air temperature range: SN54ALS564A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 55C to 125C SN74ALS564B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 70C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65C to 150C
2
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
SN54ALS564A, SN74ALS564B OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS
SDAS164A - APRIL 1982 - REVISED JANUARY 1989
recommended operating conditions
SN54ALS564A MIN VCC VIH VIL IOH IOL fclock tw tsu th TA Supply voltage High-level input voltage Low-level input voltage High-level output current Low-level output current Clock frequency Pulse duration, CLK high or low Setup time, data before CLK Hold time, data after CLK Operating free-air temperature 0 16.5 15 4 - 55 125 4.5 2 0.7 -1 12 25 0 14 15 0 0 70 NOM 5 MAX 5.5 SN74ALS564B MIN 4.5 2 0.8 - 2.6 24 30 NOM 5 MAX 5.5 UNIT V V V mA mA MHz ns ns ns C
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER VIK VOH TEST CONDITIONS VCC = 4.5 V, VCC = 4.5 V to 5.5 V, VCC = 4.5 V, VCC = 4.5 V, VCC = 4.5 V, VCC = 4.5 V, VCC = 5.5 V, VCC = 5.5 V, VCC = 5.5 V, VCC = 5.5 V, VCC = 5.5 V, VCC = 5.5 V, VCC = 5.5 V II = - 18 mA IOH = - 0.4 mA IOH = - 1 mA IOH = - 2.6 mA IOL = 12 mA IOL = 24 mA VO = 2.7 V VO = 0.4 V VI = 7 V VI = 2.7 V VI = 0.4 V VO = 2.25 V Outputs high ICC Outputs low Outputs disabled - 30 10 15 16 MIN SN54ALS564A TYP MAX - 1.2 VCC - 2 2.4 VCC - 2 3.3 2.4 0.25 0.4 20 - 20 0.1 20 - 0.2 - 112 18 24 30 - 30 10 15 16 3.2 0.25 0.35 0.4 0.5 20 - 20 0.1 20 - 0.2 - 112 18 24 30 mA V A A mA A mA mA V MIN SN74ALS564B TYP MAX - 1.2 UNIT V
VOL IOZH IOZL II IIH IIL IO
All typical values are at VCC = 5 V, TA = 25C. The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS,
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
3
SN54ALS564A, SN74ALS564B OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS
SDAS164A - APRIL 1982 - REVISED JANUARY 1989
switching characteristics (see Note 1)
VCC = 5 V, CL = 50 p , pF, , R1 = 500 , R2 = 500 , TA = 25C 'ALS564 TYP fmax tPLH tPHL tPZH tPZL tPHZ 50 CLK 9 Any Q Any Q 9 11 OC 11 MIN 25 4 4 4 4 15 15 21 21 VCC = 4.5 V to 5.5 V, CL = 50 p , pF, , R1 = 500 , R2 = 500 , TA = MIN to MAX SN54ALS564A MAX SN74ALS564B MIN 30 3 4 3 4 1 2 14 14 18 18 10 15 MAX MHz ns ns ns
PARAMETER
FROM (INPUT)
TO (OUTPUT)
UNIT
6 2 12 OC Any Q tPLZ 8 3 17 For conditions shown MIN or MAX, use the appropriate value specified under recommended operating conditions. NOTE 1: Load circuit and voltage waveforms are shown in Section 1 of the ALS/AS Logic Data Book, 1986.
4
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
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Copyright (c) 1998, Texas Instruments Incorporated

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