 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| SN74F323 8-BIT UNIVERSAL SHIFT-STORAGE REGISTER WITH SYNCHRONOUS CLEAR AND 3-STATE OUTPUTS SDFS072A - D2932, MARCH 1987 - REVISED OCTOBER 1993 * * * * * * * Four Modes of Operation: Hold (Store) Shift Right Shift Left Load Data Operates With Outputs Enabled or at High Impedance 3-State Outputs Drive Bus Lines Directly Can Be Cascaded for N-Bit Word Lengths Synchronous Clear Applications: Stacked or Push-Down Registers Buffer Storage Accumulator Registers Package Options Include Plastic Small-Outline Packages and Standard Plastic 300-mil DIPs DW OR N PACKAGE (TOP VIEW) S0 OE1 OE2 G/QG E/QE C/QC A /QA QA CLR GND 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCC S1 SL QH H/QH F/QF D/QD B/QB CLK SR description This 8-bit universal register features multiplexed I/O ports to achieve full 8-bit data handling in a single 20-pin package. Two function-select (S0, S1) and two output-enable (OE1, OE2) inputs can be used to choose the modes of operation listed in the function table. Synchronous parallel loading is accomplished by taking both S0 and S1 high. This places the 3-state outputs in a high-impedance state and permits data that is applied on the I/O ports to be clocked into the register. Reading out of the register can be accomplished while the outputs are enabled in any mode. Clearing occurs synchronously when the clear (CLR) input is low. Taking either OE1 or OE2 high disables the outputs but this has no effect on clearing, shifting, or storage of data. The SN74F323 is characterized for operation from 0C to 70C. FUNCTION TABLE INPUTS MODE CLR L Clear L L Hold Shift Right Shift Left Load H H H H H H H S1 X L H L X L L H H H S0 L X H L X H H L L H OE1 L L X L L L L L L X OE2 L L X L L L L L L X CLK X L SL X X X X X X X H L X SR X X X X X H L X X X A /QA L L X QA0 QA0 H L QBn QBn a B/QB L L X QB0 QB0 QAn QAn QCn QCn b C/QC L L X QC0 QC0 QBn QBn QDn QDn c I/O PORTS D/QD L L X QD0 QD0 QCn QCn QEn QEn d E/QE L L X QE0 QE0 QDn QDn QFn QFn e F/QF L L X QF0 QF0 QEn QEn QGn QGn f G/QG L L X QG0 QG0 QFn QFn QHn QHn g H/QH L L X QH0 QH0 QGn QGn H L h OUTPUTS QA L L L QA0 QA0 H L QBn QBn a QH L L L QH0 QH0 QGn QGn H L h NOTE: a . . . h = the level of the steady-state input at inputs A through H, respectively. These data inputs are loaded into the flip-flops while the flip-flop outputs are isolated from the I/O terminals. When one or both output-enable inputs are high the eight I/O terminals are disabled to the high-impedance state; however, sequential operation or clearing of the register is not affected. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 1993, Texas Instruments Incorporated POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 2-1 SN74F323 8-BIT UNIVERSAL SHIFT-STORAGE REGISTER WITH SYNCHRONOUS CLEAR AND 3-STATE OUTPUTS SDFS072A - D2932, MARCH 1987 - REVISED OCTOBER 1993 logic symbol 9 2 OE1 OE2 S0 S1 CLK SR A /QA 3 1 19 12 11 7 0 1 SRG8 4R & 3EN5 0 3 CLR M C4/1/2 1, 4D 3, 4D 5 8 QA B /QB C/QC D/QD E/QE F/QF G/QG H/QH SL 13 3, 4D 5 6 14 5 15 4 16 18 3, 4D 5 2, 4D 17 QH This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. 2-2 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SN74F323 8-BIT UNIVERSAL SHIFT-STORAGE REGISTER WITH SYNCHRONOUS CLEAR AND 3-STATE OUTPUTS SDFS072A - D2932, MARCH 1987 - REVISED OCTOBER 1993 logic diagram (positive logic) CLR 9 S0 1 S1 SR (shift right serial input) 19 18 11 Six Identical Channels Not Shown 12 1D C1 8 1D C1 17 QH SL (shift left serial input) CLK QA OE1 OE2 2 3 7 A/QA 16 H/QH I/O ports not shown: B/QB (13), C/QC (6), D/QD (14), E/QE (5), F/QF (15), and G/QG (4). absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 1.2 V to 7 V Input current range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 30 mA to 5 mA Voltage range applied to any output in the disabled or power-off state . . . . . . . . . . . . . . . . . . . - 0.5 V to 5.5 V Voltage range applied to any output in the high state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to VCC Current into any output in the low state: QA or QH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 mA QA thru QH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 mA Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 70C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65C to 150C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: The input voltage ratings may be exceeded provided the input current ratings are observed. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 2-3 SN74F323 8-BIT UNIVERSAL SHIFT-STORAGE REGISTER WITH SYNCHRONOUS CLEAR AND 3-STATE OUTPUTS SDFS072A - D2932, MARCH 1987 - REVISED OCTOBER 1993 recommended operating conditions MIN VCC VIH VIL IIK IOH IOL TA Supply voltage High-level input voltage Low-level input voltage Input clamp current High-level High level output current Low-level Low level output current Operating free-air temperature QA or QH QA thru QH QA or QH QA thru QH 0 4.5 2 0.8 - 18 -1 -3 20 24 70 NOM 5 MAX 5.5 UNIT V V V mA mA mA C electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK QA or QH VOH QA thru QH Any output VOL II IIH QA or QH QA thru QH A thru H Any other A thru H Any other A thru H IIL S0 or S1 Any other IOS VCC = 5.5 V, VO = 0 - 60 ICC VCC = 5.5 V, See Note 2 68 All typical values are at VCC = 5 V, TA = 25C. For I/O ports (QA thru QH), the parameters IIH and IIL include the off-state output current. Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second. NOTE 2: ICC is measured with OE1, OE2, and CLK at 4.5 V. VCC = 5.5 V, VI = 0.5 V VCC = 4.5 V VCC = 4.75 V, VCC = 4 5 V 4.5 VCC = 5 5 V 5.5 VCC = 5 5 V 5.5 V, VCC = 4.5 V, TEST CONDITIONS II = - 18 mA IOH = - 1 mA IOH = - 1 mA IOH = - 3 mA IOH = - 1 mA to - 3 mA IOL = 20 mA IOL = 24 mA VI = 5.5 V VI = 7 V VI = 2 7 V 2.7 MIN 2.5 2.5 2.4 2.7 0.3 0.35 0.5 0.5 1 0.1 70 20 - 0.65 - 1.2 - 0.6 -150 95 mA mA mA V mA A TYP 3.4 3.4 3.3 V MAX - 1.2 UNIT V 2-4 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SN74F323 8-BIT UNIVERSAL SHIFT-STORAGE REGISTER WITH SYNCHRONOUS CLEAR AND 3-STATE OUTPUTS SDFS072A - D2932, MARCH 1987 - REVISED OCTOBER 1993 timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) VCC = 5 V, TA = 25C MIN fclock tw tsu Clock frequency Pulse duration Setup time before CLK CLK high or low S0 or S1 A /QA thru H/QH, SR, or SL CLR S0 or S1 th Hold time after CLK A/QA thru H/QH, SR, or SL CLR High or low High or low High or low High or low High or low High or low 0 7 8.5 5 10 0 2 0 MAX 70 0 7 8.5 5 10 0 2 0 ns ns 70 MHz ns MIN MAX UNIT switching characteristics (see Note 3) FROM (INPUT) TO (OUTPUT) VCC = 5 V, CL = 50 pF, RL = 500 , TA = 25C MIN fmax tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ 70 CLK CLK OE1 or OE2 OE1 or OE2 QA or QH QA thru QH QA thru QH QA thru QH 3.2 2.7 3.2 4.2 2.7 3.2 1.7 1.2 TYP 100 6.6 6.1 6.6 8.1 5.6 6.6 4.1 3.6 9 8.5 9 11 8 10 6 5.5 MAX VCC = 4.5 V to 5.5 V, CL = 50 pF, RL = 500 , TA = MIN to MAX MIN 70 3.2 2.7 3.2 4.2 2.7 3.2 1.7 1.2 10 9.5 10 12 9 11 7 6.5 MAX MHz ns ns ns ns PARAMETER UNIT For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. NOTE 3: Load circuits and waveforms are shown in Section 1. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 2-5 SN74F323 8-BIT UNIVERSAL SHIFT-STORAGE REGISTER WITH SYNCHRONOUS CLEAR AND 3-STATE OUTPUTS SDFS072A - D2932, MARCH 1987 - REVISED OCTOBER 1993 2-6 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof. Copyright (c) 1998, Texas Instruments Incorporated |
Price & Availability of SDFS072A
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |