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SLAA099
Evaluation Unit of THS8083
1. Overview and main components of the evaluation circuit board.
The evaluation unit is designed to fully evaluate all the functions of the THS8083 device, meanwhile the design of the print circuit board can be used as a reference when customers try to design a system by using THS8083. The figure 2 is block diagram of the PC board. Based on the diagram, the PC board consists of following main parts. * THS8083 device. The package of this device is implemented in the power-pad package. So the PCB area directly under THS8083 is exposed cooper. The exposed bottom of the die of the device should be soldered to this area of the board. This will dramatically help the heat dissipation of the device, and increase the reliability of the system. The ALTERA FPGA contains all the control logic of the panel display. It has I2C slave module with device address 80H, display data formatter, and display timing generator. Two voltage regulators are U16 and U20. Both of them are TPS73HD301, each has dual voltage outputs. This is the power pad package also, the bottom of the device is soldered on the PCB board's ground plan to help the heat dispassion.
* *
2. Connectors and their usage
Following are the connectors that will be used for THS8083 function evaluation. There may be more connectors than the ones are drowned in the block diagram or in schematics. But they will not be used for THS8083 evaluation. Please ignore those that are not on the schematics. * * The power supply of the evaluation unit is provided by a single external power supply, which should be connected to a DIN-5 connector of the unit. Video input signals from PC graphics card can be connected to the DB15 VGA connector, or to the five separated SMA connectors on the board. For the best performance, these SMA connectors should be used. A video cable with five separated BNC connectors is shipped with the evaluation unit to fully explore the THS8083. There are no jumper selections on the board to connect or disconnect the videoinput signal from the DB15 or SMAs. Only one of the two connectors (DB15 or SMA) can be connected to input signals at the same time. DB25 is used to connect to a PC's parallel port. A window program in the PC will control the THS8083 and FPGA on the board via this connection. For details, please refer to the software manual. A 60-pin connector is used to connect to the LCD panel display via a ribbon-cable. The other end of a ribbon cable is an adapter on a small PCB, which is used for connecting to back of a LCD panel. A 6-pin connector is used to connect to a back-light module of the LCD panel. Associated with this connector, there is a potentiometer for the brightness adjustment.
* * *
Note: The Black-color wire of the back-light cable is corresponding to pin 1 of the header (U14) on the PC board. Make sure this connection is right before turn on the power. Following figure dictated the orientation of this connection.
1
SLAA099
6-pin connector
U14
Back-light inverter module
1
Figure 2. The power cable connection of back-light inverter module to THS8083 EVM board.
3. FPGA Controller
Figure3 is the top-level design schematic of the ALTERA FPGA. Figure4 is the block diagram of this design. These diagrams present a good overview of the functions of the FPGA controller. If the design of the FPGA is needed, please contact your TI local sales office. Following are the main module inside this FPGA. * * * * I2C slave module has been implemented. This allows a PC to control all the devices on board through a single interface. Timing generator generates the HS, VS timing for display module interface Data path manager controls interfacing different modes from THS8083 output data to LCD panel Register bank stores all the register settings from PC via I2C
For programmable setting, please refer to the software Manuel.
4. Jumper setting table The order of jumpers in following table is arranged according to their physical location on the PCB. Starting from the left-up corner of the board, then goes to right-down of the board. Jumper name Setting
JP22 JP5 JP52 JP2 JP62 JP57 OPEN Close Close Close Open Close
Description
Not used, always open Digital 3.3V supply, always close Digital 3.3V supply for digital data buffer, always close 3.3V of digital PLL of THS8083 These two pins are for the I2C testing, always open The THS8083 I2C address selection. When it is closed, the I2C address of THS8083 is 40H for writing and 41H for reading. When it is open, the I2C address of THS8083 is 42H for writing and 43H for reading. Analog 3.3V power supply for the PLL in THS8083
JP1
Close
2
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JP61
Close
JP21 JP35 JP20 JP43 JP40 JP41 JP42 JP23 JP26 JP68 JP67 JP9 JP69 JP70 JP71 JP46 JP50 JP12 JP17 JP38 JP39 JP13 JP47 JP48 JP49 JP60 JP25 JP27 JP4 JP16 JP15 JP33 JP36 JP34 JP37 JP29 JP30 JP3 JP32 JP53 JP7 JP8 JP10 JP11 JP14
Open Open Open Close Open Open Open Close Close Open Open Open Open Open Open Open Open Open Open Close Open Open Open Open Open Close Open Open Open Open Open Close Close Open Open Close Close Close Close Close Open Open Open Open Open
When the middle pin is connected to the 'PC' mark, the input vertical sync signal comes from a PC graphics card. When the middle pin is connected to the 'PLD' mark, the vertical sync signal is generated by the ALTERA FPGA. Not used for this version PCB Not used for this version PCB Not used for this version PCB FPGA 3.3V power supply, always closed Not used for this version PCB Not used for this version PCB Not used for this version PCB Enable/disable the data bus buffer, middle pin connected 'EN' pin will enable the bus buffer. Enable/disable the data bus buffer, middle pin connected 'EN' pin will enable the bus buffer. Always open, this is the test point of vertical sync signal. Always open, this is the test point of PLL locking signal of THS8083. Not used for this version PCB Not used for this version PCB Not used for this version PCB Not used for this version PCB Not used for this version PCB Not used for this version PCB Not used for this version PCB Not used for this version PCB FPGA output enable, always close to enable Not used for this version PCB Test point of ADCCLK1 of THS8083 Test point of ACDCLK1 of THS8083 Test point of ADCCLK2 of THS8083 Test point of DTOCLK3 of THS8083 Output enable of THS8083, always close to enable it Not used for this version PCB Not used for this version PCB Not used for this version PCB Not used for this version PCB Not used for this version PCB When middle pin is connected to 'SW', the reset signal comes from the U22(TLC7703, voltage supervising device) ADCCLK1 is selected for the input clock of FPGA If it is closed, the DTOCLK3 will be selected as the clock of FPGA Not used for this version PCB The middle pin is connected to 'EN' to enable video data output to LCD panel The middle pin is connected to 'EN' to enable video data output to LCD panel Analog 3.3V power supply, always close Analog 3.3V power supply, always close Analog 3.3V power supply, always close Not used for this version PCB Not used for this version PCB Not used for this version PCB Not used for this version PCB Not used for this version PCB
3
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JP19 JP18
Open Open
Not used for this version PCB Not used for this version PCB
4
SLAA099
Din-5 pin power supply connector Voltage regulating (3 seperated voltage output A. 3.3V digital supply B. 3.3V analog supply C. 3.3V PLL supply)
R
D_CLOCK D_HS
Data bus buffer (162244)
60-pin LCD panel connector
THS8083
Controller in FPGA (ALTERA 10K30A) 24/48 bits
48 bits
48 bits
G
DB-15 VGA Connector
B
SCL SDA
HS VS CLOCK DATA_ENABLE
Back-light connector (6 pins)
VS
HS
DB-25 to PC parallel port
Figure2 Block diagram of the THS8083 evaluation circuit board
5
SLAA099
6
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SDA SCL I2C slave module (address 80h/81h)
8-data bus
Register bank
address bus
Clock distribution
Display timing generator
V. Data output
Data path manager
Pixel counter HS VS Line/frame counter
Video data input
Figure4 Block diagram FPGA design
7
U16
R502
R503 8
C112
3
U19 1
R80
C113
C116
0
U20
R500
R501
C114
R82
C115
TP43
47
c73
4
F 89 0
44 F 0.1 79 80
48 0.1 2 3 0.001uF uF 0.1 6
5 45
3
95
.1 1
10uF
2
4 F 10 7
5
0.1 8

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