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MSP430F11x MIXED SIGNAL MICROCONTROLLER
SLAS256B - NOVEMBER 1999 - REVISED JUNE 2000
D D D D D D
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Low Supply Voltage Range 1.8 V - 3.6 V Ultralow-Power Consumption Low Operation Current, 1.6 A at 4 kHz, 2.2 V 200 A at 1 MHz, 2.2 V Five Power Saving Modes: (Standby Mode: 0.8 A, RAM Retention Off Mode: 0.1 A) Wake-Up From Standby Mode in 6 s 16-Bit RISC Architecture, 125 ns Instruction Cycle Time Basic Clock Module Configurations: - Various Internal Resistors - Single External Resistor - 32 kHz Crystal - High Frequency Crystal - Resonator - External Clock Source 16-Bit Timer With Three Capture/Compare Registers Slope A/D Converter With External Components
D D
D
Serial Onboard Programming Family Members Include: MSP430F110: 1KB + 128B Flash Memory 128B RAM MSP430F112: 4KB + 256B Flash Memory 256B RAM Available in a 20-Pin Plastic Small-Outline Wide Body (SOWB) Package and 20-Pin Plastic Thin Shrink Small-Outline Package (TSSOP)
DW OR PW PACKAGE (TOP VIEW)
TEST VCC P2.5/Rosc VSS XOUT/TCLK XIN RST/NMI P2.0/ACLK P2.1/INCLK P2.2/TA0
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
P1.7/TA2/TDO/TDI P1.6/TA1/TDI P1.5/TA0/TMS P1.4/SMCLK/TCK P1.3/TA2 P1.2/TA1 P1.1/TA0 P1.0/TACLK P2.4/TA2 P2.3/TA1
description
The Texas Instruments MSP430 series is an ultralow-power microcontroller family consisting of several devices featuring different sets of modules targeted to various applications. The microcontroller is designed to be battery operated for an extended application lifetime. With 16-bit RISC architecture, 16 bit integrated registers on the CPU, and the constant generator, the MSP430 achieves maximum code efficiency. The digitally-controlled oscillator provides fast wake-up from all low-power modes to active mode in less than 6 ms. Typical applications include sensor systems that capture analog signals, convert them to digital values, and then process the data and display them or transmit them to a host system. Stand alone RF sensor front end is another area of application. The I/O port inputs provide single slope A/D conversion capability on resistive sensors. The MSP430x11x series is an ultralow-power mixed signal microcontroller with a built in 16-bit timer and fourteen I/O pins. The MSP430x11x1 family adds a versatile analog comparator. The flash memory provides added flexibility of in-system programming and data storage without significantly increasing the current consumption of the device. The programming voltage is generated on-chip, thereby alleviating the need for an additional supply, and even allowing for reprogramming of battery-operated systems.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright (c) 2000, Texas Instruments Incorporated
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MSP430F11x MIXED SIGNAL MICROCONTROLLER
SLAS256B - NOVEMBER 1999 - REVISED JUNE 2000
AVAILABLE OPTIONS PACKAGED DEVICES TA PLASTIC 20-PIN SOWB (DW) MSP430F110IDW MSP430F112IDW PLASTIC 20-PIN TSSOP (PW) MSP430F110IPW MSP430F112IPW
- 40C to 85C
functional block diagram
XIN XOUT VCC VSS RST/NMI P1.0-7
8 Rosc Oscillator System Clock ACLK SMCLK 1/4 KB Flash +126/256B Flash INFO 128/256B RAM Power-onReset Outx CCIxA TACLK SMCLK I/O Port P1 8 I/O's, All With Interrupt Capabililty JTAG
MCLK MAB, 16 Bit MAB, 4 Bit MCB MDB, 16 Bit Bus Conv. MDB, 8 Bit
CPU Incl. 16 Reg.
Test JTAG
TEST
ACLK SMCLK
Watchdog Timer
Timer_A 3 CC Register CCR0/1/2 x = 0, 1, 2
TACLK or INCLK
INCLK I/O Port P2 6 I/O's All With Interrupt Capabililty
Outx CCIxA CCIxB
Out0 CCI1B
15/16 Bit
ACLK DCOR
P2.0 / ACLK P2.1 / INCLK
P2.5 / Rosc P2.4 / TA2 P2.3 / TA1
A pulldown resistor of 30 k is needed on F11x.
P2.2 / TA0
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Terminal Functions
TERMINAL NAME P1.0/TACLK P1.1/TA0 P1.2/TA1 P1.3/TA2 P1.4/SMCLK/TCK P1.5/TA0/TMS P1.6/TA1/TDI P1.7/TA2/TDO/TDI P2.0/ACLK P2.1/INCLK P2.2/TA0 P2.3/TA1 P2.4/TA2 P2.5/Rosc RST/NMI TEST VCC VSS XIN NO. 13 14 15 16 17 18 19 20 8 9 10 11 12 3 7 1 2 4 6 I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I General-purpose digital I/O pin/Timer_A, clock signal TACLK input General-purpose digital I/O pin/Timer_A, capture: CCI0A input, compare: Out0 output General-purpose digital I/O pin/Timer_A, capture: CCI1A input, compare: Out1 output General-purpose digital I/O pin/Timer_A, capture: CCI2A input, compare: Out2 output General-purpose digital I/O pin/SMCLK signal output/test clock, input terminal for device programming and test General-purpose digital I/O pin/Timer_A, compare: Out0 output/test mode select, input terminal for device programming and test General-purpose digital I/O pin/Timer_A, compare: Out1 output/test data input terminal General-purpose digital I/O pin/Timer_A, compare: Out2 output/test data output terminal or data input during programming General-purpose digital I/O pin/ACLK output General-purpose digital I/O pin/Timer_A, clock signal at INCLK General-purpose digital I/O pin/Timer_A, capture: CCI0B input, compare: Out0 output General-purpose digital I/O pin/Timer_A, capture: CCI1B input, compare: Out1 output General-purpose digital I/O pin/Timer_A, compare: Out2 output General-purpose digital I/O pin/Input for external resistor that defines the DCO nominal frequency Reset or nonmaskable interrupt input Select of test mode for JTAG pins on Port1. Must be tied low with less than 30 k. Supply voltage Ground reference Input terminal of crystal oscillator I/O DESCRIPTION
XOUT/TCLK 5 I/O Output terminal of crystal oscillator or test clock input TDO or TDI is selected via JTAG instruction.
short-form description
processing unit The processing unit is based on a consistent, and orthogonally-designed CPU and instruction set. This design structure results in a RISC-like architecture, highly transparent to the application development, and noted for its programming simplicity. All operations other than program-flow instructions are consequently performed as register operations in conjunction with seven addressing modes for source and four modes for destination operands.
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short-form description (continued)
CPU All sixteen registers are located inside the CPU, providing reduced instruction execution time. This reduces a register-register operation execution time to one cycle of the processor. Four registers are reserved for special use as a program counter, a stack pointer, a status register, and a constant generator. The remaining twelve registers are available as general-purpose registers. Peripherals are connected to the CPU using a data address and control buses and can be handled easily with all instructions for memory manipulation. instruction set The instructions set for this register-register architecture provides a powerful and easy-to-use assembly language. The instruction set consists of 51 instructions with three formats and seven addressing modes. Table 1 provides a summation and example of the three types of instruction formats; the addressing modes are listed in Table 2. Table 1. Instruction Word Formats
Dual operands, source-destination Single operands, destination only Relative jump, un-/conditional e.g. ADD R4, R5 e.g. CALL R8 e.g. JNE R4 + R5 R5 PC (TOS), R8 PC Jump-on equal bit = 0 Program Counter Stack Pointer Status Register Constant Generator General-Purpose Register General-Purpose Register PC/R0 SP/R1 SR/CG1/R2 CG2/R3 R4 R5
General-Purpose Register General-Purpose Register
R14 R15
Most instructions can operate on both word and byte data. Byte operations are identified by the suffix B. Examples: Instructions for word operation MOV ADD PUSH SWPB EDE,TONI #235h,&MEM R5 R5 Instructions for byte operation MOV.B ADD.B PUSH.B -- EDE,TONI #35h,&MEM R5
Table 2. Address Mode Descriptions
ADDRESS MODE Register Indexed Symbolic (PC relative) Absolute Indirect Indirect autoincrement Immediate NOTE: s = source s d = destination d SYNTAX MOV Rs, Rd MOV X(Rn), Y(Rm) MOV EDE, TONI MOV &MEM, &TCDAT MOV @Rn, Y(Rm) MOV @Rn+, RM MOV #X, TONI MOV @R10, Tab(R6) MOV @R10+, R11 MOV #45, TONI EXAMPLE MOV R10, R11 MOV 2(R5), 6(R6) R10 R11 M(2 + R5) M(6 + R6) M(EDE) M(TONI) M(MEM) M(TCDAT) M(R10) M(Tab + R6) M(R10) R11, R10 + 2 R10 #45 M(TONI) OPERATION
Rs/Rd = source register/destination register
Rn = register number
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instruction set (continued) Computed branches (BR) and subroutine calls (CALL) instructions use the same addressing modes as the other instructions. These addressing modes provide indirect addressing, ideally suited for computed branches and calls. The full use of this programming capability permits a program structure different from conventional 8- and 16-bit controllers. For example, numerous routines can easily be designed to deal with pointers and stacks instead of using flag type programs for flow control.
operation modes and interrupts
The MSP430 operating modes support various advanced requirements for ultralow-power and ultralow energy consumption. This is achieved by the intelligent management of the operations during the different module operation modes and CPU states. The advanced requirements are fully supported during interrupt event handling. An interrupt event awakens the system from each of the various operating modes and returns with the RETI instruction to the mode that was selected before the interrupt event. The different requirements of the CPU and modules, which are driven by system cost and current consumption objectives, necessitate the use of different clock signals:
D D D
Auxiliary clock ACLK (from LFXT1CLK/crystal's frequency), used by the peripheral modules Main system clock MCLK, used by the CPU and system Subsystem clock SMCLK, used by the peripheral modules
low-power consumption capabilities The various operating modes are controlled by the software through the operation of the internal clock system. This clock system provides many combinations of hardware and software capabilities to run the application with the lowest power consumption and with optimized system costs:
D D D D
Use the internal clock (DCO) generator without any external components. Select an external crystal or ceramic resonator for lowest frequency or cost. Select and activate the proper clock signals (LFXT1CLK and/or DCOCLK) and clock pre-divider function. Apply an external clock source.
Four of the control bits that influence the operation of the clock system and support fast turnon from low power operating modes are located in the status register SR. The four bits that control the CPU and the system clock generator are SCG1, SCG0, OscOff, and CPUOff:
status register R2
15 Reserved For Future Enhancements rw-0 9 8 V rw-0 7 SCG1 rw-0 6 SCG0 rw-0 5 OscOff rw-0 4 CPUOff rw-0 3 GIE rw-0 2 N rw-0 1 Z rw-0 0 C rw-0
The bits CPUOff, SCG1, SCG0, and OscOff are the most important low-power control bits when the basic function of the system clock generator is established. They are pushed onto the stack whenever an interrupt is accepted and thereby saved so that the previous mode of operation can be retrieved after the interrupt request. During execution of an interrupt handler routine, the bits can be manipulated via indirect access of the data on the stack. That allows the program to resume execution in another power operating mode after the return from interrupt (RETI). SCG1: The clock signal SMCLK, used for peripherals, is enabled when bit SCG1 is reset or disabled if the bit is set.
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SCG0:
The dc-generator is active when SCG0 is reset. The dc-generator can be deactivated only if the SCG0 bit is set and the DCOCLK signal is not used for MCLK or SMCLK. The current consumed by the dc-generator defines the basic frequency of the DCOCLK. It is a dc current. The clock signal DCOCLK is deactivated if it is not used for MCLK or SMCLK or if the SCG0 bit is set. There are two situations when the SCG0 bit cannot switch off the DCOCLK signal: 1. DCOCLK frequency is used for MCLK (CPUOff=0 and SELM.1=0). 2. DCOCLK frequency is used for SMCLK (SCG1=0 and SELS=0).
NOTE: When the current is switched off (SCG0=1) the start of the DCOCLK is delayed slightly. The delay is in the s-range (see device parameters for details).
OscOff:
The LFXT1 crystal oscillator is active when the OscOff bit is reset. The LFXT1 oscillator can only be deactivated if the OscOff bit is set and it is not used for MCLK or SMCLK. The setup time to start a crystal oscillation needs consideration when the oscillator off option is used. Mask programmable (ROM) devices can disable this feature so that the oscillator can never be switched off by software. The clock signal MCLK, used for the CPU, is active when the CPUOff bit is reset or stopped if it is set.
CPUOff:
interrupt vector addresses The interrupt vectors and the power-up starting address are located in the memory with an address range of 0FFFFh-0FFE0h. The vector contains the 16-bit address of the appropriate interrupt handler instruction sequence.
INTERRUPT SOURCE Power-up, external reset, watchdog NMI, oscillator fault, flash memory access violation INTERRUPT FLAG WDTIFG (Note1) KEYV (Note 1) NMIIFG (Notes 1 and 5) OFIFG (Notes 1 and 5) ACCVIFG (Notes 1 and 5) SYSTEM INTERRUPT Reset (non)-maskable, (non)-maskable, (non)-maskable WORD ADDRESS 0FFFEh PRIORITY 15, highest
0FFFCh 0FFFAh 0FFF8h 0FFF6h
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0, lowest
Watchdog timer Timer_A Timer_A
WDTIFG CCIFG0 (Note 2) CCIFG1, CCIFG2, TAIFG (Notes 1 and 2)
maskable maskable maskable
0FFF4h 0FFF2h 0FFF0h 0FFEEh 0FFECh 0FFEAh 0FFE8h
I/O Port P2 (eight flags - see Note 3) I/O Port P1 (eight flags)
P2IFG.0 to P2IFG.7 (Notes 1 and 2) P1IFG.0 to P1IFG.7 (Notes 1 and 2)
maskable maskable
0FFE6h 0FFE4h 0FFE2h 0FFE0h
NOTES: 1. 2. 3. 4. 5.
Multiple source flags Interrupt flags are located in the module There are eight Port P2 interrupt flags, but only six Port P2 I/O pins (P2.0-5) are implemented on the 11x devices. Nonmaskable: neither the individual nor the general interrupt enable bit will disable an interrupt event. (non)-maskable: the individual interrupt enable bit can disable an interrupt event, but the general interrupt enable cannot.
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special function registers
Most interrupt and module enable bits are collected into the lowest address space. Special function register bits that are not allocated to a functional purpose are not physically present in the device. Simple software access is provided with this arrangement. interrupt enable 1 and 2
Address 0h 7 6 5 ACCVIE rw-0 4 NMIIE rw-0 3 2 1 OFIE rw-0 0 WDTIE rw-0
WDTIE: OFIE: NMIIE: ACCVIE:
Address 01h
Watchdog timer enable signal Oscillator fault enable signal Nonmaskable interrupt enable signal Access violation at flash memory
7 6 5 4 3 2 1 0
interrupt flag register 1 and 2
Address 02h 7 6 5 4 NMIIFG rw-0 3 2 1 OFIFG rw-1 0 WDTIFG rw-0
WDTIFG: OFIFG: NMIIFG:
Address 03h
Set on overflow or security key violation or Reset on VCC power-on or reset condition at RST/NMI-pin Flag set on oscillator fault Set via RST/NMI-pin
7 6 5 4 3 2 1 0
Legend
rw: rw-0:
Bit can be read and written. Bit can be read and written. It is reset by PUC. SFR bit is not present in device.
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memory organization
MSP430F110 FFFFh FFE0h FFDFh Int. Vector FFFFh FFE0h FFDFh F000h 10FFh 1080h 128B Flash SegmentA 2 x 128B Information Flash Memory 1000h SegmentA,B 0FFFh 1 KB Boot ROM 0C00h 10FFh 02FFh 027Fh 0200h 01FFh 0100h 00FFh 0010h 000Fh 0000h 256B RAM 128B RAM 16b Per. 8b Per. SFR 0200h 01FFh 0100h 00FFh 0010h 000Fh 0000h MSP430F112 Int. Vector 4 KB Main Flash Segment0-7 Memory
1 KB Flash FC00h Segment0,1
0FFFh 0C00h
1 KB Boot ROM
16b Per. 8b Per. SFR
boot ROM containing bootstrap loader
The intention of the bootstrap loader is to download data into the flash memory module. Various write, read, and erase operations are needed for a proper download environment. The bootstrap loader is only available on F devices. functions of the bootstrap loader: Definition of read: write: apply and transmit data of peripheral registers or memory to pin P1.1 (BSLTX) read data from pin P2.2 (BSLRX) and write them into flash memory
unprotected functions
Mass erase, erase of the main memory (Segment0 to Segment7) Access to the MSP430 via the bootstrap loader is protected. It must be enabled before any protected function can be performed. The 256 bits in 0FFE0h to 0FFFFh provide the access key.
protected functions
All protected functions can be executed only if the access is enabled.
D D D D D
Write/program byte into flash memory; parameters passed are start address and number of bytes (the segment-write feature of the flash memory is not supported and not useful with the UART protocol). Segment erase of Segment0 to Segment7 in the main memory and segment erase of SegmentA and SegmentB in the information memory. Read all data in main memory and information memory. Read and write to all byte-peripheral modules and RAM. Modify PC and start program execution immediately.
NOTE: Unauthorized readout of code and data is prevented by the user's definition of the data in the interrupt memory locations.
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boot ROM containing bootstrap loader (continued)
features of the bootstrap loader are:
D D D D D D D D D D D D
UART communication protocol, fixed to 9600 baud Port pin P1.1 for transmit, P2.2 for receive TI standard serial protocol definition Implemented in flash memory version only Program execution starts with the user vector at 0FFFEh or with the bootstrap loader (start vector is at address 0C00h)
hardware resources used for serial input/output: Pins P1.1 and P2.2 for serial data transmission Test and RST/NMI to start program execution at the reset or bootstrap loader vector Basic clock module: Rsel=5, DCO=4, MOD=0, DCOCLK for MCLK and SMCLK, clock divider for MCLK and SMCLK at default: dividing by 1 Timer_A: Timer_A operates in continuous mode with MCLK source selected, input divider set to 1, using CCR0, and polling of CCIFG0. WDT: Watchdog timer is halted Interrupt: GIE=0, NMIIE=0, OFIFG=0, ACCVIFG=0 Memory allocation and stack pointer: If the stack pointer points to RAM addresses above 0220h, 6 bytes of the stack are allocated plus RAM addresses 0200h to 0219h. Otherwise the stack pointer is set to 0220h and allocates RAM from 0200h to 021Fh.
NOTE: When writing RAM data via bootstrap loader, make sure that the stack is outside the range of the data being written.
Program execution begins with the user's reset vector at FFFEh (standard method) if TEST is held low while RST/NMI goes from low to high:
VCC
RST/NMI PIN TEST PIN User Program Starts Reset Condition
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boot ROM containing bootstrap loader (continued)
Program execution begins with the bootstrap vector at 0C00h (boot ROM) if a minimum of two positive edges have been applied to TEST while RST/NMI is low, and TEST is high when RST/NMI goes from low to high. The TEST signal is normally used internally to switch pins P1.4, P1.5, P1.6, and P1.7 between their application function and the JTAG function. If the second rising edge at TEST is applied while RST/NMI is held low, the internal TEST signal is held low and the pins remain in the application mode:
VCC RST/NMI PIN
TEST PIN Bootstrap Loader Starts
TEST (Internal)
Test mode can be entered again after TEST is taken low and then back high. The bootstrap loader will not be started (via the vector in address 0C00h), if:
D D D D
There were less than two positive edges at TEST while RST/NMI is low TEST is low if RST/NMI goes from low to high JTAG has control over the MSP430 resources Supply voltage VCC drops and a POR is executed
WARNING: The bootstrap loader starts correctly only if the RST/NMI pin is in reset mode. If it is switched to the NMI function, unpredictable program execution may result. However, a bootstrap-load may be started using software and the bootstrap vector, for example the instruction BR &0C00h.
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flash memory
The flash memory consists of 512-byte segments in the main memory and 128-byte segments in the information memory. See device memory maps for specific device information. Segment0 to Segment7 can be erased individually, or altogether as a group. SegmentA and SegmentB can be erased individually, or as a group with segments 0-7. The memory in SegmentA and SegmentB is also called Information Memory. VPP is generated internally. VCC current increases during programming. During program/erase cycles, VCC must not drop below the minimum specified for program/erase operation. Program and erase timings are controlled by the flash timing generator--no software intervention is needed. The input frequency of the flash timing generator should be in the proper range and must be applied until the write/program or erase operation is completed.
0FFFFh 0FE00h 0FDFFh 0FC00h 0FBFFh 0FA00h 0F9FFh 0F800h 0F7FFh 0F600h 0F5FFh 0F400h 0F3FFh 0F200h 0F1FFh 0F000h 010FFh 01080h 0107Fh 01000h Segment0 w/ Interrupt Vectors Segment1 Segment2 Segment3 Segment4 Segment5 Segment6 Segment7 SegmentA SegmentB Information Memory Flash Main Memory
NOTE: All segments not implemented on all devices.
During program or erase, no code can be executed from flash memory and all interrupts must be disabled by setting the GIE, NMIE, ACCVIE, and OFIE bits to zero. If a user program requires execution concurrent with a flash program or erase operation, the program must be executed from memory other than the flash memory (e.g., boot ROM, RAM). In the event a flash program or erase operation is initiated while the program counter is pointing to the flash memory, the CPU will execute JMP $ instructions until the flash program or erase operation is completed. Normal execution of the previously running software then resumes. Unprogrammed, new devices may have some bytes programmed in the information memory (needed for test during manufacturing). The user should perform an erase of the information memory prior to first use. flash memory control register FCTL1 All control bits are reset during PUC. PUC is active after VCC is applied, a reset condition is applied to the RST/NMI pin, the watchdog timer expires, a watchdog access violation occurs, or an improper flash operation has been performed. A more detailed description of the control-bit functions is found in the flash memory module description (refer to MSP430x1xx User's Guide, literature number SLAU049). Any write to control register FCTL1 during erase, mass erase, or write (programming) will end in an access violation with ACCVIFG=1. Special conditions apply for segment-write mode. Refer to MSP430x1xx User's Guide, literature number SLAU049 for details.
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flash memory control register FCTL1 (continued) Read access is possible at any time without restrictions. The control bits of control register FCTL1 are:
15 8 7
SEG WRT WRT res. res. res. MEras Erase
0
res.
FCTL1 0128h
rw-0
rw-0
r0
r0
r0
rw-0
rw-0
r0
FCTL1 read: FCTL1 write:
096h 0A5h
Erase
0128h, bit1,
Erase a segment 0: No segment erase will be started. 1: Erase of one segment is enabled. The segment to be erased is defined by a dummy write into any address within the segment. The erase bit is automatically reset when the erase operation is completed. Mass Erase, main memory segments are erased together. 0: No segment erase will be started. 1: Erase of main memory segments is enabled. Erase starts when a dummy write to any address in main memory is executed. The MEras bit is automatically reset when the erase operation is completed. Bit WRT must be set for a successful write execution. If bit WRT is reset and write access to the flash memory is attempted, an access violation occurs and ACVIFG is set.
MEras
0128h, bit2,
WRT
0128h, bit6,
SEGWRT
0128h, bit7,
Bit SEGWRT may be used to reduce total programming time. Refer to MSP430x1xx User's Guide, literature number SLAU049 for details. 0: No segment-write acceleration is selected. 1: Segment-write is used. This bit needs to be reset and set between segment borders.
Table 3. Allowed Combinations of Control Bits Allowed for Flash Memory Access
FUNCTION PERFORMED Write word or byte Write word or byte in same segment, segment write mode Erase one segment by writing to any address in the target segment Erase all segments (0 to 7) but not the information memory (segments A and B) Erase all segments (0 to 7 and A and B) by writing to any address in the flash memory module SEGWRT 0 1 0 0 0 WRT 1 1 0 0 0 MEras 0 0 0 1 1 Erase 0 0 1 0 1 BUSY 0 01 0 0 0 WAIT 0 01 0 0 0 Lock 0 0 0 0 0
NOTE: The table shows all valid combinations. Any other combination will result in an access violation.
flash memory, timing generator, control register FCTL2
The timing generator (Figure 1) generates all the timing signals necessary for write, erase, and mass erase from the selected clock source. One of three different clock sources may be selected by control bits SSEL0 and SSEL1 in control register FCTL2. The selected clock source should be divided to meet the frequency requirements specified in the recommended operating conditions.
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flash memory, timing generator, control register FCTL2 (continued)
The flash timing generator is reset with PUC. It is also reset if the emergency exit bit EMEX is set. Control register FCTL2 may not be written to if the BUSY bit is set; otherwise, an access violation will occur (ACCVIFG=1). Read access is possible at any time without restrictions.
SSEL1 SSEL0 Write '1' to EMEX
FN5.......... FN0 ACLK MCLK SMCLK SMCLK 0 1 2 3 Divider, 1 .. 64 fX
PUC
Reset Flash Timing Generator
BUSY
WAIT
Figure 1. Flash Memory Timing Generator Diagram
15 8 7
SSEL1 SSEL0 FN5 FN4 FN3 FN2 FN1
0
FN0
FCTL2 012Ah
rw-0
rw-1
rw-0
rw-0
rw-0
rw-0
rw-1
rw-0
FCTL2 read: FCTL2 write:
096h 0A5h
The control bits are: FN0-FN5 012Ah, bit0-5 These six bits define the division rate of the clock signal. The division rate is 1 to 64, according to the digital value of FN5 to FN0 plus one. Clock source select 0: 1: 2: 3: ACLK MCLK SMCLK SMCLK
SSEL0, SSEL1
012Ah, bit6,7
The flash timing generator is reset with PUC. It is also reset if the EMEX bit is set.
flash memory control register FCTL3
There are no restrictions to modify this control register.
15 8 7
res. res. EMEX Lock WAIT ACCV IFG KEYV
0
BUSY
FCTL3 012Ch
r0
r0
rw-0
rw-1
rw-1
rw-0
rw-(0)
r(w)-0
FCTL3 read: FCTL3 write:
096h 0A5h
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MSP430F11x MIXED SIGNAL MICROCONTROLLER
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flash memory control register FCTL3 (continued)
BUSY 012Ch, bit0, The BUSY bit shows if an access to the flash memory is allowed (BUSY=0), or if an access violation occurs. The BUSY bit is read-only, but a write operation is allowed. The BUSY bit should be tested before each write and erase cycle. The flash timing-generator hardware immediately sets the BUSY bit after start of a write, segment-write, erase, or mass erase operation. If the timing generator has completed the operation, the BUSY bit is reset by the hardware. No program code can be executed from the busy flash memory during the entire program or erase cycle. 0: Flash memory is not busy. 1: Flash memory is busy, and remains in busy state if segment write function is in wait mode. Key violation 0: Key 0A5h (high byte) was not violated. 1: Key 0A5h (high byte) was violated. Violation occurs when a write access to registers FCTL1, FCTL2, or FCTL3 is executed and the high byte is not equal to 0A5h. If the security key is violated, bit KEYV is set and a PUC is performed. ACCVIFG, 012Ch, bit2 Access violation interrupt flag The access-violation flag is set when any combination of control bits other than those shown in Table 3 is attempted, or an instruction is fetched while a segment-write operation is active. Reading the control registers will not set the ACCVIFG bit. NOTE: The respective interrupt-enable bit ACCVIE is located in the interrupt enable register IE1 in the special function register. The software can set the ACCVIFG bit. If set by software, an NMI is also executed. WAIT, 012CH, bit3 In the segment-write mode, the WAIT bit indicates that data has been written and the flash memory is prepared to receive the next data for programming. The WAIT bit is read only, but a write to the WAIT bit is allowed. 0: The segment-write operation has began and programming is in progress. 1: The segment-write operation is active and data programming is complete.
KEYV,
012Ch, bit1
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flash memory control register FCTL3 (continued)
LOCK 012Ch, bit4, The lock bit may be set during any write, segment-erase, or mass-erase request. Any active sequence in progress is completed normally. In segment-write mode, the SEGWRT bit is reset and the WAIT bit is set after the mode ends. The lock bit is controlled by software or hardware. If an access violation occurs and the ACCVIFG is set, the LOCK bit is set automatically. 0: Flash memory may be read, programmed, erased, or mass erased. 1: Flash memory may be read but not programmed, erased, or mass erased. A current program, erase, or mass-erase operation will complete normally. The access-violation interrupt flag ACCVIFG is set when data are written to the flash memory module while the lock bit is set. EMEX, 012Ch, bit5, Emergency exit. The emergency exit should only be used if the flash memory write or erase operation is out of control. 0: No function 1: Stops the active operation immediately, and shuts down all internal parts in the flash memory controller. Current consumption immediately drops back to the active mode. All bits in control register FCTL1 are reset. Since the EMEX bit is automatically reset by hardware, the software always reads EMEX as 0.
flash memory, interrupt and security key violation
One NMI vector is used for three NMI events: RST/NMI (NMIIFG), oscillator fault (OFIFG), and flash-memory access violation (ACCVIFG). The software can determine the source of the interrupt request since all flags remain set until they are reset by software. The enable flag(s) should be set simultaneously with one instruction before the return-from-interrupt RETI instruction. This ensures that the stack remains under control. A pending NMI interrupt request will not increase stack demand unnecessarily.
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MSP430F11x MIXED SIGNAL MICROCONTROLLER
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ACCV
S FCTL1.1 ACCVIFG
ACCVIE IE1.5 Clear
Flash Module Flash Module Flash Module
PUC
RST/NMI
POR KEYV
PUC VCC
PUC
System Reset Generator
POR
NMIFG
S IFG1.4 Clear
NMIRS
NMIES TMSEL NMI WDTQn EQU PUC POR
PUC
NMIIE IE1.4 Clear IFG1.0 Clear WDT S WDTIFG
IRQ
PUC
Counter
OSCFault
S IFG1.1 OFIFG
POR
OFIF IE1.1 Clear NMI_IRQA
IRQA TIMSEL
WDTIE
IE1.0 Clear
PUC Watchdog Timer Module
PUC
IRQA: Interrupt Request Accepted
Figure 2. Block Diagram of NMI Interrupt Sources
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peripherals
Peripherals are connected to the CPU through data, address, and control buses, and they can be handled easily with memory manipulation instructions.
oscillator and system clock
Three clocks are used in the system--the system (master) clock MCLK, the subsystem (master) clock SMCLK, and the auxiliary clock ACLK: Main system clock MCLK, used by the CPU and the system Subsystem clock SMCLK, used by the peripheral modules Auxiliary clock ACLK, originated by LFXT1CLK (crystal frequency) and used by the peripheral modules After a POR, the DCOCLK is used by default, the DCOR bit is reset, and the DCO is set to the nominal initial frequency. Additionally, if LFXT1CLK fails as the source for MCLK, the DCOCLK is automatically selected to ensure fail-safe operation. SMCLK can be generated from LFXT1CLK or DCOCLK. ACLK is always generated from LFXT1CLK. The crystal oscillator can be defined to operate with watch crystals (32768 Hz) or with higher-frequency ceramic resonators or crystals. The crystal or ceramic resonator is connected across two terminals. No external components are required for watch-crystal operation. If the high frequency XT1 mode is selected, external capacitors from XIN to VSS and XOUT to VSS are required as specified by the crystal manufacturer. The LFXT1 oscillator starts after applying VCC. If the OscOff bit is set to 1, the oscillator stops when it is not used for MCLK. The clock signals ACLK and SMCLK may be used externally via port pins. Different application requirements and system conditions dictate different system clock requirements, including: High frequency for quick reaction to system hardware requests or events Low frequency to minimize current consumption, EMI, etc. Stable peripheral clock for timer applications, such as real-time clock (RTC) Start-stop operation to be enabled with minimum delay
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MSP430F11x MIXED SIGNAL MICROCONTROLLER
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oscillator and system clock (continued)
DIVA 2 LFXT1CLK /1, /2, /4, /8 OSCOff XIN SELM LFXT1 OSCILLATOR 2 3 0,1 XOUT 2 DCOCLK VCC VCC Rsel SCG0 DCO 3 0 MOD 5 SELS DIVS 2 0 /1, /2, /4, /8, Off 1 SMCLKGEN SMCLK Subsystem Clock SCG1 MCLKGEN /1, /2, /4, /8, Off MCLK Main System Clock 2 XTS ACLKGEN DIVM CPUOff ACLK Auxiliary Clock
DC Generator DCGEN DCOR
Digital Controlled Oscillator (DCO) + Modulator (MOD) DCOMOD
P2.5/Rosc
1
The DCO-Generator is connected to pin P2.5/Rosc if DCOR control bit is set. The port pin P2.5/Rosc is selected if DCOR control bit is reset (initial state). P2.5
Figure 3. Clock Signals Two clock sources, LFXT1CLK and DCOCLK, can be used to drive the MSP430 system. The LFXT1CLK is generated from the LFXT1 crystal oscillator. The LFXT1 crystal oscillator can operate in three modes--low frequency (LF), moderate frequency (XT1), and external input mode. The LFXT1 crystal oscillator may be switched off when it is not in use. DCOCLK is generated from the DCO. The nominal DCO frequency is defined by the dc generator and can be set by one external resistor, or can be set to one of eight values with integrated resistors. Additional adjustments and modulations of DCOCLK are possible by software manipulation of registers in the DCO module. DCOCLK is stopped automatically when it is not used by the CPU or peripheral modules. The dc generator can be shut down with the SCG0 bit to realize additional power savings when DCOCLK is not in use.
NOTE: The system clock generator always starts with the DCOCLK selected for MCLK (CPU clock) to ensure proper start of program execution. The software defines the final system clock generation through control bit manipulation.
digital I/O There are two eight-bit I/O ports, port P1 and port P2 - implemented (11x parts only have six port P2 I/O signals available on external pins). Both ports, P1 and P2, have seven control registers to give maximum flexibility of digital input/output to the application: * All individual I/O bits are programmable independently. * Any combination of input, output, and interrupt conditions is possible. * Interrupt processing of external events is fully implemented for all eight bits of port P1 and for six bits of port P2. * Read/write access to all registers with all instructions
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digital I/O (continued) The seven registers are:
* * * * * * *
Input register Output register Direction register Interrupt edge select Interrupt flags Interrupt enable
8 bits at port P1/P2 8 bits at port P1/P2 8 bits at port P1/P2 8 bits at port P1/P2 8 bits at port P1/P2 8 bits at port P1/P2
contains information at the pins contains output information controls direction input signal change necessary for interrupt indicates if interrupt(s) are pending contains interrupt enable bits determines if pin(s) have port or module function
Selection (Port or Mod.) 8 bits at port P1/P2
All these registers contain eight bits. Two interrupt vectors are implemented: one commonly used for any interrupt event on ports P1.0 to P1.7, and one commonly used for any interrupt event on ports P2.0 to P2.7.
NOTE: Six bits of port P2, P2.0 to P2.5, are available on external pins - but all control and data bits for port P2 are implemented.
Watchdog Timer The primary function of the watchdog timer (WDT) module is to perform a controlled system restart after a software problem has occurred. If the selected time interval expires, a system reset is generated. If this watchdog function is not needed in an application, the module can work as an interval timer, which generates an interrupt after the selected time interval. The watchdog timer counter (WDTCNT) is a 16-bit up-counter which is not directly accessible by software. The WDTCNT is controlled through the watchdog timer control register (WDTCTL), which is a 16-bit read/write register. Writing to WDTCTL is, in both operating modes (watchdog or timer), only possible by using the correct password in the high-byte. The low-byte stores data written to the WDTCTL. The high-byte must be the password 05Ah. If any value other than 05Ah is written to the high-byte of the WDTCTL, a system reset PUC is generated. When the password is read, its value is 069h. This minimizes accidental write operations to the WDTCTL register. In addition to the watchdog timer control bits, there are two bits included in the WDTCTL register that configure the NMI pin. Timer_A (Three capture/compare registers) The Timer_A module on 11x devices offers one sixteen bit counter and three capture/compare registers. The timer clock source can be selected to come from two external sources TACLK (SSEL=0) or INCLK (SSEL=3), or from two internal sources, the ACLK (SSEL=1) or SMCLK (SSEL=2). The clock source can be divided by one, two, four, or eight. The timer can be fully controlled (in word mode) since it can be halted, read, and written. It can be stopped, run continuously, counted up or up/down, using one compare block to determine the period. The three capture/compare blocks are configured by the application to run in capture or compare mode. The capture mode is primarily used to measure external or internal events using any combination of positive, negative, or both edges of the signal. Capture mode can be started and stopped by software. Three different external events TA0, TA1, and TA2 can be selected. At capture/compare register CCR2 the ACLK is the capture signal if CCI2B is selected. Software capture is chosen if CCISx=2 or CCISx=3 (see Figure 4). The compare mode is primarily used to generate timings for the software or application hardware, or to generate pulse-width modulated output signals for various purposes like D/A conversion functions or motor control. An individual output module is assigned to each of the three capture/compare registers. The output modules can run independently of the compare function, or can be triggered in several ways.
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Timer_A (3 capture/compare registers) (continued)
32 kHz to 8 MHz Timer Clock 15 Input Divider Data 16-Bit Timer
SSEL1 P1.0 TACLK ACLK SMCLK INCLK
SSEL0 0 1 2 3 ID1
0 Mode Control
P2.1
16-Bit Timer CLK RC Carry/Zero
Equ0
ID0
POR/CLR Timer Bus
MC1
MC0
Set_TAIFG
P1.1 P2.2
CCIS01 CCIS00 0 CCI0A 1 CCI0B 2 GND 3 VCC
15 Capture Capture Mode Capture/Compare Register CCR0 15 Comparator 0
0
Capture/Compare Register CCR0 OM02 OM01 OM00 Out 0 P1.1 P1.5 P2.2 EQU0
0
Output Unit 0
CCI0 CCM01 CCM00
P1.2 P2.3
CCIS11 CCIS10 0 CCI1A 1 CCI1B 2 GND 3 VCC
15 Capture Capture Mode Capture/Compare Register CCR1 15 Comparator 1
0
Capture/Compare Register CCR1 OM12 OM11 OM10 Out 1 P1.2
0
Output Unit 1 EQU1
P1.6 P2.3
CCI1 CCM11
CCM10
P1.3 ACLK
CCIS21 CCIS20 0 CCI2A 1 CCI2B 2 GND 3 VCC
15 Capture Capture Mode Capture/Compare Register CCR2 15 Comparator 2
0
Capture/Compare Register CCR2 OM22 OM21 OM20 Out 2 P1.3
0
Output Unit 2 EQU2
P1.7 P2.4
CCI2 CCM21 CCM20
Figure 4. Timer_A, MSP430x11x Configuration Two interrupt vectors are used by the Timer_A module. One individual vector is assigned to capture/compare block CCR0, and one common interrupt vector is implemented for the timer and the other two capture/compare blocks. The three interrupt events using the same vector are identified by an individual interrupt vector word. The interrupt vector word is used to add an offset to the program counter to continue the interrupt handler software at the corresponding program location. This simplifies the interrupt handler and gives each interrupt event the same overhead of 5 cycles in the interrupt handler.
UART
Serial communication is implemented by using software and one capture/compare block. The hardware supports the output of the serial-data stream, bit by bit, with the timing determined by the comparator/timer. The data input uses the capture feature. The capture flag finds the start of a character, while the compare feature latches the input-data stream, bit by bit. The software/hardware interface connects the mixed-signal controller to external devices, systems, or networks.
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peripheral file map
PERIPHERALS WITH WORD ACCESS Timer_A Reserved Reserved Reserved Reserved Capture/compare register Capture/compare register Capture/compare register Timer_A register Reserved Reserved Reserved Reserved Capture/compare control Capture/compare control Capture/compare control Timer_A control Timer_A interrupt vector Flash control 3 Flash control 2 Flash control 1 Watchdog/timer control PERIPHERALS WITH BYTE ACCESS System Clock Basic clock sys. control2 Basic clock sys. control1 DCO clock freq. control Port P2 selection Port P2 interrupt enable Port P2 interrupt edge select Port P2 interrupt flag Port P2 direction Port P2 output Port P2 input Port P1 selection Port P1 interrupt enable Port P1 interrupt edge select Port P1 interrupt flag Port P1 direction Port P1 output Port P1 input SFR interrupt flag2 SFR interrupt flag1 SFR interrupt enable2 SFR interrupt enable1 BCSCTL2 BCSCTL1 DCOCTL P2SEL P2IE P2IES P2IFG P2DIR P2OUT P2IN P1SEL P1IE P1IES P1IFG P1DIR P1OUT P1IN IFG2 IFG1 IE2 IE1 058h 057h 056h 02Eh 02Dh 02Ch 02Bh 02Ah 029h 028h 026h 025h 024h 023h 022h 021h 020h 003h 002h 001h 000h 017Eh 017Ch 017Ah 0178h 0176h 0174h 0172h 0170h 016Eh 016Ch 016Ah 0168h 0166h 0164h 0162h 0160h 012Eh 012Ch 012Ah 0128h 0120h
CCR2 CCR1 CCR0 TAR
CCTL2 CCTL1 CCTL0 TACTL TAIV FCTL3 FCTL2 FCTL1 WDTCTL
Flash Memory
Watchdog
Port P2
Port P1
Special Function
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absolute maximum ratings
Voltage applied at VCC to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 4.1 V Voltage applied to any pin (referenced to VSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to VCC+0.3 V Diode current at any device terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 mA Storage temperature, Tstg (unprogrammed device) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55C to 150C Storage temperature, Tstg (programmed device) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40C to 85C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE: All voltages referenced to VSS.
recommended operating conditions
MIN Supply voltage during program execution, VCC (see Note 6) Supply voltage during program/erase flash memory, VCC Supply voltage, VSS Operating free-air temperature range, TA LF mode selected, XTS=0 LFXT1 crystal f t l frequency, f(LFXT1) (see Note 7) XT1 mode selected, XTS=1 selected Watch crystal Ceramic resonator Crystal VCC = 1.8 V Processor frequency f(system) (MCLK signal) (y ) Flash timing generator frequency, f(FTG) Cumulative program time, segment write, t(CPT) (see Note 8) Low-level input voltage (TCK, TMS, TDI, RST/NMI), VIL (excluding XIN, XOUT) High-level input voltage (TCK, TMS, TDI, RST/NMI), VIH (excluding XIN, XOUT) Input levels at XIN XOUT XIN, VIL(XIN, XOUT) VIH(XIN, XOUT) VCC = 2.7 V/3.6 V VCC = 2.2 V/3 V VCC = 2.2 V/3 V VCC = 2.2 V/3 V 22 VSS 0.8VCC VSS 0.8xVCC VCC = 2.2 V VCC = 3.6 V 450 1000 dc dc dc 257 -40 32 768 8000 8000 2 5 8 476 3 VSS+0.6 VCC 0.2xVCC VCC 1.8 2.7 0 85 NOM MAX 3.6 3.6 UNITS V V V C Hz kHz MHz MHz MHz kHz ms V V V
NOTES: 6. The LFXT1 oscillator in LF-mode requires a resistor of 5.1 M from XOUT to VSS when VCC <2.5 V. The LFXT1 oscillator in XT1-mode accepts a ceramic resonator or a crystal frequency of 4 MHz at VCC 2.2 V. The LFXT1 oscillator in XT1-mode accepts a ceramic resonator or a crystal frequency of 8 MHz at VCC 2.8 V. 7. The LFXT1 oscillator in LF-mode requires a watch crystal. The LFXT1 oscillator in XT1-mode accepts a ceramic resonator or a crystal. 8. The cumulative program time must not be exceeded during a segment-write operation.
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recommended operating conditions (continued)
MSP430F11x Devices
f(system) - Maximum Processor Frequency - MHz 9 8 7 6 5 4 3 2 1 0 0 1 2 3 VCC - Supply Voltage - V 4 2 MHz at 1.8 V 5 MHz at 2.2 V 8 MHz at 3.6 V
NOTE: Minimum processor frequency is defined by system clock. Flash program or erase operations require a minimum VCC of 2.7 V.
Figure 5. Frequency vs Supply Voltage
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MSP430F11x MIXED SIGNAL MICROCONTROLLER
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electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
supply current (into VCC) excluding external current (f(system) = 1 MHz)
PARAMETER TEST CONDITIONS TA = -40C +85C, f(MCLK) = f(SMCLK) = 1 MHz MHz, f(ACLK) = 32,768 Hz TA = -40C +85C, f(MCLK) = f(SMCLK) = f(ACLK) = 4096 Hz I(CPUOff) Low-power mode, Low power mode (LPM0) TA = -40C +85C, f(MCLK) = 0 f(SMCLK) = 1 MHz 0, MHz, f(ACLK) = 32,768 Hz TA = -40C +85C, f(MCLK) = f(SMCLK) = 0 MHz MHz, f(ACLK) = 32,768 Hz, SCG0 = 0 TA = -40C TA = 25C I(LPM3) Low power mode (LPM3) Low-power mode, TA = 85C TA = -40C TA = 25C TA = 85C I( (LPM4) ) Low-power mode, (LPM4) TA = -40C TA = 25C f(MCLK) = 0 MHz f( (SMCLK) = 0 MHz, ) H f(ACLK) = 0 Hz, SCG0 = 1 VCC = 3 V VCC = 2.2 V VCC = 3 V VCC = 2.2 V VCC = 3 V VCC = 2.2 V VCC = 3 V VCC = 2.2 V VCC = 3 V VCC = 2.2 V MIN TYP 200 300 1.6 3 32 55 11 17 0.8 0.7 1.6 1.8 1.6 2.3 0.1 VCC = 2.2 V/3 V 0.1 0.8 MAX 250 350 3 4.3 45 70 14 22 1.2 1 2.3 2.2 1.9 3.4 0.5 0.5 1.9 A A A A A UNIT A
I(AM)
Active mode
A
I(LPM2)
Low-power mode, Low power mode (LPM2)
TA = 85C NOTE: All inputs are tied to 0 V or VCC. Outputs do not source or sink any current.
current consumption of active mode versus system frequency, F version IAM = IAM[1 MHz] x fsystem [MHz] current consumption of active mode versus supply voltage, F version IAM = IAM[3 V] + 120 A/V x (VCC-3 V) Schmitt-trigger inputs Port 1 to Port P2; P1.0 to P1.7, P2.0 to P2.5
PARAMETER VIT IT+ VIT IT- Vh hys Positive-going Positive going input threshold voltage Negative going input threshold voltage Negative-going Input voltage hysteresis, (VIT - VIT ) hysteresis IT+ IT- TEST CONDITIONS VCC = 2.2 V VCC = 3 V VCC = 2.2 V VCC = 3 V VCC = 2.2 V VCC = 3 V MIN 1.1 1.5 0.4 .90 0.3 0.5 TYP MAX 1.3 1.8 0.9 1.2 1 1.4 UNIT V V V
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electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
outputs Port 1 to P2; P1.0 to P1.7, P2.0 to P2.5
PARAMETER TEST CONDITIONS I(OHmax) = -1.5 mA I(OHmax) = -6 mA I(OHmax) = -1.5 mA I(OHmax) = -6 mA I(OHmax) = -1 mA I(OHmax) = -3.4 mA I(OHmax) = -1 mA I(OHmax) = -3.4 mA I(OLmax) = 1.5 mA I(OLmax) = 6 mA I(OLmax) = 1.5 mA VCC = 2 2 V 2.2 VCC = 3 V VCC = 2 2 V 2.2 VCC = 3 V VCC = 2 2 V 2.2 VCC = 3 V See Note 9 See Note 10 See Note 9 See Note 10 See Note 11 See Note 11 See Note 11 See Note 11 See Note 9 See Note 10 See Note 9 MIN VCC-0.25 VCC-0.6 VCC-0.25 VCC-0.6 VCC-0.25 VCC-0.6 VCC-0.25 VCC-0.6 VSS VSS VSS TYP MAX VCC VCC VCC VCC VCC VCC VCC VCC VSS+0.25 VSS+0.6 VSS+0.25 UNIT
VOH
High-level output voltage g g Port 1
V
VOH
High-level output voltage g g Port 2
V
VOL
Low-level output voltage g Port 1 and Port 2
V
I(OLmax) = 6 mA See Note 10 VSS VSS+0.6 NOTES: 9. The maximum total current, IOHmax and IOLmax, for all outputs combined, should not exceed 12 mA to hold the maximum voltage drop specified. 10. The maximum total current, IOHmax and IOLmax, for all outputs combined, should not exceed 48 mA to hold the maximum voltage drop specified. 11. One output loaded at a time.
leakage current
PARAMETER TEST CONDITIONS Port P1: P1.x, 0 x 7 (see Notes 12 and 13) Port P2: P2.x, 0 x 5 (see Notes 12 and 13) VCC = 2.2 V/3 V, VCC = 2.2 V/3 V, MIN TYP MAX 50 nA 50 UNIT
Ilkg(Px.x) lk (P )
High impedance leakage current High-impedance
NOTES: 12. The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted. 13. The leakage of the digital port pins is measured individually. The port pin must be selected for input and there must be no optional pullup or pulldown resistor.
inputs Px.x, TAx
PARAMETER t( ) (int) External interrupt timing TEST CONDITIONS Port P1, P2: P1.x to P2.x, External trigger signal for the interrupt flag, (see Note 14) VCC 2.2 V/3 V 2.2 V 3V 2.2 V/3 V t( (cap) ) Timer_A, capture timing TA0, TA1, TA2. (see Note 15) 2.2 V 3V MIN 1.5 62 50 1.5 62 50 TYP MAX UNIT cycle ns cycle ns
NOTES: 14. The external signal sets the interrupt flag every time the minimum tint cycle and time parameters are met. It may be set even with trigger signals shorter than tint. Both the cycle and timing specifications must be met to ensure the flag is set. tint is measured in MCLK cycles. 15. The external capture signal triggers the capture event every time when the minimum tcap cycles and time parameters are met. A capture may be triggered with capture signals even shorter than tcap. Both the cycle and timing specifications must be met to ensure a correct capture of the 16-bit timer value and to ensure the flag is set.
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electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued)
internal signals TAx, SMCLK at Timer_A
PARAMETER f(IN) f(TAint) Input frequency Timer_A clock frequency TEST CONDITIONS Internal TA0, TA1, TA2, tH = tL TA0 TA1 TA2 Internally, SMCLK signal applied VCC 2.2 V 3V 2.2 V/3 V dc MIN TYP MAX 8 10 fSystem UNIT MHz
outputs P1.x, P2.x, TAx
PARAMETER f(P20) f(TAx) Output frequency P2.0/ACLK, TEST CONDITIONS CL = 20 pF TA0, TA1, TA2, CL = 20 pF Internal clock source, SMCLK signal applied (See Note 16) fSMCLK = fLFXT1 = fXT1 fSMCLK = fLFXT1 = fLF P1.4/SMCLK, CL = 20 pF t(Xdc) Duty cycle of O/P frequency P2.0/ACLK, CL = 20 pF fSMCLK = fLFXT1/n fSMCLK = fDCOCLK fP20 = fLFXT1 = fXT1 fP20 = fLFXT1 = fLF 2.2 V/3 V VCC 2.2 V/3 V 2.2 V/3 V MIN TYP MAX fSystem dc 40% 2 2 V/3 V 2.2 35% 50%- 15 ns 50%- 15 ns 40% 2.2 V/3 V 30% 50% 0 50 ns 50% 50% fSystem 60% 65% 50%+ 15 ns 50%+ 15 ns 60% 70% MHz UNIT
t(TAdc) TA0, TA1, TA2, 2.2 V/3 V NOTE 16: The limits of the system clock MCLK have to be met. MCLK and SMCLK can have different frequencies.
fP20 = fLFXT1/n CL = 20 pF, Duty cycle = 50%
PUC/POR
PARAMETER t(POR_delay) V(POR) ( ) V(min) t(reset) POR TA = -40C TA = 25C TA = 85C PUC/POR Reset is accepted internally 1.4 VCC = 2.2 V/3 V 22 1.1 0.8 0 2 TEST CONDITIONS MIN TYP 150 MAX 250 1.8 1.5 1.2 0.4 UNIT s V V V V s
V VCC
V (POR) V (min) POR No POR POR
t
Figure 6. Power-On Reset (POR) vs Supply Voltage
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MSP430F11x MIXED SIGNAL MICROCONTROLLER
SLAS256B - NOVEMBER 1999 - REVISED JUNE 2000
electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued)
2.0 1.8 1.6 V POR [V] 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 -40 -20 0 20 Temperature [C] 40 60 80 25C 1.4 Min 1.1 0.8 1.5 Max 1.2 1.8
Figure 7. V(POR) vs Temperature crystal oscillator,LFXT1
PARAMETER TEST CONDITIONS XTS=0; LF mode selected. VCC = 2.2 V / 3 V XTS=1; XT1 mode selected. VCC = 2.2 V / 3 V (Note 17) XTS=0; LF mode selected. VCC = 2.2 V / 3 V XTS=1; XT1 mode selected. VCC = 2.2 V / 3 V (Note 17) MIN TYP 12 pF 2 12 pF F 2 MAX UNIT
C(XIN)
Input capacitance
C(XOUT)
Out ut ca acitance Output capacitance
NOTE 17: Requires external capacitors at both terminals. Values are specified by crystal manufacturers.
RAM
PARAMETER MIN TYP MAX UNIT V(RAMh) CPU halted (see Note 18) 1.6 V NOTE 18: This parameter defines the minimum supply voltage VCC when the data in the program memory RAM remains unchanged. No program execution should happen during this supply voltage condition.
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MSP430F11x MIXED SIGNAL MICROCONTROLLER
SLAS256B - NOVEMBER 1999 - REVISED JUNE 2000
electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued)
DCO
PARAMETER f(DCO03) f(DCO13) f(DCO23) f(DCO33) f(DCO43) f(DCO53) f(DCO63) f(DCO73) f(DCO77) f(DCO47) S(Rsel) S(DCO) Dt DV TEST CONDITIONS Rsel = 0, DCO = 3, MOD = 0, DCOR = 0, 3 0 0 l0 Rsel = 1, DCO = 3, MOD = 0, DCOR = 0, 3 0 0 l1 Rsel = 2, DCO = 3, MOD = 0, DCOR = 0, 3 0 0 l2 Rsel = 3, DCO = 3, MOD = 0, DCOR = 0, 3 0 0 l3 Rsel = 4, DCO = 3, MOD = 0, DCOR = 0, 3 0 0 l4 Rsel = 5, DCO = 3, MOD = 0, DCOR = 0, 3 0 0 l5 Rsel = 6, DCO = 3, MOD = 0, DCOR = 0, 3 0 0 l6 Rsel = 7, DCO = 3, MOD = 0, DCOR = 0, 3 0 0 l7 Rsel = 7, DCO = 7, MOD = 0, DCOR = 0, 7 7 0 0 Rsel = 4, DCO = 7, MOD = 0, DCOR = 0, 7 0 0 l4 SR = fRsel+1/fRsel SDCO = fDCO+1/fDCO Temperature drift, Rsel = 4, DCO = 3, MOD = 0 (see Note 18) Drift with VCC variation, Rsel = 4, DCO = 3, MOD = 0 (see Note 19) TA = 25C TA = 25C TA = 25C TA = 25C TA = 25C TA = 25C TA = 25C TA = 25C TA = 25C TA = 25C VCC = 2.2 V VCC = 3 V VCC = 2.2 V VCC = 3 V VCC = 2.2 V VCC = 3 V VCC = 2.2 V VCC = 3 V VCC = 2.2 V VCC = 3 V VCC = 2.2 V VCC = 3 V VCC = 2.2 V VCC = 3 V VCC = 2.2 V VCC = 3 V VCC = 2.2 V VCC = 3 V VCC = 2 2 V/3 V 2.2 VCC = 2.2 V/3 V VCC = 2.2 V/3 V VCC = 2.2 V VCC = 3 V VCC = 2.2 V/3 V MIN 0.08 0.08 0.14 0.14 0.22 0.22 0.37 0.37 0.61 0.61 1 1 1.6 1.69 2.4 2.7 4 4.4 TYP 0.12 0.13 0.19 0.18 0.30 0.28 0.49 0.47 0.77 0.75 1.2 1.3 1.9 2.0 2.9 3.2 4.5 4.9 MAX 0.15 0.16 0.23 0.22 0.36 0.34 0.59 0.56 0.93 0.9 1.5 1.5 2.2 2.29 3.4 3.65 4.9 5.4 MHz ratio UNIT MHz MHz MHz
MHz
MHz
MHz
MHz
MHz
MHz
FDCO40 FDCO40 FDCO40 x1.7 x2.1 x2.5 1.35 1.07 -0.31 -0.33 0 1.65 1.12 -0.36 -0.38 5 2 1.16 -0.40 -0.43 10
%/C %/V
NOTE 19: These parameters are not production tested.
f(DCOx7)
Max Min
f(DCOx0)
Max Min
28
IIIIII IIIIII IIIIII IIIIII
2.2 V 3V VCC
Frequency Variance
1 f DCOCLK
0
1
2
3
4
5
6
7
DCO Steps
Figure 8. DCO Characteristics
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MSP430F11x MIXED SIGNAL MICROCONTROLLER
SLAS256B - NOVEMBER 1999 - REVISED JUNE 2000
electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued)
principle characteristics of the DCO
D D D D
Individual devices have a minimum and maximum operation frequency. The specified parameters for fDCOx0 to fDCOx7 are valid for all devices. The DCO control bits DCO0, DCO1 and DCO2 have a step size as defined in parameter SDCO. The modulation control bits MOD0 to MOD4 select how often fDCO+1 is used within the period of 32 DCOCLK cycles. fDCO is used for the remaining cycles. The frequency is an average = fDCO x (2MOD/32). The ranges selected by RSel4 to RSel5, RSel5 to RSel6, and RSel6 to RSel7 are overlapping.
wake-up from lower power modes (LPMx)
PARAMETER t(LPM0) t(LPM2) t( (LPM3) ) TEST CONDITIONS VCC = 2.2 V/3 V VCC = 2.2 V/3 V f(MCLK) = 1 MHz, f(MCLK) = 2 MHz, f(MCLK) = 3 MHz, f(MCLK) = 1 MHz, f(MCLK) = 2 MHz, VCC = 2.2 V/3 V VCC = 2.2 V/3 V VCC = 2.2 V/3 V VCC = 2.2 V/3 V VCC = 2.2 V/3 V VCC = 2.2 V/3 V MIN TYP 100 100 6 6 6 6 6 6 s s MAX UNIT ns
Delay time (see Note 20)
t( (LPM4) )
f(MCLK) = 3 MHz, NOTE 20: Parameter applicable only if DCOCLK is used for MCLK.
JTAG/programming
PARAMETER f(TCK) I(DD-PGM) I(DD-ERASE) t(retention) ( t ti ) TEST CONDITIONS TCK frequency, JTAG/test (see Note 21) frequency Current during program cycle (see Note 22) Current during erase cycle (see Note 22) Write/erase cycles VCC = 2.2 V VCC = 3 V VCC = 2.7 V/3.6 V VCC = 2.7 V/3.6 V 104 MIN dc dc 3 3 105 TYP MAX 5 10 5 5 UNIT MHz mA mA
Data retention TA = 25C 100 Year NOTES: 21. f(TCK) may be restricted to meet the timing requirements of the module selected. 22. Duration of the program/erase cycle is determined by f(FTG) applied to the flash timing controller. It can be calculated as follows: t(word write) = 35 x 1/f(FTG) t(segment write, byte 0) = 30 x 1/f(FTG) t(segment write, byte 1 - 63) = 20 x 1/f(FTG) t(mass erase) = 5297 x 1/f(FTG) t(page erase) = 4819 x 1/f(FTG)
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MSP430F11x MIXED SIGNAL MICROCONTROLLER
SLAS256B - NOVEMBER 1999 - REVISED JUNE 2000
APPLICATION INFORMATION input/output schematic
Port P1, P1.0 to P1.3, input/output with Schmitt-trigger
P1SEL.x P1DIR.x Direction Control From Module P1OUT.x Module X OUT 0 1 0 1 Pad Logic P1.0 - P1.3
P1IN.x EN Module X IN P1IRQ.x D
P1IE.x P1IFG.x Q EN Set Interrupt Flag
Interrupt Edge Select
P1IES.x P1SEL.x
NOTE: x = Bit/identifier, 0 to 3 for port P1 Direction control from module P1DIR.0 P1DIR.1 P1DIR.2
PnSel.x P1Sel.0 P1Sel.1 P1Sel.2
PnDIR.x P1DIR.0 P1DIR.1 P1DIR.2
PnOUT.x P1OUT.0 P1OUT.1 P1OUT.2 P1OUT.3
Module X OUT VSS Out0 signal Out1 signal Out2 signal
PnIN.x P1IN.0 P1IN.1 P1IN.2 P1IN.3
Module X IN TACLK CCI0A CCI1A CCI2A
PnIE.x P1IE.0 P1IE.1 P1IE.2 P1IE.3
PnIFG.x P1IFG.0 P1IFG.1 P1IFG.2 P1IFG.3
PnIES.x P1IES.0 P1IES.1 P1IES.2 P1IES.3
P1Sel.3 P1DIR.3 P1DIR.3 Signal from or to Timer_A
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MSP430F11x MIXED SIGNAL MICROCONTROLLER
SLAS256B - NOVEMBER 1999 - REVISED JUNE 2000
APPLICATION INFORMATION
Port P1, P1.4 to P1.7, input/output with Schmitt-trigger and in-system access features
P1SEL.x P1DIR.x Direction Control From Module P1OUT.x Module X OUT
0 1 0 1 Pad Logic P1.4-P1.7
TST P1IN.x EN Module X IN D TST P1IRQ.x P1IE.x P1IFG.x Q EN Set Interrupt Flag Interrupt Edge Select P1IES.x P1SEL.x Control By JTAG Fuse 60 k Typical GND Fuse Blow TST Control TEST Bus Keeper
NOTE: Fuse not implemented in F11x
P1.x TDO Controlled By JTAG
P1.7/TDI/TDO Controlled by JTAG TDI TST P1.x
P1.6/TDI
NOTE: The test pin should be protected from potential EMI and ESD voltage spikes. This may require a smaller external pulldown resistor in some applications. x = Bit identifier, 4 to 7 for port P1 During programming activity and during blowing the fuse, the pin TDO/TDI is used to apply the test input for JTAG circuitry. PnSel.x P1Sel.4 P1Sel.5 P1Sel.6 P1Sel.7 PnDIR.x P1DIR.4 P1DIR.5 P1DIR.6 P1DIR.7 Direction control from module P1DIR.4 P1DIR.5 P1DIR.6 P1DIR.7 PnOUT.x P1OUT.4 P1OUT.5 P1OUT.6 P1OUT.7
TST TMS
P1.x
P1.5/TMS TST TCK P1.4/TCK P1.x
Module X OUT SMCLK Out0 signal Out1 signal Out2 signal
PnIN.x P1IN.4 P1IN.5 P1IN.6 P1IN.7
Module X IN unused unused unused unused
PnIE.x P1IE.4 P1IE.5 P1IE.6 P1IE.7
PnIFG.x P1IFG.4 P1IFG.5 P1IFG.6 P1IFG.7
PnIES.x P1IES.4 P1IES.5 P1IES.6 P1IES.7
Signal from or to Timer_A
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MSP430F11x MIXED SIGNAL MICROCONTROLLER
SLAS256B - NOVEMBER 1999 - REVISED JUNE 2000
APPLICATION INFORMATION
Port P2, P2.0 to P2.4, input/output with Schmitt-trigger
P2SEL.x P2DIR.x Direction Control From Module P2OUT.x Module X OUT 0 1 0: Input 1: Output Pad Logic
0 1
P2.0 - P2.4
P2IN.x EN Module X IN P2IRQ.x D
P2IE.x P2IFG.x Q EN Set Interrupt Flag
Interrupt Edge Select
P2IES.x P2SEL.x
NOTE: x = Bit Identifier, 0 to 4 For Port P2 PnSel.x PnDIR.x Direction control from module P2DIR.0 P2DIR.1 P2DIR.2 P2DIR.3 PnOUT.x Module X OUT ACLK VSS Out0 signal Out1 signal Out2 signal PnIN.x Module X IN unused INCLK CCI0B CCI1B unused PnIE.x PnIFG.x PnIES.x
P2Sel.0 P2Sel.1 P2Sel.2 P2Sel.3
P2DIR.0 P2DIR.1 P2DIR.2 P2DIR.3
P2OUT.0 P2OUT.1 P2OUT.2 P2OUT.3 P2OUT.4
P2IN.0 P2IN.1 P2IN.2 P2IN.3 P2IN.4
P2IE.0 P2IE.1 P2IE.2 P2IE.3 P2IE.4
P2IFG.0 P2IFG.1 P2IFG.2 P2IFG.3 P2IFG.4
P1IES.0 P1IES.1 P1IES.2 P1IES.3 P1IES.4
P2Sel.4 P2DIR.4 P2DIR.4 Signal from or to Timer_A
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MSP430F11x MIXED SIGNAL MICROCONTROLLER
SLAS256B - NOVEMBER 1999 - REVISED JUNE 2000
Port P2, P2.5, input/output with Schmitt-trigger and ROSC function for the Basic Clock module
P2SEL.5 0 P2DIR.5 Direction Control From Module P2OUT.5 Module X OUT 1 0 1
0: Input 1: Output
Pad Logic
P2.5
P2IN.5
Bus Keeper
EN Module X IN D
P2IRQ.5
P2IE.5 P2IFG.5 Q EN Set Interrupt Flag
Interrupt Edge Select
Internal to Basic Clock Module 0 VCC
1
P2IES.5
DCOR CAPD.5
P2SEL.5 NOTE: DCOR: Control bit from basic clock module if it is set, P2.5 Is disconnected from P2.5 pad PnSel.x P2Sel.5 PnDIR.x P2DIR.5 Direction control from module P2DIR.5 PnOUT.x P2OUT.5 Module X OUT VSS PnIN.x P2IN.5 Module X IN unused PnIE.x P2IE.5
DC Generator
PnIFG.x P2IFG.5
PnIES.x P2IES.5
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MSP430F11x MIXED SIGNAL MICROCONTROLLER
SLAS256B - NOVEMBER 1999 - REVISED JUNE 2000
APPLICATION INFORMATION
Port P2, unbonded bits P2.6 and P2.7
P2SEL.x 0 P2DIR.x Direction Control From Module P2OUT.x Module X OUT P2IN.x Node Is Reset With PUC EN Bus Keeper Module X IN D 1 0 1 0: Input 1: Output
P2IRQ.x
P2IE.x P2IFG.x Q EN Set Interrupt Flag
Interrupt Edge Select
PUC
P2IES.x P2SEL.x
NOTE: x = Bit/identifier, 6 to 7 for port P2 without external pins P2Sel.x P2Sel.6 P2Sel.7 P2DIR.x P2DIR.6 P2DIR.7 Direction control from module P2DIR.6 P2DIR.7 P2OUT.x P2OUT.6 P2OUT.7 Module X OUT VSS VSS P2IN.x P2IN.6 P2IN.7 Module X IN unused unused P2IE.x P2IE.6 P2IE.7 P2IFG.x P2IFG.6 P2IFG.7 P2IES.x P2IES.6 P2IES.7
NOTE: A good use of the unbonded bits 6 and 7 of port P2 is to use the interrupt flags. The interrupt flags can not be influenced from any signal other than from software. They work then as a soft interrupt.
JTAG fuse check mode
MSP430 devices that have the fuse on the TEST terminal have a fuse check mode that tests the continuity of the fuse the first time the JTAG port is accessed after a power-on reset (POR). When activated, a fuse check current can flow from the TEST pin to ground if the fuse is not burned. Care must be taken to avoid accidentally activating the fuse check mode and increasing overall system power consumption. When the TEST pin is taken back low after a test or programming session, the fuse check mode and sense currents are terminated.
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MSP430F11x MIXED SIGNAL MICROCONTROLLER
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MECHANICAL DATA
DW (R-PDSO-G**)
16 PIN SHOWN 0.050 (1,27) 16 0.020 (0,51) 0.014 (0,35) 9
PLASTIC SMALL-OUTLINE PACKAGE
0.010 (0,25) M
0.419 (10,65) 0.400 (10,15) 0.299 (7,59) 0.293 (7,45) 0.010 (0,25) NOM
Gage Plane 0.010 (0,25) 1 A 8 0- 8 0.050 (1,27) 0.016 (0,40)
Seating Plane 0.104 (2,65) MAX 0.012 (0,30) 0.004 (0,10) PINS ** DIM A MAX 0.004 (0,10)
16 0.410 (10,41) 0.400 (10,16)
20 0.510 (12,95) 0.500 (12,70)
24 0.610 (15,49) 0.600 (15,24) 4040000 / D 02/98
A MIN
NOTES: A. B. C. D.
All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15). Falls within JEDEC MS-013
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MSP430F11x MIXED SIGNAL MICROCONTROLLER
SLAS256B - NOVEMBER 1999 - REVISED JUNE 2000
MECHANICAL DATA
PW (R-PDSO-G**)
14 PINS SHOWN
PLASTIC SMALL-OUTLINE PACKAGE
0,65 14 8
0,30 0,19
0,10 M
0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 A 7 0- 8 0,75 0,50
Seating Plane 1,20 MAX 0,15 0,05 0,10
PINS ** DIM A MAX
8
14
16
20
24
28
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-153
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IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Customers are responsible for their applications using TI components. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof.
Copyright (c) 2000, Texas Instruments Incorporated

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