View SLAU012_1002427.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

MSP430x3xx Family
User's Guide
July 2000
Mixed Signal Products
SLAU012
IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Customers are responsible for their applications using TI components. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof.
Copyright (c) 2000, Texas Instruments Incorporated
How to Use This Manual
Preface
Read This First
About This Manual
The MSP430x3xx User's Guide is intended to assist the development of MSP430x3xx family products by assembling together and presenting hardware and software information in a manner that is easy for engineers and programmers to use. This manual discusses modules and peripherals of the MSP430x3xx family of devices. Each discussion presents the module or peripheral in a general sense. Not all features and functions of all modules or peripherals are present on all devices. In addition, modules or peripherals may differ in their exact implementation between device families, or may not be fully implemented on an individual device or device family. Therefore, a user must always consult the data sheet of any device of interest to determine what peripherals and modules are implemented, and exactly how they are implemented on that particular device.
How to Use This Manual
This document contains the following chapters and appendixes: Chapter 1. Introduction Chapter 2. Architectural Overview Chapter 3. System Resets, Interrupts, and Operating Modes Chapter 4. Memory Chapter 5. 16-Bit CPU Chapter 6. Hardware Multiplier Chapter 7. FLL Clock Module Chapter 8. Digital I/O Configuration Chapter 9. Universal Timer/Port Module
iii
Related Documentation From Texas Instruments
Chapter 10. Timers Chapter 11. Timer_A Chapter 12. USART Peripheral Interface, UART Mode Chapter 13. USART Peripheral Interface, SPI Mode Chapter 14. Liquid Crystal Display Drive Chapter 15. ADC12+2 A-to-D Converter Appendix A. Peripheral File Map Appendix B. Instruction Set Description Appendix C. EPROM Programming
Notational Conventions
This document uses the following conventions.
-
Program listings, program examples, and interactive displays are shown in a special typeface similar to a typewriter's. Here is a sample program listing:
0011 0012 0013 0014 0005 0005 0005 0006 0001 0003 0006 .field .field .field .even 1, 2 3, 4 6, 3
Related Documentation From Texas Instruments
For related documentation see the web site http://www.ti.com/sc/msp430.
FCC Warning
This equipment is intended for use in a laboratory test environment only. It generates, uses, and can radiate radio frequency energy and has not been tested for compliance with the limits of computing devices pursuant to subpart J of part 15 of FCC rules, which are designed to provide reasonable protection against radio frequency interference. Operation of this equipment in other environments may cause interference with radio communications, in which case the user at his own expense will be required to take whatever measures may be required to correct this interference.
iv
Contents
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 Features and Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 31x Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 32x Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 33x Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 Central Processing Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3 Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4 Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5 Operation Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.6 Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7 Oscillator and Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1-2 1-3 1-3 1-4 2-1 2-2 2-2 2-3 2-3 2-3 2-4 2-4
2
3
System Resets, Interrupts, and Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3.1 System Reset and Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3.1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3.1.2 Device Initialization after System Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 3.2 Global Interrupt Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 3.3 MSP430 Interrupt-Priority Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 3.3.1 Operation of Global Interrupt--Reset/NMI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 3.3.2 Operation of Global Interrupt--Oscillator Fault Control . . . . . . . . . . . . . . . . . . . 3-8 3.4 Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 3.4.1 Interrupt Control Bits in Special-Function Registers (SFRs) . . . . . . . . . . . . . . 3-11 3.4.2 Interrupt Vector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14 3.5 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14 3.5.1 Low-Power Modes 0 and 1 (LPM0 and LPM1) . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18 3.5.2 Low-Power Modes 2 and 3 (LPM2 and LPM3) . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19 3.5.3 Low-Power Mode 4 (LPM4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19 3.6 Basic Hints for Low-Power Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2 Data in the Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3 Internal ROM Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.1 Processing of ROM Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.2 Computed Branches and Calls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4 RAM and Peripheral Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4-2 4-3 4-4 4-4 4-5 4-6
4
v
Contents
4.4.1 4.4.2 4.4.3 5
Random Access Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 Peripheral Modules--Address Allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8 Peripheral Modules--Special Function Registers (SFRs) . . . . . . . . . . . . . . . . 4-10
16-Bit CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5.1 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 5.1.1 The Program Counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 5.1.2 The System Stack Pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 5.1.3 The Status Register (SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 5.1.4 The Constant Generator Registers CG1 and CG2 . . . . . . . . . . . . . . . . . . . . . . . 5-5 5.2 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7 5.2.1 Register Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8 5.2.2 Indexed Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9 5.2.3 Symbolic Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 5.2.4 Absolute Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11 5.2.5 Indirect Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12 5.2.6 Indirect Autoincrement Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13 5.2.7 Immediate Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14 5.2.8 Clock Cycles, Length of Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15 5.3 Instruction Set Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-17 5.3.1 Double-Operand Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-18 5.3.2 Single-Operand Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-19 5.3.3 Conditional Jumps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-20 5.3.4 Short Form of Emulated Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-21 5.3.5 Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-22 5.4 Instruction Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-23 Hardware Multiplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 6.1 Hardware Multiplier Module Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2 6.2 Hardware Multiplier Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3 6.2.1 Multiply Unsigned, 16 x 16 bit, 16x 8 bit, 8 x 16 bit, 8 x 8 bit . . . . . . . . . . . . . . . . 6-5 6.2.2 Multiply Signed, 16 x 16 bit, 16 x 8 bit, 8 x 16 bit, 8 x 8 bit . . . . . . . . . . . . . . . . . . . 6-6 6.2.3 Multiply Unsigned and Accumulate, 16x16bit, 16x8bit, 8x16bit, 8x8bit . . . . . . 6-7 6.2.4 Multiply Signed and Accumulate, 16x16bit, 16x8bit, 8x16bit, 8x8bit . . . . . . . . 6-8 6.3 Hardware Multiplier Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9 6.4 Hardware Multiplier Special Function Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-10 6.5 Hardware Multiplier Software Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-10 6.5.1 Hardware Multiplier Software Restrictions--Address Mode . . . . . . . . . . . . . . . 6-10 6.5.2 Hardware Multiplier Software Restrictions--Interrupt Routines . . . . . . . . . . . . 6-11 6.5.3 Hardware Multiplier Software Restrictions--MACS . . . . . . . . . . . . . . . . . . . . . . 6-12 FLL Clock Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1 The FLL Clock Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2 Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.3 Digitally-Controlled Oscillator (DCO) and Frequency-Locked Loop . . . . . . . . . . . . . . . . 7.3.1 FLL Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.3.2 Modulator Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.3.3 DCO Frequency Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.3.4 Disabling the FLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.3.5 MCLK Stability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.3.6 Oscillator Fault Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 7-2 7-3 7-4 7-4 7-5 7-5 7-6 7-6 7-6
6
7
vi
Contents
7.4
7.5 7.6
FLL Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7 7.4.1 Starting From Power Up Clear (PUC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7 7.4.2 Adjusting the FLL Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7 7.4.3 FLL Features for Low-Power Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7 Buffered Clock Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-8 FLL Module Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9 7.6.1 MCLK Frequency Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9 7.6.2 Special-Function Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-10
8
Digital I/O Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2 8.2 Port P0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3 8.2.1 Port P0 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3 8.2.2 Port P0 Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6 8.2.3 Port P0 Interrupt Control Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-9 8.3 Ports P1, P2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-11 8.3.1 Port P1, Port P2 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-12 8.3.2 Port P1, Port P2 Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-15 8.3.3 Port P1, P2 Interrupt Control Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-16 8.4 Ports P3, P4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-17 8.4.1 Port P3, P4 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-17 8.4.2 Port P3, P4 Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-19 Universal Timer/Port Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 9.1 Timer/Port Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2 9.2 Timer/Port Module Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3 9.2.1 Timer/Port Counter TPCNT1, 8-Bit Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3 9.2.2 Timer/Port Counter TPCNT2, 8-Bit Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4 9.2.3 Timer/Port Counter, 16-Bit Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4 9.2.4 Enable Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6 9.2.5 Comparator Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6 9.3 Timer/Port Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7 9.4 Timer/Port Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-11 9.5 Timer/Port in an ADC Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-12
9
10 Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1 10.1 Basic Timer1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2 10.1.1 Basic Timer1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3 10.1.2 Special Function Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5 10.1.3 Basic Timer1 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5 10.1.4 Basic Timer1 Operation: Signal fLCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6 10.2 8-Bit Interval Timer/Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-7 10.2.1 Operation of 8-Bit Timer/Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-8 10.2.2 8-Bit Timer/Counter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-9 10.2.3 Special Function Register Bits, 8-Bit Timer/Counter Related . . . . . . . . . . . . . 10-11 10.2.4 Implementing a UART With the 8-Bit Timer/Counter . . . . . . . . . . . . . . . . . . . . 10-11 10.3 The Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-13 10.3.1 Watchdog Timer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-14 10.3.2 Watchdog Timer Interrupt Control Functions . . . . . . . . . . . . . . . . . . . . . . . . . . 10-16 10.3.3 Watchdog Timer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-16 11 Timer_A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1 11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2
vii
Contents
11.2
11.3
11.4
11.5
11.6
11.7
Timer_A Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4 11.2.1 Timer Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4 11.2.2 Clock Source Select and Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5 11.2.3 Starting the Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6 Timer Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6 11.3.1 Timer - Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6 11.3.2 Timer - Up Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6 11.3.3 Timer - Continuous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-9 11.3.4 Timer - Up/Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-10 Capture/Compare Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-13 11.4.1 Capture/Compare Block - Capture Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-14 11.4.2 Capture/Compare Block - Compare Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-18 The Output Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-19 11.5.1 Output Unit - Output Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-20 11.5.2 Output Control Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-21 11.5.3 Output Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-22 Timer_A Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-25 11.6.1 Timer_A Control Register TACTL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-25 11.6.2 Timer_A Register TAR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-27 11.6.3 Capture/Compare Control Register CCTLx . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-27 11.6.4 Timer_A Interrupt Vector Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-30 Timer_A UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-34
12 USART Peripheral Interface, UART Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1 12.1 USART Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2 12.2 USART Peripheral Interface, UART Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-3 12.2.1 UART Serial Asynchronous Communication Features . . . . . . . . . . . . . . . . . . . 12-3 12.3 Asynchronous Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4 12.3.1 Asynchronous Frame Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4 12.3.2 Baud Rate Generation in Asynchronous Communication Format . . . . . . . . . . 12-5 12.3.3 Asynchronous Communication Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-7 12.3.4 Idle-Line Multiprocessor Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-7 12.3.5 Address-Bit Multiprocessor Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-9 12.4 Interrupt and Enable Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-11 12.4.1 USART Receive Enable Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-11 12.4.2 USART Transmit Enable Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-12 12.4.3 USART Receive Interrupt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-13 12.4.4 USART Transmit Interrupt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-14 12.5 Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-15 12.5.1 USART Control Register UCTL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-15 12.5.2 Transmit Control Register UTCTL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-17 12.5.3 Receiver Control Register URCTL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-18 12.5.4 Baud Rate Select and Modulation Control Registers . . . . . . . . . . . . . . . . . . . 12-20 12.5.5 Receive-Data Buffer URXBUF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-21 12.5.6 Transmit Data Buffer UTXBUF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-22 12.6 Utilizing Features of Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-23 12.6.1 Receive-Start Operation From UART Frame . . . . . . . . . . . . . . . . . . . . . . . . . . 12-23 12.6.2 Maximum Utilization of Clock Frequency vs Baud Rate UART Mode . . . . . 12-25 12.6.3 Support of Multiprocessor Modes for Reduced Use of MSP430 Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-26 12.7 Baud Rate Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-26
viii
Contents
12.7.1 Bit Timing in Transmit Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-27 12.7.2 Typical Baud Rates and Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-29 12.7.3 Synchronization Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-30 13 USART Peripheral Interface, SPI Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1 13.1 USART Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2 13.2 USART Peripheral Interface, SPI Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-3 13.2.1 SPI Mode Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-3 13.3 Synchronous Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4 13.3.1 Master SPI Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-7 13.3.2 Slave SPI Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-8 13.4 Interrupt and Control Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-9 13.4.1 USART Receive/Transmit Enable Bit, Receive Operation . . . . . . . . . . . . . . . . 13-9 13.4.2 USART Receive/Transmit Enable Bit, Transmit Operation . . . . . . . . . . . . . . . 13-11 13.4.3 USART Receive-Interrupt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-13 13.4.4 Transmit-Interrupt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-14 13.5 Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-15 13.5.1 USART Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-15 13.5.2 Transmit Control Register UTCTL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-16 13.5.3 Receive Control Register URCTL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-18 13.5.4 Baud Rate Select and Modulation Control Registers . . . . . . . . . . . . . . . . . . . 13-18 13.5.5 Receive Data Buffer URXBUF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-19 13.5.6 Transmit Data Buffer UTXBUF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-19 14 Liquid Crystal Display Drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1 14.1 LCD Drive Basics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-2 14.2 LCD Controller/Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-7 14.2.1 LCD Controller/Driver Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-8 14.2.2 LCD Timing Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-8 14.2.3 LCD Voltage Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-9 14.2.4 LCD Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-10 14.2.5 LCD Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-14 14.2.6 LCD Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-16 14.3 Code Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-21 14.3.1 Example Code for Static LCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-21 14.3.2 Example Code for Two MUX, 1/2-Bias LCD . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-22 14.3.3 Example Code for Three MUX, 1/3-Bias LCD . . . . . . . . . . . . . . . . . . . . . . . . . 14-23 14.3.4 Example Code for Four MUX, 1/3-Bias LCD . . . . . . . . . . . . . . . . . . . . . . . . . . 14-24 15 ADC12+2 A-to-D Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1 15.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-2 15.2 Analog-to-Digital Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-4 15.2.1 A/D Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-4 15.2.2 A/D Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-7 15.2.3 A/D Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-7 15.2.4 A/D Current Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-8 15.2.5 Analog Inputs and Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-9 15.2.6 A/D Grounding and Noise Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-10 15.2.7 A/D Converter Input and Output Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-12 15.3 ADC12+2 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-13 15.3.1 Input Register AIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-13
ix
Contents
15.3.2 Input Enable Register AEN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-14 15.3.3 ADC12+2 Data Register ADAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-14 15.3.4 ADC12+2 Control Register ACTL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-15 A Peripheral File Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1 A.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-2 A.2 Special Function Register of MSP430x3xx Family, Byte Access . . . . . . . . . . . . . . . . . . . A-2 A.3 Digital I/O, Byte Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-3 A.4 LCD Registers, Byte Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-5 A.5 8-Bit Timer/Counter, Basic Timer, Timer/Port, Byte Access . . . . . . . . . . . . . . . . . . . . . . . A-6 A.6 FLL Registers, Byte Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-6 A.7 EPROM Control Register and Crystal Buffer, Byte Access . . . . . . . . . . . . . . . . . . . . . . . A-7 A.8 USART, UART Mode (Sync=0), Byte Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-7 A.9 USART, SPI Mode (Sync=1), Byte Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-8 A.10 ADC12+2, Word Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-9 A.11 Watchdog/Timer, Word Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-10 A.12 Hardware Multiplier, Word Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-10 A.13 Timer_A Registers, Word Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-11 Instruction Set Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B.1 Instruction Set Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B.1.1 Instruction Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B.1.2 Conditional and Unconditional Jumps (Core Instructions) . . . . . . . . . . . . . . . . . B.1.3 Emulated Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B.2 Instruction Set Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EPROM Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C.1 EPROM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C.1.1 Erasure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C.1.2 Programming Methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C.1.3 EPROM Control Register EPCTL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C.1.4 EPROM Protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C.2 FAST Programming Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C.3 Programming an EPROM Module Through a Serial Data Link Using the JTAG Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C.4 Programming an EPROM Module With Controller's Software . . . . . . . . . . . . . . . . . . . . . C.5 Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1 B-2 B-4 B-5 B-6 B-8 C-1 C-2 C-2 C-2 C-3 C-4 C-4 C-5 C-6 C-8
B
C
x
Contents
Figures
2-1 2-2 3-1 3-2 3-3 3-4 3-5 3-6 3-7 3-8 3-9 3-10 3-11 4-1 4-2 4-3 4-4 4-5 4-6 4-7 5-1 5-2 5-3 5-4 5-5 5-6 5-7 5-8 5-9 5-10 6-1 6-2 6-3 7-1 7-2 7-3 7-4 7-5 7-6 MSP430 System Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Bus Connection of Modules/Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 Power-on Reset and Power-Up Clear Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 Power-On Reset Timing on Fast VCC Rise Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 Power-on Reset Timing on Slow VCC Rise Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 Interrupt Priority Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 Block Diagram of NMI Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 RST/NMI Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 Return from Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 Status Register (SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 MSP430x3xx Family Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17 Typical Current Consumption vs Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18 Memory Map of Basic Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 Memory Data Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 Bits, Bytes, and Words in a Byte-Organized Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 ROM Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 Byte and Word Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 Register-Byte/Byte-Register Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 Example of RAM/Peripheral Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8 Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 System Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 Stack Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 PUSH SP and POP SP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 Operand Fetch Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13 Double Operand Instruction Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-18 Single Operand Instruction Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-19 Conditional-Jump Instruction Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-20 Core Instruction Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-23 Connection of the Hardware Multiplier Module to the Bus System . . . . . . . . . . . . . . . . . . . 6-2 Block Diagram of the MSP430 16x16-Bit Hardware Multiplier . . . . . . . . . . . . . . . . . . . . . . . 6-3 Registers of the Hardware Multiplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9 Frequency-Locked Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2 Crystal Oscillator Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3 Fractional Tap Frequency Required . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4 Modulator Hop Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5 Schematic of Clock Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-8 SCFQCTL Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9
xi
Contents
7-7 7-8 8-1 8-2 8-3 8-4 8-5 8-6 8-7 8-8 8-9 8-10 8-11 9-1 9-2 9-3 9-4 9-5 9-6 9-7 9-8 10-1 10-2 10-3 10-4 10-5 10-6 10-7 10-8 10-9 10-10 10-11 10-12 10-13 10-14 11-1 11-2 11-3 11-4 11-5 11-6 11-7 11-8 11-9 11-10 11-11 11-12 11-13 11-14 11-15
SCFI0 and SCFI1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9 Crystal Buffer Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-10 Port P0 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3 Interrupt Flags Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-5 Interrupt Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6 Schematic of Bits P07 to P03 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-7 Schematic of Bit P02 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-7 Schematic of Bit P01 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-8 Schematic of Bit P00 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-8 Port P1, Port P2 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-11 Schematic of One Bit in Port P1, P2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-15 Ports P3, P4 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-17 Schematic of Bits Pnx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-19 Timer/Port Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2 Timer/Port Counter, 16-Bit Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5 Timer/Port Comparator Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6 Timer/Port Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7 Timer/Port Counter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-8 Timer/Port Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-9 Timer/Port Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-9 Timer/Port Interrupt Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-11 Basic Timer1 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2 Basic Timer1 Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3 Basic Timer1 Control Register Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4 Basic Timer1 Counter BTCNT1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4 Basic Timer1 Counter BTCNT2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5 8-Bit Timer/Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-7 8-Bit Counter Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-8 8-Bit Timer/Counter Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-9 Start Bit Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-12 Data Latching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-12 Schematic of Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-13 Watchdog Timer Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-14 Reading WDTCTL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-15 Writing to WDTCTL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-15 Timer_A Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3 Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4 Schematic of 16-Bit Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5 Schematic of Clock Source Select and Input Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5 Timer Up Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-7 Up Mode Flag Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-7 New Period > Old Period . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-8 New Period < Old Period . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-8 Timer Continuous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-9 Continuous Mode Flag Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-9 Output Unit in Continuous Mode for Time Intervals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-10 Timer Up/Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-10 Output Unit in Up/Down Mode (II) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-11 Timer Up/Down Direction Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-11 Up/Down Mode Flag Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-12
xii
Contents
11-16 11-17 11-18 11-19 11-20 11-21 11-22 11-23 11-24 11-25 11-26 11-27 11-28 11-29 11-30 11-31 11-32 11-33 11-34 12-1 12-2 12-3 12-4 12-5 12-6 12-7 12-8 12-9 12-10 12-11 12-12 12-13 12-14 12-15 12-16 12-17 12-18 12-19 12-20 12-21 12-22 12-23 12-24 12-25 12-26 12-27 12-28 12-29 13-1 13-2
Altering CCR0 - Timer in Up/Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-12 Capture/Compare Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-13 Capture Logic Input Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-14 Capture Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-15 Capture Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-16 Software Capture Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-17 Output Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-19 Output Control Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-21 Output Examples - Timer in Up Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-23 Output Examples - Timer in Continuous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-23 Output Examples - Timer in Up/Down Mode (I) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-24 Timer_A Control Register TACTL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-25 TAR Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-27 Capture/Compare Control Register CCTLx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-27 Capture/Compare Interrupt Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-30 Schematic of Capture/Compare Interrupt Vector Word . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-31 Vector Word Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-31 UART Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-35 Timer_A UART Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-36 Block Diagram of USART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2 Block Diagram of USART - UART Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-3 Asynchronous Frame Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4 Asynchronous Bit Format Example for n or n + 1 Clock Periods . . . . . . . . . . . . . . . . . . . . 12-4 Typical Baud-Rate Generation Other Than MSP430 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-5 MSP430 Baud Rate Generation Example for n or n + 1 Clock Periods . . . . . . . . . . . . . . 12-6 Idle-Line Multiprocessor Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-7 USART Receiver Idle Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-8 Double-Buffered WUT and TX Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-8 USART Transmitter Idle Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-9 Address-Bit Multiprocessor Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-10 State Diagram of Receiver Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-11 State Diagram of Transmitter Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-12 Receive Interrupt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-13 Transmit Interrupt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-14 USART Control Register UCTL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-15 Transmitter Control Register UTCTL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-17 Receiver-Control Register URCTL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-18 USART Baud Rate Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-20 USART Modulation Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-21 USART Receive Data Buffer URXBUF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-21 Transmit Data Buffer UTXBUF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-22 Receive-Start Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-23 Receive-Start Timing Using URXS Flag, Start Bit Accepted . . . . . . . . . . . . . . . . . . . . . . . 12-24 Receive Start Timing Using URXS Flag, Start Bit Not Accepted . . . . . . . . . . . . . . . . . . . 12-24 Receive Start Timing Using URXS Flag, Glitch Suppression . . . . . . . . . . . . . . . . . . . . . . 12-24 MSP430 Transmit Bit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-27 MSP430 Transmit Bit Timing Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-27 Synchronization Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-30 Block Diagram of USART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2 Block Diagram of USART--SPI Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-3
xiii
Contents
13-3 13-4 13-5 13-6 13-7 13-8 13-9 13-10 13-11 13-12 13-13 13-14 13-15 13-16 13-17 13-18 13-19 13-20 13-21 13-22 14-1 14-2 14-3 14-4 14-5 14-6 14-7 14-8 14-9 14-10 14-11 14-12 14-13 14-14 14-15 14-16 14-17 15-1 15-2 15-3 15-4 15-5 15-6 15-7 15-8 15-9 15-10 15-11 15-12 15-13
MSP430 USART as Master, External Device With SPI as Slave . . . . . . . . . . . . . . . . . . . . 13-5 Serial Synchronous Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-6 Data Transfer Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-6 MSP430 USART as Slave in Three-Pin or Four-Pin Configuration . . . . . . . . . . . . . . . . . . 13-7 State Diagram of Receiver Enable Operation--MSP430 as Master . . . . . . . . . . . . . . . . 13-10 State Diagram of Receive/Transmit Enable--MSP430 as Slave, Three-Pin Mode . . . . 13-10 State Diagram of Receive Enable--MSP430 as Slave, Four-Pin Mode . . . . . . . . . . . . . 13-11 State Diagram of Transmit Enable--MSP430 as Master . . . . . . . . . . . . . . . . . . . . . . . . . . 13-11 State Diagram of Transmit Enable--MSP430 as Slave . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-12 Receive Interrupt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-13 Receive Interrupt State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-13 Transmit-Interrupt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-14 USART Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-15 Transmit Control Register UTCTL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-16 USART Clock Phase and Polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-17 Receive Control Register URCTL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-18 USART Baud-Rate Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-18 USART Modulation Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-19 Receive Data Buffer URXBUF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-19 Transmit Data Buffer UTXBUF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-19 Static Wave-Form Drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-3 Two-MUX Wave-Form Drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-4 Three-MUX Wave-Form Drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-5 Four-MUX Wave-Form Drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-6 LCD Controller/Driver Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-7 External LCD Module Analog Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-9 Schematic of LCD Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-10 Segment Line or Output Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-11 Mixed LCD and Port Mode Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-12 Schematic of LCD Pin - Timer/Port Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-13 LCD Control and Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-14 Information Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-15 Display Memory Bits Attached to Segment Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-16 Example With the Static Drive Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-17 Example With the Two-MUX Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-18 Example With the 3-MUX Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-19 Example With the Four-MUX Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-20 ADC12+2 Module Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-2 ADC12+2 Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-5 ADC12+2 Timing, 12-Bit Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-6 ADC12+2 Timing, 12+2-Bit Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-6 ADC, Input Sampling Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-7 A/D Current Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-9 Analog Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-10 A/D Grounding and Noise Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-11 ADC12+2 Input Register, Input Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-12 Input Register AIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-13 Input Enable Register AEN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-14 ADC12+2 Data Register ADAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-14 ADC12+2 Control Register ACTL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-15
xiv
Contents
B-1 B-2 B-3 B-4 B-5 B-6 B-7 B-8 B-9 B-10 B-11 C-1 C-2 C-3
Double-Operand Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-4 Single-Operand Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-5 Conditional and Unconditional Jump Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-5 Decrement Overlap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-26 Main Program Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-46 Destination Operand--Arithmetic Shift Left . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-47 Destination Operand--Carry Left Shift . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-48 Destination Operand--Arithmetic Right Shift . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-49 Destination Operand--Carry Right Shift . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-51 Destination Operand Byte Swap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-58 Destination Operand Sign Extension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-59 EPROM Control Register EPCTL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-3 EPROM Programming With Serial Data Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-5 EPROM Programming With Controller's Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-6
xv
Contents
Tables
3-1 3-2 3-3 3-4 3-5 3-6 4-1 4-2 4-3 5-1 5-2 5-3 5-4 5-5 5-6 5-7 5-8 5-9 5-10 5-11 5-12 5-13 5-14 5-15 5-16 5-17 5-18 6-1 6-2 7-1 8-1 8-2 8-3 8-4 9-1 9-2 9-3 9-4 9-5 Interrupt Control Bits in SFRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11 Interrupt Enable Registers 1 and 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12 Interrupt Flag Register 1 and 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13 Module Enable Registers 1 and 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13 Interrupt Sources, Flags, and Vectors of 3xx Configurations . . . . . . . . . . . . . . . . . . . . . . . 3-14 Low-Power Mode Logic Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17 Peripheral File Address Map--Word Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9 Peripheral File Address Map--Byte Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10 Special Function Register Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11 Register by Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 Description of Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 Values of Constant Generators CG1, CG2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5 Source/Destination Operand Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7 Register Mode Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8 Indexed Mode Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9 Symbolic Mode Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 Absolute Mode Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11 Indirect Mode Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12 Indirect Autoincrement Mode Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13 Immediate Mode Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14 Instruction Format I and Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15 Instruction Format-II and Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16 Miscellaneous Instructions or Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16 Double Operand Instruction Format Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-18 Single Operand Instruction Format Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-19 ConditIonal-Jump Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-20 Emulated Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-21 Sum Extension Register Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4 Hardware Multiplier Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9 The DCO Range Control Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5 Port P0 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4 Port P1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-12 Port P2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-12 Port P3 P4 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-18 Timer/Port Counter Signals, 16-Bit Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6 Timer/Port Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7 Bit EN1 Level/Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-8 Timer/Port Clock Source Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-8 Counter TPCNT2 Clock Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-10
xvi
Contents
10-1 10-2 10-3 10-4 10-5 11-1 11-2 11-3 11-4 11-5 11-6 11-7 11-8 11-9 12-1 12-2 12-3 12-4 12-5 13-1 13-2 14-1 14-2 15-1 15-2 15-3 15-4 15-5
Basic Timer1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3 BTCNT2 Input Frequency Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4 8-Bit Timer/Counter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-9 Clock Input Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-10 WDTCNT Taps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-14 Timer Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4 State of OUTx at Next Rising Edge of Timer Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-22 Timer_A Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-25 Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-26 Input Clock Divider Control Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-26 Clock Source Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-26 Capture/Compare Control Register Output Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-29 Capture/Compare Control Register Capture Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-29 Vector Register TAIV Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-32 USART Interrupt Control and Enable Bits - UART Mode . . . . . . . . . . . . . . . . . . . . . . . . . 12-11 Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-15 Interrupt Flag Set Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-19 Receive Data Buffer Characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-22 Commonly Used Baud Rates, Baud Rate Data, and Errors . . . . . . . . . . . . . . . . . . . . . . . 12-29 USART Interrupt Control and Enable Bits - SPI Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-9 USART Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-15 LCDM Selections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-15 LCDM Signal Outputs for Port Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-15 ADC12+2 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-13 A/D Input Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-15 A/D Current Source Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-16 Range Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-16 ADCLK Clock Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-16
xvii
Contents
Examples
12-1 4800 Baud . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-6 12-2 19,200 Baud . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-6 12-3 Error Example for 2400 Baud . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-28 12-4 Synchronization Error--2400 Baud . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-31 C-1 MSP430 On-Chip Program Memory Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-3 C-2 Fast Programming Subroutine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-4 C-3 Programming EPROM Module With Controller's Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-7 C-4 Subroutine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-7
xviii
Contents
Notes, Cautions, and Warnings
Word-Byte Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 Status Register Bits V, N, Z and C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5 Data in Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8 Instruction Format II Immediate Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16 Destination Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-17 Instructions CMP and SUB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-18 Writing to the Read-Only Register P0IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4 Port P0 Interrupt Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6 Writing to Read-Only Registers P1IN, P2IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-12 Port P1, Port P2 Interrupt Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-14 Function Select With P1SEL, P2SEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-15 Writing to Read-Only Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-18 Function Select With PnSEL Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-19 RC1FG and RC2FG When Software Disables the Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7 Watchdog Timer, Changing the Time Interval . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-17 Capture With Timer Halted . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-16 Changing Timer_A Control Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-27 Modifying Timer A Register TAR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-27 Simultaneous Capture and Capture Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-30 Writing to Read-Only Register TAIV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-32 URXE Reenabled, UART Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-11 Writing to UTXBUF, UART Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-12 Write to UTXBUF/Reset of Transmitter, UART Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-12 Mark and Space Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-17 Receive Status Control Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-20 Break Detect (BRK) Bit With Halted UART Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-25 USART Synchronous Master Mode, Receive Initiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-7 USPIIE Re-Enabled, SPI Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-10 Writing to UTXBUF, SPI Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-12 Write to UTXBUF/Reset of Transmitter, SPI Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-12 ADC, Start-of-Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-3 ADC12+2 Offset Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-8 Asterisked Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-3 Operations Using the Status Register (SR) for Destination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-4 Conditional and Unconditional Jumps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-6 Disable Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-28 Enable Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-29 Emulating No-Operation Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-42 The System Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-43
xix
Contents
The System Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-44 RLA Substitution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-47 RLC and RLC.B Emulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-48 Borrow Is Treated as a .NOT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-52 Borrow Is Treated as a .NOT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-56 Borrow Is Treated as a .NOT. Carry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-57 EPROM Exposed to Ambient Light (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-2
xx
Chapter 1
Introduction
This chapter outlines the features and capabilities of the Texas Instruments (TI) MSP430x3xx family of microcontrollers. The MSP430 employs a von-Neumann architecture, therefore, all memory and peripherals are in one address space. The MSP430 devices constitute a family of ultralow-power, 16-bit RISC microcontrollers with an advanced architecture and rich peripheral set. The architecture uses advanced timing and design features, as well as a highly orthogonal structure to deliver a processor that is both powerful and flexible. The MSP430 consumes less than 400 A in active mode operating at 1 MHz in a typical 3-V system and can wake up from a <2-A standby mode to fully synchronized operation in less than 6 s. These exceptionally low current requirements, combined with the fast wake-up time, enable a user to build a system with minimum current consumption and maximum battery life. Additionally, the MSP430 family has an abundant mix of peripherals and memory sizes enabling true system-on-a-chip designs. The peripherals include a 14-bit A/D, slope A/D, multiple timers (some with capture/compare registers and PWM output capability), LCD driver, on-chip clock generation, H/W multiplier, USART, Watchdog Timer, GPIO, and others. See http://www.ti.com for the latest device information and literature for the MSP430 family.
Topic
1.1 1.2 1.3 1.4
Page
Features and Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 31x Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 32x Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 33x Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
Introduction
1-1
Features and Capabilities
1.1 Features and Capabilities
The TI MSP430x3xx family of controllers has the following features and capabilities:
-
Ultralow-power architecture: 0.1- 400 A nominal operating current @1 MHz 2.5 - 5.5 V operation available 6 s wake-up from standby mode Extensive interrupt capability relieves need for polling Flexible and powerful processing capabilities: Seven source-address modes Four destination-address modes Only 27 core instructions Prioritized, nested interrupts No interrupt or subroutine level limits Large register file Ram execution capability Efficient table processing Fast hex-to-decimal conversion Extensive, memory-mapped peripheral set including: Integrated 14-bit A/D converter Multiple timers and PWM capability Slope A/D conversion (all devices) Integrated USART Integrated LCD driver Watchdog Timer Multiple I/O with extensive interrupt capability Integrated programmable oscillator 32-kHz crystal oscillator (all devices) Powerful, easy-to-use development tools including: Simulator (including peripheral and interrupt simulation) C compiler Assembler Linker Emulators (ICE and JTAG) Evaluation kits Device programmer Application notes Example code Versatile ultralow-power device options including: Masked ROM OTP (in-system programmable) EPROM (UV-erasable, in-system programmable) -40C to 85C operating temperature range Up to 64K addressing space Memory mixes to support all types of applications
-
-
-
-
1-2
31x Devices
1.2 31x Devices
The 31x devices contain the following peripherals:
-
FLL clock system (on-chip DCO + crystal oscillator) Watchdog Timer/General-Purpose Timer Timer/Port (2 8-bit or 1 16-bit timer with analog comparator, 5 outputs, and 1 I/O. Ideal for slope A/D conversion) Basic Timer1 (2 8-bit timers or 1 16-bit timer) LCD Controller/Driver (up to 92 segments) 8-Bit Timer/Counter (8-bit counter with preload. Can be used as UART) I/O Port0 (8 I/O's all with interrupt)
Available 31x devices are: MSP430C311S MSP430C312 MSP430C314 MSP430C315 MSP430P315 MSP430P315S PMS430E315 2KB ROM, 128B RAM 4KB ROM, 256B RAM 12KB ROM, 512B RAM 16KB ROM, 512B RAM 16KB OTP, 512B RAM 16KB OTP, 512B RAM 16KB EPROM, 512B RAM
1.3 32x Devices
The 32x devices contain the following peripherals:
-
FLL clock system (on-chip DCO + crystal oscillator) Watchdog Timer/General-Purpose Timer Timer/Port (2 8-bit or 1 16-bit timer with analog comparator, 5 outputs, and 1 I/O. Ideal for slope A/D conversion) Basic Timer1 (2 8-bit timers or 1 16-bit timer) LCD Controller/Driver (up to 84 segments) 8-bit Timer/Counter (8-bit counter with preload. Can be used as UART) I/O Port0 (8 I/O's all with interrupt) ADC12+2 (14-bit A/D)
Available 32x devices are: MSP430C323 MSP430C325 MSP430P325A PMS430E325A 8KB ROM, 256B RAM 16KB ROM, 512B RAM 16KB OTP, 512B RAM 16KB EPROM, 512B RAM
Introduction
1-3
33x Devices
1.4 33x Devices
The 33x devices contain the following peripherals:
-
FLL clock system (on-chip DCO + crystal oscillator) Watchdog Timer/General-Purpose Timer Timer/Port (2 8-bit or 1 16-bit timer with analog comparator, 5 outputs, and 1 I/O. Ideal for slope A/D conversion) Basic Timer1 (2 8-bit timers or 1 16-bit timer) LCD Controller/Driver (up to 120 segments) 8-Bit Timer/Counter (8-bit counter with preload. Can be used as UART) I/O Port0 (8 I/O's all with interrupt) I/O Port1,2 (8 I/O's each all with interrupt) I/O Port3,4 (8 I/O's each) Hardware Multiplier (16 x 16-bit) Timer_A (16-bit timer with 5 capture/compare registers and PWM output) USART
Available 33x devices are: MSP430C336 MSP430C337 MSP430P337A PMS430E337A 24KB ROM, 1KB RAM 32KB ROM, 1KB RAM 32KB OTP, 1KB RAM 32KB EPROM, 1KB RAM
1-4
Chapter 2
Architectural Overview
This section describes the basic functions of an MSP430-based system. The MSP430 devices contain the following main elements:
-
Central processing unit Program memory Data memory Operation control Peripheral modules Oscillator and clock generator
Topic
2.1 2.2 2.3 2.4 2.5 2.6 2.7
Page
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Central Processing Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 Operation Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 Oscillator and Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
Architectural Overview
2-1
Introduction
2.1 Introduction
The architecture of the MSP430 family is based on a memory-to-memory architecture, a common address space for all functional blocks, and a reduced instruction set applicable to all functional blocks as illustrated in Figure 2-1. See specific device data sheets for complete block diagrams of individual devices.
Figure 2-1. MSP430 System Configuration
Oscillator System Clock
ACLK PROGRAM MCLK DATA I/O Port USART I/O Port
MAB, 16 Bit
MAB, 4 Bit
CPU Incl. 16 Reg. MDB, 16 Bit Bus Conv.
R/W MDB, 8 Bit
ADC Random Logic Module Select
WDT
Basic Timer
8-Bit Timer
LCD DRIVER
2.2 Central Processing Unit
The CPU incorporates a reduced and highly transparent instruction set and a highly orthogonal design. It consists of a 16-bit arithmetic logic unit (ALU), 16 registers, and instruction control logic. Four of these registers are used for special purposes. These are the program counter (PC), stack pointer (SP), status register (SR), and constant generator (CGx). All registers, except the constant-generator registers R3/CG2 and part of R2/CG1, can be accessed using the complete instruction set. The constant generator supplies instruction constants, and is not used for data storage. The addressing mode used on CG1 separates the data from the constants. The CPU control over the program counter, the status register, and the stack pointer (with the reduced instruction set) allows the development of applications with sophisticated addressing modes and software algorithms.
2-2
Program Memory
2.3 Program Memory
Instruction fetches from program memory are always 16-bit accesses, whereas data memory can be accessed using word (16-bit) or byte (8-bit) instructions. Any access uses the 16-bit memory data bus (MDB) and as many of the least-significant address lines of the memory address bus (MAB) as required to access the memory locations. Blocks of memory are automatically selected through module-enable signals. This technique reduces overall current consumption. Program memory is integrated as programmable or mask-programmed memory. In addition to program code, data may also be placed in the ROM section of the memory map and may be accessed using word or byte instructions; this is useful for data tables, for example. This unique feature gives the MSP430 an advantage over other microcontrollers, because the data tables do not have to be copied to RAM for usage. Sixteen words of memory are reserved for reset and interrupt vectors at the top of the 64-kilobytes address space from 0FFFFh down to 0FFE0h.
2.4 Data Memory
The data memory is connected to the CPU through the same two buses as the program memory (ROM): the memory address bus (MAB) and the memory data bus (MDB). The data memory can be accessed with full (word) data width or with reduced (byte) data width. Additionally, because the RAM and ROM are connected to the CPU via the same busses, program code can be loaded into and executed from RAM. This is another unique feature of the MSP430 devices, and provides valuable, easy-to-use debugging capability.
2.5 Operation Control
The operation of the different MSP430 members is controlled mainly by the information stored in the special-function registers (SFRs). The different bits in the SFRs enable interrupts, provide information about the status of interrupt flags, and define the operating modes of the peripherals. By disabling peripherals that are not needed during an operation, total current consumption can be reduced. The individual peripherals are described later in this manual.
Architectural Overview
2-3
Peripherals
2.6 Peripherals
Peripheral modules are connected to the CPU through the MAB, MDB, and interrupt service and request lines. The MAB is usually a 5-bit bus for most of the peripherals. The MDB is an 8-bit or 16-bit bus. Most of the peripherals operate in byte format. Modules with an 8-bit data bus are connected by bus-conversion circuitry to the 16-bit CPU. The data exchange with these modules must be handled with byte instructions. The SFRs are also handled with byte instructions. The operation for 8-bit peripherals follows the order described in Figure 2-2.
Figure 2-2. Bus Connection of Modules/Peripherals
MAB MDB
Interrupt Request Module/Peripheral Interrupt Bus Grant
Interrupt Request Interrupt Bus Grant
PUC
2.7 Oscillator and Clock Generator
The oscillator is designed for the commonly used 32,768 Hz, low-currentconsumption clock crystal. All analog components are integrated into the MSP430x3xx; only the crystal needs to be connected with no other external components required. In addition to the crystal oscillator, all MSP430 devices contain a digitallycontrolled RC oscillator (DCO). The DCO is different from RC oscillators found on other microcontrollers because it is digitally controllable and tuneable. MSP430x3xx devices contain an additional logic block called the frequency locked loop (FLL). The FLL continuously and automatically adjusts the frequency of the DCO relative to the 32768-Hz crystal oscillator to stabilize the DCO over voltage and temperature. This provides an effective, stable, ultralow-power oscillator for the CPU and peripherals. Clock source selection for peripherals is very flexible. Most peripherals are capable of using the 32768-Hz crystal oscillator clock or the DCO clock. The CPU executes from the DCO clock. See Chapter 7 for details on the clock module.
2-4
Chapter 3
System Resets, Interrupts, and Operating Modes
This chapter discusses the MSP430x3xx system resets, interrupts, and operating modes.
Topic
3.1 3.2 3.3 3.4 3.5 3.6
Page
System Reset and Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 Global Interrupt Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 MSP430 Interrupt-Priority Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14 Basic Hints for Low-Power Applications . . . . . . . . . . . . . . . . . . . . . . . 3-20
System Resets, Interrupts, and Operating Modes
3-1
System Reset and Initialization
3.1 System Reset and Initialization
3.1.1 Introduction
The MSP430 system reset circuitry (shown in Figure 3-1) sources two internal reset signals: power-on reset (POR) and power-up clear (PUC). Different events trigger these reset signals and different initial conditions exist depending on which signal was generated.
Figure 3-1. Power-on Reset and Power-up Clear Schematic
VCC POR Detect 0V RST/MNI NMI(WDTCTL.5) TIMSEL WDTQn WDTIFG EQU 0V 0V Delay S S S POR S Latch R VCC POR Delay
S POR S Latch R
POR
PUC_FLL
Resetwd1
PUC
Resetwd2
From watchdog timer peripheral module
MCLK
A POR is a device reset. It is only generated by the two following events:
-
Powering up the device A low signal on the RST/NMI pin when configured in the reset mode
A PUC is always generated when a POR is generated, but a POR is not generated by a PUC. The following events trigger a PUC: A POR signal Watchdog Timer expiration (in watchdog mode only) Watchdog Timer security key violation A low signal on the RST/NMI pin when configured in the NMI mode
Note: If desired, software can cause a PUC by simply writing to the watchdog timer control register with an incorrect password.
3-2
System Reset and Initialization
Note: Generation of the POR/PUC signals does not necessarily generate a system reset interrupt. Anytime a POR is activated, a system reset interrupt is generated. However, when a PUC is activated, a system reset interrupt may or may not be generated. Instead, a lower priority interrupt vector may be generated, depending on what action caused the PUC. Each device data sheet gives a detailed table of what action generates each interrupt. This table should be consulted for the proper handling of all interrupts. When the VCC supply provides a fast rise time as shown in Figure 3-2, the POR delay provides enough active time on the POR signal to allow the signal to initialize the circuitry correctly after power up. When the VCC rise time is slow, as shown in Figure 3-3, the POR detector holds the POR signal active until Vcc has risen above the V(POR) level. This also ensures a correct initialization.
Figure 3-2. Power-On Reset Timing on Fast VCC Rise Time
V VCC POR
tPOR_Delay
t
If power to the chip is cycled, the supply voltage VCC must fall below the V(min) (see Figure 3-3) to ensure that another POR signal occurs when VCC is powered up again. If VCC does not fall below V(min) during a cycle or a glitch, a POR is not generated and power-up conditions do not set correctly.
Figure 3-3. Power-on Reset Timing on Slow VCC Rise Time
V VCC
V (POR) V (min) POR No POR POR
t
System Resets, Interrupts, and Operating Modes
3-3
System Reset and Initialization
3.1.2
Device Initialization after System Reset
After a device reset (POR/PUC combination), the initial system conditions are:
-
I/O pins switched to input mode (see note below). I/O flags are cleared as described in the I/O chapter (see note below). Other peripherals and registers initialized as described in their respective chapters. Status register is reset. Program counter is loaded with address contained at reset vector location (0FFFEh). CPU execution begins at that address. FLL begins regulation of the DCO.
Note: I/O pins and flags are only initialized after power up. After the '430 is powered and running, if a reset is generated with RST/NMI pin (in reset mode), the I/O pins are unaffected. After a system reset, the user program can evaluate the various flags to determine the source of the reset and take appropriate action. The initial state of registers and peripherals is discussed in each applicable section of this manual. Each register is shown with a key indicating the accessibility of the register and the initial condition, for example, rw-(0), or rw-0. In these examples, the r indicates read, the w indicates write, and the value after the dash indicates the initial condition. If the value is in parenthesis, the initial condition takes effect only after a POR - a PUC alone will not effect the bit(s). If the value is not in parenthesis, it takes effect after a PUC alone or after a POR/PUC combination. Some examples follow: Type rw-(0) rw-0 r-1 r w Description Read/write, reset with POR Read/write, reset with POR or PUC Read only, set with POR or PUC Read only, no initial state Write only, no initial state
3-4
Global Interrupt Structure
3.2 Global Interrupt Structure
There are four types of interrupts:
-
System reset Maskable Nonmaskable (Non)maskable
System reset (POR/PUC) is discussed in section 3.1. Maskable interrupts are caused by: A Watchdog-Timer overflow (if timer mode is selected) Other modules with interrupt capability Nonmaskable interrupts are not maskable in any way. No individual interrupt enable bit is implemented for them, and the general interrupt enable bit (GIE) has no effect on them. (Non)maskable interrupts are not masked by the general interrupt enable bit (GIE) but are individually enabled or disabled by an individual interrupt enable bit. When a (non)maskable interrupt is accepted, the corresponding interrupt enable bit is automatically reset, therefore disabling the interrupt for execution of the interrupt service routine (ISR). The RETI (return from interrupt) instruction has no effect on the individual enable bits of the (non)maskable interrupts. So the software must set the corresponding interrupt enable bit in the ISR before execution of the RETI instruction for the interrupt to be re-enabled after the ISR. A nonmaskable NMI interrupt can be generated by an edge on the RST/NMI pin if NMI mode is selected. Additionally, a (non)maskable interrupt event can be generated when an oscillator fault occurs, if the oscillator fault interrupt enable bit is set.
System Resets, Interrupts, and Operating Modes
3-5
MSP430 Interrupt-Priority Scheme
3.3 MSP430 Interrupt-Priority Scheme
The interrupt priority of the modules, as shown in Figure 3-4, is defined by the arrangement of the modules in the connection chain: the nearer a module is to the CPU/NMIRS, the higher the priority.
Figure 3-4. Interrupt Priority Scheme
Priority High Low
GMIRS
CPU
GIE NMIRS
Module 1 1 2
Module 2 1 2
WD Timer 1 2
Module m 1 2
Module n 1
PUC
Bus Grant
PUC OSCfault
Circuit
Reset/NMI
WDT Security Key
MAB - 5LSBs
Reset and NMI, as shown in Figure 3-5, can only be used as alternative interrupts because they use the same input pin. The associated control bits are located in the watchdog timer control register shown in Figure 3-6, and are password protected.
3-6
MSP430 Interrupt-Priority Scheme
Figure 3-5. Block Diagram of NMI Interrupt Sources
RST/NMI
VCC
PUC System Reset Generator POR
S IFG1.4 Clear
NMIFG NMIRS
NMIES
TMSEL
NMI
WDTQn
EQU
PUC
POR
PUC
OSCFault OFIFG Counter WDT POR OFIE IE1.1 Clear NMI_IRQA PUC IRQA TIMSEL IFG1.0
S
WDTIFG IRQ
S IFG1.1
Clear
WDTIE IRQA: Interrupt Request Accepted
IE1.0 Clear
Watchdog Timer Module
PUC
Figure 3-6. RST/NMI Mode Selection
7 WDTCTL 0120h HOLD rw-0 NMIES rw-0 NMI rw-0 TMSEL CNTCL rw-0 (w)-0 SSEL rw-0 IS1 rw-0 0 IS0 rw-0
BITS 0-4,7 See Timers chapter. BIT 5: The NMI bit selects the function of the RST/NMI input pin. It is cleared after a PUC signal. NMI = 0: NMI = 1: BIT 6: The RST/NMI input works as reset input. As long as the RST/NMI pin is held low, the internal PUC signal is active (level-sensitive). The RST/NMI input works as an edge-sensitive, nonmaskable interrupt input.
This bit selects the activating edge of the RST/NMI input if the NMI function is selected. It is cleared after a PUC signal. NMIES = 0: A rising edge triggers an NMI interrupt. NMIES = 1: A falling edge triggers an NMI interrupt.
System Resets, Interrupts, and Operating Modes
3-7
MSP430 Interrupt-Priority Scheme
3.3.1
Operation of Global Interrupt--Reset/NMI
If the RST/NMI pin is set to the reset function, the CPU is held in the reset state as long as the RST/NMI pin is held low. After the input changes to a high state, the CPU starts program execution at the word address stored in word location 0FFFEh (reset vector). If the RST/NMI pin is set to the NMI function, a signal edge (selected by the NMIES bit) will generate an unconditional interrupt. When accepted, program execution begins at the address stored in location 0FFFCh. The RST/NMI flag in the SFR IFG1.4 is also set. Note: When configured in the NMI mode, a signal generating an NMI event should not hold the RST/NMI pin low, unless it is intended to hold the processor in reset. When an NMI event occurs on the pin, the PUC signal is activated, thus resetting the bits in the WDTCTL register. This results in the RST/NMI pin being configured in the reset mode. If the signal on the RST/NMI pin that generated the NMI event remains low, the processor will be held in the reset state. When NMI mode is selected and the NMI edge select bit is changed, an NMI can be generated, depending on the actual level at RST/NMI pin. When the NMI edge select bit is changed before selecting the NMI mode, no NMI is generated.
3.3.2
Operation of Global Interrupt--Oscillator Fault Control
The oscillator fault signal warns of a possible error condition with the crystal oscillator. It is generated by different events in the FLL Clock and Basic Clock systems.
3.3.2.1
Oscillator Fault Control in the FLL Clock System
The oscillator fault signal is triggered if the 5MSB (29-25) DCO control taps in the SCFI1 register are equal to 0, or greater than or equal to 28h. The oscillator fault signal can be enabled to generate an NMI by bit IE1.1 in the SFRs. The interrupt flag IFG1.1 in the SFRs can then be tested by the interrupt service routine to determine if the NMI was caused by an oscillator fault. See chapter 7 for more details on the operation of the DCO oscillator and the FLL.
3-8
Interrupt Processing
3.4 Interrupt Processing
The MSP430 programmable interrupt structure allows flexible on-chip and external interrupt configurations to meet real-time interrupt-driven system requirements. Interrupts may be initiated by the processor's operating conditions such as watchdog overflow; or by peripheral modules or external events. Each interrupt source can be disabled individually by an interrupt enable bit, or all maskable interrupts can be disabled by the general interrupt enable (GIE) bit in the status register. Whenever an interrupt is requested and the appropriate interrupt enable bit and general interrupt enable (GIE) bit are set, the interrupt service routine becomes active as follows: 1) CPU active: The currently executing instruction is completed. 2) CPU stopped: The low-power modes are terminated. 3) The program counter pointing to the next instruction is pushed onto the stack. 4) The status register is pushed onto the stack. 5) The interrupt with the highest priority is selected if multiple interrupts occurred during the last instruction and are pending for service. 6) The appropriate interrupt request flag resets automatically on singlesource flags. Multiple source flags remain set for servicing by software. 7) The GIE bit is reset; the CPUOff bit, the OscOff bit, and the SCG1 bit are cleared; the status bits V, N, Z, and C are reset. SCG0 is left unchanged, and loop control remains in the previous operating condition. 8) The content of the appropriate interrupt vector is loaded into the program counter: the program continues with the interrupt handling routine at that address. The interrupt latency is six cycles, starting with the acceptance of an interrupt request, and lasting until the start of execution of the appropriate interrupt-service routine first instruction, as shown in Figure 3-7.
Figure 3-7. Interrupt Processing
Before Interrupt After Interrupt
Item1 SP Item2 TOS
Item1 Item2 PC SP SR TOS
System Resets, Interrupts, and Operating Modes
3-9
Interrupt Processing
The interrupt handling routine terminates with the instruction:
RETI (return from an interrupt service routine)
which performs the following actions: 1) The status register with all previous settings pops from the stack. All previous settings of GIE, CPUOFF, etc. are now in effect, regardless of the settings utilized during the interrupt service routine. 2) The program counter pops from the stack and begins execution at the point where it was interrupted. The return from the interrupt is illustrated in Figure 3-8.
Figure 3-8. Return from Interrupt
Before Return From Interrupt Item1 Item2 PC SP SR TOS SP Item1 Item2 PC SR TOS After
A RETI instruction takes five cycles. Interrupt nesting is activated if the GIE bit is set inside the interrupt handling routine. The GIE bit is located in status register SR/R2, which is included in the CPU as shown in Figure 3-9.
Figure 3-9. Status Register (SR)
15 Reserved For Future Enhancements 8 V 7 SCG1 SCG0 OSC CPU GIE Off Off N Z 0 C
rw-0
Apart from the GIE bit, other sources of interrupt requests can be enabled/ disabled individually or in groups. The interrupt enable flags are located together within two addresses of the special-function registers (SFRs). The program-flow conditions on interrupt requests can be easily adjusted using the interrupt enable masks. The hardware serves the highest priority within the empowered interrupt source.
3-10
Interrupt Processing
3.4.1
Interrupt Control Bits in Special-Function Registers (SFRs)
Most of the interrupt control bits, interrupt flags, and interrupt enable bits are collected in SFRs under a few addresses, as shown in Table 3-1. The SFRs are located in the lower address range and are implemented in byte format. SFRs must be accessed using byte instructions.
Table 3-1. Interrupt Control Bits in SFRs
Address 000Fh 000Eh 000Dh 000Ch 000Bh 000Ah 0009h 0008h 0007h 0006h 0005h 0004h 0003h 0002h 0001h 0000h 7 0 Not yet defined or implemented Not yet defined or implemented Not yet defined or implemented Not yet defined or implemented Not yet defined or implemented Not yet defined or implemented Not yet defined or implemented Not yet defined or implemented Not yet defined or implemented Not yet defined or implemented Module enable 2 (ME2.x) Module enable 1 (ME1.x) Interrupt flag reg. 2 (IFG2.x) Interrupt flag reg. 1 (IFG1.x) Interrupt enable 2 (IE2.x) Interrupt enable 1 (IE1.x)
The MSP430 family supports SFRs by applying the correct logic and functions to each individual module. Each module interrupt source can be individually enabled or disable using the bits described in Table 3-2. The interrupt-flag registers are described in Table 3-3. The module-enable bits are described in Table 3-4.
System Resets, Interrupts, and Operating Modes
3-11
Interrupt Processing
Table 3-2. Interrupt Enable Registers 1 and 2
Bit Position IE1.0 Short Form Initial State Comments WDTIE Reset Watchdog Timer enable signal. Inactive if watchdog mode is selected. Active if Watchdog Timer is configured as generalpurpose timer. Oscillator fault interrupt enable Dedicated I/O P0.0 interrupt enable Dedicated I/O P0.1 or 8-Bit Timer/Counter interrupt enable Reserved Reserved Reserved Reserved USART receive interrupt enable (33x devices) USART transmit interrupt enable (33x devices) ADC enable (32x devices), Timer/Port enable (31x devices) Timer/Port (32x, 33x devices) Reserved Reserved Reserved Basic timer interrupt enable signal
IE1.1 IE1.2 IE1.3 IE1.4 IE1.5 IE1.6 IE1.7 IE2.0 IE2.1 IE2.2 IE2.3 IE2.4 IE2.5 IE2.6 IE2.7
OFIE P0IE.0 P0IE.1
Reset Reset Reset Reset Reset Reset Reset
URXIE UTXIE ADIE/TPIE TPIE
Reset Reset Reset Reset Reset Reset Reset
BTIE
Reset
The initial state is the logical state after the PUC signal.
3-12
Interrupt Processing
Table 3-3. Interrupt Flag Register 1 and 2
Bit Position IFG1.0 Short Form Initial State Comments WDTIFG Set Or reset IFG1.1 IFG1.2 IFG1.3 IFG1.4 IFG1.5 IFG1.6 IFG1.7 IFG2.0 IFG2.1 IFG2.2 IFG2.3 IFG2.4 IFG2.5 IFG2.6 IFG2.7 BTIFG Unchanged URXIFG UTXIFG ADIFG Reset Set Reset OFIFG P0IFG.0 P0IFG.1 NMIIFG Set Reset Reset Reset Set on Watchdog Timer overflow in watchdog mode or security key violation. Reset with VCC power-up, or a reset condition at the RST/NMI pin in reset mode. Flag set on oscillator fault Dedicated I/O P0.0 Dedicated I/O P0.1 or 8-Bit Timer/Counter Set through the RST/NMI pin Reserved Reserved Reserved USART receive flag (33x devices) USART transmitter ready (33x devices) ADC, set on end-of-conversion Reserved Reserved Reserved Reserved Basic timer flag
Table 3-4. Module Enable Registers 1 and 2
Bit Position ME1.0 ME1.1 ME1.2 ME1.3 ME1.4 ME1.5 ME1.6 ME1.7 ME2.0 ME2.1 ME2.2 ME2.3 ME2.4 ME2.5 ME2.6 ME2.7 URXE USPIIE UTXE Reset Reset Reset Short Form Initial State Comments Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved USART receiver enable (33x devices, UART mode) USART transmit and receive enable (33x devices, SPI mode) USART transmit enable (33x devices, UART mode) Reserved Reserved Reserved Reserved Reserved Reserved
System Resets, Interrupts, and Operating Modes
3-13
Operating Modes
3.4.2
Interrupt Vector Addresses
The interrupt vectors and the power-up starting address are located in the ROM, using the address range 0FFFFh - 0FFE0h as described in Table 3-5. The vector contains the 16-bit address of the appropriate interrupt handler instruction sequence. The interrupt vectors for 3xx devices are shown in Table 3-5 in decreasing order of priority. See device data sheet for interrupt vectors for a specific device.
Table 3-5. Interrupt Sources, Flags, and Vectors of 3xx Configurations
Interrupt Source Power-up, ext. reset, watchdog NMI OSC. fault Dedicated I/O Dedicated I/O Watchdog Timer Timer_A Timer_A USART receive USART transmit ADC, Timer/Port Timer/Portw Port P2 Port P1 Basic timer Port 0 P2IFG.07 P1IFG.07 BTIFG P0IFG.27 Interrupt Flag WDTIFG NMIIFG OFIFG P0IFG.0 P0IFG.1 WDTIFG CCIFG0 TAIFG URXIFG UTXIFG ADCIFG System Interrupt Reset See Note (Non)maskable Maskable Maskable Maskable Maskable Maskable Maskable Maskable Maskable Maskable Maskable Maskable Maskable Maskable Maskable Word Address 0FFFEh 0FFFCh 0FFFAh 0FFF8h 0FFF6h 0FFF4h 0FFF2h 0FFF0h 0FFEEh 0FFECh 0FFEAh 0FFE8h 0FFE6h 0FFE4h 0FFE2h 0FFE0h Priority 15 (highest) 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 (lowest)
Multiple source flags Timer/Port vector in '31x configuration Timer/Port vector in '32x and '33x configuration Interrupt can be disabled with individual interrupt enable bit, but not with the general interrupt enable bit, GIE.
3.4.2.1
External Interrupts
All eight bits of ports P0, P1, and P2 are designed for interrupt processing of external events. All individual I/O bits are independently programmable. Any combinations of inputs, outputs, and interrupt conditions are possible. This allows easy adaptation to different I/O configurations. See Chapter 8 for more details on I/O ports.
3.5 Operating Modes
The MSP430 family was developed for ultra-low power applications and uses different levels of operating modes. The MSP430 operating modes, shown in Figure 3-10, give advanced support to various requirements for ultra-low power and ultra-low energy consumption. This support is combined with an intelligent management of operations during the different module and CPU states. An interrupt event wakes the system from each of the various operating
3-14
Operating Modes
modes and the RETI instruction returns operation to the mode that was selected before the interrupt event. The ultra-low power system design which uses complementary metal-oxide semiconductor (CMOS) technology, takes into account three different needs:
-
The desire for speed and data throughput despite conflicting needs for ultralow-power Minimization of individual current consumption Limitation of the activity state to the minimum required by the use of low-power modes
There are four bits that control the CPU and the system clock generator: CPUOff, OscOff, SCG0, and SCG1. These four bits support discontinuous active mode (AM) requests, to limit the time period of the full operating mode, and are located in the status register. The major advantage of including the operating mode bits in the status register is that the present state of the operating condition is saved onto the stack during an interrupt service request. As long as the stored status register information is not altered, the processor continues (after RETI) with the same operating mode as before the interrupt event. Another program flow may be selected by manipulating the data stored on the stack or the stack pointer. Being able to access the stack and stack pointer with the instruction set allows the program structures to be individually optimized, as illustrated in the following program flow:
-
Enter interrupt routine
The interrupt routine is entered and processed if an enabled interrupt awakens the MSP430:
J J
The SR and PC are stored on the stack, with the content present at the interrupt event. Subsequently, the operation mode control bits OscOff, SCG1, and CPUOff are cleared automatically in the status register.
-
Return from interrupt
Two different modes are available to return from the interrupt service routine and continue the flow of operation:
J J
Return with low-power mode bits set. When returning from the interrupt, the program counter points to the next instruction. The instruction pointed to is not executed, since the restored low-power mode stops CPU activity. Return with low-power mode bits reset. When returning from the interrupt, the program continues at the address following the instruction that set the OscOff or CPUOff-bit in the status register. To use this mode, the interrupt service routine must reset the OscOff, CPUOff, SCGO, and SCG1 bits on the stack. Then, when the SR contents are popped from the stack upon RETI, the operating mode will be active mode (AM).
System Resets, Interrupts, and Operating Modes
3-15
Operating Modes
The software can configure five operating modes:
-
Active mode AM; SCG1=0, SCG0=0, OscOff=0, CPUOff=0: CPU clocks are active Low-power mode 0 (LPM0); SCG1=0, SCG0=0, OscOff=0, CPUOff=1:
CPU is disabled ACLK and MCLK remain active Loop control for MCLK remains active
Low-power mode 1 (LPM1); SCG1=0, SCG0=1, OscOff=0, CPUOff=1:
CPU is disabled Loop control for MCLK is disabled ACLK and MCLK remain active
Low-power mode 2 (LPM2); SCG1=1, SCG0=0, OscOff=0, CPUOff=1:
CPU is disabled MCLK and loop control for MCLK are disabled DCO's dc-generator remains enabled ACLK remains active
Low-power mode 3 (LPM3); SCG1=1, SCG0=1, OscOff=0, CPUOff=1:
CPU is disabled MCLK and loop control for MCLK are disabled DCO oscillator is disabled DCO's dc-generator is disabled ACLK remains active
-
Low-power mode 4 (LPM4); SCG1=X, SCG0=X, OscOff=1, CPUOff=1:
CPU is disabled ACLK is disabled MCLK and loop control for MCLK are disabled DCO oscillator is disabled DCO's dc-generator is disabled Crystal oscillator is stopped
Note: Peripheral operation is not halted by CPUOff. Peripherals are controlled by their individual control registers.
3-16
Operating Modes
Table 3-6. Low-Power Mode Logic Chart
SCG1 LPM0 LPM1 LPM2 LPM3 LPM4 0 0 1 1 X SCG0 0 1 0 1 X OscOff 0 0 0 0 1 CPUOff 1 1 1 1 1
These modes are illustrated in Figure 3-10.
Figure 3-10. MSP430x3xx Family Operating Modes
RST/NMI Reset Active VCC On
POR WDT Active, Time Expired, Overflow WDTIFG = 1 WDTIFG = 1 WDT Active, Security Key Violation WDTIFG = 0 PUC RST/NMI is Reset Pin FLL is Slowed Down WDT is Active
RST/NMI NMI Active
CPUOff = 1 SCG0,1 = 0 LP Mode LPM0 CPU Off, FLL On MCLK on, ACLK On
Active Mode CPU is Active Various Modules are Active
CPUOff = 1 OscOff = 1 SG0,1 = X LP-Mode LPM4 CPU Off, FLL Off MCLK Off, ACLK Off DC Generator Off
CPUOff = 1 SCG0 = 1 SCG1 = 0
LP Mode LPM1 CPU Off, FLL Off MCLK On, ACLK On
CPUOff = 1 SCG0 = 0 SCG1 = 1
CPUOff = 1 SCG0,1 = 1 LP Mode LPM3 CPU Off, FLL Off MCLK Off, ACLK On DC Generator Off
LP Mode LPM2 CPU Off, FLL Off MCLK Off, ACLK On
System Resets, Interrupts, and Operating Modes
3-17
Operating Modes
Figure 3-11. Typical Current Consumption vs Operating Modes
730
700 600 500 400 300 200 100 0 ICC/ A
400
VCC = 5 V VCC = 3 V
100 50 100 50 13 6 4 1.3 0.1 0.1
AM
LPM0
LPM1 LPM2 Operating Modes
LPM3
LPM4
The low-power modes 1-4 enable or disable the CPU and the clocks. In addition to the CPU and clocks, enabling or disabling specific peripherals may further reduce total current consumption of the individual modes. The activity state of each peripheral is controlled by the control registers for the individual peripherals. An example is the enable/disable function of the segment lines of the LCD peripheral: they can be turned on or off using a single register bit in the LCD control and mode register. In addition, the SFRs include module enable bits that may be used to enable or disable the operation of specific peripheral modules (see Table 3-4).
3.5.1
Low-Power Modes 0 and 1 (LPM0 and LPM1)
Low-power mode 0 or 1 is selected if bit CPUOff in the status register is set. Immediately after the bit is set the CPU stops operation, and the normal operation of the system core stops. The operation of the CPU halts and all internal bus activities stop until an interrupt request or reset occurs. The system clock generator continues operation, and the clock signals MCLK and ACLK stay active depending on the state of the other three status register bits, SCG0, SCG1, and OscOff. The peripherals are enabled or disabled according with their individual control register settings, and with the module enable registers in the SFRs. All I/O port pins and RAM/registers are unchanged. Wake up is possible through all enabled interrupts. The following are examples of entering and exiting LPM0. The method shown is applicable to all low-power modes. The following example describes entering into low-power mode 0.
;===Main program flow with switch to CPUOff Mode============== ; BIS #18h,SR ;Enter LPM0 + enable general interrupt GIE ;(CPUOff=1, GIE=1). The PC is incremented ;during execution of this instruction and ;points to the consecutive program step. ...... ;The program continues here if the CPUOff ;bit is reset during the interrupt service ;routine. Otherwise, the PC retains its ;value and the processor returns to LPM0.
3-18
Operating Modes
The following example describes clearing low-power mode 0.
;===Interrupt service routine================================= ...... ;CPU is active while handling interrupts BIC #10h,0(SP) ;Clears the CPUOff bit in the SR contents ;that were stored on the stack. RETI ;RETI restores the CPU to the active state ;because the SR values that are stored on ;the stack were manipulated. This occurs ;because the SR is pushed onto the stack ;upon an interrupt, then restored from the ;stack after the RETI instruction.
3.5.2
Low-Power Modes 2 and 3 (LPM2 and LPM3)
Low-power mode 2 or 3 is selected if bits CPUOff and SCG1 in the status register are set. Immediately after the bits are set, CPU, and MCLK operations halt and all internal bus activities stop until an interrupt request or reset occurs. Peripherals that operate with the MCLK signal are inactive because the clock signal is inactive. Peripherals that operate with the ACLK signal are active or inactive according with the individual control registers and the module enable bits in the SFRs. All I/O port pins and the RAM/registers are unchanged. Wake up is possible by enabled interrupts coming from active peripherals or RST/NMI.
3.5.3
Low-Power Mode 4 (LPM4)
In low-power mode 4 all activities cease; only the RAM contents, I/O ports, and registers are maintained. Wake up is only possible by enabled external interrupts. Before activating LPM4, the software should consider the system conditions during the low-power mode period. The two most important conditions are environmental (that is, temperature effect on the DCO), and the clocked operation conditions. The environment defines whether the value of the frequency integrator should be held or corrected. A correction should be made when ambient conditions are anticipated to change drastically enough to increase or decrease the system frequency while the device is in LPM4.
System Resets, Interrupts, and Operating Modes
3-19
Basic Hints for Low-Power Applications
3.6 Basic Hints for Low-Power Applications
There are some basic practices to follow when current consumption is a critical part of a system application:
-
Switch off analog circuitry when possible. Select the lowest possible operating frequency for the core and the individual peripheral module. Select the weakest drive capability if an LCD is used or switch the drive off. Use the interrupt driven software; the program starts execution rapidly. Tie all unused inputs to an applicable voltage level. The list below defines the correct termination for all unused pins.
PIN
AVCC: AVSS: SVCC: A0 to A7: Xout: XBUF: CI: TP0.0 to TP0.5: Px.0 to Px.7: R03: R13: R23: R33: S0 to S1: S3 to S20: Com0 to Com3: RST/NMI: TDO: TDI: TMS: TCK: specific terRefer to device s ecific datasheets for the correct ter mination of these pins.
Potential
DVCC DVSS open open open open VSS open open VSS VSS VSS open open open open DVCC resp. VCC
Comment
May be used as a low impedance output Switched to analog inputs: AEN.x=0
May be used as a digital input TP.5 switched to output direction, others to Hi-Z Unused ports switched to output direction
Switched to output direction
Pullup resistor 100k
3-20
Chapter 4
Memory
MSP430 devices are configured as a von-Neumann architecture. It has code memory, data memory, and peripherals in one address space. As a result, the same instructions are used for code, data, or peripheral accesses. Also, code may be executed from RAM.
Topic
4.1 4.2 4.3 4.4
Page
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 Data in the Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 Internal ROM Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 RAM and Peripheral Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
Memory
4-1
Introduction
4.1 Introduction
All of the physically separated memory areas (ROM, RAM, SFRs, and peripheral modules) are mapped into the common address space, as shown in Figure 4-1 for the MSP430 family. The addressable memory space is 64KB. Future expansion is possible.
Figure 4-1. Memory Map of Basic Address Space
Address (Hex.) 0FFFFh 0FFE0h 0FFDFh Function Access
Interrupt Vector Table Program Memory Branch Control Tables Data Tables...
ROM
Word/Byte
ROM
Word/Byte
0200h 01FFh
Data Memory
RAM Timer, ADC, . . . I/O, LCD 8bT/C, . . . SFR
Word/Byte Word
16-Bit Peripheral Modules 0100h 0FFh 010h 0Fh 0h 8-Bit Peripheral Modules Special Function Registers
Byte Byte
The memory data bus (MDB) is 16- or 8-bits wide. For those modules that can be accessed with word data the width is always 16 bits. For the other modules, the width is 8 bits, and they must be accessed using byte instructions only. The program memory (ROM) and the data memory (RAM) can be accessed with byte or word instructions.
Figure 4-2. Memory Data Bus
Address Range 0000h - 00FFh LCD USART High Byte Data Bus Low Byte SFRs SCI Byte/Word Access ADC WDT ROM RAM CPU
8-Bit Peripheral Modules, Byte Access
16-Bit Peripheral Modules, Word Access
4-2
Data in the Memory
4.2 Data in the Memory
Bytes are located at even or odd addresses as shown in Figure 4-3. However, words are only located at even addresses. Therefore, when using word instructions, only even addresses may be used. The low byte of a word is always at an even address. The high byte of a word is at the next odd address after the address of the word. For example, if a data word is located at address xxx2h, then the low byte of that data word is located at address xxx2h, and the high byte of that word is located at address xxx3h.
Figure 4-3. Bits, Bytes, and Words in a Byte-Organized Memory
xxxAh 15 7 14 6 . . Bits . . . . Bits . . Byte Byte Word (High Byte) Word (Low Byte) 9 1 8 0 xxx9h xxx8h xxx7h xxx6h xxx5h xxx4h xxx3h
Memory
4-3
Internal ROM Organization
4.3 Internal ROM Organization
Various sizes of ROM (OTP, masked-ROM, or EPROM) are available within the 64-kB address space, as shown in Figure 4-4. The common address space is shared with SFRs, peripheral module registers, data and code memory. The SFRs and peripheral modules are mapped into the address range, starting with 0 and ending with 01FFh. The remaining address space, 0200h to 0FFFFh, is shared by data and code memory. The start address for ROM depends on the amount of ROM present. The interrupt vector table is mapped into the the upper 16 words of ROM address space, with the highest priority interrupt vector at the highest ROM word address (0FFFEh). See the individual data sheets for specific memory maps.
Figure 4-4. ROM Organization
0FFFEh 0FFE0h Vectors 4k 0F000h 0EFFFh 12 k Vectors Vectors Vectors
0D000h 0CFFFh
32 k xx k
08000h
4.3.1
Processing of ROM Tables
The MSP430 architecture allows for the storage and usage of large tables in ROM without the need to copy the tables to RAM before using them. This ROM accessing of tables allows fast and clear programming in applications where data tables are necessary. This offers the flexible advantages listed below, and saves on ROM and RAM requirements. To access these tables, all word and byte instructions can be used.
4-4
ROM storage of an output programmable logic array (OPLA) for display character conversion The use of as many OPLA terms as needed (no restriction on n terms) OTP version automatically includes OPLA programmability Computed table accessibility (for example, for a bar graph display) Table-supported program flows
Internal ROM Organization
4.3.2
Computed Branches and Calls
Computed branches and subroutine calls are possible using standard instructions. The call and branch instructions use the same addressing modes as the other instructions. The addressing modes allow indirect-indirect addressing that is ideally suited for computed branches and calls. This programming technique permits a program structure that is different from conventional 8- and 16-bit microcontrollers. Most of the routines can be handled easily by using software status handling instead of flag-type program-flow control. The computed branch and subroutine calls are valid throughout the entire ROM space.
Memory
4-5
RAM and Peripheral Organization
4.4 RAM and Peripheral Organization
The entire RAM can be accessed with byte or word instructions using the appropriate instruction suffix. The peripheral modules, however, are located in two different address spaces and must be accessed with the appropriate instruction length.
4.4.1
The SFRs are byte-oriented and mapped into the address space from 0h up to 0Fh. Peripheral modules that are byte-oriented are mapped into the address space from 010h up to 0FFh. Peripheral modules that are word-oriented are mapped into the address space from 100h up to 01FFh.
Random Access Memory
RAM can be used for both code and data memory. Code accesses are always performed on even byte addresses. The instruction mnemonic suffix defines the data as being word or byte data. Example:
ADD.B ADDC.B ADD ADDC &TCDATA,TCSUM_L TCSUM_H R5,SUM_A SUM_B = = ADD.W ADDC.W R5,SUM_A SUM_A ;Byte access ;Byte access ;Word access ;Word access
A word consists of two bytes: a high byte (bit 15 to bit 8), and a low byte (bit 7 to bit 0) as shown in Figure 4-5. It must always align to an even address.
Figure 4-5. Byte and Word Operation
xxxAh Byte1: 012h Byte2: 034h Word1 (High Byte): 056h Word1 (Low Byte): 078h Word2 (High Byte): 09Ah Word2 (Low Byte): 0BCh ADD.B Byte1, Byte2: xxx9h Byte2 = 012h + 034h = 046h xxx8h xxx7h xxx6h ADD.W Word1, Word2: xxx5h Word2 = 05678h + 09ABCh = 0F134h xxx4h xxx3h
All operations on the stack and PC are word operations and use even-aligned memory addresses.
4-6
RAM and Peripheral Organization
In the following examples, word-to-word and byte-to-byte operations show the results of the operation and the status bit information. Example Word-Word Operation R5 = 0F28Eh EDE .EQU 0212h Mem(0F28Eh) = 0FFFEh Mem(0212h) = 00112h ADD @R5,&EDE Example Byte-Byte Operation R5 = 0223h EDE .EQU 0202h Mem(0223h) = 05Fh Mem(0202h) = 043h ADD.B @R5,&EDE
Mem(0212h) = 00110h C = 1, Z = 0, N = 0
Mem(0202h) = 0A2h C = 0, Z = 0, N = 1
Figure 4-6 shows the register-byte and byte-register operations.
Figure 4-6. Register-Byte/Byte-Register Operations
Register-Byte Operation High Byte Unused Low Byte Register Byte-Register Operation High Byte Low Byte Byte Memory
Byte
Memory
0h
Register
The following examples describe the register-byte and byte-register operations. Example Register-Byte Operation Example Byte-Register Operation R5 = 0A28Fh R6 = 0203h Mem(0203h) = 012h ADD.B R5,0(R6) 08Fh + 012h 0A1h Mem (0203h) = 0A1h C = 0, Z = 0, N = 1 (Low byte of register) + (Addressed byte) ->(Addressed byte) R5 = 01202h R6 = 0223h Mem(0223h) = 05Fh ADD.B 05Fh + 002h 00061h R5 = 00061h C = 0, Z = 0, N = 0 (Addressed byte) + (Low byte of register) ->(Low byte of register, zero to High byte) ;Low byte of R5 ;->Store into R5 ;High byte is 0 @R6,R5
Note: Word-Byte Operations Word-byte or byte-word operations on memory data are not supported. Each register-byte or byte-register is performed as a byte operation.
Memory
4-7
RAM and Peripheral Organization
4.4.2
Peripheral Modules--Address Allocation
Some peripheral modules are accessible only with byte instructions, while others are accessible only with word instructions. The address space from 0100 to 01FFh is reserved for word modules, and the address space from 00h to 0FFh is reserved for byte modules. Peripheral modules that are mapped into the word address space must be accessed using word instructions (for example, MOV R5,&WDTCTL). Peripheral modules that are mapped into the byte address space must be accessed with byte instructions (MOV.B #1,&TCCTL). The addressing of both is through the absolute addressing mode or the 16-bit working registers using the indexed, indirect, or indirect autoincrement addressing mode. See Figure 4-7 for the RAM/peripheral organization.
Figure 4-7. Example of RAM/Peripheral Organization
Address (Hex.) 01FFh 16-Bit Peripheral Modules 0100h 0FFh 010h 0Fh 0h Function 7 0 Timer, ADC, . . . I/O, LCD 8b T/C, . . . SFR Word Access
8-Bit Peripheral Modules Special Function Registers
Byte Byte
4.4.2.1
Word Modules
Word modules are peripherals that are connected to the 16-bit MDB. Word modules can be accessed with word or byte instructions. If byte instructions are used, only even addresses are permissible, and the high byte of the result is always '0'. The peripheral file address space is organized into sixteen frames with each frame representing eight words as described in Table 4-1.
4-8
RAM and Peripheral Organization
Table 4-1. Peripheral File Address Map--Word Modules
Address 1F0h - 1FFh 1E0h - 1EFh 1D0h - 1DFH 1C0h - 1CFH 1B0h - 1BFH 1A0h - 1AFH 190h - 19FH 180h - 18FH 170h - 17FH 160h - 16FH 150h - 15FH 140h - 14FH 130h - 13FH 120h - 12FH 110h - 11FH 100h - 10FH Description Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Timer_A Timer_A Reserved Reserved Multiplier Watchdog Timer Analog-to-Digital Converter Reserved
4.4.2.2
Byte Modules
Byte modules are peripherals that are connected to the reduced (eight LSB) MDB. Access to byte modules is always by byte instructions. The hardware in the peripheral byte modules takes the low byte (the LSBs) during a write operation. Byte instructions operate on byte modules without any restrictions. Read access to peripheral byte modules using word instructions results in unpredictable data in the high byte. Word data is written into a byte module by writing the low byte to the appropriate peripheral register and ignoring the high byte. The peripheral file address space is organized into sixteen frames as described in Table 4-2.
Memory
4-9
RAM and Peripheral Organization
Table 4-2. Peripheral File Address Map--Byte Modules
Address 00F0h - 00FFh 00E0h - 00EFh 00D0h - 00DFh 00C0h - 00CFh 00B0h - 00BFh 00A0h - 00AFh 0090h - 009Fh 0080h - 008Fh 0070h - 007Fh 0060h - 006Fh 0050h - 005Fh 0040h - 004Fh 0030h - 003Fh 0020h - 002Fh 0010h - 001Fh 0000h - 000Fh Description Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved USART Reserved System clock generator, EPROM and Crystal Buffer Basic timer, 8-Bit Timer/Counter, Timer/Port LCD Digital I/O port P1 and P2 control Digital I/O port P0, P3, and P4 control Special function
4.4.3
Peripheral Modules--Special Function Registers (SFRs)
The system configuration and the individual reaction of the peripheral modules to the processor operation is configured in the SFRs as described in Table 4-3. The SFRs are located in the lower address range, and are organized by bytes. SFRs must be accessed using byte instructions only.
4-10
RAM and Peripheral Organization
Table 4-3. Special Function Register Address Map
Address 7 000Fh 000Eh 000Dh 000Ch 000Bh 000Ah 0009h 0008h 0007h 0006h 0005h 0004h 0003h 0002h 0001h 0000h Data Bus 0 Not yet defined or implemented Not yet defined or implemented Not yet defined or implemented Not yet defined or implemented Not yet defined or implemented Not yet defined or implemented Not yet defined or implemented Not yet defined or implemented Not yet defined or implemented Not yet defined or implemented Module enable 2; ME2.2 Module enable 1; ME1.1 Interrupt flag reg. 2; IFG2.x Interrupt flag reg.1; IFG1.x Interrupt enable 2; IE2.x Interrupt enable 1; IE1.x
The system power consumption is influenced by the number of enabled modules and their functions. Disabling a module from the actual operation mode reduces power consumption while other parts of the controller remain fully active (unused pins must be tied appropriately or power consumption will increase; see Basic Hints for Low Power Applications in section 3.6.
Memory
4-11
4-12
Chapter 5
16-Bit CPU
The MSP430 von-Neumann architecture has RAM, ROM, and peripherals in one address space, both using a single address and data bus. This allows using the same instruction to access either RAM, ROM, or peripherals and also allows code execution from RAM.
Topic
5.1 5.2 5.3 5.4
Page
CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7 Instruction Set Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-17 Instruction Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-23
16-Bit CPU
5-1
CPU Registers
5.1 CPU Registers
Sixteen 16-bit registers (R0, R1, and R4 to R15) are used for data and addresses and are implemented in the CPU. They can address up to 64 Kbytes (ROM, RAM, peripherals, etc.) without any segmentation. The complete CPU-register set is described in Table 5-1. Registers R0, R1, R2, and R3 have dedicated functions, which are described in detail later.
Table 5-1. Register by Functions
Program counter (PC) Stack pointer (SP) Status register (SR) Constant generator (CG1) Constant generator (CG2) Working register R4 Working register R5 : : Working register R13 Working register R14 Working register R15 R0 R1 R2 R3 R4 R5 : : R13 R14 R15
5.1.1
The Program Counter (PC)
The 16-bit program counter points to the next instruction to be executed. Each instruction uses an even number of bytes (two, four, or six), and the program counter is incremented accordingly. Instruction accesses are performed on word boundaries, and the program counter is aligned to even addresses. Figure 5-1 shows the program counter bits.
Figure 5-1. Program Counter
15 Program Counter Bits 15 to 1 1 0 0
5.1.2
The System Stack Pointer (SP)
The system stack pointer must always be aligned to even addresses because the stack is accessed with word data during an interrupt request service. The system SP is used by the CPU to store the return addresses of subroutine calls and interrupts. It uses a predecrement, postincrement scheme. The advantage of this scheme is that the item on the top of the stack is available. The SP can be used by the user software (PUSH and POP instructions), but the user should remember that the CPU also uses the SP. Figure 5-2 shows the system SP bits.
Figure 5-2. System Stack Pointer
15 System Stack Pointer Bits 15 to 1 1 0 0
5-2
CPU Registers
5.1.2.1
Examples for System SP Addressing (Refer to Figure 5-4)
MOV MOV MOV MOV MOV PUSH POP MOV SP,R4 @SP,R5 2(SP),R6 R7,0(SP) R8,4(SP) R12 R12 @SP+,R5 ; SP -> R4 ; Item I3 (TOS) -> R5 ; Item I2 -> R6 ; Overwrite TOS with R7 ; Modify item I1 ; Store R12 in address 0xxxh - 6; SP points to same address ; Restore R12 from address 0xxxh - 6; SP points to 0xxxh - 4 ; Item I3 -> R5 (popped from stack); same as POP instruction
Figure 5-3 shows stack usage.
Figure 5-3. Stack Usage
Address 0xxxh 0xxxh - 2 0xxxh - 4 0xxxh - 6 0xxxh - 8 I1 I2 I3 SP PUSH #1 I1 I2 I3 #1 SP POP R8 I1 I2 I3 SP
5.1.2.2
Special Cases--PUSH SP and POP SP
The special cases of using the SP as an argument to the PUSH and POP instructions are described below.
Figure 5-4. PUSH SP and POP SP
PUSH SP POP SP
SPold SP1 SP1 SP2 SP1
The stack pointer is changed after a PUSH SP instruction.
The stack pointer is not changed after a POP SP instruction.
After the sequence
PUSH SP I I POP SP ; SP1 is stack pointer after this instruction
; SP2 is stack pointer after this instruction
The stack pointer is two bytes lower than before this sequence.
16-Bit CPU
5-3
CPU Registers
5.1.3
The Status Register (SR)
The status register SR contains the following CPU status bits:
15
V SCG1 SCG0 OscOff CPUOff GIE N Z C
Overflow bit System clock generator control bit 1 System clock generator control bit 0 Crystal oscillator off bit CPU off bit General interrupt enable bit Negative bit Zero bit Carry bit
Figure 5-5 shows the SR bits.
Figure 5-5. Status Register Bits
9 8 V 7 SCG1 SCG0 OSC CPU GIE Off Off N Z 0 C Reserved For Future Enhancements
rw-0
Table 5-2 describes the status register bits.
Table 5-2. Description of Status Register Bits
Bit V Description Overflow bit. Set if the result of an arithmetic operation overflows the signed-variable range. The bit is valid for both data formats, byte and word: ADD(.B), ADDC(.B) Set when: Positive + Positive = Negative Negative + Negative = Positive, otherwise reset Set when: Positive - Negative = Negative Negative - Positive = Positive, otherwise reset
SUB(.B), SUBC(.B), CMP(.B)
SCG1, SCG0 OscOFF
These bits control four activity states of the system-clock generator and therefore influence the operation of the processor system. If set, the crystal oscillator enters off mode: all activities cease; however, the RAM contents, the port, and the registers are maintained. Wake up is possible only through enabled external interrupts when the GIE bit is set and from the NMI. If set, the CPU enters off mode: program execution stops. However, the RAM, the port registers, and especially the enabled peripherals (for example, basic timer, UART, etc.) stay active. Wake up is possible through all enabled interrupts. If set, all enabled maskable interrupts are handled. If reset, all maskable interrupts are disabled. The GIE bit is cleared by interrupts and restored by the RETI instruction as well as by other appropriate instructions. Set if the result of an operation is negative. Word operation: Negative bit is set to the value of bit 15 of the result Byte operation: Negative bit is set to the value of bit 7 of the result Set if the result of byte or word operation is 0; cleared if the result is not 0. Set if the result of an operation produced a carry; cleared if no carry occurred. Some instructions modify the carry bit using the inverted zero bits.
CPU Off
GIE
N
Z C
5-4
CPU Registers
Note: Status Register Bits V, N, Z and C The status register bits V, N, Z, and C are modified only with the appropriate instruction. For additional information, see the detailed description of the instruction set in Appendix B.
5.1.4
The Constant Generator Registers CG1 and CG2
Commonly-used constants are generated with the constant generator registers R2 and R3, without requiring an additional 16-bit word of program code. The constant used for immediate values is defined by the addressing mode bits (As) as described in Table 5-3. See Section 5.3 for a description of the addressing mode bits (As).
Table 5-3. Values of Constant Generators CG1, CG2
Register R2 R2 R2 R2 R3 R3 R3 R3 As 00 01 10 11 00 01 10 11 Constant ----- (0) 00004h 00008h 00000h 00001h 00002h 0FFFFh Remarks Register mode Absolute address mode +4, bit processing +8, bit processing 0, word processing +1 +2, bit processing -1, word processing
The major advantages of this type of constant generation are:
-
No special instructions required Reduced code memory requirements: no additional word for the six most used constants Reduced instruction cycle time: no code memory access to retrieve the constant
The assembler uses the constant generator automatically if one of the six constants is used as a source operand in the immediate addressing mode. The status register SR/R2, used as a source or destination register, can be used in the register mode only. The remaining combinations of addressing-mode bits are used to support absolute-address modes and bit processing without any additional code. Registers R2 and R3, used in the constant mode, cannot be addressed explicitly; they act like source-only registers.
16-Bit CPU
5-5
CPU Registers
The RISC instruction set of the MSP430 only has 27 instructions. However, the constant generator allows the MSP430 assembler to support 24 additional, emulated instructions. For example, the single-operand instruction: CLR dst
is emulated by the double-operand instruction with the same length: MOV R3,dst or the equivalent MOV #0,dst where #0 is replaced by the assembler, and R3 is used with As = 00, which results in:
-
One word instruction No additional control operation or hardware within the CPU Register-addressing mode for source: no extra-fetch cycle for constants (#0)
5-6
Addressing Modes
5.2 Addressing Modes
All seven addressing modes for the source operand and all four addressing modes for the destination operand can address the complete address space. The bit numbers in Table 5-4 describe the contents of the As and Ad mode bits. See Section 5.3 for a description of the source address As and the destination address Ad bits.
Table 5-4. Source/Destination Operand Addressing Modes
As/Ad 00/0 01/1 Addressing Mode Register mode Indexed mode Syntax Rn X(Rn) Description Register contents are operand (Rn + X) points to the operand X is stored in the next word 01/1 Symbolic mode ADDR (PC + X) points to the operand X is stored in the next word. Indexed mode X(PC) is used. 01/1 10/- 11/- Absolute mode Indirect register mode Indirect autoincrement Immediate mode &ADDR @Rn @Rn+ The word following the instruction contains the absolute address. Rn is used as a pointer to the operand. Rn is used as a pointer to the operand. Rn is incremented afterwards. The word following the instruction contains the immediate constant N. Indirect autoincrement mode @PC+ is used.
11/-
#N
The seven addressing modes are explained in detail in the following sections. Most of the examples show the same addressing mode for the source and destination, but any valid combination of source and destination addressing modes is possible in an instruction.
16-Bit CPU
5-7
Addressing Modes
5.2.1
Register Mode
The register mode is described in Table 5-5.
Table 5-5. Register Mode Description
Assembler Code MOV R10,R11 Content of ROM MOV R10,R11
Length: Operation: Comment: Example:
Before: R10 0A023h
One or two words Move the content of R10 to R11. R10 is not affected. Valid for source and destination MOV R10,R11
After: R10 0A023h
R11
0FA15h
R11
0A023h
PC
PCold
PC
PCold + 2
Note: Data in Registers The data in the register can be accessed using word or byte instructions. If byte instructions are used, the high byte is always 0 in the result. The status bits are handled according to the result of the byte instruction.
5-8
Addressing Modes
5.2.2
Indexed Mode
The indexed mode is described in Table 5-6.
Table 5-6. Indexed Mode Description
Assembler Code MOV 2(R5),6(R6) Content of ROM MOV X(R5),Y(R6) X=2 Y=6
Length: Operation:
Two or three words Move the contents of the source address (contents of R5 + 2) to the destination address (contents of R6 + 6). The source and destination registers (R5 and R6) are not affected. In indexed mode, the program counter is incremented automatically so that program execution continues with the next instruction. Valid for source and destination MOV 2(R5),6(R6):
Register After: Address Space 0xxxxh 0FF16h 00006h 0FF14h 0FF12h 00002h 04596h Register PC R5 01080h R6 0108Ch
Comment: Example:
Before: Address Space
0FF16h 0FF14h 0FF12h
00006h 00002h 04596h PC
R5 R6
01080h 0108Ch
01094h 01092h 01090h
0xxxxh 05555h 0xxxxh
0108Ch +0006h 01092h
01094h 01092h 01090h
0xxxxh 01234h 0xxxxh
01084h 01082h 01080h
0xxxxh 01234h 0xxxxh
01080h +0002h 01082h
01084h 01082h 01080h
0xxxxh 01234h 0xxxxh
16-Bit CPU
5-9
Addressing Modes
5.2.3
Symbolic Mode
The symbolic mode is described in Table 5-7.
Table 5-7. Symbolic Mode Description
Assembler Code MOV EDE,TONI Content of ROM MOV X(PC),Y(PC) X = EDE - PC Y = TONI - PC
Length: Operation:
Two or three words Move the contents of the source address EDE (contents of PC + X) to the destination address TONI (contents of PC + Y). The words after the instruction contain the differences between the PC and the source or destination addresses. The assembler computes and inserts offsets X and Y automatically. With symbolic mode, the program counter (PC) is incremented automatically so that program execution continues with the next instruction. Valid for source and destination MOV EDE,TONI ;Source address EDE = 0F016h, ;dest. address TONI=01114h
After: Address Space 0xxxxh 011FEh 0F102h 04090h Register PC
Comment: Example:
Before:
Address Space 011FEh 0F102h 04090h PC
Register
0FF16h 0FF14h 0FF12h
0FF16h 0FF14h 0FF12h
0F018h 0F016h 0F014h
0xxxxh 0A123h 0xxxxh
0FF14h +0F102h 0F016h
0F018h 0F016h 0F014h
0xxxxh 0A123h 0xxxxh
01116h 01114h 01112h
0xxxxh 01234h 0xxxxh
0FF16h +011FEh 01114h
01116h 01114h 01112h
0xxxxh 0A123h 0xxxxh
5-10
Addressing Modes
5.2.4
Absolute Mode
The absolute mode is described in Table 5-8.
Table 5-8. Absolute Mode Description
Assembler Code MOV &EDE,&TONI Content of ROM MOV X(0),Y(0) X = EDE Y = TONI
Length: Operation:
Two or three words Move the contents of the source address EDE to the destination address TONI. The words after the instruction contain the absolute address of the source and destination addresses. With absolute mode, the PC is incremented automatically so that program execution continues with the next instruction. Valid for source and destination MOV &EDE,&TONI ;Source address EDE = 0F016h, ;dest. address TONI=01114h
After: Address Space 0xxxxh 01114h 0F016h 04292h Register PC
Comment: Example:
Before:
Address Space 01114h 0F016h 04292h PC
Register
0FF16h 0FF14h 0FF12h
0FF16h 0FF14h 0FF12h
0F018h 0F016h 0F014h
0xxxxh 0A123h 0xxxxh
0F018h 0F016h 0F014h
0xxxxh 0A123h 0xxxxh
01116h 01114h 01112h
0xxxxh 01234h 0xxxxh
01116h 01114h 01112h
0xxxxh 0A123h 0xxxxh
This address mode is mainly for hardware peripheral modules that are located at an absolute, fixed address. These are addressed with absolute mode to ensure software transportability (for example, position-independent code).
16-Bit CPU
5-11
Addressing Modes
5.2.5
Indirect Mode
The indirect mode is described in table 5-9.
Table 5-9. Indirect Mode Description
Assembler Code MOV @R10,0(R11) Content of ROM MOV @R10,0(R11)
Length: Operation:
One or two words Move the contents of the source address (contents of R10) to the destination address (contents of R11). The registers are not modified. Valid only for source operand. The substitute for destination operand is 0(Rd). MOV.B @R10,0(R11)
Register After: Address Space 0xxxxh 0FF16h 0000h 0FF14h 0FF12h 04AEBh 0xxxxh Register PC R10 0FA33h R11 002A7h
Comment:
Example:
Before: Address Space 0xxxxh 0000h 04AEBh 0xxxxh
0FF16h 0FF14h 0FF12h
R10 PC R11
0FA33h 002A7h
0FA34h 0FA32h 0FA30h
0xxxxh 05BC1h 0xxxxh
0FA34h 0FA32h 0FA30h
0xxxxh 05BC1h 0xxxxh
002A8h 002A7h 002A6h
0xxh 012h 0xxh
002A8h 002A7h 002A6h
0xxh 05Bh 0xxh
5-12
Addressing Modes
5.2.6
Indirect Autoincrement Mode
The indirect autoincrement mode is described in Table 5-10.
Table 5-10.Indirect Autoincrement Mode Description
Assembler Code MOV @R10+,0(R11) Content of ROM MOV @R10+,0(R11)
Length: Operation:
One or two words Move the contents of the source address (contents of R10) to the destination address (contents of R11). Register R10 is incremented by 1 for a byte operation, or 2 for a word operation after the fetch; it points to the next address without any overhead. This is useful for table processing. Valid only for source operand. The substitute for destination operand is 0(Rd) plus second instruction INCD Rd. MOV @R10+,0(R11)
Register After: Address Space 0xxxxh 00000h 0xxxxh PC R10 0FA34h R11 010A8h Register
Comment: Example:
Before:
Address Space 0xxxxh 00000h 0xxxxh
0FF18h 0FF16h 0FF12h
R10 PC R11
0FA32h 010A8h
0FF18h 0FF16h 0FF12h
0FF14h 04ABBh
0FF14h 04ABBh
0FA34h 0FA32h 0FA30h
0xxxxh 05BC1h 0xxxxh
0FA34h 0FA32h 0FA30h
0xxxxh 05BC1h 0xxxxh
010AAh 010A8h 010A6h
0xxxxh 01234h 0xxxxh
010AAh 010A8h 010A6h
0xxxxh 05BC1h 0xxxxh
The autoincrementing of the register contents occurs after the operand is fetched. This is shown in Figure 5-6.
Figure 5-6. Operand Fetch Operation
Instruction Address Operand +1/ +2
16-Bit CPU
5-13
Addressing Modes
5.2.7
Immediate Mode
The immediate mode is described in Table 5-11.
Table 5-11. Immediate Mode Description
Assembler Code MOV #45,TONI Content of ROM MOV @PC+,X(PC) 45 X = TONI - PC
Length:
Two or three words It is one word less if a constant of CG1 or CG2 can be used. Move the immediate constant 45, which is contained in the word following the instruction, to destination address TONI. When fetching the source, the program counter points to the word following the instruction and moves the contents to the destination. Valid only for a source operand. MOV #45,TONI
Address Space 01192h 00045h 040B0h PC Register After: Address Space 0xxxxh 01192h 00045h 040B0h Register PC
Operation:
Comment: Example:
Before:
0FF16h 0FF14h 0FF12h
0FF18h 0FF16h 0FF14h 0FF12h
010AAh 010A8h 010A6h
0xxxxh 01234h 0xxxxh
0FF16h +01192h 010A8h
010AAh 010A8h 010A6h
0xxxxh 00045h 0xxxxh
5-14
Addressing Modes
5.2.8
Clock Cycles, Length of Instruction
The operating speed of the CPU depends on the instruction format and addressing modes. The number of clock cycles refers to the MCLK.
5.2.8.1
Format-I Instructions
Table 5-12 describes the CPU format-I instructions and addressing modes.
Table 5-12.Instruction Format I and Addressing Modes
Address Mode As 00, Rn 00, Rn Ad 0, Rm 0, PC 1, x(Rm) 1, EDE 1, &EDE 0, Rm No. of Cycles 1 2 4 Length of Instruction 1 1 2 2 2 2 2 2 3 3 3 3 1 2 2 2 1 1 2 2 2 3 2 3 MOV BR ADD XOR MOR MOV AND MOV ADD CMP MOV ADD AND XOR MOV XOR ADD BR MOV BR MOV ADD MOV ADD Example R5,R8 R9 R5,3(R6) R8,EDE R5,&EDE 2(R5),R7 EDE,R6 &EDE,R8 3(R4),6(R9) EDE,TONI 2(R5),&TONI EDE,&TONI @R4,R5 @R5,8(R6) @R5,EDE @R5,&EDE @R5+,R6 @R9+ #20,R9 #2AEh @R9+,2(R4) #33,EDE @R9+,&EDE #33,&EDE
01, x(Rn) 01, EDE 01, &EDE 01, x(Rn) 01, EDE 01, &EDE 10, @Rn 10, @Rn
3
1, x(Rm) 1, TONI 1, &TONI 0, Rm 1, x(Rm) 1, EDE 1, &EDE 0, Rm 0, PC 0, Rm 0, PC 1, x(Rm) 1, EDE 1, &EDE
6
2 5
11, @Rn+ 11, #N 11, @Rn+ 11, #N 11, @Rn+ 11, #N
2 3 2 3 5
16-Bit CPU
5-15
Addressing Modes
5.2.8.2
Format-II Instructions
Table 5-13 describes the CPU format II instructions and addressing modes.
Table 5-13.Instruction Format-II and Addressing Modes
No. of Cycles RRA RRC SWPB SXT 1 4 4 3 3 Length of Instruction (words) 1 2 2 1 1 2
Address Mode A(s/d) 00, Rn 01, X(Rn) 01, EDE 01, &EDE 10, @Rn 11, @Rn+ (see Note) 11, #N
PUSH/ CALL 3/4 5 5 4 4/5
Example SWPB R5 CALL 2(R7) PUSH EDE SXT &EDE RRC @R9 SWPB @R10+ CALL #81H
Note: Instruction Format II Immediate Mode Do not use instructions RRA, RRC, SWPB, and SXT with the immediate mode in the destination field. Use of these in the immediate mode will result in an unpredictable program operation.
5.2.8.3
Format-III Instructions
Format-III instructions are described as follows: Jxx--all instructions need the same number of cycles, independent of whether a jump is taken or not. Clock cycle: Two cycles Length of instruction: One word
5.2.8.4
Miscellaneous-Format Instructions
Table 5-14 describes miscellaneous-format instructions.
Table 5-14.Miscellaneous Instructions or Operations
Activity RETI Interrupt WDT reset Reset (RST/NMI)
Length of instruction
Clock Cycle 5 cycles 1 word 6 cycles 4 cycles 4 cycles
5-16
Instruction Set Overview
5.3 Instruction Set Overview
This section gives a short overview of the instruction set. The addressing modes are described in Section 5.2. Instructions are either single or dual operand or jump. The source and destination parts of an instruction are defined by the following fields: src dst As S-reg Ad D-reg B/W The source operand defined by As and S-reg The destination operand defined by Ad and D-reg The addressing bits responsible for the addressing mode used for the source (src) The working register used for the source (src) The addressing bits responsible for the addressing mode used for the destination (dst) The working register used for the destination (dst) Byte or word operation: 0: word operation 1: byte operation
Note: Destination Address Destination addresses are valid anywhere in the memory map. However, when using an instruction that modifies the contents of the destination, the user must ensure the destination address is writeable. For example, a masked-ROM location would be a valid destination address, but the contents are not modifiable, so the results of the instruction would be lost.
16-Bit CPU
5-17
Instruction Set Overview
5.3.1
Double-Operand Instructions
Figure 5-7 illustrates the double-operand instruction format.
Figure 5-7. Double Operand Instruction Format
15 14 13 12 11 10 9 8 7 Ad 6 B/W 5 4 As 3 2 1 0 Opcode S-Reg D-Reg
Table 5-15 describes the effects of an instruction on double operand instruction status bits.
Table 5-15.Double Operand Instruction Format Results
Mnemonic MOV ADD ADDC SUB SUBC CMP DADD AND BIT BIC BIS XOR S-Reg, D-Reg src,dst src,dst src,dst src,dst src,dst src,dst src,dst src,dst src,dst src,dst src,dst src,dst Operation V src -> dst src + dst -> dst src + dst + C -> dst dst + .not.src + 1 -> dst dst + .not.src + C -> dst dst - src src + dst + C -> dst (dec) src .and. dst -> dst src .and. dst .not.src .and. dst -> dst src .or. dst -> dst src .xor. dst -> dst - * * * * * * 0 0 - - * Status Bits N - * * * * * * * * - - * Z - * * * * * * * * - - * C - * * * * * * * * - - *
* - 0 1
The status bit is affected The status bit is not affected The status bit is cleared The status bit is set
Note: Instructions CMP and SUB The instructions CMP and SUB are identical except for the storage of the result. The same is true for the BIT and AND instructions.
5-18
Instruction Set Overview
5.3.2
Single-Operand Instructions
Figure 5-8 illustrates the single-operand instruction format.
Figure 5-8. Single Operand Instruction Format
15 14 13 12 11 Opcode 10 9 8 7 6 B/W 5 4 Ad 3 2 1 0 D/S-Reg
Table 5-16 describes the effects of an instruction on the single operand instruction status bits.
Table 5-16.Single Operand Instruction Format Results
Mnemonic S-Reg, D-Reg Operation V RRC RRA PUSH SWPB CALL dst dst src dst dst C -> MSB ->.......LSB -> C MSB -> MSB ->....LSB -> C SP - 2 -> SP, src -> @ SP swap bytes SP - 2 -> SP PC+2 -> stack, dst -> PC RETI TOS -> SR, SP <- SP + 2 TOS -> PC, SP <- SP + 2 SXT dst Bit 7 -> Bit 8........Bit 15 0 * * * X X X X * 0 - - - Status Bits N * * - - - Z * * - - - C * * - - -
* - 0 1
The status bit is affected The status bit is not affected The status bit is cleared The status bit is set
All addressing modes are possible for the CALL instruction. If the symbolic mode (ADDRESS), the immediate mode (#N), the absolute mode (&EDE) or the indexed mode X (RN) is used, the word that follows contains the address information.
16-Bit CPU
5-19
Instruction Set Overview
5.3.3
Conditional Jumps
Conditional jumps support program branching relative to the program counter. The possible jump range is from - 511 to +512 words relative to the program counter state of the jump instruction. The 10-bit program-counter offset value is treated as a signed 10-bit value that is doubled and added to the program counter. None of the jump instructions affect the status bits. The instruction code fetch and the program counter increment technique end with the formula: PCnew = PCold + 2 + PCoffset x 2 Figure 5-9 shows the conditional-jump instruction format.
Figure 5-9. Conditional-Jump Instruction Format
15 14 Opcode 13 12 11 C 10 9 8 7 6 5 4 3 2 1 0 10-Bit PC Offset
Table 5-17 describes these conditional-jump instructions.
Table 5-17.ConditIonal-Jump Instructions
Mnemonic S-Reg, D-Reg Operation
JEQ/JZ JNE/JNZ JC JNC
JN
Label Label Label Label
Label
Jump to label if zero bit is set Jump to label if zero bit is reset Jump to label if carry bit is set Jump to label if carry bit is reset Jump to label if negative bit is set Jump to label if (N .XOR. V) = 0 Jump to label if (N .XOR. V) = 1 Jump to label unconditionally
JGE JL JMP
Label Label Label
5-20
Instruction Set Overview
5.3.4
Short Form of Emulated Instructions
The basic instruction set, together with the register implementations of the program counter, stack pointer, status register, and constant generator, form the emulated instruction set; these make up the popular instruction set. The status bits are set according to the result of the execution of the basic instruction that replaces the emulated instruction. Table 5-18 describes these instructions.
Table 5-18.Emulated Instructions
Mnemonic Description Status Bits V ArIthmetic Instructions ADC[.W] ADC.B DADC[.W] DADC.B DEC[.W] DEC.B DECD[.W] DECD.B INC[.W] INC.B INCD[.W] INCD.B SBC[.W] SBC.B INV[.W] INV.B RLA[.W] RLA.B RLC[.W] RLC.B CLR[.W] CLR.B CLRC CLRN CLRZ POP SETC SETN SETZ dst dst dst dst dst dst dst dst dst dst dst dst dst dst dst dst dst dst dst dst dst Add carry to destination Add carry to destination Add carry decimal to destination Add carry decimal to destination Decrement destination Decrement destination Double-decrement destination Double-decrement destination Increment destination Increment destination Increment destination Increment destination Subtract carry from destination Subtract carry from destination Invert destination Invert destination Rotate left arithmetically Rotate left arithmetically Rotate left through carry Rotate left through carry Clear destination Clear destination Clear carry bit Clear negative bit Clear zero bit Item from stack Set carry bit Set negative bit Set zero bit * * * * * * * * * * * * * * * * * * * * - - - - - - - - - * * * * * * * * * * * * * * * * * * * * - - - 0 - - - 1 - * * * * * * * * * * * * * * * * * * * * - - - - 0 - - - 1 * * * * * * * * * * * * * * * * * * * * - - 0 - - - 1 - - ADDC ADDC.B DADD DADD.B SUB SUB.B SUB SUB.B ADD ADD.B ADD ADD.B SUBC SUBC.B XOR XOR.B ADD ADD.B ADDC ADDC.B MOV MOV.B BIC BIC BIC MOV BIS BIS BIS #0,dst #0,dst #0,dst #0,dst #1,dst #1,dst #2,dst #2,dst #1,dst #1,dst #2,dst #2,dst #0,dst #0,dst #0FFFFh,dst #-1,dst dst,dst dst,dst dst,dst dst,dst #0,dst #0,dst #1,SR #4,SR #2,SR @SP+,dst #1,SR #4,SR #2,SR N Z C Emulation
Logical Instructions
Data Instructions (common use)
16-Bit CPU
5-21
Instruction Set Overview
Table 5-18. Emulated Instructions (Continued)
Mnemonic Description Status Bits V Data Instructions (common use) (continued) TST[.W] TST.B BR DINT EINT NOP RET dst dst dst Test destination Test destination Branch to . . . Disable interrupt Enable interrupt No operation Return from subroutine 0 0 - - - - - * * - - - - - * * - - - - - * * - - - - - CMP CMP.B MOV BIC BIS MOV MOV #0,dst #0,dst dst,PC #8,SR #8,SR #0h,#0h @SP+,PC N Z C Emulation
Program Flow Instructions
5.3.5
Miscellaneous
Instructions without operands, such as CPUOff, are not provided. Their functions are switched on or off by setting or clearing the function bits in the status register or the appropriate I/O register. Other functions are emulated using dual operand instructions. Some examples are as follows:
BIS #28h,SR ; Enter OscOff mode ; + Enable general interrupt (GIE) BIS #18h,SR ; Enter CPUOff mode ; + Enable general interrupt (GIE) BIC #SVCC,&ACTL ; Switch SVCC off
5-22
Instruction Map
5.4 Instruction Map
The instruction map in Figure 5-10 is an example of how to encode instructions. There is room for more instructions, if needed.
Figure 5-10. Core Instruction Map
000 0x 04x 08x 0Cx 10x 14x 18x 1Cx 20x 24x 28x 2Cx 30x 34x 38x 3Cx 40x-4Cx 50x-5Cx 60x-6Cx 70x-7Cx 80x-8Cx 90x-9Cx A0x-ACx B0x-BCx C0x-CCx D0x-DCx E0x-ECx F0x-FCx 040 080 0C0 100 140 180 1C0 200 240 280 2C0 300 340 380 3C0
RRC RRC.B SWPB
RRA
RRA.B
SXT
PUSH
PUSH.B
CALL
RETI
JNE/JNZ JEQ/JZ JNC JC JN JGE JL JMP MOV, MOV.B ADD, ADD.B ADDC, ADDC.B SUBC, SUBC.B SUB, SUB.B CMP, CMP.B DADD, DADD.B BIT, BIT.B BIC, BIC.B BIS, BIS.B XOR, XOR.B AND, AND.B
16-Bit CPU
5-23
5-24
Chapter 6
Hardware Multiplier
The hardware multiplier is a 16-bit peripheral module. It is not integrated into the CPU. Therefore, it requires no special instructions and operates independent of the CPU. To use the hardware multiplier, the operands are loaded into registers and the results are available the next instruction--no extra cycles are required for a multiplication.
Topic
6.1 6.2 6.3 6.4 6.5
Page
Hardware Multiplier Module Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2 Hardware Multiplier Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3 Hardware Multiplier Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9 Hardware Multiplier Special Function Bits . . . . . . . . . . . . . . . . . . . . . . 6-10 Hardware Multiplier Software Restrictions . . . . . . . . . . . . . . . . . . . . . 6-10
Hardware Multiplier
6-1
Hardware Multiplier Module Support
6.1 Hardware Multiplier Module Support
The hardware multiplier module expands the capabilities of the MSP430 family without changing the basic architecture. Multiplication is possible for:
-
16 x 16 bits 16 x 8 bits 8 x 16 bits 8 x 8 bits
The hardware multiplier module supports four types of multiplication: unsigned multiplication (MPY), signed multiplication (MPYS), unsigned multiplication with accumulation (MAC), and signed multiplication with accumulation (MACS). Figure 6-1 shows how the hardware multiplier module interfaces with the bus system to support multiplication operations.
Figure 6-1. Connection of the Hardware Multiplier Module to the Bus System
ROM RAM
TDI TDO MAB, 16 Bit
CPU Incl. 16 Reg.
Test JTAG MDB, 16 Bit
TMS TCK MPY MPYS MAC MACS Other Modules
6-2
Hardware Multiplier Operation
6.2 Hardware Multiplier Operation
The hardware multiplier has two 16-bit registers for both operands and three registers to store the results of the multiplication. The multiplication is executed correctly when the first operand is written to the operand register OP1 prior to writing the second operand to OP2. Writing the first operand to the applicable register selects the type of multiplication. Writing the second operand to OP2 starts the multiplication. Multiplication is completed before the result registers are accessed using the indexed address mode for the source operand. When indirect or indirect autoincrement address modes are used, another instruction is needed between the writing of the second operand and accessing the result registers. Both operands, OP1 and OP2, utilize all seven address mode capabilities. No instruction is necessary for the multiplication; as a result, the real-time operation does not require additional clock cycles and the interrupt latency is unchanged. The multiplier architecture is illustrated in Figure 6-2.
Figure 6-2. Block Diagram of the MSP430 16x16-Bit Hardware Multiplier
15 Operand 1 (address defines operation) rw MPY 130h MPYS 132h MAC 134h MACS 136h 31 Product Register Accessible Register 0 15 rw Operand 1 Mode 16 x 16 Multiplier 0 0 15 rw 0
Operand 2 138h
0000 32-Bit Adder MACS MPY MPYS MAC Mode Multiplexer MPY, MPYS 32-Bit Multiplexer MAC, MACS Mode
SumExt 13Eh 15 r 0
C
S 15
Accumulator ACC SumHi 13Ch SumLo 013Ah rw 0 15 rw 0
Hardware Multiplier
6-3
Hardware Multiplier Operation
The sum extension register contents differ, depending on the operation and on the results of the operation.
Table 6-1. Sum Extension Register Contents
Register Operand1 Operand2 SumExt
Note:
MPY x x 0000h
MPYS +- +- 0000h ++ -- 0FFFFh
MAC (OP1xOP2 + ACC) 0FFFFFFFFh 0000h (OP1xOP2 + ACC) > 0FFFFFFFFh 0001h
MACS, see Notes (OP1xOP2 + ACC) > 07FFFFFFFh 0FFFFh (OP1xOP2 + ACC) 07FFFFFFFh 0000h
The following two overflow conditions may occur when using the MACS function and should be handled by software or avoided. 1) The result of a MACS operation is positive and larger than 07FFF FFFFh. In this case, the SumExt register contains 0FFFFh and the ACC register contains a negative number (8000 0000h .... 0FFFF FFFFh). 2) The result of a MACS operation is negative and less than or equal to 07FFF FFFFh. In this case, the SumExt register contains 0000h and the ACC register contains a positive number (0000 0000h ... 07FFF FFFFh).
6-4
Hardware Multiplier Operation
6.2.1
Multiply Unsigned, 16x16 bit, 16x 8 bit, 8x 16 bit, 8 x 8 bit
The following multiplication operation shows 32 bytes of program code and 32 execution cycles (16 x16 bit multiplication).
********************************************************** * TRANSFER BOTH OPERANDS TO THE REGISTERS IN THE * * HARDWARE MULTIPLIER MODULE * * USE CONSTANT OPERAND1 AND OPERAND2 TO IDENTIFY * * BYTE DATA * ********************************************************** OPERAND1 .EQU OPERAND2 .EQU MPY MPYS MAC MACS OP2 RESLO RESHI SUMEXT .EQU .EQU .EQU .EQU .EQU .EQU .EQU .EQU .BSS .BSS .BSS 0 0 ; ; ; ; 0: 8: 0: 8: OPERAND1 OPERAND1 OPERAND2 OPERAND2 IS IS IS IS WORD BYTE WORD BYTE (16BIT) ( 8BIT) (16BIT) ( 8BIT)
0130H 0132H 0134H 0136H 0138H 013AH 013CH 013EH OPER1,2,200H OPER2,2 RAM,8
.IF OPERAND1=8 MOV.B &OPER1,&MPY ; LOAD 1ST OPERAND, ; DEFINES ADD. UNSIGNED MULTIPLY .ELSE MOV .ENDIF .IF OPERAND1=8 MOV.B &OPER2,&OP2 ; LOAD 2ND OPERAND AND START ; MULTIPLICATION .ELSE MOV .ENDIF ********************************************************** * EXAMPLE TO ADD THE RESULT OF THE HARDWARE * * MULTIPLICATION TO THE RAM DATA, 64BITS * ********************************************************** ADD ADDC ADC ADC &RESLO,&RAM &RESHI,&RAM+2 &RAM+4 &RAM+6 ; ; ; ; ADD LOW RESULT TO RAM ADD HIGH RESULT TO RAM+2 ADD CARRY TO EXTENSION WORD IF 64 BIT LENGTH IS USED &OPER2,&OP2 ; LOAD 2ND OPERAND AND START ; MULTIPLICATION &OPER1,&MPY ; LOAD 1ST OPERAND, ; DEFINES ADD. UNSIGNED MULTIPLY
Hardware Multiplier
6-5
Hardware Multiplier Operation
6.2.2
Multiply Signed, 16x16 bit, 16x8 bit, 8x16 bit, 8x8 bit
The following multiplication operation shows 36 bytes of program code and 36 execution cycles (16 x 16 bit multiplication).
********************************************************** * TRANSFER BOTH OPERANDS TO THE REGISTERS IN THE * * HARDWARE MULTIPLIER MODULE * * IF ONE OF THE OPERANDS IS 8 BIT, SIGN EXTENSION * * is NEEDED. USE CONSTANT OPERAND1 AND OPERAND2 TO * * IDENTIFY BYTE DATA * ********************************************************** OPERAND1 .EQU OPERAND2 .EQU MPY .EQU MPYS .EQU MAC .EQU MACS .EQU OP2 .EQU RESLO .EQU RESHI .EQU SUMEXT .EQU .BSS .BSS .BSS 0 0 0130H 0132H 0134H 0136H 0138H 013AH 013CH 013EH OPER1,2,200H OPER2,2 RAM,8 ; ; ; ; 0: 8: 0: 8: OPERAND1 OPERAND1 OPERAND2 OPERAND2 IS IS IS IS WORD BYTE WORD BYTE (16BIT) ( 8BIT) (16BIT) ( 8BIT)
.IF OPERAND1=0 MOV &OPER1,&MPYS ; LOAD 1ST (WORD) OPERAND, ; DEFINES ADD. SIGNED MULTIPLY .ELSE MOV.B &OPER1,&MPYS ; ; SXT &MPYS ; .ENDIF .IF OPERAND2=0 MOV &OPER2,&OP2 ; ; LOAD 1ST (BYTE) OPERAND, DEFINES ADD. SIGNED MULTIPLY EXPAND BYTE TO SIGNED WORD DATA
LOAD 2ND (WORD) OPERAND AND START SIGNED MULTIPLICATION
.ELSE MOV.B &OPER2,&OP2 ; LOAD 2ND (BYTE) OPERAND, SXT &OP2 ; RE-LOAD 2ND OPERAND AND START ; SIGNED `FINAL' MULTIPLICATION .ENDIF ********************************************************** * EXAMPLE TO ADD THE RESULT OF THE HARDWARE * * MULTIPLICATION TO THE RAM DATA, 64 BITS * ********************************************************** ADD ADDC ADDC ADDC &RESLO,&RAM ; &RESHI,&RAM+2 ; &SUMEXT,&RAM+4 ; &SUMEXT,&RAM+6 ; ADD LOW RESULT TO RAM ADD HIGH RESULT TO RAM+2 ADD SIGN WORD TO EXTENSION WORD IF 64 BIT LENGTH IS USED
6-6
Hardware Multiplier Operation
6.2.3
Multiply Unsigned and Accumulate, 16x16bit, 16x8bit, 8x16bit, 8x8bit
The following multiplication operation shows 32 bytes of program code and 32 execution cycles (16X16-bit multiplication).
********************************************************** * TRANSFER BOTH OPERANDS TO THE REGISTERS IN THE * * HARDWARE MULTIPLIER MODULE * * THE RESULT OF THE MULTIPLICATION IS ADDED TO THE * * CONTENT OF BOTH RESULT REGISTERS, RESLO AND RESHI * * USE CONSTANT OPERAND1 AND OPERAND2 TO IDENTIFY * * BYTE DATA * ********************************************************** OPERAND1 .EQU OPERAND2 .EQU MPY MPYS MAC MACS OP2 RESLO RESHI SUMEXT .EQU .EQU .EQU .EQU .EQU .EQU .EQU .EQU .BSS .BSS .BSS 0 0 ; ; ; ; 0: 8: 0: 8: OPERAND1 OPERAND1 OPERAND2 OPERAND2 IS IS IS IS WORD BYTE WORD BYTE (16BIT) ( 8BIT) (16BIT) ( 8BIT)
0130H 0132H 0134H 0136H 0138H 013AH 013CH 013EH OPER1,2,200H OPER2,2 RAM,8
.IF OPERAND1=8 MOV.B &OPER1,&MAC ; LOAD 1ST OPERAND, ; DEFINES ADD. UNSIGNED MULTIPLY .ELSE MOV .ENDIF .IF OPERAND1=8 MOV.B &OPER2,&OP2 ; LOAD 2ND OPERAND AND START ; MULTIPLICATION .ELSE MOV .ENDIF ********************************************************** * EXAMPLE TO ADD THE RESULT OF THE HARDWARE * * MULTIPLICATION TO THE RAM DATA, 64BITS * * THE RESULT OF THE MULTIPLICATION IS HELD IN RESLO* * AND RESHI REGISTERS. THE UPPER TWO WORDS IN THE * * EXAMPLE ARE FURTHER LOCATED IN THEIR RAM LOCATION* ********************************************************** ADDC ADC &SUMEXT,&RAM+4 &RAM+6 ; ADD SUMEXTENSTION TO RAM+4 ; IF 64 BIT LENGTH IS USED &OPER2,&OP2 ; LOAD 2ND OPERAND AND START ; MULTIPLICATION &OPER1,&MAC ; LOAD 1ST OPERAND, ; DEFINES ADD. UNSIGNED MULTIPLY
Hardware Multiplier
6-7
Hardware Multiplier Operation
6.2.4
Multiply Signed and Accumulate, 16x16bit, 16x8bit, 8x16bit, 8x8bit
******************************************************************** * TRANSFER BOTH OPERANDS TO THE REGISTERS IN THE HARDWARE * * MULTIPLIER MODULE * * USE CONSTANT OPERAND1 AND OPERAND 2 TO IDENTIFY BYTE DATA * ******************************************************************** OPERAND1 .EQU 0 ; 0: OPERAND1 IS WORD (16BIT) ; 8: OPERAND1 IS BYTE ( 8BIT) OPERAND2 .EQU 0 ; 0: OPERAND2 IS WORD (16BIT) ; 8: OPERAND2 IS BYTE ( 8BIT) MPY .EQU 0130H MPYS .EQU 0132H MAC .EQU 0134H MACS .EQU 0136H OP2 .EQU 0138H RESLO .EQU 013AH RESHI .EQU 013CH SUMEXT .EQU 013EH MAXMACS .EQU 32H ;NUMBER OF MACS FUNCTIONS WHICH COULD ;BE EXECUTED TILL AN OVERFLOW OR UNDERFLOW ;COULD OCCUR THE FIRST TIME .BSS OPER1,2,200H .BSS OPER2,2 .BSS RAM,8 .BSS MCOUNT,2 .IF OPERAND1=8 MOV.B &OPER1,&MACS ; LOAD 1ST OPERAND, ; DEFINES ADD. UNSIGNED MULTIPLY SXT &MACS ; EXPAND BYTE TO SIGNED WORD DATA .ELSE MOV &OPER1,&MACS ; LOAD 1ST OPERAND, ; DEFINES ADD. UNSIGNED MULTIPLY .ENDIF .IF OPERAND1=8 SXT &OPER2 ; OPER2 MEMORY LOCATION NEEDS ; 2 BYTES MOV.B &OPER2,&OP2 ; LOAD 2ND OPERAND AND START ; MULTIPLICATION .ELSE MOV &OPER2,&OP2 ; LOAD 2ND OPERAND AND START ; MULTIPLICATION .ENDIF ******************************************************************** * EXAMPLE TO ADD THE RESULT OF THE HARDWARE MULTIPLICATION * * TO THE RAM DATA IF NECESSARY * * THE RESULT OF THE MULTIPLICATION IS HELD IN RESLO AND * * RESHI REGISTERS. THE UPPER TWO WORDS IN THE EXAMPLE ARE * * FURTHER LOCATED IN THEIR RAM LOCATION * ******************************************************************** INC MCOUNT ; INC MACS COUNTER CMP #MAXMACS,MCOUNT ; ONLY ADD TO RAM IF NECESSARY JNE NEXTMACS ; ADDC &RESLO,&RAM+0 ; ADD SUMEXTENSION TO RAM+0 ADDC &RESHI,&RAM+2 ; ADD SUMEXTENSION TO RAM+2 ADDC &SUMEXT,&RAM+4 ; ADD SUMEXTENSION TO RAM+4 ADDC &SUMEXT,&RAM+6 ; IF 64 BIT LENGTH IS USED CLR MCOUNT NEXTMACS ...
6-8
Hardware Multiplier Registers
6.3 Hardware Multiplier Registers
Hardware multiplier registers are word structured, but can be accessed using word or byte processing instructions. Table 6-2 describes the hardware multiplier registers.
Table 6-2. Hardware Multiplier Registers
Register Multiply Unsigned (Operand1) Multiply Signed (Operand1) Multiply+Accumulate (Operand1) Multiply Signed+Accumulate (Operand1) Second Operand Result Low Word Result High Word Sum Extend Short Form MPY MPYS MAC MACS OP2 ResLo ResHi SumExt Register Type Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read Address 0130h 0132h 0134h 0136h 0138h 013Ah 013Ch 013Eh Initial State Unchanged Unchanged Unchanged Unchanged Unchanged Undefined Undefined Undefined
Two registers are implemented for both operands, OP1 and OP2, as shown in Figure 6-3. Operand 1 uses four different addresses to address the same register. The different address information is decoded and defines the type of multiplication operation used.
Figure 6-3. Registers of the Hardware Multiplier
15 MPY (130h),MPYS (132h) MAC (134h), MACS(136h) OP2 (138h) ResLo (13Ah) ResHi (13Ch) SumExt (13Eh) Operand 1, OP1 Operand 2, OP2 Result Low Word, ResLo Result High Word, ResHi Sum Extension Word, SumExt 0
The multiplication result is located in two word registers: result high (RESHI) and result low (RESLO). The sum extend register (SumExt) holds the result sign of a signed operation or the overflow of the multiply and accumulate (MAC) operation. See Section 6.5.3 for a description of overflow and underflow when using the MACS operations. All registers have the least significant bit (LSB) at bit0 and the most significant bit (MSB) at bit7 (byte data) or bit15 (word data).
Hardware Multiplier
6-9
Hardware Multiplier Special Function Bits
6.4 Hardware Multiplier Special Function Bits
Because the hardware multiplier module completes all multiplication operations quickly, without interrupt intervention, no special function bits are used.
6.5 Hardware Multiplier Software Restrictions
Two restrictions require attention when the hardware multiplier is used:
6.5.1
The indirect or indirect autoincrement address mode used to process the result The hardware multiplier used in an interrupt routine
Hardware Multiplier Software Restrictions--Address Mode
The result of the multiplication operation can be accessed in indexed, indirect, or indirect autoincrement mode. The result registers may be accessed without any restrictions if you use the indexed address mode including the symbolic and absolute address modes. However, when you use the indirect and indirect autoincrement address modes to access the result registers, you need at least one instruction between loading the second operand and accessing one of the result registers.
********************************************************** * EXAMPLE: MULTIPLY OPERAND1 AND OPERAND2 ********************************************************** RESLO .SET PUSH MOV MOV MOV 013AH R5 #RESLO,R5 ; RESLO = ADDRESS OF RESLO ; R5 WILL HOLD THE ADDRESS OF ; THE RESLO REGISTER LOAD 1ST OPERAND, DEFINES ADD. UNSIGNED MULTIPLY LOAD 2ND OPERAND AND START MULTIPLICATION
&OPER1,&MPY ; ; &OPER2,&OP2 ; ;
********************************************************** * EXAMPLE TO ADD THE RESULT OF THE HARDWARE * * MULTIPLICATION TO THE RAM DATA, 64BITS * ********************************************************** NOP ; ; ; ; @R5+,&RAM ; @R5,&RAM+2 ; &RAM+4 ; &RAM+6 ; R5 MIN. ONE CYCLES BETWEEN MOVING THE OPERAND2 TO HW-MULTIPLIER AND PROCESSING THE RESULT WITH INDIRECT ADDRESS MODE ADD LOW RESULT TO RAM ADD HIGH RESULT TO RAM+2 ADD CARRY TO EXTENSION WORD IF 64 BIT LENGTH IS USED
ADD ADDC ADC ADC POP
The previous example shows that the indirect or indirect autoincrement address modes, when used to transfer the result of a multiplication operation to the destination, need more cycles and code than the absolute address mode. There is no need to access the hardware multiplier using the indirect addressing mode.
6-10
Hardware Multiplier Software Restrictions
6.5.2
Hardware Multiplier Software Restrictions--Interrupt Routines
The entire multiplication routine requires only three steps: 1) Move operand OP1 to the hardware multiplier; this defines the type of multiplication. 2) Move operand OP2 to the hardware multiplier; the multiplication starts. 3) Process the result of the multiplication in the RESLO, RESHI, and SUMEXT registers. The following considerations describe the main routines that use hardware multiplication. If no hardware multiplication is used in the main routine, multiplication in an interrupt routine is protected from further interrupts, because the GIE bit is reset after entering the interrupt service routine. Typically, a multiplication operation that uses the entire data process occurs outside an interrupt routine and the interrupt routines are as short as possible. A multiplication operation in an interrupt routine has some feedback to the multiplication operation in the main routine.
6.5.2.1
Interrupt Following an OP1 Transfer
The two LSBs of the first operand address define the type of multiplication operation. This information cannot be recovered by any later operation. Therefore an interrupt must not be accepted between the first two steps: move operand OP1 and OP2 to the multiplier.
6.5.2.2
Interrupt Following an OP2 Transfer
After the first two steps, the multiplication result is in the corresponding registers RESLO, RESHI, and SUMEXT. It can be saved on the stack (using the PUSH instruction) and can be restored after completing another multiplication operation (using the POP instruction). However, this operation takes additional code and cycles in the interrupt routine. You can avoid this, by making an entire multiplication routine uninterruptible, by disabling any interrupt (DINT) before entering the multiplication routine, and by enabling interrupts (EINT) after the multiplication routine is completed. The negative aspect of this method is that the critical interrupt latency is increased drastically for events that occur during this period.
6.5.2.3
General Recommendation
In general, one should avoid a hardware multiplication operation within an interrupt routine when a hardware multiplication is already used in the main program. (This will depend upon the application-specific software, applied libraries, and other included software.) The methods previously discussed have some negative implications; therefore, the best practice is to keep interrupt routines as short as possible.
Hardware Multiplier
6-11
Hardware Multiplier Software Restrictions
6.5.3
Hardware Multiplier Software Restrictions--MACS
The multiplier does not automatically detect underflow or overflow in the MACS mode. An overflow occurs when the sum of the accumulator register and the result of the signed multiplication exceed the maximum binary range. The binary range of the accumulator for positive numbers is 0 to 231-1 (7FFF FFFFh) and for negative numbers is -1 (0FFFF FFFFh) to -231 (8000 0000h). An overflow occurs when the sum of two negative numbers yields a result that is in the range given above for a positive number. An underflow occurs when the sum of two positive numbers yields a result that is in the range for a negative number. The maximum number of successive MACS instructions without underflow or overflow is limited by the individual application and should be determined using a worst-case calculation. Care should then be exercised to not exceed the maximum number or to handle the conditions accordingly.
6-12
Chapter 7
FLL Clock Module
This chapter discusses the FLL clock module used in the MSP430x3xx families. The FLL clock module in the MSP430x3xx includes a watch-crystal oscillator, an RC-type digitally-controlled oscillator (DCO), and a frequencylocked-loop (FLL) to ensure the accuracy of the DCO.
Topic
7.1 7.2 7.3 7.4 7.5 7.6
Page
The FLL Clock Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2 Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3 Digitally-Controlled Oscillator (DCO) and Frequency-Locked Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4 FLL Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7 Buffered Clock Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-8 FLL Module Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9
FLL Clock Module
7-1
7.1 The FLL Clock Module
The frequency-locked loop (FLL) clock module (shown in Figure 7-1) follows the major design targets of low system cost and low-power consumption. The FLL operates completely using a 32768-Hz watch crystal. A second asynchronous high-speed clock signal is generated on-chip using a digitally-controlled oscillator (DCO). The DCO frequency is stabilized to a multiple of the watch crystal frequency by dividing the DCO frequency and digitally locking the two frequencies. This technique is known as frequency-locked loop.
Figure 7-1. Frequency-Locked Loop
ACLK OscOff f Crystal SCG0 PUC
Enable Reset
10-bit Frequency Integrator /(N+1) Divider
10 SCG1 FN4 FN3 FN2 Enable DC Generator DCO and Modulator MCLK M
f System
The FLL module supplies the MSP430x3xx family of devices with two clock signals and an associated software-selectable buffered clock output.
-
ACLK, a crystal oscillator signal used by peripheral modules. This signal is identical to the frequency of the crystal oscillator input, XIN. ACLK is also known as fcrystal. MCLK, the controller's main system clock used by the CPU; this clock is software selectable for individual peripheral modules. The MCLK is identical to the frequency generated by the DCO. MCLK is also known as fsystem. XBUF, buffered output of either MCLK, ACLK, ACLK/2, ACLK/4, or off.
7-2
Crystal Oscillator
7.2 Crystal Oscillator
The crystal oscillator supports low-current consumption by using a 32,768 Hz watch crystal. The crystal connects to XIN and XOUT without any other external components. This oscillator generates the ACLK signal which is available to on-chip peripherals and XBUF. Two factors determine the choice of the watch crystal:
-
Low-current consumption Stable time base
The oscillator operates after applying VCC. Since the OscOff control bit in the Status register (SR) is reset. It can be stopped by software by setting the OscOff bit in the SR (OscOff = 1). When OscOff mode is selected (see Chapter 3) the ACLK signal is held in a high state. All components required for crystal operation are integrated into the MSP430 as shown in Figure 7-2. No additional external components are necessary for operation. Because the oscillator is designed for ultralow-power dissipation, short connections between the crystal and MSP430 devices should be used for the PWB layout.
Figure 7-2. Crystal Oscillator Schematic
-12 pF 0V XIN ACLK OscOff XOUT 0V 32,768 Hz -12 pF MSP430
FLL Clock Module
7-3
Digitally-Controlled Oscillator (DCO) and Frequency-Locked Loop
7.3 Digitally-Controlled Oscillator (DCO) and Frequency-Locked Loop
The DCO is an integrated RC-type oscillator in the MSP430x3xx FLL clock module. The DCO generates a clock signal called MCLK. The MCLK generated by the DCO is used by the MSP430x3xx CPU and is available to on-chip peripherals and XBUF. MCLK is set to an N+1 multiple of ACLK. The N multiplier is contained in the lowest 7 bits of control register SCFQCTL (SCFQCTL.6 ... SCFQCTL.0). N is set to 31 on PUC by default, resulting in an effective ACLK multiplier of 32 and an MCLK of 1.048576 MHz, assuming that ACLK is 32, 768 Hz. The multiplier (N+1) sets the frequency of MCLK: MCLK = (N + 1) x ACLK MCLK is stabilized using a frequency-locked loop technique. When combined with the DCO, two important benefits result:
-
Fast start-up. The MSP430x3xx DCO is active in less than 6 s, which supports extended sleep periods and burst performance. Digital control signals. The DCO starts at exactly the same setting as when shutoff. Thus a long locking period is not required for normal operation.
User software can modify MCLK by changing the multiplier N at any time. The exact minimum and maximum MCLK allowed is specified in the device data sheet.
7.3.1
FLL Operation
As with any RC-type oscillator, frequency varies with temperature and voltage. The FLL hardware automatically stabilizes MCLK. The FLL compares the ACLK to MCLK/(N+1) and counts up or down a 10-bit frequency integrator. The MCLK is constantly adjusted to one of 1024 possible settings. The output of the frequency integrator that drives the DCO can be read in SCFI1 and SCFI0. The count is adjusted +1 or -1 with each crystal period (30.5 s using 32,768 Hz). Of the 10-bits from the frequency integrator, 5-bits are used for DCO frequency taps and 5-bits are used for a modulator. The 5-bits for the DCO tap are contained in the SCFI1 (SCFI1.7 . . . SCFI11.3). There are 29 taps implemented in the DCO (TAPS 28, 29, 30, and 31 are equivalent), each being approximately 10% higher than the previous. In most applications, a fraction tap may be required to achieve the programmed MCLK over the full range of system operation (see Figure 7-3).
Figure 7-3. Fractional Tap Frequency Required
Discrete DCO Taps fn-2 fn-1 fn fn+1 fn+2 fn+3
DCO Output Frequency Spectrum Required 'Fractional Tap'
7-4
Digitally-Controlled Oscillator (DCO) and Frequency-Locked Loop
7.3.2
Modulator Operation
The modulator overcomes relatively-large tap steps by mixing a DCO tap with the next higher-frequency tap DCO+1. The DCO mixing or hop pattern is controlled with 5-bits; thus there are 32 possible mix patterns (see Figure 7-4). The 5-bits for the modulator are contained in SCFI1 and SCFI0 (SCFI1.2...SCFI1.0, SCFI0.1, and SCFI0.0).
Figure 7-4. Modulator Hop Patterns
NDCOmod 31 24 16 15 5 4 3 2 Lower DCO Tap Frequency fn 1 0 Upper DCO Tap Frequency fn+1
MCLK Cycles (1.048 MHz) One ACLK Cycle
7.3.3
DCO Frequency Range
The fundamental-frequency range of the DCO is centered based on fnominal approximately equal to 1 MHz using bits FN_2, FN_3, and FN_4 in SCFIO (see Table 7-1). The range control allows the DCO to operate near the center of the available taps for a given MCLK.
Table 7-1. The DCO Range Control Bits
FN_4 0 0 0 1 FN_3 0 0 1 X FN_2 0 1 X X MCLK FREQUENCY 1 x fnominal 2 x fnominal 3 x fnominal 4 x fnominal
FLL Clock Module
7-5
Digitally-Controlled Oscillator (DCO) and Frequency-Locked Loop
7.3.4
Disabling the FLL
FLL loop control and modulation can be disabled independently. FLL loop control can be disabled by setting the SCG0 bit in the status register (SR). In this case, the DCO runs at the previous tap--open loop. Then the MCLK is not automatically stabilized to (N+1) x ACLK. The influence of the modulator can be disabled by setting the modulation bit M (SCFQCTL.7). In this case the MCLK is stabilized to (N+1) x ACLK every 1024 cycles to the nearest 32 DOC taps.
7.3.5
MCLK Stability
The DCO is absolutely monotonic and the 10-bits of the frequency integrator continuously count up/down by one. The accuracy of MCLK is the same as that of ACLK if the FLL is running continuously. The accumulated error in MCLK tends to zero over a long period. The 10-bit FLL integrator is automatically adjusted every period of the ACLK. Thus, a positive frequency deviation over one ACLK period is compensated with a negative deviation over the next ACLK period. Variation between MCLK clock periods can be approximately 10% due to the modulator mixing of DCO taps, while the accumulated system clock error over longer time periods is zero.
7.3.6
Oscillator Fault Detection
MSP430x3xx devices have a fail-safe mode when the external crystal fails. If the crystal fails and no ACLK signal is generated, the FLL will continue to count down to zero in an attempt to lock ACLK and MCLK/(N+1). An internal oscillator fault is detected if the DCO tap moves out of the range 07-6
FLL Operating Modes
7.4 FLL Operating Modes
Control bits SCG0, SCG1, OscOff, and CPUOff in the status register configure the MSP430x3xx operating modes as discussed in Chapter 3, System Resets, Interrupts, and Operating Modes.
7.4.1
Starting From Power Up Clear (PUC)
On a valid PUC, SCFQCTL = 31, SCFIO and SCFI1 are cleared, and SCG0, SCG1, OscOff, and CPUOff in the status register are reset. The FLL is fully operational and will adjust the DCO until MCLK = (31+1) x ACLK. Using a 32,768-Hz watch crystal for ACLK, MCLK will stabilize to 1.048576 MHz. Because the DCO starts at the lowest tap on PUC, enough time must be allowed for the DCO to settle on the proper tap for normal operation. This is necessary only after PUC, or when SCFIO and SCFI1 are cleared. 32 ACLK cycles are required to get from one tap to another. Twenty-nine taps are implemented, requiring 27 x 32 ACLK cycles as the worst case for the DCO to settle on the proper tap (taps 0 and 27 are not counted since OFIFG is set at these taps). During initialization, this time should be left prior to precise MCLK timing. During normal operation, the FLL will constantly adjust the DCO, requiring no special considerations.
7.4.2
Adjusting the FLL Frequency
User software can adjust the FLL frequency at any time by changing the N multiplier in the SCFQCTL register. Also, bits FN_2, FN_3, and FN_4 are adjusted to the appropriate MCLK frequency range. Example, MCLK = 64 x ACLK = 2097152
bic #GIE,SR ; Disable interrupts
mov.b mov.b
bis
#(64-1),&SCFQTL #FN_2,&SCFIO
#GIE,SR
; MCLK = 64 * ACLK ; DCO centered at 2 MHz
; Enable interrupts
Example, MCLK = 100 x ACLK = 3276800
bic #GIE,SR ; Disable interrupts
mov.b mov.b
bis
#(100-1),&SCFQTL #FN_3,&SCFIO
#GIE,SR
; MCLK = 100 * ACLK ; DCO centered at 3 MHz
; Enable interrupts
7.4.3
FLL Features for Low-Power Applications
Three conflicting requirements typically exist in battery-powered MSP430x3xx real-time applications:
-
Low-frequency clock for energy conservation and time keeping High-frequency clock for fast reaction to events and fast burst-processing capability
FLL Clock Module
7-7
Buffered Clock Output
-
Clock stability
The MSP430x3xx FLL clock system addresses the above conflicting requirements by providing both a low-frequency ACLK with crystal stability and a stable high-frequency MCLK with near instant on-capability. The DCO, which generates the MSP430x3xx MCLK, is operation in less than 6 S. The choice of a digital frequency-locked loop versus an analog-phase locked loop enables the benefit of fast-start and stability. A phase-locked loop takes hundreds or thousands of clock cycles to start and stabilize. The MSP430x3xx frequency-locked-loop starts immediately at the exact setting prior to shut down. For minimum power consumption, the MSP430x3xx system operates for extended periods in low-power mode 3 (LPM3) with only the ACLK active for timers and low-power peripherals. Interrupts, both from external and internal events, drive the activation of MCLK for the CPU and high-speed peripherals. In the MSP430x3xx, any interrupt stores the SR operating modes on the stack and then clears the SCG1 bit in the SR, automatically starting the DCO and MCLK. After the interrupt handler has completed, the saved SR is popped from the stack with the RETI instruction, restoring the previous operating mode.
7.5 Buffered Clock Output
The clock buffer shown in Figure 7-5 allows ACLK, ACLK/2, ACLK/4, or MCLK to be output on MSP430x3xx pin XBUF. The clock buffer is controlled using the three bits CBE, CBSEL1, and CBSEL0 in control register CBCTL.
Figure 7-5. Schematic of Clock Buffer
POR CL Q0 Q1 CBSEL1 CBSEL0 00 01 10 11 XBUF CBE XBUF
ACLK
ACLK ACLK/2 ACLK/4 MCLK
MCLK
CBE enables XBUF when set. CBSEL1 and CBSEL0 select the clock source of an enabled XBUF. On a POR condition, CBSEL1, CBSEL0, and CBE are reset and XBUF is disabled. If either ACLK or MCLK is shut down (generating no frequency) and this clock source (or fraction of) is selected for XBUF, no frequency will be output on XBUF regardless of CBE. Note: Control register CBCTL is a write-only register. Only mov.B #xxh, &CBCTL instructions should be used to access this register. Other Format 1 instructions, which are a read-then-write type, will result in incorrect setting.
7-8
FLL Module Control Registers
7.6 FLL Module Control Registers
The FLL module is configured using control registers SCFQCTL, SCFIO, SCFI1, CBCTL, and four bits from the CPU status register: SCG1, SCG0, OscOff, and CPUOff. User software can modify these control registers from their default condition at any time. The FLL control registers are located in the byte-wide peripheral map and should be accessed with byte (.B) instructions.
Register System clock control System clock frequency integrator 0 System clock frequency integrator 1 Clock buffer Short Form SCFQCTL SCFI0 SCFI1 CBCTL Register Type Read/write Read/write Read/write Write only Address 052h 050h 051h 053h Initial State 031h Reset Reset Reset
7.6.1
MCLK Frequency Control
The contents of register SCFQCTL controls the multiplication of the crystal frequency. The contents of register SCFQCTL is shown in Figure 7-6.
Figure 7-6. SCFQCTL Register
7 SCFQCTL 052h M 26 25 24 23 22 21 0 20
rw-0 rw-0 rw-0 rw-1 rw-1 rw-1 rw-1 rw-1
The seven bits indicate a range of 1 +1 to 127+1. Any value below 1 results in unpredictable operation. The user should ensure that the value selected does not exceed the maximum MCLK value specified in the device data sheet. fSystem = (x26 + x25 + x24 + x23 + x22 + x21 + x20 + 1) fcrystal The default value in SCFQCTL is 31 after a PUC signal is active, resulting in a factor of 32. The output of the frequency integrator controls the DCO. This value can be read using the SCFI1 and SCFI0 addresses as shown in Figure 7-7.
Figure 7-7. SCFI0 and SCFI1 Registers
If the modulation bit M is set, only the DCO taps determine the system frequency. Adjacent DCO taps are not mixed. Note, however, that if the FLL remains active (SCG0=0), it will continue to adjust the DCO taps. If an application requires the system frequency to remain constant for a short period of time, both the modulation and the FLL should be disabled (M=1, SCG0=1).
7 SCFI0 050h r 7 SCFI1 051h
29 28 27 26 25 24 23 0 0 0 FN_4 FN_3 FN_2 21
0
20
r
r
rw-0 rw-0 rw-0 rw-0 rw-0 0
22
rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0
FLL Clock Module
7-9
FLL Module Control Registers
Figure 7-8. Crystal Buffer Control Register
CBCTL 053h
Not implemented
CBSEL CBSEL 0 1 CBE
w-(0) w-(0) w-(0)
Bit 0:
Bit CBE controls the output buffer configuration. CBE = 1: Output buffer enabled CBE = 0: Output buffer disabled Bits CBSEL1 and CBSEL0 select the frequency that can be applied to output pin XBUF.
CBSEL1 X 0 0 1 1 CBSEL0 X 0 1 0 1 XBUF Disabled ACLK ACLK/2 ACLK/4 MCLK
Bits 1, 2:
CBE 0 1 1 1 1
7.6.2
Special-Function Register Bits
The FLL clock module affects two bits in the special-function registers, OFIFG and OFIE. The oscillator fault-interrupt enable bit (OFIE) is located in bit 1 of the interrupt-enable register IE1. The oscillator fault-interrupt flag bit (OFIFG) is located in bit 1 of the interrupt-flag register IFG1.
IE1 00h 7 6 5 4 3 2 1 OFIE rw-0 IFG1 02h 7 6 5 4 3 2 1 OFIFG rw-1 0 0
The oscillator fault signal sets the OFIFG as long as the oscillator fault condition is active. The detection and effect of the oscillator fault condition is described in section 7.3.6. The oscillator fault interrupt requests a nonmaskable interrupt if the OFIE bit is set. The oscillator interrupt-enable bit is reset automatically if a non-maskable interrupt is accepted. The initial state of the OFIE bit is reset, and no oscillator fault requests an interrupt even if a fault condition occurs.
7-10
Chapter 8
Digital I/O Configuration
This chapter describes the digital I/O configuration.
Topic
8.1 8.2 8.3 8.4
Page
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2 Port P0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3 Ports P1, P2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-11 Ports P3, P4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-17
Digital I/O Configuration
8-1
Introduction
8.1 Introduction
The general-purpose I/O ports of the MSP430 are designed to give maximum flexibility. Each I/O line is individually configurable, and most have interrupt capability. There are several different I/O port modules that function in slightly different ways. For this reason, names have been given to each port module. For example, port P0, P1, P2, etc. These names refer to specific port modules, and apply to all MSP430 devices. For example, port P0 and P1 may be available on a particular MSP430 device, while ports P1 and P3 may be available on another device. It is important for the user to understand the operating differences and which port(s) are available on the device in use. Additionally, the I/O port pins are often multiplexed with other pin functions on the devices to provide maximum flexibility while optimizing pin count on the devices.
8-2
Port P0
8.2 Port P0
The general-purpose port P0 contains 8 general-purpose I/O lines and the required registers to control and configure them. Each I/O line is capable of being controlled independently. In addition, each I/O line has interrupt capability. Six registers are used to control the port I/O pins (see Section 8.2.1). Port P0 is connected to the processor core through the 8-bit memory data bus (MDB) and the memory address bus (MAB). Port P0 should be accessed using byte instructions in the absolute address mode, such as: MOV.B #12h,&P0OUT.
Figure 8-1. Port P0 Configuration
MDB 8 B Input Register P0IN 010h 8 8 R/W 6/2 R/W R/W 6/2 R/W 8
Output Register P0OUT 011h Direction Register P0DIR 012h
Interrupt Flags P0IFG 013h Interrupt Flags IFG1.2/3 002h
Interrupt Edge Select P0IES 014h
R/W
Interrupt Enable P0IE 015h Interrupt Enable IE1.2/3 000h
MSB P0.7
LSB P0.0
8.2.1
Port P0 Control Registers
Port P0 has six registers to control the I/O pins. The six control registers give maximum input/output configuration flexibility:
-
All individual I/O bits are independently programmable. Any combination of input, output, and interrupt condition is possible. Interrupt processing of external events is fully implemented for all eight bits of port P0.
Digital I/O Configuration
8-3
Port P0
The six registers are shown in Table 8-1.
Table 8-1. Port P0 Control Registers
Register Input Output Direction Interrupt flags Interrupt enable Short Form P0IN P0OUT P0DIR P0IFG P0IE Register Type Read only Read/write Read/write Read/write Read/write Read/write Address 010h 011h 012h 013h 014h 015h Initial State ----- Unchanged Reset Reset Unchanged Reset
Interrupt edge select P0IES
These registers contain eight bits except for the two LSBs in the interrupt flag register and interrupt enable register. These two bits are included in the special function register. The registers should be accessed using byte instructions and absolute address mode.
8.2.1.1
Input Register P0IN
The input register is a read-only register that shows the values of the signals at the I/O pins. The direction of the pin must be selected as input. Note: Writing to the Read-Only Register P0IN Any attempt to write to this read-only register results in increased current consumption while the write attempt is active.
8.2.1.2
Output Register P0OUT
The output register shows the information of the output buffer. The output buffer can be modified using all instructions that write to a destination. If read, the contents of the buffer are independent of the pin direction. A direction change does not modify the output buffer contents.
8.2.1.3
Direction Register P0DIR
The direction register contains eight bits that define the direction of each I/O pin. All bits are reset by the PUC signal. When: Bit = 0: The I/O pin is switched to input direction Bit = 1: The I/O pin is switched to output direction
8-4
Port P0
8.2.1.4
Interrupt Flags P0IFG
The interrupt flags register contains six flags that reflect whether or not an interrupt is pending from the corresponding I/O pin, if the I/O pins are interrupt-enabled. Three interrupt vectors are implemented for port P0; one for port P0.0, one for port P0.1, and one for interrupt events on ports P0.2 to P0.7. The six flags shown in Figure 8-2 are located in bits 7 to 2 and correspond to pins P0.7 to P0.2. The interrupt flags for pins P0.1 and P0.0 are located in the SFRs.
Figure 8-2. Interrupt Flags Register
7 P0IFG 013h
P0IFG.7 P0IFG.6 P0IFG.5 P0IFG.4 P0IFG.3 P0IFG.2
0
rw-0
rw-0
rw-0
rw-0
rw-0
rw-0
r0
r0
When: Bit = 0: No interrupt is pending Bit = 1: An interrupt is pending due to a transition at the I/O pin or software setting the bit. Manipulation of P0OUT and P0DIR can also set the P0IFG bits. Writing a zero to an interrupt flag resets it; writing a one to an interrupt flag sets it and generates an interrupt. Interrupt flags P0IFG.2 to P0IFG.7 use only one interrupt vector. These flags are not reset automatically when any interrupt from these events is served. The software should determine which event is served and reset the appropriate flag(s). Flags P0IFG.0 and P0IFG.1 generate individual interrupts, and are reset automatically when serviced. Note: Any external interrupt event should be as long as 1.5 times MCLK or longer to ensure that is accepted and the corresponding interrupt flag is set.
8.2.1.5
Interrupt Edge Select P0IES
The interrupt edge select register contains a bit for each I/O pin, which controls which transition triggers the interrupt flag. All eight bits corresponding to pins P0.7 to P0.0 are located in this register. When: Bit = 0: The interrupt flag is set with a low-to-high transition Bit = 1: The interrupt flag is set with a high-to-low transition Note: Any change in the P0IES bit(s) may result in setting the associated interrupt flags.
Digital I/O Configuration
8-5
Port P0
8.2.1.6
Interrupt Enable P0IE
The interrupt enable register contains bits for I/O pins P0.7 to P0.2, as shown in Figure 8-3, which enable an interrupt request for an interrupt event on these pins. Two interrupt enable bits for P0.0 and P0.1 are located in special function registers IE1.2 and IE1.3.
Figure 8-3. Interrupt Enable Register
7 P0IE 015h
P0IE.7 P0IE.6 P0IE.5 P0IE.4 P0IE.3 P0IE.2
0
rw-0
rw-0
rw-0
rw-0
rw-0
rw-0
r0
r0
When: Bit = 0: The interrupt request is disabled Bit = 1: The interrupt request is enabled Note: Port P0 Interrupt Sensitivity Only transitions, not static levels, cause interrupts. The interrupt routine must reset the interrupt flags P0IFG.2 to P0IFG.7. Flags P0IFG.0 and P0IFG.1 are reset automatically when these interrupts are serviced. If an interrupt flag is still set when the RETI instruction is executed (for example, a transition occurs during the interrupt service routine), an interrupt occurs again after RETI is completed. This ensures that each transition is acknowledged by the software.
8.2.2
Port P0 Schematic
The pin logic of each individual port P0 signal can be read from and written to as described in the following sections.
8.2.2.1
Port P0, Bits P0.3 to P0.7
Each port P0 signal's pin logic is built from five identical register bits--P0DIR, P0OUT, P0IFG, P0IE, P0IES--and one read-only input buffer, P0IN. Bits 3 through 7 function identically as shown in Figure 8-4.
8-6
Port P0
Figure 8-4. Schematic of Bits P0.7 to P0.3
P0DIRx P0.x P0OUT.x Output
P0IN.x P0IRQ.x P0IE.x P0IFG.x PnIRQ.y Request Interrupt P0.27 PnIRQ.z NOTE: 3 x 7
Input MUX
Pad Logic
Interrupt Flag
Interrupt Edge Select
P0IES.x
8.2.2.2
Port P0, Bit P0.2
Bit 2 is slightly different from bits 3 to 7 as shown in Figure 8-5. The output signal can be determined either by the port P0OUT.2 bit or by the 8-Bit Timer/Counter signal (TXD). When the output control register bit (TXE) is set to a logic 1, the TXD signal is selected as the relevant output signal and the pad logic is switched to the output, independent of the direction control bit P0DIR.2.
Figure 8-5. Schematic of Bit P0.2
TXE P0DIR.2 P0OUT.2 TXD Output MUX P0.2
P0IN.2 P0IRQ.2 P0IE.2 P0IFG.2 P0IRQ.3 Request Interrupt P0.27 P0IRQ.7
Input MUX
Pad Logic
Interrupt Flag
Interrupt Edge Select
P0IES.2
Digital I/O Configuration
8-7
Port P0
8.2.2.3
Port P0, Bit P0.1
Bit 1 is slightly different from bits 3 to 7 as shown in Figure 8-6. The interrupt signal can be sourced by the input signal at pin P0.1, or by the 8-Bit Timer/Counter carry signal. Whenever the interrupt source control bit (ISCTL) in the 8-Bit Timer/Counter control register (TCCTL) is set, the interrupt source is switched from pin P0.1 to the carry signal from the counter in the 8-bit Timer/Counter. Flag P0IFG.1 is reset automatically when the interrupt is serviced (IRQA signal).
Figure 8-6. Schematic of Bit P0.1
P0DIR.1 P0.1 P0OUT.1 Output
P0IN.1 P0IES.1
Input Interrupt Edge Select
Pad Logic
P0.1D (To 8-bit T/C) Carry Request Interrupt P0.1 P0IRQ.1 P0IE.1 P0IFG.1 Interrupt Flag Interrupt Source Select ISCTL (From 8-bit T/C)
IRQA (Interrupt request accepted)
8.2.2.4
Port P0, Bit P0.0
Bit 0 is identical to bits 3 to 7 as shown in Figure 8-7, but has its own interrupt vector. Flag P0IFG.0 is reset automatically when the interrupt is serviced (IRQA signal).
Figure 8-7. Schematic of Bit P0.0
P0DIR.0 P0.0 P0OUT.0 Output
P0IN.0 P0IRQ.0 P0IE.0 P0IFG.0
Input MUX
Pad Logic
Request Interrupt P0.0
Interrupt Flag
Interrupt Edge Select
P0IES.0 IRQA (Interrupt request accepted)
8-8
Port P0
8.2.3
Port P0 Interrupt Control Functions
Port P0 uses eight bits for interrupt flags, eight bits to enable interrupts, eight bits to select the effective edge of an interrupt event, and three different interrupt vector addresses. The three interrupt vector addresses are assigned to:
-
P0.0 P0.1/RXD P0.2 to P0.7
The two port P0 signals, P0.0 and P0.1/RXD, are used for dedicated signal processing. Four bits in the SFR address range and two bits in the port0 address frame handle the interrupt events on P0.0 and P0.1/RXD : P0.0 interrupt flag P0IFG.0 (located in IFG1.2, initial state is reset) P0.1/RXD interrupt flag P0IFG.1 (located in IFG1.3, initial state is reset) P0.0 interrupt enable P0IE.0 (located in IE1.2, initial state is reset) P0.1/RXD interrupt enable P0IE.1 (located in IE1.3, initial state is reset) P0.0 interrupt edge select (located in P0IES.0, initial state is reset) P0.1/RXD interrupt edge select (located in P0IES.1, initial state is reset)
Both interrupt flags (P0IFG.0 and P0IFG.1/RXD) are single source flags and are automatically reset when the processor serves them. The enable bits and edge select bits remain unchanged. The interrupt control bits of the remaining six I/O signals, P0.2 to P0.7, are located in the I/O address frame. Each signal uses three bits for configuration and interrupt. Interrupt flag, P0IFG.2 to P0IFG.7 Interrupt enable bit, P0IE.2 to P0IE.7 Interrupt edge select bit, P0IES.2 to P0IES.7
-
The interrupt flags P0IFG.2 to P0IFG.7 share the same interrupt vector. An interrupt event on one or more pins of P0.2 to P0.7 requests an interrupt when two conditions are met: the appropriate individual enable bit P0IE.x (2 x 7) is set and the general interrupt enable (GIE) bit is set. Since the interrupts share the same interrupt vector, interrupt flags P0.2 to P0.7 are not automatically reset and, therefore, continue to generate interrupts until reset. The interrupt service routine software should handle the detection of the source and reset the appropriate flag when it is serviced. Note: Modifying the direction control bit or interrupt edge select bit for an I/O may result in setting the interrupt flag for that I/O line.
Digital I/O Configuration
8-9
Port P0
8.2.3.1
I/O-Pin Interrupt Handler for P0.2 to P0.7: Programming Example
The following code describes how to set the I/O pin interrupt handler.
; The I/O-PIN ; IOINTR PUSH MOV.B BIC.B interrupt handler for P0.2 to P0.7 starts here R5 &P0IFG,R5 R5,&P0IFG ;Save R5 ;Read interrupt flags ;Clear status flags with the ;read data ;Additional set bits are not ;cleared! ;Allow interrupt nesting
EINT ;
;R5 contains information about which I/O-pin(s) cause ;interrupts: ;the processing starts here. ; ..... ..... POP R5 RETI ..... .....
;JOB done: restore R5 ;Return from interrupt
;Definition of interrupt vector table .sect "IO27_vec",0FFE0h ;The interrupt vector for ;flags P0IFG.2 and P0IFG.7 ;are at memory address 0FFE0h ;in 3xx devices. ;I/O-Pin (2 to 7) Vector in ;ROM ;Interrupt Vectors
.WORD IOINTR ; .sect "RST_vec",0FFFEh .WORD RESET
8-10
Ports P1, P2
8.3 Ports P1, P2
Each of the general-purpose ports P1 and P2 contain 8 general-purpose I/O lines and all of the registers required to control and configure them. Each I/O line is capable of being controlled independently. In addition, each I/O line is capable of producing an interrupt. Separate vectors are allocated to ports P1 and P2 modules. The pins for port P1 (P1.0-7) source one interrupt, and the pins for port P2 (P2.0-7) source another interrupt. Seven registers are used to control the port I/O pins (see Section 8.3.1). Ports P1 and P2 are connected to the processor core through the 8-bit MDB and the MAB. They should be accessed using byte instructions in the absolute address mode.
Figure 8-8. Port P1, Port P2 Configuration
MDB 8 R8
8 R/W 8 8 R/W 8 8 R/W R/W Function Select PnSEL n = 1: 026h n = 2: 02Eh
Input Register PnIN n = 1: 020h n = 2: 028h Output Register PnOUT n = 1: 021h n = 2: 029h R/W Direction Register PnDIR n = 1: 022h n = 2: 02Ah
Interrupt Flags PnIFG n = 1: 023h n = 2: 02Bh R/W Interrupt Edge Select PnIES n = 1: 024h n = 2: 02Ch
Interrupt Enable PnIE n = 1: 025h n = 2: 02Dh
MSB Pn.7
LSB Pn.0
Digital I/O Configuration
8-11
Ports P1, P2
8.3.1
Port P1, Port P2 Control Registers
The seven control registers give maximum digital input/output configuration flexibility:
-
All individual I/O bits are independently programmable. Any combination of input, output, and interrupt condition is possible. Interrupt processing of external events is fully implemented for all eight bits of ports P1 and P2.
The seven registers for port P1 and the seven registers for port P2 are shown in Table 8-2 and Table 8-3, respectively.
Table 8-2. Port P1 Registers
Register Input Output Direction Interrupt Flags Short Form P1IN P1OUT P1DIR P1IFG Register Type Read only Read/write Read/write Read/write Read/write Read/write Read/write Address 020h 021h 022h 023h 024h 025h 026h Initial State ----- Unchanged Reset Reset Unchanged Reset Reset
Interrupt Edge Select P1IES Interrupt Enable Function Select P1IE P1SEL
Table 8-3. Port P2 Registers
Register Input Output Direction Interrupt Flags Short Form P2IN P2OUT P2DIR P2IFG Register Type Read only Read/write Read/write Read/write Read/write Read/write Read/write Address 028h 029h 02Ah 02Bh 02Ch 02Dh 02Eh Initial State ----- Unchanged Reset Reset Unchanged Reset Reset
Interrupt Edge Select P2IES Interrupt Enable Function Select P2IE P2SEL
These registers contain eight bits, and should be accessed using byte instructions in absolute-address mode.
8.3.1.1
Input Registers P1IN, P2IN
Both Input registers are read-only registers that reflect the signals at the I/O pins. Note: Writing to Read-Only Registers P1IN, P2IN Writing to these read-only registers results in increased current consumption while the write attempt is active.
8.3.1.2
Output Registers P1OUT, P2OUT
Each output register shows the information of the output buffer. The output buffer can be modified by all instructions that write to a destination. If read, the
8-12
Ports P1, P2
contents of the output buffer are independent of pin direction. A direction change does not modify the output buffer contents.
8.3.1.3
Direction Registers P1DIR, P2DIR
The direction registers contain eight independent bits that define the direction of the I/O pin. All bits are reset by the PUC signal. When: Bit = 0: The port pin is switched to input direction (3-state) Bit = 1: The port pin is switched to output direction
8.3.1.4
Interrupt Flags P1IFG, P2IFG
Each interrupt flag register contains eight flags that reflect whether or not an interrupt is pending for the corresponding I/O pin, if the I/O is interrupt-enabled. When: Bit = 0: No interrupt is pending Bit = 1: An interrupt is pending due to a transition at the I/O pin or from software setting the bit. Note: Manipulating P1OUT and P1DIR, as well as P2OUT and P2DIR, can result in setting the P1IFG or P2IFG bits. Writing a zero to an interrupt flag resets it; writing a one to an interrupt flag sets it and generates an interrupt. Each group of interrupt flags P1FLG.0 to P1FLG.7 and P2FLG.0 to P2FLG.7 sources its own interrupt vector. Interrupt flags P1IFG.0 to P1IFG.7 and P2IFG.0 to P2IFG.7 are not reset automatically when an interrupt from these events is serviced. The software should determine the origin of the interrupt and reset the appropriate flag(s). Note: Any external interrupt event should be at least 1.5 times MCLK or longer, to ensure that it is accepted and the corresponding interrupt flag is set.
Digital I/O Configuration
8-13
Ports P1, P2
8.3.1.5
Interrupt Edge Select P1IES, P2IES
Each interrupt edge select register contains a bit for each corresponding I/O pin to select what type of transition triggers the interrupt flag. When: Bit = 0: The interrupt flag is set with a low-to-high transition Bit = 1: The interrupt flag is set with a high-to-low transition Note: Changing the P1IES and P2IES bits can result in setting the associated interrupt flags. PnIES.x 01 01 10 10 PnIN.x 0 1 0 1 PnIFG.x Unchanged May be set May be set Unchanged
8.3.1.6
Interrupt Enable P1IE, P2IE
Each interrupt enable register contains bits to enable the interrupt flag for each I/O pin in the port. Each of the sixteen bits corresponding to pins P1.0 to P1.7 and P2.0 to P2.7 is located in the P1IE and P2IE registers. When: Bit = 0: The interrupt request is disabled Bit = 1: The interrupt request is enabled Note: Port P1, Port P2 Interrupt Sensitivity Only transitions, not static levels, cause interrupts. If an interrupt flag is still set when the RETI instruction is executed (for example, a transition occurs during the interrupt service routine), an interrupt occurs again after RETI is completed. This ensures that each transition is acknowledged by the software.
8.3.1.7
Function Select Registers P1SEL, P2SEL
P1 and P2 port pins are often multiplexed with other peripheral modules to reduce overall pin count on MSP430 devices (see the specific device data sheet to determine which other peripherals also use the device pins). Control registers P1SEL and P2SEL are used to select the desired pin function--I/O port or other peripheral module. Each register contains eight bits corresponding to each pin, and each pin's function is individually selectable. All bits in these registers are reset by the PUC signal. The bit definitions are: Bit = 0: Port P1 or P2 function is selected for the pin Bit = 1: Other peripheral module function is selected for the pin
8-14
Ports P1, P2
Note: Function Select With P1SEL, P2SEL The interrupt-edge-select circuitry is disabled if control bit PnSEL.x is set. Therefore, the input signal can no longer generate an interrupt. When a port pin is selected to be used as an input to a peripheral module other than the I/O port (PnSEL.x = 1), the actual input signal to the peripheral module is a latched representation of the signal at the device pin (see Figure 8-9 schematic). The latch uses the PnSEL.x bit as its enable, so while PnSEL.x=1, the internal input signal simply follows the signal at the pin. However, if the PnSEL.x bit is reset, then the output of the latch (and therefore the input to the other peripheral module) represents the value of the signal at the device pin just prior to the bit being reset.
8.3.2
Port P1, Port P2 Schematic
The pin logic of each individual port P1 and port P2 signal is identical. Each bit can be read and written to as shown in Figure 8-9.
Figure 8-9. Schematic of One Bit in Port P1, P2
PnSEL.x PnDIR.x Direction Control From Module PnOUT.x Module X OUT Output MUX Pad Logic Output MUX
Pn.x
PnIN.x EN Module x IN Y A PnIRQ.x PnIE.x PnIFG.x PnIRQ.y Request Interrupt Pn.07 PnIRQ.z Interrupt Flag Interrupt Edge Select PnIES.x PnSEL.x
x = 0 to 7, according to bits 0 to 7 n = 1 for Port P1 and 2 for Port P2
Digital I/O Configuration
8-15
Ports P1, P2
8.3.3
Port P1, P2 Interrupt Control Functions
Ports P1 and P2 use eight bits for interrupt flags, eight bits to enable interrupts, eight bits to select the effective edge of an interrupt event, one interrupt vector address for port P1, and one interrupt vector address for port P2. Each signal uses three bits for configuration and interrupt:
-
Interrupt flag, P1IFG.0 to P1IFG.7 and P2IFG.0 to P2IFG.7 Interrupt enable bit, P1IE.0 to P1IE.7 and P2IE.0 to P2IE.7 Interrupt edge select bit, P1IES.0 to P1IES.7 and P2IES.0 to P2IES.7
The interrupt flags P1IFG.0 to P1IFG.7 source one interrupt and P2IFG.0 to P2IFG.7 source one interrupt. Any interrupt event on one or more pins of P1.0 to P1.7 or P2.0 to P2.7 requests an interrupt when two conditions are met: the appropriate individual bit PnIE.x is set, and the GIE bit is set. Interrupt flags P1IFG.0 to P1IFG.7 or P2IFG.0 to P2IFG.7 are not automatically reset. The software of the interrupt service routine should handle the detection of the source, and reset the appropriate flag when it is serviced.
8-16
Ports P3, P4
8.4 Ports P3, P4
General-purpose ports P3 and P4 function as shown in Figure 8-10. Each pin can be selected to operate with the I/O port function, or to be used with a different peripheral module. This multiplexing of pins allows for a reduced pin count on MSP430 devices. Four registers control each of the ports (see Section 8.4.1). Ports P3 and P4 are connected to the processor core through the 8-bit MDB and the MAB. They should be accessed with byte instructions using the absolute address mode.
Figure 8-10. Ports P3, P4 Configuration
MDB 8 R8
8 R/W 8
Input Register PnIN n = 3: 018h n = 4: 01Ch Output Register PnOUT n = 3: 019h n = 4: 01Dh R/W Direction Register PnDIR R/W n = 3: 01Ah Function Select n = 4: 01Eh Register PnSEL n = 3: 01Bh n = 4: 01Fh
MSB Pn.7
LSB Pn.0
8.4.1
Port P3, P4 Control Registers
The four control registers of each port give maximum configuration flexibility of digital I/O.
-
All individual I/O bits are programmed independently Any combination of input is possible Any combination of port or module function is possible
The four registers for each port are shown in Table 8-4. They each contain eight bits and should be accessed with byte instructions.
Digital I/O Configuration
8-17
Ports P3, P4
Table 8-4. Port P3. P4 Registers
Register Input Output Direction Port Select Short Form P3IN P4IN P3OUT P4OUT P3DIR P4DIR P3SEL P4SEL Address 018h 01Ch 019h 01Dh 01Ah 01Eh 01Bh 01Fh Register Type Read only Read only Read/write Read/write Read/write Read/write Read/write Read/write Initial State ----- ----- Unchanged Unchanged Reset Reset Reset Reset
8.4.1.1
Input Registers
The input registers are read-only registers that reflect the signal at the I/O pins. Note: Writing to Read-Only Register Any attempt to write to these read-only registers results in an increased current consumption while the write attempt is active.
8.4.1.2
Output Registers
The output registers show the information of the output buffers. The output buffers can be modified by all instructions that write to a destination. If read, the contents of the output buffer are independent of the pin direction. A direction change does not modify the output buffer contents.
8.4.1.3
Direction Registers
The direction registers contain eight independent bits that define the direction of each I/O pin. All bits are reset by the PUC signal. When: Bit = 0: The port pin is switched to input direction Bit = 1: The port pin is switched to output direction
8-18
Ports P3, P4
8.4.1.4
Function Select Registers PnSEL
Ports P3, P4 pins are often multiplexed with other peripheral modules to reduce overall pin count on MSP430 devices (see the specific device data sheet to determine which other peripherals also use the device pins). Control registers PnSEL are used to select the desired pin function--I/O port or other peripheral module. Each register contains eight bits corresponding to each pin, and each pin's function is individually selectable. All bits in these registers are reset by the PUC signal. The bit definitions are: Bit = 0: Port function is selected for the pin Bit = 1: Other peripheral module function is selected for the pin Note: Function Select With PnSEL Registers The interrupt-edge-select circuitry is disabled if control bit PnSEL.x is set. Therefore, the input signal can no longer generate an interrupt. When a port pin is selected to be used as an input to a peripheral module other than the I/O port (PnSEL.x=1), the actual input signal to the peripheral module is a latched representation of the signal at the device pin (see Figure 8-11 schematic). The latch uses the PnSEL.x bit as its enable, so while PnSEL.x=1, the internal input signal simply follows the signal at the pin. However, if the PnSEL.x bit is reset, then the output of the latch (and therefore the input to the other peripheral module) represents the value of signal at the device pin, just prior to the bit being reset.
8.4.2
Port P3, P4 Schematic
The pin logic of each individual port signal is shown in Figure 8-11.
Figure 8-11. Schematic of Bits Pn.x
PnSEL.x PnDIR.x Direction Control From Module PnOUT.x Module x OUT Output MUX Pad Logic Output MUX
Pn.x
PnIN.x EN Module x IN Y A n = 3 for Port3, 4 for Port P4 x = 0 to 7, according to bits 0 to 7
Digital I/O Configuration
8-19
8-20
Chapter 9
Universal Timer/Port Module
The Universal Timer/Port module supports the following system features:
-
Up to six independent outputs Two 8-bit counters or one 16-bit counter A precision comparator for slope A/D conversion
Topic
9.1 9.2 9.3 9.4 9.5
Page
Timer/Port Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2 Timer/Port Module Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3 Timer/Port Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7 Timer/Port Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-11 Timer/Port in an ADC Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-12
Universal Timer/Port Module
9-1
Timer/Port Configuration
9.1 Timer/Port Configuration
The Timer/Port is configured as shown in Figure 9-1.
Figure 9-1. Timer/Port Configuration
CPON ENB CIN Sxx/Oxx/CMPI VCC/4 0
+ _
ENA
CMP TPIN.5 Enable Control TPSSEL0 TPSSEL1 TPSSEL0 0 1 2 3 B16 Set_RC1FG Set_EN1FG EN1 8-Bit Counter CLK1 TPCNT1 r/w RC1
1
CMP ACLK MCLK
TPSSEL3 TPSSEL2 TPIN.5 ACLK MCLK TPx.0 GND TPD.0 TPE.0 TPx.1 TPD.1 TPx.2 TPE.1 TPD.2 TPE.2 TPx.3 TPD.3 0 1 2 3
1
0
EN2 8-Bit Counter CLK2 TPCNT2 r/w RC2 Set_RC2FG
Control Register TPCTL TPSSEL1 TPSSEL0 ENB RC1FG EN1FG
EN1
ENA
RC2FG
Data Register TPD B16 TPD.5...........................TPD.0
TPx.4
TPE.3 TPD.4 TPE.4 TPIN.5
CPON Data Register TPD TPSSEL3 TPE.5...........................TPE.0 TPSSEL2
TPx.5 TPD.5 TPE.5
9-2
Timer/Port Module Operation
9.2 Timer/Port Module Operation
This section describes the Timer/Port counters.
9.2.1
Timer/Port Counter TPCNT1, 8-Bit Operation
Refer to Figure 9-1 for the following discussion. The Universal Timer/Port offers much more application flexibility than other simple timer/counters by providing for flexible clocking and enable conditions. The clock input to counter TPCNT1 can be selected from three different sources. MCLK, ACLK, or CMP (an external signal, or the comparator output) can be used to increment the timer/counter. The counter increments with each positive edge of the CLK1 clock input when enable signal EN1 is set. When the counter reaches full scale (0FFh), a ripple-carry signal RC1 goes high and remains high as long as the counter data equals 0FFh. When the counter increments from 0FFh to 000h, RC1 goes back low, but the negative edge of signal RC1 sets a ripple-carry flag bit in the TPCTL register (RC1FG) to indicate that the counter has rolled over. Setting the ripple carry flag RC1FG will generate a CPU interrupt if the Timer/Port interrupt enable flag (TPIE) is set. The RC1FG is not automatically reset, so it must be reset by the interrupt service routine (ISR). The user has several choices to configure the enable signal EN1 (see Table 9-1). The counter is enabled when one or both ENA and ENB bits are set. Both of these bits are reset with a system reset (POR or PUC). Further, an external event can be used to enable or disable the timer. When an external event on signals CMP or TPIN.5 disables the counter, flag EN1FG of the TPCTL register is set and a CPU interrupt is generated if the Timer/Port interrupt is enabled. The EN1FG flag is not automatically reset, so it must be reset by the ISR. Note that the EN1FG flag is not set if the counter is disabled through software manipulation of the ENA or ENB bits. Any time the counter is disabled, the counter data is frozen, but the software can write a different value to the counter to change its data. Note that this write operation does not re-enable the counter. The counter can be read or written to at anytime. A timer read can occur asynchronously to a timer increment if the clock source for the timer is either the ACLK or the CMP signal. In this situation the user software should perform several reads of the timer and take a majority vote to determine the correct timer value. When MCLK is selected as the clock source, the read is performed synchronously to the increment, so a majority vote software routine is not necessary. Reading the timer/counter does not effect the count. The timer/counter will accurately increment with each clock regardless of when a read occurs. Also, performing a read of the counter directly after writing to it could result in reading different data than was written to it, depending on when the clock signal is applied.
Universal Timer/Port Module
9-3
Timer/Port Module Operation
9.2.2
Timer/Port Counter TPCNT2, 8-Bit Operation
Counter TPCNT2 operates similarly to TPCNT1, with a few differences in the enable signal and clock source. The enable signal for TPCNT2 is primarily controlled with bit B16 of the TPD register. Bit B16 selects 8 or 16-bit mode for the Timer/Port. When B16 is reset, the Timer/Port is in 8-bit mode and counter TPCNT2 is always enabled. Additionally, in 8-bit mode, counter TPCNT2 is completely independent from TPCNT1 and has a separate clock source. The clock source for TPCNT2 in 8-bit mode can be selected to be ACLK, MCLK, or the TPIN.5 pin. Like TPCNT1, TPCNT2 has a ripple-carry output (RC2) that is high while the counter data is equal to 0FFh and the enable signal EN2 is high. When the counter increments from 0FFh to 000h, RC2 goes back low. The negative edge of RC2 sets a ripple-carry flag in the TPCTL register (RC2FG) to indicate that the counter has rolled over. Setting RC2FG generates a CPU interrupt if the Timer/Port interrupt is enabled. RC2FG is not automatically reset and should be reset by the ISR. Any time the counter is disabled, the counter data is frozen, but the software can write a different value to the counter to change its data. Note that this write operation does not reenable the counter. The counter can be read or written to at any time. A timer read can occur asynchronously to a timer increment if the clock source for the timer is either ACLK or the TPIN.5 signal. In this situation, the user software should perform several reads of the timer and take a majority vote to determine the correct timer value. When MCLK is selected as the clock source, the read is performed synchronously to the increment, so a majority vote software routine is not necessary. Reading the timer does not effect the count. The timer will accurately increment with each clock regardless of when a read occurs. Also, performing a read of the counter immediately after writing to it could result in reading different data than was written to it, depending on whether a clock signal was applied between the write and the read.
9.2.3
Timer/Port Counter, 16-Bit Operation
In 16-bit mode (B16 = 1), counters TPCNT1 and TPCNT2 are cascaded to form one 16-bit timer (see Figure 9-2). In this configuration, both counters operate from the same clock and the ripple-carry output of TPCNT1 serves as the enable for TPCNT2. In 16-bit mode, clock source selection for the counter is made with the TPSSEL0 and TPSSEL1 bits, and TPSSEL2 and TPSSEL3 become don't cares. Clock source choices are the same as those for TPCNT1 in 8-bit mode: ACLK, MCLK, or CMP.
9-4
Timer/Port Module Operation
Figure 9-2. Timer/Port Counter, 16-Bit Operation
CPON ENB CIN Sxx/Oxx/CMPI VCC/4 0
+ _
ENA
CMP TPIN.5 Enable Control TPSSEL0 RC1 EN1 CLK1 8-Bit Counter TPCNT1 r/w EN2 8-Bit Counter CLK2 TPCNT2 r/w RC2 Set_RC2FG EN1
1
TPSSEL1 TPSSEL0 CMP ACLK MCLK 0 1 2 3
In 16-bit mode, the ripple carry signal is RC2 and is set when the counter value is equal to 0FFFFh. When the counter increments to 00000h, the negative edge of RC2 sets the RC2FG flag generating a CPU interrupt, and indicating that the counter has rolled over. The RC2FG flag must be reset by the ISR. RC1FG is not set in 16-bit mode - it remains unchanged. Like in the 8-bit operation of TPCNT1, an external event can be used to enable or disable the timer when in 16-bit mode. When an external event on signal CMP or TPIN.5 disables the counter, flag EN1FG of the TPCTL register is set and a CPU interrupt is generated if the Timer/Port interrupt is enabled. The EN1FG flag is not automatically reset, so it must be reset by the ISR. Note that the EN1FG flag is not set if the counter is disabled through software manipulation of the ENA or ENB bits. Read and write access to the Timer/Port is always done using byte instructions--even when the counter is configured in 16-bit mode. This requires special software considerations to access the counter while it is running to assure that the value read is correct. If a clock edge increments the counter between readings of the TPCNT1 and TPCNT2 values, the counter data will not be correct.
Universal Timer/Port Module
9-5
Timer/Port Module Operation
9.2.4
Enable Control
The signals ENA, ENB, TPSSEL0, and TPSSEL1 control the operation of the counter as described in Table 9-1. Therefore, the counter can be configured to run unconditionally, to run based on signals TPIN.5 or CMP, or to stop. Additionally, several clock choices are available within each operating mode.
Table 9-1. Timer/Port Counter Signals, 16-Bit Operation
ENB 0 0 0 0 0 0 1 1 1 1 1 1 1 1 ENA 0 0 0 1 1 1 0 0 0 0 1 1 1 1 TPSSel1 0 0 1 0 0 1 0 0 1 1 0 0 1 1 TPSSel0 0 1 X 0 1 X 0 1 0 1 0 1 0 1 EN1 0 0 0 1 1 1 TPIN.5 TPIN.5 TPIN.5 TPIN.5 CMP CMP CMP CMP CLK1 CMP ACLK MCLK CMP ACLK MCLK CMP ACLK MCLK MCLK CMP ACLK MCLK MCLK
9.2.5
Comparator Input
The comparator input is typically shared with one segment line as shown in Figure 9-3. The LCD segment function is selected for this pin after the PUC signal is active. The comparator input is selected when the CPON bit is set. Note that once selected, the comparator input can not be deselected without a PUC signal. See Chapter 3 for details on the PUC signal.
Figure 9-3. Timer/Port Comparator Input
LCD Module Sxx/Oxx/CMPI 0
Sxx/Oxx/CMPI
CPON PUC CPON 1 CMP 0
S R
1
+ _
CPON VCC/4 1 VCC
VSS 0 V Timer/Port Module - Schematic detail
CIN
9-6
Timer/Port Registers
9.3 Timer/Port Registers
The Timer/Port module registers listed in Table 9-2 are byte structured and must be accessed using byte instructions (suffix B).
Table 9-2. Timer/Port Registers
Register TP Control TP Counter 1 TP Counter 2 TP Data TP Data Enable Short Form TPCTL TPCNT1 TPCNT2 TPD TPE Register Type Read/write Read/write Read/write Read/write Read/write Address 04Bh 04Ch 04Dh 04Eh 04Fh Initial State Reset Unchanged Unchanged Reset Reset
9.3.1
Timer/Port Control Register
The information stored in the control register (see Figure 9-4) determines the operation of the Timer/Port module.
Figure 9-4. Timer/Port Control Register
7 TPCTL 04Bh TPSSEL 1 TPSSEL 0 rw-0 rw-0 0
ENB ENA EN1 RC2FG RC1FG EN1FG
rw-0
rw-0
r-0
rw-0
rw-0
rw-0
Bit 0:
Enable flag EN1FG is set with the negative edge of enable signal EN1, if an event on CMP or TPIN.5 causes EN1 to go low. Note that EN1FG is not set if EN1 goes low as a result of software manipulation of ENA or ENB. EN1FG must be reset by software. The EN1FG bit can be used during the Timer/Port interrupt service routine to determine if the interrupt event came from enable EN1 or from a ripple/carry.
Bit 1:
In 8-bit mode, bit RC1FG indicates that counter TPCNT1 rolled from 0FFh to 0h (overflow condition). In 16-bit mode, RC1FG is not active. However, if software sets RC1FG, an interrupt request will be generated (if enabled), even if the counter is in 16-bit mode. RC1FG must be reset by software. In 8-bit mode, bit RC2FG indicates that counter TPCNT2 rolled from 0FFh to 0h (overflow condition). In 16-bit mode, RC2FG indicates the 16-bit counter has rolled from 0FFFFh to 0000h. RC2FG must be reset by software.
Bit 2:
Note: RC1FG and RC2FG When Software Disables the Counter When the counter is disabled with software via bits ENA and ENB, flag RC1FG (8-bit mode), or flag RC2FG (16-bit mode) may or may not be set if the counter rolls over to zero at the same time.
Universal Timer/Port Module
9-7
Timer/Port Registers
Bit 3:
Enable signal EN1. This bit represents the state of enable signal EN1 and can be read by software. The signal at TPx.5 can be used in the module internally and can be read with bit EN1 when TPE.5 is reset.
Bits 4, 5: The value of enable signal EN1 is defined by bits ENA, ENB and TPSSEL0, as described in Table 9-3.
Table 9-3. Bit EN1 Level/Signal
ENB 0 0 1 1 1 1 ENA 0 1 0 0 1 1 TPSSel0 X X 0 1 0 1 EN1 0 1 TPIN.5 TPIN.5 CMP CMP
Bits 6, 7:
The Timer/Port clock source-select bits TPSSEL0 and TPSSEL1 select the clock source for TPCNT1, as described in Table 9-4.
Table 9-4. Timer/Port Clock Source Selection
TPSSel1 0 0 1 TPSSel0 0 1 X CLK1 CMP ACLK MCLK
9.3.1.1
Timer/Port Counter Registers TPCNT1 and TPCNT2
Both counter registers are read and written independently. The counter registers are shown in Figure 9-5.
Figure 9-5. Timer/Port Counter Registers
7 TPCNT1 04Ch rw 7 TPCNT2 04Dh rw
27 26 25 24 23 22 21 20 27 26 25 24 23 22 21 20
0
rw
rw
rw
rw
rw
rw
rw 0
rw
rw
rw
rw
rw
rw
rw
9-8
Timer/Port Registers
9.3.1.2
Timer/Port Data Register
The data register holds the value of the six outputs, the 16-bit mode control bit, and the comparator control bit, as shown in Figure 9-5.
Figure 9-6. Timer/Port Data Register
7 TPD 04Eh
B16 CPON TPD.5 TPD.4 TPD.3 TPD.2 TPD.1
0
TPD.0
rw-0
rw-0
rw-0
rw-0
rw-0
rw-0
rw-0
rw-0
Bits 0 to 5: Bits TPD.0 to TPD.5 hold the data for the output pins TPx.0 to TPx.5. The values are applied to these pins when the three-state output is enabled by TPE.0 to TPE.5. They are reset with a PUC. Bit 6: The comparator CPON bit enables the comparator. It is reset with a PUC. Current consumption is reduced by disabling the comparator when not in use. Control bit B16 selects 8- or 16-bit operation. B16 = 0: 8-bit counter mode is selected. TPCNT1 and TPCNT2 are independent 8-bit counters. B16 = 1: 16-bit counter mode is selected. TPCNT1 and TPCNT2 form one 16-bit counter.
Bit 7:
9.3.1.3
Timer/Port Enable Register
The Timer/Port enable register contains the enable bits for the six outputs and two bits for clock source selection for TPCNT2.
Figure 9-7. Timer/Port Enable Register
7 TPE 04Fh
TPSSEL TPSSEL TPE.5 3 2 TPE.4 TPE.3 TPE.2 TPE.1
0
TPE.0
rw-1
rw-1
rw-0
rw-0
rw-0
rw-0
rw-0
rw-0
Bits 0 to 5:Bits TPE.0 to TPE.5 are the enable bits for outputs TPx.0 to TPx.5. The bits are reset with a PUC, with the resulting outputs being in the high impedance state. Note: TPE.5 must be reset to use pin TPx.5 as an input.
Universal Timer/Port Module
9-9
Timer/Port Registers
Bits 6, 7: Timer/Port clock source-select bits TPSSEL2 and TPSSEL3 select the clock source for TPCNT2 when bit B16 is reset, as shown in Table 9-5. In 16-bit mode (B16 = 1) the clock source for counters TPCNT1 and TPCNT2 are identical and are selected by TPSSEL0 and TPSSEL1.
Table 9-5. Counter TPCNT2 Clock Sources
B16 0 0 0 0 1 TPSSel3 0 0 1 1 X TPSSel2 0 1 0 1 X CLK2 TPIN.5 ACLK MCLK MCLK = CLK1
9-10
Timer/Port Interrupts
9.4 Timer/Port Interrupts
The Timer/Port has one interrupt vector sourced by up to three interrupt flags (RC1FG, RC2FG, and EN1FG), as shown in Figure 9-8. When in 8-bit mode, all three flags source the Timer/Port interrupt. When in 16-bit mode, only flags RC2FG and EN1FG source the interrupt. The Timer/Port interrupt service routine should check the flags to determine the source of a Timer/Port interrupt and handle it appropriately. All three flags must be reset by software. Note that even though RC1FG is inactive in 16-bit mode, an interrupt request will be generated (if enabled) when set by software.
Figure 9-8. Timer/Port Interrupt Scheme
ENB EN1 D Q
B16 RC1
D
Q TPIE
Request_Interrupt_Service
HIGH RC2
D
Q
The Timer/Port interrupt is enabled by the TPIE bit located in the SFR register IE2. The bit must be set to enable the Timer/Port interrupt. The initial state is reset. See chapter 3 for a discussion of the IEx registers. Note: When software is used to stop the counter via the ENA and ENB bits, flags RC1FG and RC2FG may be set (as appropriate, according to 8- or 16-bit mode) if the counter(s) roll over at the same time.
Universal Timer/Port Module
9-11
Timer/Port in an ADC Application
9.5 Timer/Port in an ADC Application
In addition to supporting a variety of counting and timing applications, the Universal Timer/Port also supports slope A/D conversion. Slope A/D conversion is extremely useful in sensor applications where the sensor is either resistive or capacitive. In general, slope A/D conversion involves comparing the discharge times of two RC networks--one with a known time constant, and one with a sensor controlling the time constant. The value of the sensor can then be determined by a simple ratio of the discharge times. For example, to use the Universal Timer/Port to measure a resistive sensor, one would first charge and discharge an RC network, made up of a known resistor value and a known capacitor value, while measuring the discharge time. Next, the known resistor would be replaced in the circuit by the unknown sensor and the charge/discharge cycle would be repeated, again measuring the discharge time. The value of the sensor could then be calculated by dividing the discharge times and multiplying by the known resistor value. All of the required charging, discharging, timing, and switching of the resistors or capacitors can be done completely with the Universal Timer/Port, its highimpedance outputs, and its integrated comparator. See the MSP430 Application Report Book and other application notes for details and circuit diagrams on using the Universal Timer/Port in slope A/D applications. Application notes may be downloaded from www.ti.com/sc/msp430.
9-12
Chapter 10
Timers
The MSP430 microcontrollers offer a variety of very flexible timers that can be used to support a wide array of applications while also optimizing ultralowpower operation.
Topic
Page
10.1 Basic Timer1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2 10.2 8-Bit Interval Timer/Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-7 10.3 The Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-13
Timers
10-1
Basic Timer1
10.1 Basic Timer1
The Basic Timer1 (shown in Figure 10-1) supplies other peripheral modules or the software with low frequency control signals. The Basic Timer1 operation supports two independent 8-bit timing/counting functions, or one 16-bit timing/counting function. Some uses for the Basic Timer1 include:
-
Real-time clock (RTC) Debouncing keys (keyboard) Software time increments
Figure 10-1. Basic Timer1 Configuration
Control Register BTCTL
SSEL DIV 1 0 2 1 0 Hold FRFQ IP IP IP
DIV Hold ACLK EN1 CLK1 BTCNT1
Q4 Q5 Q6 Q7
FRFQ1 FRFQ0 SSEL DIV 0 1 2 3 Hold EN2 CLK2 0123 fLCD
ACLK:256 MCLK
BTCNT2
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
IP2 IP1 IP0
Set Interrupt 0 1 2 3 4 5 6 7 Flag BTIFG
10-2
Basic Timer1
10.1.1 Basic Timer1 Registers
The Basic Timer1 register is byte structured, and should be accessed using byte processing instructions (suffix .B). Table 10-1 describes the Basic Timer1 registers.
Table 10-1.Basic Timer1 Registers
Register BT Control BT Counter 1 BT Counter 2
Note:
Short Form BTCTL BTCNT1 BTCNT2
Register Type Read/write Read/write Read/write
Address 040h 046h 047h
Initial State Unchanged Unchanged Unchanged
The user's software should configure these registers at power-up, as there is no defined initial state.
10.1.1.1 Basic Timer1 Control Register
The information stored in the control register determines the operation of Basic Timer1. The state of the different bits selects the frequency source, the interrupt frequency, and the framing frequency of the LCD control circuitry as shown in Figure 10-2.
Figure 10-2. Basic Timer1 Control Register
7 BTCTL 040h
SSEL Hold DIV FRFQ1 FRFQ0 IP2 IP1
0
IP0
rw
rw
rw
rw
rw
rw
rw
rw
Bits 0 to 2:The three least-significant bits IP2 to IP0 determine the interrupt interval time. It is the interval of consecutive settings of the interrupt-request flag BTIFG, as illustrated in Figure 10-3. Bits 3 to 4:The two bits FRFQ1 and FRFQ0 select the frequency fLCD as described in Figure 10-3. Devices with the LCD peripheral on the chip use this frequency to generate the timing of the common and select lines. Bit 5: Bit 6: See bit 7. The hold bit stops the counter operation. BTCNT2 is held if the hold bit is set. BTCNT1 is held if the hold and DIV bits are set. The SSEL and DIV bits select the frequency source for BTCNT2, as described in Table 10-2.
Bit 7:
Timers
10-3
Basic Timer1
Table 10-2.BTCNT2 Input Frequency Sources
SSEL 0 0 1 1 DIV 0 1 0 1 CLK2 ACLK ACLK/256 MCLK ACLK/256
Figure 10-3. Basic Timer1 Control Register Function
7 BTCTL 040h
SSEL Hold DIV FRFQ1 FRFQ0 IP2 IP1
0
IP0
rw
rw
rw
rw
rw
rw
rw
rw Interrupt Frequency
0 0 0 0 1 1 1 1 0 0 1 1 0 1 0 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
fCLK2/2 fCLK2/2 fCLK2/8 fCLK2/16 fCLK2/32 fCLK2/64 fCLK2/128 fCLK2/256
fLCD = fACLK/32 fLCD = fACL/64 fLCD = fACLK/128 fLCD = fACLK/256
10.1.1.2 Basic Timer1 Counter BTCNT1
The Basic Timer1 counter BTCNT1, shown in Figure 10-4 divides the auxiliary clock ACLK. The frame frequency for the LCD-drive is selected from four outputs of the counter's bits. The output of the most significant bit can be used for the clock input to the second counter BTCNT2. The value of bits Q0 to Q7 can be read, and the software can write to bits Q0 to Q7.
Figure 10-4. Basic Timer1 Counter BTCNT1
7 BTCNT1 046h
27 26 25 24 23 22 21
0
20
rw
rw
rw
rw
rw
rw
rw
rw
10-4
Basic Timer1
10.1.1.3 Basic Timer1 Counter BTCNT2
The Basic Timer1 counter BTCNT2, shown in Figure 10-5, divides the inputclock frequency. The input-clock source can be MCLK, ACLK, or ACLK/256. The interrupt period can be selected using IP0 to IP2, located in the Basic Timer1 control register BTCTL. It selects one of the eight bits of BTCNT2 as the source signal to set the Basic Timer1 interrupt flag BTIFG. The value of the counter bits can be read, as well as written.
Figure 10-5. Basic Timer1 Counter BTCNT2
7 BTCNT2 047h
27 26 25 24 23 22 21
0
20
rw
rw
rw
rw
rw
rw
rw
rw
10.1.2 Special Function Register Bits
Two SFR bits pertain to the Basic Timer1 Interrupt:
-
Basic Timer1 interrupt flag (BTIFG) (located in IFG2.7) Basic Timer1 interrupt enable (BTIE) (located in IE2.7)
The BTIFG flag indicates that a Basic Timer1 interrupt is pending and is reset automatically when the interrupt is accepted. The BTIE bit enables or disables the interrupt from the Basic Timer1 and is reset with a PUC. The Basic Timer1 interrupt is also enabled or disabled with the general interrupt enable bit, GIE.
10.1.3 Basic Timer1 Operation
The Basic Timer1 is constantly incremented by the selected clock source. The hold bit inhibits all functions of the module and reduces power consumption. The Basic Timer1 registers may be accessed at any time, regardless of the state of the hold bit. An interrupt can be used to control system operation. The interrupt is a single source interrupt. The basic timer can operate in two different modes:
-
Two independent 8-Bit Timer/Counters One 16-bit timer/counter
Timers
10-5
Basic Timer1
10.1.3.1 8-Bit Counter Mode
In the 8-Bit Timer/Counter mode, counter BTCNT1 is incremented constantly with ACLK. When reading the counters, the user should be aware that the counter clock and CPU clock may be asynchronous. Therefore, special software consideration may be required to assure a correct reading. The BTCNT2 clock signal can be selected to be MCLK, ACLK, or ACLK/256 using the control signals SSEL and DIV. Counter BTCNT2 is incremented with the signal selected. One of the eight counter outputs can be selected to set the Basic Timer1 interrupt flag. Read and write access can be asynchronous when ACLK or ACLK/256 is selected. The hold bit stops all operations.
10.1.3.2 16-bit Counter Mode
The 16-bit timer/counter mode is selected when control bit DIV is set. In this mode, the clock source of counters BTCNT1 and BTCNT2 is the ACLK signal. The hold bit stops all operations.
10.1.4 Basic Timer1 Operation: Signal fLCD
The LCD controller uses the fLCD signal from the Basic Timer1 to generate the timing for common and segment lines. The frequency of signal fLCD is generated from ACLK. Using a 32,768-Hz crystal, the fLCD frequency can be 1024 Hz, 512 Hz, 256 Hz, or 128 Hz. Bits FRFQ1 and FRFQ0 allow the correct selection of frame frequency. The proper frequency fLCD depends on the LCD's requirement for framing frequency and LCD multiplex rate and is calculated by: fLCD = 2 x MUX rate x fFraming A 3 MUX example follows: LCD data sheet: fFraming = 100 Hz .... 30 Hz FRFQ: fLCD = 6 x fFraming fLCD = 6 x 100 Hz = 600 Hz ... 6 x 30 Hz = 180 Hz Select fLCD: 1024 Hz, 512 Hz, 256 Hz, or 128 Hz fLCD = 32,768/128 = 256 Hz FRFQ1 = 1; FRFQ0 = 0
See the LCD Driver chapter for more details on the LCD driver.
10-6
8-Bit Interval Timer/Counter
10.2 8-Bit Interval Timer/Counter
The 8-Bit Timer/Counter supports three major application functions:
-
Serial communication or data exchange Pulse counting or pulse accumulation Timing
Figure 10-6 shows the 8-Bit Timer/Counter functions.
Figure 10-6. 8-Bit Timer/Counter
Interrupt Request P0IES.1 P0.1 1 1 1 1 G1 A P0IE.1 P0IFG.1 Set Clear IRQA: Interrupt Request Accepted ISCTL P0.1 - 8bT/C Interrupt Logic Carry + D Q Clear Detect Start Cond. Write To TCDAT 1 3 2 4 A B EN1 EN2 P0DIR.2 P0OUT.2 SSEL1 SSEL0 ISCTL TXE ENCNT RXACT PUC Set Q D D Set TXD_FF RXD_FF PUC Q TXD RXD LSB 8 MSB Load CLK 8 Enable MDB 8b Counter 8b Preload Reg. 8 Q IRQP0.1
MCLK ACLK
P0.2
Interval/Timer Control Register
Timers
10-7
8-Bit Interval Timer/Counter
10.2.1 Operation of 8-Bit Timer/Counter
The 8-Bit Timer/Counter includes the following major blocks:
-
8-bit up-counter with a preload register 8-bit control register Input clock selector Edge detection, (for example, a start bit of asynchronous protocols) Input and output data latch, triggered by the carry-out signal from the 8-bit counter
10.2.1.1 8-Bit Timer/Counter With Preload Register
The 8-bit counter counts up with the selected input clock. Two counter inputs, load and enable, control the operation. Figure 10-7 shows the 8-bit counter functions.
Figure 10-7. 8-Bit Counter Example
8-Bit Preload Register
Counter is loaded with 037h each time the carry signal goes high.
Carry 8b Counter CLK Load Enable
Clock Selected Via Input Multiplexer
CLK Q7-Q0 CARRY LOAD NCLK = 100h - 037h
FA FB FC FD FE FF 00/37 38 39 3A 3B
Either of two events controls the load function: a carry from the counter or a write access loads the counter with the data of the preload register. Note that writing to the counter (TCDAT register) loads the counter with the preload value, not the contents of the write instruction. The software may write or read the preload register. The preload register acts as a buffer and can be written to immediately after the load of the counter is complete. When the enable signal is set high, the counter counts up each time a positive-clock edge is applied to the counter's clock input.
10-8
8-Bit Interval Timer/Counter
10.2.1.2 8-Bit Control Register
The information stored in the 8-bit control register selects the operating mode of the timer/counter and controls the function.
10.2.1.3 Input Clock Selector
Two bits in the 8-bit control register select the source for the clock input of the 8-bit counter. The four sources are the system clock MCLK, the auxiliary clock ACLK, the external signal from pin P0.1, and the signal from the logical .AND. of MCLK and pin P0.1.
10.2.1.4 Edge Detection
Serial protocols such as UART need start-bit edge detection at the receiver to determine the start of data transmission. This edge detection is supported by the 8-Bit Timer/Counter and used to implement a UART with the timer.
10.2.1.5 Input and Output Data Latch, RXD_FF and TXD_FF
The clock used to latch data into the input and output data latches is the carry signal from the 8-bit counter. Both latches are used as single-bit buffers and change their outputs with the predefined timing.
10.2.2 8-Bit Timer/Counter Registers
The timer/counter registers, described in Table 10-3, are accessed using byte instructions.
Table 10-3.8-Bit Timer/Counter Registers
Register TC Control Preload Counter Short Form TCCTL TCPLD TCDAT Register Type Read/write Read/write Read/(write) Address 042h 043h 044h Initial State Reset Unchanged Unchanged
10.2.2.1 8-Bit Timer/Counter Control Register
The information stored in the control register, as shown in Figure 10-8, determines the operation of the 8-Bit Timer/Counter.
Figure 10-8. 8-Bit Timer/Counter Control Register
7 TCCTL 042h
SSEL1 SSEL0 ISCTL TXE ENCNT RXACT TXD
0
RXD
rw-0
rw-0
rw-0
rw-0 rw-0
rw-0
rw-0
r(-1)
Bit 0:
Bit RXD is read only. The signal from external pin P0.1 is latched with the carry signal of the 8-bit counter. Register bit TXD is buffered and clocked out with the carry signal from the 8-bit counter at pin P0.2 .
Bit 1:
Timers
10-9
8-Bit Interval Timer/Counter
Bit 2:
Bit RXACT controls the edge detect logic. The edge detect logic needs a reset ENCNT bit (bit 3) for correct counter-enable operation. RXACT = 0: The edge-detect FF is cleared and it cannot be the source for enabling the counter operation. RXACT = 1: The edge-detect FF is enabled. A positive or negative edge at pin P0.1, selected by P0IES.1, sets the FF, and the counter is prepared for count operation. Once the FF is set, it remains set until it is reset with RXACT = 0.
Bit 3:
Bit ENCNT sets the counter-enable signal. The 8-bit counter increments its value with each rising edge of the clock input. Together with bit RXACT (bit2, 0), this bit provides start/stop operation.
Bit 4:
Signal TXE controls the three-state output buffer for the TXD bit: TXE = 0: The direction control bit P0DIR.2 (see I/O chapter) determines if the buffer is active or in high-impedance state. TXE = 1: Output buffer active (independent of the value of P0DIR.2) Signal ISCTL controls the interrupt source between the I/O pin P0.1 and the carry signal of the 8-bit counter. ISCTL = 0: The I/O pin P0.1 is the source of interrupt P0IFG.1. ISCTL = 1: The carry signal from the 8-bit counter is the source of interrupt P0IFG.1.
Bit 5:
Bits 6, 7: Bits SSEL0 and SSEL1 select the source of the clock input. Table 10-4 describes the clock input source.
Table 10-4.Clock Input Source
SSEL1
0 1 0 1
SSEL0
0 0 1 1
Clock Source Signal at pin P0.1 (according to P0IES.1) MCLK ACLK Signal pin P0.1(according to P0IES.1) .AND. MCLK
10-10
8-Bit Interval Timer/Counter
10.2.2.2 8-Bit Timer/Counter Preload Register
The information stored in the preload register, not the data included with the instruction, is loaded into the 8-bit counter when a write access to the counter (TCDAT) is performed, as shown in the following code:
;========= Definitions ================================= Dummy .EQU 0 ; Value for dummy is not loaded into ; counter TCDAT .EQU 044h ; Address of 8-Bit Timer/Counter ;==Write pre-load register contents to 8-bit Timer/Counter= ; MOV.B #Dummy,&TCDAT ; The pre-load register (TCPLD) can be accessed using the address 043h.
10.2.2.3 8-Bit Counter Data
The data of the 8-bit counter can be read using address 044h. Writing to the counter loads the contents of the preload register--not the data included with the instruction.
10.2.3 Special Function Register Bits, 8-Bit Timer/Counter Related
The 8-Bit Timer/Counter has no individual interrupt bits; it shares the interrupt bits with port P0. Bit ISCTL, in control register TCCTL, selects the interrupt source for the interrupt flag. The port0 signal P0.1/RXD, or the carry signal of the 8-bit counter is used for the interrupt source. One SFR bit and one port P0 bit configure the interrupt events on P0.1/RXD.1 as follows:
-
P0.1/RXD interrupt enable P0IE.1 (located in IE1.3, initial state is reset) P0.1/RXD interrupt edge select P0IES.1 (located in P0IES, initial state is reset)
The interrupt flag is a single-source flag that automatically resets when the processor system services the interrupt. The enable bit and edge select bit remain unchanged.
10.2.4 Implementing a UART With the 8-Bit Timer/Counter
The 8-Bit Timer/Counter is uniquely capable of implementing a UART function, with the following features:
-
Automatic start-bit detection - even from all ultralow-power modes Hardware baud-rate generation Hardware latching of RXD and TXD data Baud rates of 75 to 115,200 baud
Timers
10-11
8-Bit Interval Timer/Counter
This UART implementation is different from other microcontroller implementations where a UART may be implemented with general-purpose I/O and manual bit manipulation via software polling. Those implementations require great CPU overhead and therefore increase power consumption and decrease the usability of the CPU. In this particular implementation, the 8-Bit Timer/Counter is configured as the baud clock and waits for the start bit. With the falling edge of the start bit, the counter begins counting (see Figure 10-9).
Figure 10-9.
Start Bit Detection
P0IES.1 P0.1 1 1 A VCC D Q Clear Edge Detect RXACT ENCNT Clock Source Enable 8b Counter
CLK
Note that no CPU overhead is required for the start-bit detection. Start-bit detection is automatic and occurs if the processor is in active mode, or low power modes 0-4. When the counter reaches full-scale, the TXD and RXD data is automatically latched, the baud rate is automatically preloaded into the counter, the counter automatically begins counting, and an interrupt is generated for the CPU to retrieve the RXD data or write the next TXD data. Software overhead is only required to read and write the RXD and TXD data. (see Figure 10-10).
Figure 10-10. Data Latching
Carry 8b Counter
CLK
Clock Source PUC Set TXD Q D To P0OUT.2 From P0.1 D Set TXD_FF RXD_FF PUC Q RXD
A complete application note including connection diagrams and complete software listing, may be found at www.ti.com/sc/msp430.
10-12
The Watchdog Timer
10.3 The Watchdog Timer
The primary function of the watchdog-timer module (WDT) is to perform a controlled-system restart after a software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed in an application, the module can work as an interval timer, to generate an interrupt after the selected time interval. The WDT diagram is shown in Figure 10-11.
Figure 10-11.Schematic of Watchdog Timer
See Interrupt Definition Int. Flag WDTQn Y 4 3 2 1 A Pulse Generator B Q6 Q9 Q13 Q15 16b Counter WDTCNT 0 1 0 1 1 0 1 Clear PUC (Asyn) EQU MCLK ACLK 1 1 A EN CLK 0 EQU Write Enable Low Byte R/W HOLD NMIES NMI TMSEL CNTCL SSEL IS1 IS0 Watchdog Timer Control Register LSB PUC Password Cmp. 16 WDTCTL MDB MSB
Some features of the Watchdog Timer include:
-
Eight software-selectable time intervals Two operating modes: as watchdog or interval timer Expiration of the time interval in watchdog mode, which generates a system reset; or in timer mode, which generates an interrupt request Safeguards which ensure that writing to the WDT control register is only possible using a password Support of ultralow-power using the hold mode
Timers
10-13
The Watchdog Timer
10.3.1 Watchdog Timer Register
The watchdog-timer counter (WDTCNT) is a 16-bit up-counter that is not directly accessible by software. The WDTCNT is controlled through the watchdog-timer control register (WDTCTL), shown in Figure 10-12, which is a 16-bit read/write register located at the low byte of word address 0120h. Any read or write access must be done using word instructions with no suffix or .w suffix. In both operating modes (watchdog or timer), it is only possible to write to WDTCTL using the correct password.
Figure 10-12. Watchdog Timer Control Register
15 WDTCTL 0120h WDTCTL read WDTCTL write 8 7 HOLD NMIES NMI rw-0 069h 05Ah rw-0 rw-0 TMSEL CNTCL SSEL rw-0 r0(w) rw-0 IS1 rw-0 0 IS0 rw-0
Bits 0, 1: Bits IS0 and IS1 select one of four taps from the WDTCNT, as described in Table 10-5. Assuming fcrystal = 32,768 Hz and fSystem = 1 MHz, the following intervals are possible:
Table 10-5.WDTCNT Taps
SSEL 0 0 1 0 1 0 1 1 IS1 1 1 1 0 1 0 0 0 IS0 1 0 1 1 0 0 1 0 Interval [ms] 0.064 0.5 1.9 8 16.0 32 250 1000 tMCLK x 26 tMCLK x 29 tACLK x 26 tMCLK x 213 tACLK x 29 tMCLK x 215 <- Value after PUC (reset) tACLK x 213 tACLK x 215
Bit 2:
The SSEL bit selects the clock source for WDTCNT. SSEL = 0: WDTCNT is clocked by MCLK. SSEL = 1: WDTCNT is clocked by ACLK. Counter clear bit. In both operating modes, writing a 1 to this bit restarts the WDTCNT at 00000h. The value read is not defined. The TMSEL bit selects the operating mode: watchdog or timer. TMSEL = 0: Watchdog mode TMSEL = 1: Interval-timer mode
Bit 3:
Bit 4:
10-14
The Watchdog Timer
Bit 5:
The NMI bit selects the function of the RST/NMI input pin. It is cleared by the PUC signal. NMI = 0: The RST/NMI input works as reset input. As long as the RST/NMI pin is held low, the internal signal is active (level sensitive). NMI = 1: The RST/NMI input works as an edge-sensitive nonmaskable interrupt input. If the NMI function is selected, this bit selects the activating edge of the RST/NMI input. It is cleared by the PUC signal. NMIES = 0: A rising edge triggers an NMI interrupt. NMIES = 1: A falling edge triggers an NMI interrupt. CAUTION: Changing the NMIES bit with software can generate an NMI interrupt. This bit stops the operation of the watchdog counter. The clock multiplexer is disabled and the counter stops incrementing. It holds the last value until the hold bit is reset and the operation continues. It is cleared by the PUC signal. HOLD = 0: The WDT is fully active. HOLD = 1: The clock multiplexer and counter are stopped.
Bit 6:
Bit 7:
10.3.1.1 Accessing the WDTCTL (Watchdog Timer Control Register)
The WDTCTL register can be read or written to. As illustrated in Figure 10-13, WDTCTL can be read without the use of a password. A read access is performed by accessing word address 0120h. The low byte contains the value of WDTCTL. The value of the high byte is always read as 069h.
Figure 10-13. Reading WDTCTL
15 WDTCTL 0120h
0 1 1 0 1 0 0
8
1
7
Read Data
0
r
r 6
r
r
r
r 9
r
r
rw-x, (w)
Write access to WDTCTL, illustrated in Figure 10-14, is only possible using the correct high-byte password. To change register WDTCTL, write to word address 0120h. The low byte contains the data to write to WDTCTL. The high byte is the password, which is 05Ah. A system reset (PUC) is generated if any value other than 05Ah is written to the high byte of address 0120h.
Figure 10-14. Writing to WDTCTL
15 WDTCTL 0120h
0 1 0 1 1 0 1
8
0
7
Write Data
0
(w) (w) (w) (w) (w) (w) (w) (w) 5 A
rw-x, (w)
Timers
10-15
The Watchdog Timer
10.3.2 Watchdog Timer Interrupt Control Functions
The Watchdog Timer (WDT) uses two bits in the SFRs for interrupt control.
-
The WDT interrupt flag (WDTIFG) (located in IFG1.0, initial state is reset) The WDT interrupt enable (WDTIE) (located in IE1.0, initial state is reset)
When using the watchdog mode, the WDTIFG flag is used by the reset interrupt service routine to determine if the watchdog caused the device to reset. If the flag is set, then the Watchdog Timer initiated the reset condition (either by timing out or by a security key violation). If the flag is cleared, then the PUC was caused by a different source. See chapter 3 for more details on the PUC and POR signals. When using the Watchdog Timer in interval-timer mode, the WDTIFG flag is set after the selected time interval and a watchdog interval-timer interrupt is requested. The interrupt vector address in interval-timer mode is different from that in watchdog mode. In interval-timer mode, the WDTIFG flag is reset automatically when the interrupt is serviced. The WDTIE bit is used to enable or disable the interrupt from the Watchdog Timer when it is being used in interval-timer mode. Also, the GIE bit enables or disables the interrupt from the Watchdog Timer when it is being used in interval-timer mode.
10.3.3 Watchdog Timer Operation
The WDT module can be configured in two modes: watchdog and the intervaltimer modes.
10.3.3.1 Watchdog Mode
When the WDT is configured to operate in watchdog mode, both a watchdog overflow and a security violation trigger the PUC signal, which automatically clears the appropriate system register bits. This results in a system configuration for the WDTCTL bits where the WDT is set into the watchdog mode and the RST/NMI pin is switched to the reset configuration. After a power-on reset or a system reset, the WDT module automatically enters the watchdog mode and all bits in the WDTCTL register and the watchdog counter (WDTCNT) are cleared. The initial conditions at register WDTCTL cause the WDT to start running at a relatively-low frequency, due to the range of the digitally-controlled oscillator (DCO) automatically being set in these situations. Since the WDTCNT is reset, the user software has ample time to set up or halt the WDT and to adjust the system frequency.
10-16
The Watchdog Timer
When the module is used in watchdog mode, the software should periodically reset the WDTCNT by writing a 1 to bit CNTCL of WDTCTL to prevent expiration of the selected time interval. If a software problem occurs and the time interval expires because the counter is no longer being reset, a system reset is generated and a system PUC signal is activated. The system restarts at the same program address that follows a power up. The cause of reset can be determined by testing bit 0 of interrupt flag register 1 in the SFRs. The appropriate time interval is selected by setting bits SSEL, IS0, and IS1 accordingly.
10.3.3.2 Timer Mode
Setting WDTCTL register bit TMSEL to 1 selects the timer mode. This mode provides periodic interrupts at the selected time interval. A time interval can also be initiated by writing a 1 to bit CNTCL in the WDTCTL register. When the WDT is configured to operate in timer mode, the WDTIFG flag is set after the selected time interval, and it requests a standard interrupt service. The WDT interrupt flag is a single-source interrupt flag and is automatically reset when it is serviced. The enable bit remains unchanged. In interval-timer mode, the WDT interrupt-enable bit and the GIE bit must be set to allow the WDT to request an interrupt. The interrupt vector address in timer mode is different from that in watchdog mode. Note: Watchdog Timer, Changing the Time Interval Changing the time interval without clearing the WDTCNT may result in an unexpected and immediate system reset or interrupt. The time interval must be changed together with a counter-clear command using a single instruction (for example, MOV #05A0Ah,&WDTCTL). Changing the clock source during normal operation may result in an incorrect interval. The timer should be halted before changing the clock source.
10.3.3.3 Operation in Low-Power Modes
The MSP430 devices have several low-power modes. Different clock signals are available in different low-power modes. The requirements of the user's application and the type of clocking circuit on the MSP430 device determine how the Watchdog Timer and clocking signals should be configured. Review the clock-system chapter to determine the clocking circuit, clock signals, and low-power modes available. For example, the WDT should not be configured in watchdog mode with MCLK as its clock source if the user wants to use low-power mode 3 because MCLK is not active in LPM3, therefore the WDT would not function properly. The WDT hold condition can also be used to support low power operation. The hold condition can be used in conjunction with low-power modes when needed.
Timers
10-17
The Watchdog Timer
10.3.3.4 Software Example
The following example illustrates the watchdog-reset operation.
; After RESET or power-up, the WDTCTL register and WDTCNT ; are cleared and the initial operating conditions are ; watchdog mode with a time interval of 32 ms. ; ;Constant definitions: ; WDTCTL .EQU 0120h ; Address of Watchdog Timer WDTPW .EQU 05A00h ; Password T250MS .EQU 5 ; SSEL, IS0, IS1 set to 250 ms T05MS .EQU 2 ; SSEL, IS0, IS1 set to 0.5 ms CNTCL .EQU 8 ; Bit position to reset WDTCNT TMSEL .EQU 010h ; Bit position to select timer mode ; ; As long as watchdog mode is selected, watchdog reset has ; to be done periodically through an instruction e.g.: ; ........ ........ MOV #WDTPW+CNTCL,&WDTCTL ; ; To change to timer mode and a time interval of 250 ms, ; the following instruction sequence can be used: ; MOV #WDTPW+CNTCL+TMSEL+T250MS,&WDTCTL ; Clear WDTCNT and ; select 250 ms and timer ; mode ........ ........ ; Note: The time interval and clear of WDTCNT should be ; modified within one instruction to avoid ; unexpected reset or interrupt ; ; Switching back to watchdog mode and a time interval of ; 0.5 ms is performed by: ; ........ ........ MOV #WDTPW+CNTCL,&WDTCTL ; Reset WDT counter ; MOV #WDTPW+T05MS,&WDTCTL ; Select watchdog mode ; and 0.5 ms ........
10-18
Chapter 11
Timer_A
This section describes the basic functions of the MSP430 general-purpose 16-bit Timer_A. Note: Throughout this chapter, the word count is used in the text. As used in these instances, it refers to the literal act of counting. It means that the counter must be in the process of counting for the action to take place. If a particular value is directly written to the counter, then the associated action will not take place. For example, the CCR0 interrupt flag is set when the timer counts up to the value in CCR0. The counter must count from CCR0-1 to CCR0. If the CCR0 value were simply written directly to the timer with software, the interrupt flag would not be set, even though the values in the timer and the CCR0 registers are the same.
Topic
Page
11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2 11.2 Timer_A Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4 11.3 Timer Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6 11.4 Capture/Compare Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-13 11.5 The Output Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-19 11.6 Timer_A Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-25 11.7 Timer_A UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-34
Timer_A
11-1
Introduction
11.1 Introduction
Timer_A is an extremely versatile timer made up of :
-
16-bit counter with 4 operating modes Selectable and configurable clock source Five independently configurable inputs configurable capture/compare registers with
Five individually configurable output modules with 8 output modes
Timer_A can support multiple, simultaneous, timings; multiple capture/ compares; multiple output waveforms such as PWM signals; and any combination of these. Additionally, Timer_A has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers on captures or compares. Each capture/compare block is individually configurable and can produce interrupts on compares or on rising, falling, or both edges of an external capture signal. The block diagram of Timer_A is shown in Figure 11-1.
11-2
Introduction
Figure 11-1. Timer_A Block Diagram
TPSSEL1
TACLK ACLK MCLK INCLK
TPSSEL0
0 1 2 3
Timer Clock 15 Input Divider
Data 0 16-Bit Timer Mode Control
16-Bit Timer
CLK 1
POR/CLR
RC Carry/Zero Timer Bus
Equ0
Set_TAIFG
ID1 ID0
MC1
MC0
CCIS01 CCIS00
CCI0A CCI0B GND VCC 0 1 2 3 CCI0 Capture Mode Capture
0 15 Capture/Compare Register CCR0
Capture/Compare Register CCR0 OM02 OM01 OM00
Out 0
Output Unit 0 Comparator 0 EQU0
CCM01 CCM00 Capture/Compare Register CCR1 OM12 OM11 OM10
CCIS11 CCIS10
CCI1A CCI1B GND VCC 0 1 2 3 CCI1 Capture Capture Mode
0 15 Capture/Compare Register CCR1
Out 1
Output Unit 1 Comparator 1 EQU1
CCM11 CCM10 Capture/Compare Register CCR2 OM22 OM21 OM20
CCIS21 CCIS20
CCI2A CCI2B GND VCC 0 1 2 3 CCI2 Capture Capture Mode
0 15 Capture/Compare Register CCR2
Out 2
Output Unit 2 Comparator 2 EQU2
CCM21 CCM20 Capture/Compare Register CCR3 OM32 OM31 OM30
CCIS31 CCIS30
CCI3A CCI3B GND VCC 0 1 2 3 CCI3 Capture Capture Mode
15 Capture/Compare Register CCR3
0
Out 3
Output Unit 3
Comparator 3 EQU3 CCM31 CCM30 Capture/Compare Register CCR4 OM42 OM41 OM40
CCIS41 CCIS40
CCI4A CCI4B GND VCC 0 1 2 3 CCI4 Capture Capture Mode
15 Capture/Compare Register CCR4
0
Out 4
Output Unit 4
Comparator 4 EQU4 CCM41 CCM40
Timer_A
11-3
Timer_A Operation
11.2 Timer_A Operation
The 16-bit timer has 4 modes of operation selectable with the MC0 and MC1 bits in the TACTL register. The timer increments or decrements (depending on mode of operation) with each rising edge of the clock signal. The timer can be read or written to with software. Additionally, the timer can generate an interrupt with its ripple-carry output when it overflows.
11.2.1 Timer Mode Control
The timer has four modes of operation as shown in Figure 11-2 and described in Table 11-1: stop, up, continuous, and up/down. The operating mode is software selectable with the MC0 and MC1 bits in the TACTL register.
Figure 11-2. Mode Control
Data 15 Timer Clock 16-Bit Timer
CLK
0 Mode Control
Equ0
RC Carry/Zero
POR
MC1 0 0 1 1
MC0 0 1 0 1
Set_TAIFG Stop Mode Up Mode Continuous Mode Up/Down Mode
Table 11-1. Timer Modes
Mode Control MC1 0 0 1 1 MC0 0 1 0 1 Mode Stop Up Continuous Up/Down Description The timer is halted. The timer counts upward until value is equal to value of compare register CCR0. The timer counts upward continuously. The timer counts up until the timer value is equal to compare register 0 and then it counts down to zero.
11-4
Timer_A Operation
11.2.2 Clock Source Select and Divider
The timer clock can be sourced from internal clocks (i.e. ACLK, MCLK) or from an external source (TACLK) as shown in Figure 11-3. The clock source is selectable with the SSEL0 and SSEL1 bits in the TACTL register. It is important to note that when changing the clock source for the timer, errant timings can occur. For this reason it is recommended to stop the timer before changing the clock source. The selected clock source may be passed directly to the timer or divided by 2,4, or 8, as shown in Figure 11-4. The ID0 and ID1 bits in the TACTL register select the clock division. Note that the input divider is reset by a POR signal (see chapter 3, System Resets, Interrupts, and Operating Modes for more information on the POR signal) or by setting the CLR bit in the TACTL register. Otherwise, the input divider remains unchanged when the timer is modified. The state of the input divider is invisible to software.
Figure 11-3. Schematic of 16-Bit Timer
SSEL1 SSEL0
Timer Clock 0 Input Divider
CLK
Data 15 16-Bit Timer RC Carry/Zero Mode Control
Equ0
TACLK ACLK MCLK INCLK
0 1
2 ID1 3 0 0 1 1 ID0 0 1 0 1 Pass 1/2 1/4 1/8 POR/CLR
MC1 0 0 1 1
MC0 0 1 0 1
Set_TAIFG Stop Mode Up Mode Continuous Mode Up/Down Mode
Figure 11-4. Schematic of Clock Source Select and Input Divider
SSEL1 SSEL0 Input Divider
TACLK ACLK MCLK INCLK
0 1
T
Q C
T
Q C
T
Q C
16-Bit Timer Clock
2 3 ID1 0 0 1 1 ID0 0 1 0 1 POR Pass 1/2 1/4 1/8 CLR
Timer_A
11-5
Timer Modes
11.2.3 Starting the Timer
The timer may be started or restarted in a variety of ways:
-
Release Halt Mode: The timer counts in the selected direction when a timer mode other than stop mode is selected with the MCx bits. Halted by CCR0 = 0, restarted by CCR0 > 0 when the mode is either up or up/down: When the timer mode is selected to be either up or up/down, the timer may be stopped by writing 0 to capture/compare register 0 (CCR0). The timer may then be restarted by writing a non-zero value to CCR0. In this scenario, the timer starts incrementing in the up direction from zero. Setting the CLR bit in TACTL register: Setting the CLR bit in the TACTL register clears the timer value and input clock divider value. The timer increments upward from zero with the next clock cycle as long as stop-mode is not selected with the MCx bits. TAR is loaded with 0: When the counter (TAR register) is loaded with zero with a software instruction the timer increments upward from zero with the next clock cycle as long as stop-mode is not selected with the MCx bits.
-
11.3 Timer Modes
11.3.1 Timer - Stop Mode
Stopping and starting the timer is done simply by changing the mode control bits (MCx). The value of the timer is not affected. When the timer is stopped from up/down mode and then restarted in up/down mode, the timer counts in the same direction as it was counting before it was stopped. For example, if the timer is in up/down mode and counting in the down direction when the MCx bits are reset, when they are set back to the up/down direction, the timer starts counting in the down direction from its previous value. If this is not desired in an application, the CLR bit in the TACTL register can be used to clear this direction memory feature.
11.3.2 Timer - Up Mode
The up mode is used if the timer period must be different from the 65,536 (16-bit) clock cycles of the continuous mode period. The capture/compare register CCR0 data define the timer period. The counter counts up to the content of compare register CCR0, as shown in Figure 11-5. When the timer value and the value of compare register CCR0 are equal (or if the timer value is greater than the CCR0 value), the timer restarts counting from zero.
11-6
Timer Modes
Figure 11-5. Timer Up Mode
0FFFFh CCR0
0h
Flag CCIFG0 is set when the timer equals the CCR0 value. The TAIFG flag is set when the timer counts from CCR0 to zero. All interrupt flags are set independently of the corresponding interrupt enable bit, but an interrupt is requested only if the corresponding interrupt enable bit and the GIE bit are set. Figure 11-6 shows the flag set cycle.
Figure 11-6. Up Mode Flag Setting
Timer Clock Timer Set Flag TAIFG Set Flag CCIFG0
CCR0-1 CCR0 0h 1h CCR0-1 CCR0 0h 1h
11.3.2.1 Timer in Up Mode - Changing the Period Register CCR0 Value
Changing the timer period register CCR0 while the timer is running can be a little tricky. When the new period is greater than or equal to the old period, the timer simply counts up to the new period and no special attention is required (see Figure 11-7). However, when the new period is less than the old period, the phase of the timer clock during the CCR0 update affects how the timer reacts to the new period. If the new, smaller period is written to CCR0 during a high phase of the timer clock, then the timer rolls to zero (or begins counting down when in the up/down mode) on the next rising edge of the timer clock. However, if the new, smaller period is written during a low phase of the timer clock, then the timer continues to increment with the old period for one more clock cycle before adopting the new period and rolling to zero (or beginning counting down). This is shown in Figure 11-8.
Timer_A
11-7
Timer Modes
Figure 11-7. New Period > Old Period
Timer Register 3 2 1 0 CCR0old = 2 CCR0new = 3
CCR0
2
Figure 11-8. New Period < Old Period
Timer Register 5 4 3 2 1 0
CCR0old = 5 CCR0new = 2
0 12 3 45 01 2 301 2 01 2 01 CCR0 5 2 CCR0
CCR0 Loaded With 2 During High Clock Phase Timer Clock Timer CCR0 CCRold n 0 or n-1 CCRnew
Load New CCR0 During High Phase of Clock
Up mode: 0; up/down mode: n-1
11-8
IIIII IIIII
0
1
2
0
1
2
3
0 3
1
2
3
0
1
Timer Register 5 4 3 2 1 0
CCR0old = 5 CCR0new = 2
012 3 45 012 3 401 201 201 5 2
CCR0 Loaded With 2 During Low Clock Phase
Timer Clock Timer CCR0 n CCRold n+1 CCRnew 0 or n
Load New CCR0 During Low Phase of Clock
Up mode: 0; up/down mode: n
Timer Modes
11.3.3 Timer - Continuous Mode
The continuous mode is used if the timer period of 65,536 clock cycles is used for the application. A typical application of the continuous mode is to generate multiple, independent timings. In continuous mode, the capture/compare register CCR0 works in the same way as the other compare registers. The capture/compare registers and different output modes of each output unit are useful to capture timer data based on external events or to generate various different types of output signals. Examples of the different output modes used with timer-continuous mode are shown in Figure 11-25. In continuous mode, the timer starts counting from its present value. The counter counts up to 0FFFFh and restarts by counting from zero as shown in Figure 11-9.
Figure 11-9. Timer Continuous Mode
0FFFFh
0h
The TAIFG flag is set when the timer counts from 0FFFFh to zero. The interrupt flag is set independently of the corresponding interrupt enable bit, as shown in Figure 11-10. An interrupt is requested if the corresponding interrupt enable bit and the GIE bit are set.
Figure 11-10.Continuous Mode Flag Setting
Timer Clock Timer Set Interrupt Flag TAIFG
FFFE FFFF 0h 1h FFFE FFFF 0h 1h
Timer_A
11-9
Timer Modes
11.3.3.1 Timer - Use of the Continuous Mode
The continuous mode can be used to generate time intervals for the application software. Each time an interval is completed, an interrupt can be generated. In the interrupt service routine of this event, the time until the next event is added to capture/compare register CCRx as shown in Figure 11-11. Up to five independent time events can be generated using all five capture/compare blocks.
Figure 11-11. Output Unit in Continuous Mode for Time Intervals
0FFFFh
CCR0f CCR0e CCR0d CCR0c CCR0b CCR0a CCR0h CCR0g CCR0m CCR0l CCR0k CCR0j CCR0i
0h
Interrupt Events
t
t
t
t
t
t
t
t
t
t
t
t
Time intervals can be produced with other modes as well, where CCR0 is used as the period register. Their handling is more complex since the sum of the old CCRx data and the new period can be higher than the CCR0 value. When the sum CCRxold plus t is greater than the CCR0 data, the CCR0 value must be subtracted to obtain the correct time interval. The period is twice the value in the CCR0 register.
11.3.4 Timer - Up/Down Mode
The up/down mode is used if the timer period must be different from the 65,536 clock cycles, and if symmetrical pulse waveform generation is needed. In up/down mode, the timer counts up to the content of compare register CCR0, then back down to zero, as shown in Figure 11-12. The period is twice the value in the CCR0 register.
Figure 11-12.Timer Up/Down Mode
CCR0
0h
11-10
Timer Modes
The up/down mode also supports applications that require dead times between output signals. For example, to avoid overload conditions, two outputs driving an H-bridge must never be in a high state simultaneously. In the following example (see Figure 11-13), the tdead is: tdead = ttimer x (CCR1 - CCR3)= With: tdead ttimer Time during which both outputs need to be inactive Cycle time of the timer clock
CCRx Content of capture/compare register x
Figure 11-13.Output Unit in Up/Down Mode (II)
0FFFFh CCR0 CCR1 CCR3 0h Dead Time Output Mode 6: PWM Toggle/Set Output Mode 2: PWM Toggle/Reset TAIFG EQU1 EQU1 TAIFG EQU1 EQU1 EQU3 EQU0 EQU3 EQU3 EQU0 EQU3 Interrupt Events
The count direction is always latched with a flip-flop (Figure 11-14). This is useful because it allows the user to stop the timer and then restart it in the same direction it was counting before it was stopped. For example, if the timer was counting down when the MCx bits were reset, then it will continue counting in the down direction if it is restarted in up/down mode. If this is not desired, the CLR bit in the TACTL register must be used to clear the direction. Note that the CLR bit affects other setup conditions of the timer. Refer to Section 11.6 for a discussion of the Timer_A registers.
Figure 11-14.Timer Up/Down Direction Control
POR CLR in TACTL
Up/Down Mode TAR => CCR0 Timer Clock
Set D Reset Q
Up/Down For 16-Bit Timer TAR Low: Down Direction High: Up Direction
Timer_A
11-11
Timer Modes
In up/down mode, the interrupt flags (CCIFG0 and TAIFG) are set at equal time intervals (Figure 11-15). Each flag is set only once during the period, but they are separated by 1/2 the timer period. CCIFG0 is set when the timer counts from CCR0-1 to CCR0, and TAIFG is set when the timer completes counting down from 0001h to 0000h. Each flag is capable of producing a CPU interrupt when enabled.
Figure 11-15.Up/Down Mode Flag Setting
Timer Clock Timer Up/Down Set CCIFG0 Set TAIFG
CCR0-1 CCR0 CCR0-1 CCR0-2 2h 1h 0h 1h
11.3.4.1 Timer In Up/Down Mode - Changing the Value of Period Register CCR0
Changing the period value while the timer is running in up/down mode is even trickier than in up mode. Like in up mode, the phase of the timer clock when CCR0 is changed affects the timer's behavior. Additionally, in up/down mode, the direction of the timer also affects the behavior. If the timer is counting in the up direction when the new period is written to CCR0, the conditions in the up/down mode are identical to those in the up mode. See Section 11.3.2.1 for details. However, if the timer is counting in the down direction when CCR0 is updated, it continues its descent until it reaches zero. The new period takes effect only after the counter finishes counting down to zero. See Figure 11-16.
Figure 11-16.Altering CCR0 - Timer in Up/Down Mode
Timer Register 5 4 3 2 1 0
0 123 4 5 432 1 01 234 3 2 1 012 3 21 012 1 0123 4 5 4 3 2 1 01 2 1 CCR0 5 2 4 2 5 2
11-12
Timer Modes
11.4 Capture/Compare Blocks
Five identical capture/compare blocks (shown in Figure 11-17) provide flexible control for real-time processing. Any one of the blocks may be used to capture the timer data at an applied event, or to generate time intervals. Each time a capture occurs or a time interval is completed, interrupts can be generated from the applicable capture/compare register. The mode bit CAPx, in control word CCTLx, selects the compare or capture operation and the capture mode bits CCMx1 and CCMx0 in control word CCTLx define the conditions under which the capture function is performed. Both the interrupt enable bit CCIEx and the interrupt flag CCIFGx are used for capture and compare modes. CCIEx enables the corresponding interrupt. CCIFGx is set on a capture or compare event. The capture inputs CCIxA and CCIxB are connected to external pins or internal signals. Different MSP430 devices may have different signals connected to CCIxA and CCIxB. The data sheet should always be consulted to determine the Timer_A connections for a particular device.
Figure 11-17.Capture/Compare Blocks
Overflow x Logic
CCISx1 CCISx0
COVx Timer Bus 15 0
CCIxA CCIxB GND VCC
0 1 2 3
CAPx Capture Mode Capture
Capture/Compare Register CCRx
CCMx1 CCMx0 0 0 1 1 0 1 0 1 Disabled Positive Edge Negative Edge Both Edges Comparator x EQUx CAPx 0 1 Set_CCIFGx
EN A Y
SCCIx
CCIx
Timer_A
11-13
Timer Modes
11.4.1 Capture/Compare Block - Capture Mode
The capture mode is selected if the mode bit CAPx, located in control word CCTLx, is set. The capture mode is used to fix time events. It can be used for speed computations or time measurements. The timer value is copied into the capture register (CCRx) with the selected edge (positive, negative, or both) of the input signal. Captures may also be initiated by software as described in section 11.4.1.1. If a capture is performed:
-
The interrupt flag CCIFGx, located in control word CCTLx, is set. An interrupt is requested if both interrupt enable bits CCIEx and GIE are set.
The input signal to the capture/compare block is selected using control bits CCISx1 and CCISx0, as shown in Figure 11-18. The input signal can be read at any time by the software by reading bit CCIx. The input signal may also be latched with compare signal EQUx (see SCCIx bit below) when in compare mode. This feature was designed specifically to support implementing serial communications with Timer_A. See section 11.7 for more details on using Timer_A as a UART.
Figure 11-18.Capture Logic Input Signal
CCISx1 CCISx0
CAPx CMPx Capture Mode Timer Clock Synchronize Capture EQUx 0 1 SCSx Capture 1 0 Set_CCIFGx
CCIxA CCIxB GND VCC
0 1 2 3
CCMx1 CCMx0 0 0 1 1 CCIx 0 1 0 1
Disabled Positive Edge Negative Edge Both Edges
EN A
Y
SCCIx
The capture signal can also be synchronized with the timer clock to avoid race conditions between the timer data and the capture signal. This is illustrated in Figure 11-19. The bit SCSx in capture/compare control register CCTLx selects the capture signal synchronization.
11-14
Timer Modes
Figure 11-19.Capture Signal
Timer Clock Timer CCIx Capture Set CCIFGx
n-2 n-1 n n+1 n+2 n+3 n+4 n+5 n+6
Applications with slow timer clocks can use the nonsynchronized capture signal. In this scenario the software can validate the data and correct it if necessary as shown in the following example:
; Software example for the handling of asynchronous ; capture signals ; ; The data of the capture/compare register CCRx are taken ; by the software in the according interrupt routine ; - they are taken only after a CCIFG was set. ; The timer clock is much slower than the system clock ; MCLK. ; CCRx_Int_hand ... ; Start of interrupt ; handler ... ... CMP &CCRx,&TAR ; Test if the data ; CCRX = TAR JEQ Data_Valid MOV &TAR,&CCRx ; The data in CCRx is ; wrong, use the timer data
Data_Valid ... ... ; The data in CCRx are valid
;
Overflow logic is provided with each capture/compare register to flag the user if a second capture is performed before data from the first capture was read successfully. Bit COVx in register CCTLx is set when this occurs as shown in Figure 11-20.
III III
... ... RETI
Timer_A
11-15
Timer Modes
Figure 11-20.Capture Cycle
Idle Capture Capture Read
No Capture Taken
Capture Taken
Capture
Read Taken Capture
Capture Read and No Capture
Capture
Clear Bit COV in Register CCTL Second Capture Taken COV = 1
Idle
Overflow bit COVx is reset by the software as described in the following example:
; Software example for the handling of captured data ; looking for overflow condition ; ; The data of the capture/compare register CCRx are taken ; by the software and immediately with the next ; instruction the overflow bit is tested and a decision is ; made to proceed regularly or with an error handler ; CCRx_Int_hand ... ; Start of handler Interrupt ... ... MOV &CCRx,RAM_Buffer BIT #COV,&CCTLx JNZ Overflow_Hand ... ... ... RETI Overflow_Hand BIC #COV,&CCTLx ; reset capture ; overflow flag ; get back to lost ; synchronization ... ... ; RETI
Note: Capture With Timer Halted The capture should be disabled when the timer is halted. The sequence to follow is: stop the capture, then stop the timer. When the capture function is restarted, the sequence should be: start the capture, then start the timer.
11-16
Timer Modes
11.4.1.1 Capture/Compare Block, Capture Mode - Capture Initiated by Software
In addition to internal and external signals, captures can be initiated by software. This is useful for various purposes, such as:
-
To measure time used by software routines To measure time between hardware events To measure the system frequency
Two bits, CCISx1 and CCISx0, and the capture mode selected by bits CCMx1 and CCMx0 are used by the software to initiate the capture. The simplest realization is when the capture mode is selected to capture on both edges of CCIx and bit CCISx1 is set. Software then toggles bit CCISx0 to switch the capture signal between VCC and GND, initiating a capture each time the input is toggled, as shown in Figure 11-21.
Figure 11-21.Software Capture Example
CCISx1 CCISx0 CCIx Capture
CCISx1 CCISx0
CCIxA CCIxB GND VCC
0 1 2 3
CMPx Capture Mode CCIx CCMx1 CCMx0
1 1
Capture
Both Edges Selected
The following is a software example of a capture performed by software:
; ; ; ; ; ; The data of capture/compare register CCRx are taken by the software. It is assumed that CCMx1, CCMx0, and CCISx1 bits are set. Bit CCIS0 selects the CCIx signal to be high or low.
... ... XOR ... ... ...
#CCISx0, &CCTLx
Timer_A
11-17
Timer Modes
11.4.2 Capture/Compare Block - Compare Mode
The compare mode is selected if the CAPx bit, located in control word CCTLx, is reset. In compare mode all the capture hardware circuitry is inactive and the capture-mode overflow logic is inactive. The compare mode is most often used to generate interrupts at specific time intervals or used in conjunction with the output unit to generate output signals such as PWM signals. If the timer becomes equal to the value in compare register x, then:
-
Interrupt flag CCIFGx, located in control word CCTLx, is set. An interrupt is requested if interrupt enable bits CCIEx and GIE are set. Signal EQUx is output to the output unit. This signal affects the output OUTx, depending on the selected output mode.
The EQU0 signal is true when the timer value is greater or equal to the CCR0 value. The EQU1 to EQU4 signals are true when the timer value is equal to the corresponding CCR1 to CCR4 values.
11-18
Timer Modes
11.5 The Output Unit
Each capture/compare block contains an output unit shown in Figure 11-22. The output unit is used to generate output signals such as PWM signals. Each output unit has 8 operating modes that can generate a variety of signals based on the EQU0 and EQUx signals. The output mode is selected with the OMx bits located in the CCTLx register.
Figure 11-22.Output Unit
OUTx
EQU0 EQUx
Output Control Block
D
Set Reset
OUTx Signal
Q
Timer Clock
POR OUTx OMx2 OMx1 OMx0
0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Output mode: OUTx signal reflects the value of the OUTx bit Set mode: OUT x signal reflects the value of signal EQUx PWM toggle/reset: EQUx toggles OUTx. EQU0 resets OUTx. PWM set/reset: EQUx sets OUTx. EQU0 resets OUTx Toggle: EQUx toggles OUTx signal. Reset: EQUx resets OUTx. PWM toggle/set: EQUx toggles OUTx. EQU0 sets OUTx. PWM reset/set: EQUx resets OUTx. EQUx sets OUTx. Note: OUTx signal updates with rising edge of timer clock for all modes except mode 0. Modes 2, 3, 6, 7 not useful for output unit 0.
Timer_A
11-19
Timer Modes
11.5.1 Output Unit - Output Modes
The output modes are defined by the OMx bits and are discussed below. The OUTx signal is changed with the rising edge of the timer clock for all modes except mode 0. Output modes 2, 3, 6, and 7 are not useful for output unit 0. Output mode 0: Output mode: The output signal OUTx is defined by the OUTx bit in control register CCTLx. The OUTx signal updates immediately upon completion of writing the bit information. Output mode 1: Set mode: The output is set when the timer value becomes equal to capture/compare data CCRx. It remains set until a reset of the timer, or until another output mode is selected. Output mode 2: PWM toggle/reset mode: The output is toggled when the timer value becomes equal to capture/compare data CCRx. It is reset when the timer value becomes equal to CCR0. Output mode 3: PWM set/reset mode: The output is set when the timer value becomes equal to capture/compare data CCRx. It is reset when the timer value becomes equal to CCR0. Output mode 4: Toggle mode: The output is toggled when the timer value becomes equal to capture/compare data CCRx. The output period is double the timer period. Output mode 5: Reset mode: The output is reset when the timer value becomes equal to capture/compare data CCRx. It remains reset until another output mode is selected. Output mode 6: PWM toggle/set mode: The output is toggled when the timer value becomes equal to capture/compare data CCRx. It is set when the timer value becomes equal to CCR0. Output mode 7: PWM toggle/set mode: The output is reset when the timer value becomes equal to capture/compare data CCRx. It is set when the timer value becomes equal to CCR0.
11-20
Timer Modes
11.5.2 Output Control Block
The output control block prepares the value of the OUTx signal, which is latched into the OUTx flip-flop with the next positive timer clock edge, as shown in Figure 11-23 and Table 11-2. The equal signals EQUx and EQU0 are sampled during the negative level of the timer clock, as shown in Figure 11-23.
Figure 11-23.Output Control Block
OUTx
EQU0 EQUx
Output Control Block
D
Set Reset
OUTx Signal
Q
Timer Clock
POR OUTx OMx2 OMx1 OMx0
The timer is Incremented with the rising edge of the timer clock. Timer Clock
Timer TAR
n-2
n-1 TAR = n
n
n+1
FFFF or CCR0
0
1
EQUx
CCRx = n
EQU0
TAR = 0 or TAR = CCR0
EQU0, Delayed Used in Up Mode Only
EQU0 delayed is used in up mode, not EQU0. EQU0 is active high when TAR = CCR0. EQU0 delayed is active high when TAR = 0.
Timer_A
11-21
Timer Modes
Table 11-2. State of OUTx at Next Rising Edge of Timer Clock
Mode 0 1 2 EQU0 x x x 0 0 1 1 0 0 1 1 x x x x 0 0 1 1 0 0 1 1 EQUx x 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 D x(OUTx bit) OUTx (no change) 1 (set) OUTx (no change) OUTx (toggle) 0 (reset) 1 (set) OUTx (no change) 1 (set) 0 (reset) 1 (set) OUTx (no change) OUTx (toggle) OUTx (no change) 0 (reset) OUTx (no change) OUTx (toggle) 1 (set) 0 (reset) OUTx (no change) 0 (reset) 1 (set) 0 (reset)
3
4 5 6
7
11.5.3 Output Examples
The following are some examples of possible output signals using the various timer and output modes.
11.5.3.1 Output Examples - Timer in Up Mode
The OUTx signal is changed when the timer counts up to the CCRx value, and rolls from CCR0 to zero, depending on the output mode, as shown in Figure 11-24.
11-22
Timer Modes
Figure 11-24.Output Examples - Timer in Up Mode
0FFFFh CCR0 CCR1 Example, EQU1 Used
0h Output Mode 1: Set Output Mode 2: PWM Toggle/Reset Output Mode 3: PWM Set/Reset Output Mode 4: Toggle Output Mode 5: Reset Output Mode 6: PWM Toggle/Set Output Mode 7: PWM Reset/Set EQU0 EQU1 EQU0 EQU1 EQU0 Interrupt Events
11.5.3.2 Output Examples - Timer in Continuous Mode
The OUTx signal is changed when the timer reaches the CCRx and CCR0 values, depending on the output mode, as shown in Figure 11-25.
Figure 11-25.Output Examples - Timer in Continuous Mode
0FFFFh CCR0 CCR1
0h
Output Mode 1: Set Output Mode 2: PWM Toggle/Reset Output Mode 3: PWM Set/Reset Output Mode 4: Toggle Output Mode 5: Reset Output Mode 6: PWM Toggle/Set Output Mode 7: PWM Reset/Set TAOV EQU1 EQU0 TAOV EQU1 EQU0 Interrupt Events
Timer_A
11-23
Timer Modes
11.5.3.3
Output Examples - Timer in Up/Down Mode
The OUTx signal changes when the timer equals CCRx in either count direction and when the timer equals CCR0, depending on the output mode, as shown in Figure 11-26.
Figure 11-26.Output Examples - Timer in Up/Down Mode (I)
0FFFFh CCR0
CCR3 0h Output Mode 1: Set Output Mode 2: PWM Toggle/Reset Output Mode 3: PWM Set/Reset Output Mode 4: Toggle Output Mode 5: Reset Output Mode 6: PWM Toggle/Set Output Mode 7: PWM Reset/Set TIMOV EQU3 EQU0 EQU3 TIMOV EQU3 EQU0 EQU3 Interrupt Events
11-24
Timer_A Registers
11.6 Timer_A Registers
The Timer_A registers, described in Table 11-3, are word-structured and must be accessed using word instructions.
Table 11-3. Timer_A Registers
Register Timer_A control Timer_A register Cap/com control 0 Capture/compare 0 Cap/com control 1 Capture/compare 1 Cap/com control 2 Capture/compare 2 Cap/com control 3 Capture/compare 3 Cap/com control 4 Capture/compare 4 Interrupt vector Short Form TACTL TAR CCTL0 CCR0 CCTL1 CCR1 CCTL 2 CCR2 CCTL3 CCR3 CCTL4 CCR4 TAIV Register Type Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read Address 160h 170h 162h 172h 164h 174h 166h 176h 168h 178h 16Ah 17Ah 12Eh Initial State POR reset POR reset POR reset POR reset POR reset POR reset POR reset POR reset POR reset POR reset POR reset POR reset (POR reset)
11.6.1 Timer_A Control Register TACTL
The timer and timer operation control bits are located in the timer control register (TACTL) shown in Figure 11-27. All control bits are reset automati- cally by the POR signal, but are not affected by the PUC signal. The control register must be accessed using word instructions.
Figure 11-27.Timer_A Control Register TACTL
15 TACTL 160h rw(0) rw(0)
Unused Input Select Input Divider Mode Control
0
UnCLR TAIE TAIFG used
rw(0)
rw(0)
rw(0)
rw(0)
rw(0)
rw(0)
rw(0)
rw(0)
rw(0)
rw (0)
rw(0)
w(0)
rw(0)
rw(0)
Bit 0:
TAIFG: This flag indicates a timer overflow event. Up mode: TAIFG is set if the timer counts from CCR0 value to 0000h. Continuous mode: TAIFG is set if the timer counts from 0FFFFh to 0000h. Up/down mode: TAIFG is set if the timer counts down from 0001h to 0000h. Timer overflow interrupt enable (TAIE) bit. An interrupt request from the timer overflow bit is enabled if this bit is set, and is disabled if reset.
Bit 1:
Timer_A
11-25
Timer_A Registers
Bit 2:
Timer clear (CLR) bit. The timer and input divider are reset with the POR signal, or if bit CLR is set. The CLR bit is automatically reset and is always read as zero. The timer starts in the upward direction with the next valid clock edge, unless halted by cleared mode control bits. Not used
Bit 3:
Bits 4, 5: Mode control: Table 11-4 describes the mode control bits.
Table 11-4. Mode Control
MC1 0 0 1 1 MC0 0 1 0 1 Count Mode Stop Up to CCR0 Continuous up Up/down Description Timer is halted. Timer counts up to CCR0 and restarts at 0. Timer counts up to 0FFFFh and restarts at 0. Timer continuously counts up to CCR0 and back down to 0.
Bits 6, 7: Input divider control bits. Table 11-5 describes the input divider control bits.
Table 11-5. Input Clock Divider Control Bits
ID1 0 0 1 1 ID0 0 1 0 1 Operation /1 /2 /4 /8 Description Input clock source is passed to the timer. Input clock source is divided by two. Input clock source is divided by four. Input clock source is divided by eight.
Bits 8, 9: Clock source selection bits. Table 11-6 describes the clock source selections.
Table 11-6. Clock Source Selection
SSEL1 0 0 1 1 SSEL0 0 1 0 1 O/P Signal TACLK ACLK MCLK INCLK Comment See data sheet device description Auxiliary clock ACLK is used System clock MCLK See device description in data sheet
Bits 10 to 15:
Unused
11-26
Timer_A Registers
Note: Changing Timer_A Control Bits If the timer operation is modified by the control bits in the TACTL register, the timer should be halted during this modification. Critical modifications are the input select bits, input divider bits, and the timer clear bit. Asynchronous clocks, input clock, and system clock can result in race conditions where the timer reacts unpredictably. The recommended instruction flow is: 1) Modify the control register and stop the timer. 2) Start the timer operation. For example: MOV #01C6,&TACTL BIS #10h,&TACTL ; ACLK/8, timer stopped, timer cleared ; Start timer with up mode
11.6.2 Timer_A Register TAR
The TAR register is the value of the timer.
Figure 11-28.TAR Register
15 TAR 170h
Timer Value
0
rw-(0) rw-(0) rw-(0) rw-(0)rw-(0) rw-(0) rw-(0)rw-(0)rw-(0)rw-(0)rw-(0) rw-(0) rw-(0)rw-(0)rw-(0) rw-(0)
Note: Modifying Timer A Register TAR When ACLK or the external clock TACLK or INCLK is selected for the timer clock, any write to timer register TAR should occur while the timer is not operating; otherwise, the results may be unpredictable. In this case, the timer clock is asynchronous to the CPU clock MCLK and critical race conditions exist.
11.6.3 Capture/Compare Control Register CCTLx
Each capture/compare block has its own control word CCTLx, shown in Figure 11-29. The POR signal resets all bits of CCTLx; the PUC signal does not affect these bits.
Figure 11-29.Capture/Compare Control Register CCTLx
15 CCTLx 162h to 16Ah
Capture Mode Input Select SCS SCCI Unused CAP OUTMODx CCIE CCI
0
OUT COV CCIFG
rw-(0) rw-(0) rw-(0) rw-(0)rw-(0) rw-(0) r-(0) rw-(0)rw-(0)rw-(0)rw-(0) rw-(0)
r
rw-(0)rw-(0) rw-(0)
Timer_A
11-27
Timer_A Registers
Bit 0:
Capture/compare interrupt flag CCIFGx Capture mode: If set, it indicates that a timer value was captured in the CCRx register. Compare mode: If set, it indicates that a timer value was equal to the data in the CCRx register. CCIFG0 flag: CCIFG0 is automatically reset when the interrupt request is accepted. CCIFG1 to CCIFG4 flags: The flag that caused the interrupt is automatically reset after the TAIV word is accessed. If the TAIV register is not accessed, the flags must be reset with software. No interrupt is generated if the corresponding interrupt enable bit is reset, but the flag will be set. In this scenario, the flag must be reset by the software. Setting the CCIFGx flag with software will request an interrupt if the interrupt-enable bit is set.
Bit 1:
Capture overflow flag COV Compare mode selected, CAP = 0: Capture signal generation is reset. No compare event will set COV bit. Capture mode selected, CAP = 1: The overflow flag COV is set if a second capture is performed before the first capture value is read. The overflow flag must be reset with software. It is not reset by reading the capture value. The OUTx bit determines the value of the OUTx signal if the output mode is 0. Capture/compare input signal CCIx: The selected input signal (CCIxA, CCIxB, VCC. or GND) can be read by this bit. See Figure 11-18. Interrupt enable CCIEx: Enables or disables the interrupt request signal of capture/compare block x. Note that the GIE bit must also be set to enable the interrupt. 0: Interrupt disabled 1: Interrupt enabled Output mode select bits: Table 11-7 describes the output mode selections.
Bit 2:
Bit 3:
Bit 4:
Bits 5 to 7:
11-28
Timer_A Registers
Table 11-7. Capture/Compare Control Register Output Mode
Bit Value 0 1 2 3 4 5 6 7
Note:
Output Mode Output only Set PWM toggle/reset PWM set/reset Toggle Reset PWM toggle/set PWM reset/set
Description The OUTx signal reflects the value of the OUTx bit EQUx sets OUTx EQUx toggles OUTx. EQU0 resets OUTx. EQUx sets OUTx. EQU0 resets OUTx EQUx toggles OUTx signal. EQUx resets OUTx. EQUx toggles OUTx. EQU0 sets OUTx. EQUx resets OUTx. EQUx sets OUTx.
OUTx updates with rising edge of timer clock for all modes except mode 0. Modes 2, 3, 6, 7 not useful for output unit 0.
Bit 8:
CAP sets capture or compare mode. 0: Compare mode 1: Capture mode Read only, always read as 0. SCCIx bit: The selected input signal (CCIxA, CCIxB, VCC, or GND) is latched with the EQUx signal into a transparent latch and can be read via this bit. SCSx bit: This bit is used to synchronize the capture input signal with the timer clock. 0: asynchronous capture 1: synchronous capture
Bit 9: Bit 10:
Bit 11:
Bits 12, 13: Input select, CCIS0 and CCIS1: These two bits define the capture signal source. These bits are not used in compare mode. 0 Input CCIxA is selected 1 Input CCIxB is selected 2 GND 3 VCC Bits 14, 15: Capture mode bits: Table 11-8 describes the capture mode selections.
Table 11-8. Capture/Compare Control Register Capture Mode
Bit Value 0 1 2 3 Capture Mode Disabled Pos. Edge Neg. Edge Both Edges Description The capture mode is disabled. Capture is done with rising edge. Capture is done with falling edge. Capture is done with both rising and falling edges.
Timer_A
11-29
Timer_A Registers
Note: Simultaneous Capture and Capture Mode Selection Captures must not be performed simultaneously with switching from compare to capture mode. Otherwise, the result in the capture/compare register will be unpredictable. The recommended instruction flow is: 1) Modify the control register to switch from compare to capture. 2) Capture For example: BIS #CAP,&CCTL2 XOR #CCIS1,&CCTL2 ; Select capture with register CCR2 ; Software capture: ; CCIS0 = 0 Capture mode = 3
11.6.4 Timer_A Interrupt Vector Register
Two interrupt vectors are associated with the 16-bit Timer_A module:
-
CCR0 interrupt vector (highest priority) TAIV interrupt vector for flags CCIFG1-CCIFGx and TAIFG.
11.6.4.1 CCR0 Interrupt Vector
The interrupt flag associated with capture/compare register CCR0, as shown in Figure 11-30, is set if the timer value is equal to the compare register value.
Figure 11-30.Capture/Compare Interrupt Flag
Capture
CCIE0
EQ0 CCR0 = Timer CAP Timer Clock
IRQ, Interrupt_Service_Requested
D
Set
Q
Reset
IRACC, Interrupt_Request_Accepted
Capture/compare register 0 has the highest Timer_A interrupt priority, and uses its own interrupt vector.
11-30
Timer_A Registers
11.6.4.2 Vector Word, TAIFG, CCIFG1 to CCIFG4 Flags
The CCIFGx (other than CCIFG0) and TAIFG interrupt flags are prioritized and combined to source a single interrupt as shown in Figure 11-31. The interrupt vector register TAIV (shown in Figure 11-32) is used to determine which flag requested an interrupt.
Figure 11-31.Schematic of Capture/Compare Interrupt Vector Word
CCI1 EQ1 CMP1 Timer Clock
S S Sel CCIFG1
CCIE1
R
IRACC
CCI2 EQ2 CMP2 Timer Clock
S S Sel
CCIFG2
CCIE2
R
IRACC Interrupt_Service_Request CCIFG3 Priority and Vector Word Generator Interrupt_Vector_Address CCIFG4
CCI3 EQ3 CMP3 Timer Clock
S S Sel
CCIE3
R
IRACC
CCI4 EQ4 CMP4 Timer Clock
S S Sel
CCIE4
R
IRACC
Timer FFFF Timer = CCR0 XXX Timer Clock
S S Sel
TAIFG
TAIE
R
IRACC
Figure 11-32.Vector Word Register
15 TAIV 12Eh r0
0 0 0 0 0 0 0 0 0 0 0 0 Interrupt Vector
0
0
r0
r0
r0
r0
r0
r0
r0
r0
r0
r0
r0
r-(0) r-(0) r-(0) r0
The flag with the highest priority generates a number from 2 to 12 in the TAIV register as shown in Table 11-9. (If the value of the TAIV register is 0, no interrupt is pending.) This number can be added to the program counter to automatically enter the appropriate software routine without the need for reading and evaluating the interrupt vector. The software example in section 11.6.4.3 shows this technique.
Timer_A
11-31
Timer_A Registers
Table 11-9. Vector Register TAIV Description
Interrupt Priority Highest Interrupt Source Capture/compare 1 Capture/compare 2 Capture/compare 3 Capture/compare 4 Timer overflow Reserved Lowest Reserved No interrupt pending Short Form CCIFG1 CCIFG2 CCIFG3 CCIFG4 TAIFG Vector Register TAIV Contents 2 4 6 8 10 12 14 0
Highest pending interrupt other than CCIFG0. CCIFG0 is always the highest priority Timer_A interrupt.
Accessing the TAIV register automatically resets the highest pending interrupt flag. If another interrupt flag is set, then another interrupt will be immediately generated after servicing the initial interrupt. For example, if both CCIFG2 and CCIFG3 are set, when the interrupt service routine accesses the TAIV register (either by reading it or by adding it directly to the PC), CCIFG2 will be reset automatically. After the RETI instruction of the interrupt service routine is executed, the CCIFG3 flag will generate another interrupt. Note: Writing to Read-Only Register TAIV Register TAIV should not be written to. If a write operation to TAIV is performed, the interrupt flag of the highest-pending interrupt is reset. Therefore, the requesting interrupt event is missed. Additionally, writing to this read-only register results in increased current consumption as long as the write operation is active.
11.6.4.3 Timer Interrupt Vector Register, Software Example
The following software example describes the use of vector word TAIV and the handling overhead. The numbers at the right margin show the necessary cycles for every instruction. The example is written for continuous mode: the time difference to the next interrupt is added to the corresponding compare register.
; Software example for the interrupt part Cycles ; ; Interrupt handler for Capture/Compare Module 0. ; The interrupt flag CCIFG0 is reset automatically ; TIMMOD0 ... ; Start of handler Interrupt latency 6 RETI 5 ; ; Interrupt handler for Capture/Compare Modules 1 to 4. ; The interrupt flags CCIFGx and TAIFG are reset by ; hardware. Only the flag with the highest priority ; responsible for the interrupt vector word is reset. TIM_HND $ ; Interrupt latency 6 ADD &TAIV,PC ; Add offset to Jump table 3 RETI ; Vector 0: No interrupt 5 JMP TIMMOD1 ; Vector 2: Module 1 2
11-32
Timer_A Registers
JMP JMP JMP
TIMMOD2 TIMMOD3 TIMMOD4
; Vector 4: Module 2 ; Vector 6: Module 3 ; Vector 8: Module 4
2 2 2
; ; Module 5. Timer Overflow Handler: the Timer Register is ; expanded into the RAM location TIMEXT (MSBs) ; TIMOVH ; Vector 10: TIMOV Flag INC TIMEXT ; Handle Timer Overflow 4 RETI 5 ; TIMMOD2 ; Vector 4: Module 2 ADD #NN,&CCR2 ; Add time difference 5 ... ; Task starts here RETI ; Back to main program 5 ; ; TIMMOD1 ; Vector 2: Module 1 ADD #MM,&CCR1 ; Add time difference 5 ... ; Task starts here RETI ; Back to main program 5 ; If all five CCR registers are not implemented on a ; device, the interrupt vectors for the register that are ; present must still be handled. TIMMOD4 RETI ; Simply return 5 ; The Module 3 handler shows a way to look if any other ; interrupt is pending: 5 cycles have to be spent, but ; 9 cycles may be saved if another interrupt is pending ; TIMMOD3 ; Vector 6: Module 3 ADD #PP,&CCR3 ; Add time difference 5 ... ; Task starts here JMP TIM_HND ; Look for pending interrupts 2 ; .SECT "VECTORS",0FFF0h ; Interrupt Vectors ; The vector address may be different for different ; devices. ; .WORD TIM_HND ; Vector for Capture/Compare ; Module 1..4 and timer overflow ; TAIFG .WORD TIMMOD0 ; Vector for Capture/Compare ; Module 0
If the FLL is turned off, then two additional cycles need to be added for a synchronous start of the CPU and system clock MCLK. The software overhead for different interrupt sources includes interrupt latency and return-from-interrupt cycles (but not the task handling itself), as described:
-
Capture/compare block CCR0 Capture/compare blocks CCR1 to CCR4 Timer overflow TAIFG
11 cycles 16 cycles 14 cycles
Timer_A
11-33
Timer_A UART
11.6.4.4 Timing Limits
With the TAIV register and the previous software, the shortest repetitive time distance tCRmin between two events using a compare register is: tCRmin = ttaskmax + 16 x tcycle With: ttaskmax Maximum (worst case) time to perform the task during the interrupt routine (for example, incrementing a counter) tcycle Cycle time of the system frequency MCLK
The shortest repetitive time distance tCLmin between two events using a capture register is: tCLmin = ttaskmax + 16 x tcycle
11.7 Timer_A UART
The Timer_A is uniquely capable of implementing a UART function, with the following features:
-
Automatic start-bit detection - even from ultralow-power modes Hardware baud-rate generation Hardware latching of RXD and TXD data Baud rates of 75 to 115,200 baud Full-duplex operation
This UART implementation is different from other microcontroller implementations where a UART may be implemented with general-purpose I/O and manual bit manipulation via software polling. Those implementations require great CPU overhead and therefore increase power consumption and decrease the usability of the CPU. The transmit feature uses one compare function to shift data through the output unit to the selected pin. The baud rate is ensured by reconfiguring the compare data with each interrupt. The receive feature uses one capture/compare function to shift pin data into memory through bit SCCIx. The receive start time is recognized by capturing the timer data with the negative edge of the input signal. The same capture/compare block is then switched to compare mode and the receive bits are latched automatically with the EQUx signal. The interrupt routine collects the bits for later software processing. Figure 11-33 illustrates the UART implementation.
11-34
Timer_A UART
Figure 11-33.UART Implementation
Overflow x Logic CCISx1 CCISx0 CCIxA CCIxB GND VCC 0 1 2 3 CCMx1 0 0 1 1 CCMx0 0 1 0 1 Disabled Positive Edge Negative Edge Both Edges Comparator x CAPx 15 Capture Mode Capture Capture/Compare Register CCRx 0 COVx Timer Bus
CAPx EQUx 0 1 Set_CCIFGx Receive Data Path EN A CCIx Y SCCIx
D Timer Clock
Set Reset
OUTx Signal Q
Transmit Data Path OMx2 OMx1 OMx0 0 1 0 0 1 Set, EQUx set OUTx signal clock synchronized with timer clock 1 Reset, EQUx resets OUTx signal clock synchronized with timer clock
Timer_A
11-35
Timer_A UART
One capture/compare block is used when half-duplex communication mode is desired. Two capture/compare blocks are used for full-duplex mode. Figure 11-34 illustrates the capture/compare timing for the UART.
Figure 11-34.Timer_A UART Timing
URXD Signal Capture Compare Receive Capture Compare Compare Compare Compare UTXD Signal Transmit Compare Compare Compare Compare Compare Compare Compare Compare Compare Compare Compare
A complete application note including connection diagrams and complete software listing may be found at www.ti.com/sc/msp430.
11-36
Chapter 12
USART Peripheral Interface, UART Mode
The universal synchronous/asynchronous receive/transmit (USART) serialcommunication peripheral supports two serial modes with one hardware configuration. These modes shift a serial bit stream in and out of the MSP430 at a programmed rate or at a rate defined by an external clock. The first mode is the universal asynchronous receive/transmit (UART) communication protocol; the second is the serial peripheral interface (SPI) protocol (discussed in Chapter 13). Bit SYNC in control register UCTL selects the required mode: SYNC = 0: UART - asynchronous mode selected SYNC = 1: SPI - synchronous mode selected This chapter addresses the UART mode.
Topic
Page
12.1 USART Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2 12.2 USART Peripheral Interface, UART Mode . . . . . . . . . . . . . . . . . . . . . . 12-3 12.3 Asynchronous Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4 12.4 Interrupt and Enable Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-11 12.5 Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-15 12.6 Utilizing Features of Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . 12-23 12.7 Baud Rate Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-26
USART Peripheral Interface, UART Mode
12-1
USART Peripheral Interface
12.1 USART Peripheral Interface
The USART peripheral interface connects to the CPU as a byte peripheral module. It connects the MSP430 to the external system environment with three or four external pins. Figure 12-1 shows the USART peripheral interface module.
Figure 12-1. Block Diagram of USART
Receive Status Receive Buffer URXBUF SYNC RXE
Listen 0 1
MM 1 0
SYNC SOMI SYNC 0 STE
Receive Shift Register SSEL1 SSEL0 UCLKI ACLK MCLK MCLK 0 1 2 3 Baud Rate Generator URXD
SYNC
Baud Rate Register UBR SYNC UCLKS 1 0 UTXD
Baud Rate Generator
WUT
Transmit Shift Register
SIMO
TXWake
Transmit Buffer UTXBUF
CKPH
SYNC
CKPL UCLK
UCLKI UCLKS
Clock Phase and Polarity
12-2
USART Peripheral Interface, UART Mode
12.2 USART Peripheral Interface, UART Mode
The USART peripheral interface is a serial channel that shifts a serial bit stream of 7 or 8 bits in and out of the MSP430. The UART mode is chosen when control bit SYNC in the USART control register (UCTL) is reset.
12.2.1 UART Serial Asynchronous Communication Features
Some of the UART features include:
-
Asynchronous formats that include idle line/address bit-communication protocols Two shift registers that shift a serial data stream into URXD and out of UTXD Data that is transmitted/received with the LSB first Programmable transmit and receive bit rates Status flags
Figure 12-2 shows the USART in UART mode.
Figure 12-2. Block Diagram of USART - UART Mode
Receive Status Receive Buffer URXBUF RXE SYNC = 0 URXD
Listen 0 1
Receive Shift Register SSEL1 SSEL0 UCLKI ACLK MCLK MCLK 0 1 2 3 Baud Rate Generator UCLKS
Baud Rate Register UBR
Baud Rate Generator
WUT
Transmit Shift Register
LSB First UTXD
TXWake
Transmit Buffer UTXBUF
CKPL Clock Polarity UCLK
UCLKI UCLKS
USART Peripheral Interface, UART Mode
12-3
Asynchronous Operation
12.3 Asynchronous Operation
In the asynchronous mode, the receiver synchronizes itself to frames but the external transmitting and receiving devices do not use the same clock source; the baud rate is generated locally.
12.3.1 Asynchronous Frame Format
The asynchronous frame format, shown in Figure 12-3, consists of a start bit, seven or eight data bits, an even/odd/no parity bit, an address bit in address bit mode, and one or two stop bits. The bit period is defined by the selected clock source and the data in the baud rate registers.
Figure 12-3. Asynchronous Frame Format
ST D0 D6 D7 AD PA SP SP Mark Space [2nd Stop Bit, SP = 1] [Parity Bit, PENA = 1] [Address Bit, MM = 1] [Optional Bit, Condition] [8th Data Bit, CHAR = 1]
The receive (RX) operation is initiated by the receipt of a valid start bit. It begins with a negative edge at URXD, followed by the taking of a majority vote from three samples where two of the samples must be zero. These samples occur at n/2-X, n/2, and n/2+X of the BRCLK periods following the negative edge. This sequence provides false start-bit rejection, and also locates the center of the bits in the frame, where the bits can be read on a majority basis. The timing of X is 1/32 to 1/63 times that of the BRCLK, depending on the division rate of the baud rate generator and provides complete coverage of at least two BRCLK periods. Figure 12-4 shows an asynchronous bit format.
Figure 12-4. Asynchronous Bit Format. Example for n or n + 1 Clock Periods
Falling Edge on UEXD Indicates Start bit 1 2 3 Majority Vote Taken From URXD Data Line n/2-x n/2 n/2+x n-1 n-1 n 1 n n+1 2 1 3 2
H BRCLK L H UTXD L
Data Bit Period = n or n+1 BRCLK Periods URXD H L Data Bit Period = n or n+1 BRCLK Periods
12-4
Asynchronous Operation
12.3.2 Baud Rate Generation in Asynchronous Communication Format
Baud rate generation in the MSP430 differs from other standard serial-communication interface implementations.
12.3.2.1 Typical Baud Rate Generation
Typical baud-rate generation uses a prescaler from any clock source and a fixed, second-clock divider that is usually divide-by-16. Figure 12-5 shows a typical baud-rate generation.
Figure 12-5. Typical Baud-Rate Generation Other Than MSP430
0 Select Clock Source Clock1 BRCLK UBR0 8 70 UBR1 8 15 RC BRSCLK :16 BITCLK 7 Start
16-Bit Prescaler/Divider
Clockn Start BRSCLK H L H L 1 2 3 4 5 6 7
8
9
10 11
12 13
14 15
16
1
Take Majority Vote of Receive Bit H BITCLK L
Baud rate = BRCLK n 16 Typical baud-rate schemes often require specific crystal frequencies or cannot generate some baud rates required by some applications. For example, division factors of 18 are not possible, nor are noninteger factors such as 13.67.
12.3.2.2 MSP430 Baud Rate Generation
The MSP430 baud rate generator uses one prescaler/divider and a modulator as shown in Figure 12-6. This combination works with crystals whose frequencies are not multiples of the standard baud rates, allowing the protocol to run at maximum baud rate with a watch crystal (32,768 Hz). This technique results in power advantages because sophisticated, MSP430 low-power operations are possible.
USART Peripheral Interface, UART Mode
12-5
Asynchronous Operation
Figure 12-6. MSP430 Baud Rate Generation. Example for n or n + 1 Clock Periods
SSEL1 SSEL0 UCLKI ACLK MCLK MCLK 0 1 2 3 BRCLK 0 UBR0 1 7 7 0 UBR1 8 15 7 Start
15-Bit Prescaler/Divider Q1 Compare 0 or 1 Q15 Toggle FF
BITCLK
Shift Modulation Register Data m Shift_out Shift_in 7 Modulation Register UMOD H L H BRCLK L Counter Start
0
n/2 n/2-1 n/2-2
1 1 1
0 n/2 n/2
n/2 n/2-1 n/2-1 n/2-2 n/2-1 n/2-2
2 1 1
n/2 0 1 n/2 n/2-1 0 n/2 n/2-1 n/2-2
H BITCLK L INT(n/2), m = 0 INT(n/2)+m(=1) Divide By n(Even), m = 0 n(Odd) or n(Even)+m(=1) n(Odd)+m(=1)
The modulation register LSB is first used for modulation, which begins with the start bit. A set modulation bit increases the division factor by one.
Example 12-1. 4800 Baud
Assuming a clock frequency of 32,768 Hz for the BRCLK signal and a required baud rate of 4800, the division factor is 6.83. The baud rate generation in the MSP430 USART uses a factor of six plus a modulation register load of 6Fh (0110 1111). The divider runs the following sequence: 7 - 7 - 7 - 7 - 6 - 7 - 7 - 6 and so on. The sequence repeats after all eight bits of the modulator are used.
Example 12-2. 19,200 Baud
Assuming a clock frequency of 1.04 MHz (32 x 32,768 Hz) for the BRCLK signal and a required baud rate of 19,200, the division factor is 54.61. The baud rate generation in the MSP430 USART uses a factor of 54 (36h) plus a modulation register load of 0D5h. The divider runs the following sequence: 55 - 54 - 55 - 54 - 55 - 54 - 55 - 55, and so on. The sequence repeats after all eight bits of the modulator are used.
12-6
Asynchronous Operation
12.3.3 Asynchronous Communication Formats
The USART module supports two multiprocessor communication formats when asynchronous mode is used. These formats can transfer information between many microcomputers on the same serial link. Information is transferred as a block of frames from a particular source to one or more destinations. The USART has features that identify the start of blocks and suppress interrupts and status information from the receiver until a block start is identified. In both multiprocessor formats, the sequence of data exchanged with the USART module is based on data polling, or on the use of the receive interrupt features. Both of the asynchronous multiprocessor formats--idle-line and address-bit --allow efficient data transfer between multiple communication systems. They can also minimize the activity of the system to save current consumption or processing resources. The control register bit MM defines the address bit or idle-line multiprocessor format. Both use the wake-up-on-transfer mode by activating the TXWake bit (address feature function) and RXWake bit. The URXWIE and URXIE bits control the transmit and receive features of these asynchronous communication formats.
12.3.4 Idle-Line Multiprocessor Format
In the idle-line multiprocessor format, shown in Figure 12-7, blocks of data are separated by an idle time. An idle-receive line is detected when ten or more 1s in a row are received after the first stop bit of a character.
Figure 12-7. Idle-Line Multiprocessor Format
Block of Frames
UTXD/URXD
Idle Periods of 10 Bits or More UTXD/URXD Expanded
UTXD/URXD
ST
Address
SP ST
Data
SP
ST
Data
SP
First Frame Within Block is Address. It Follows Idle Period of 10 Bits or More
Frame Within Block
Frame Within Block
Idle Period Less Than 10 Bits
USART Peripheral Interface, UART Mode
12-7
Asynchronous Operation
When two stop bits are used for the idle line, as shown in Figure 12-8, the second one is counted as the first mark bit of the idle period. The first character received after an idle period is an address character. The RXWake bit can be used as an address tag for the character. In the idle-line multiprocessor format, the RXWake bit is set when a received character is an address character and is transferred into the receive buffer.
Figure 12-8. USART Receiver Idle Detect
Example: One Stop Bit Mark XXXX Space SP ST XXXXXXX 10-Bit Idle Period
Example: Two Stop Bits Mark XXXX Space SP: Stop Bit ST: Start Bit SP SP
10-Bit Idle Period ST XXXXXXX
Normally, if the USART URXWIE bit is set in the receive control register, characters are assembled as usual by the receiver. They are not, however, transferred to the receiver buffer, URXBUF, nor are interrupts generated. When an address character is received, the receiver is temporarily activated to transfer the character to URXBUF and to set the URXIFG interrupt flag. Applicable error status flags are set. The application software can validate the received address. If there is a match, the application software further processes the data and executes the operation. If there is no match, the processor waits for the next address character to arrive. The URXWIE bit is not modified by the USART: it must be modified manually to receive nonaddress or address characters. In idle-line multiprocessor format, a precise idle period can be generated to create efficient address character identifiers. The wake-up temporary (WUT) flag is an internal flag and is double-buffered with TXWake. When the transmitter is loaded from UTXBUF, WUT is loaded from TXWake, and the TXWake bit is reset as shown in Figure 12-9.
Figure 12-9. Double-Buffered WUT and TX Shift Register
TXWake TX Buffer UTXBUF Start Bit WUT TX Shift Register Parity Bit TX Signal
12-8
Asynchronous Operation
The following procedure sends out an idle frame to identify an address character: 1) Set the TXWake bit and then write any word (don't care) to the UTXBUF (UTXIFG must be set). When the transmitter shift register is empty, the contents of UTXBUF are shifted to the transmit shift register and the TXWake value is shifted to WUT. 2) Set bit WUT, which suppresses the start, data, and parity bits and transmits an idle period of exactly 11 bits, as shown in Figure 12-10. The next data word, shifted out of the serial port after the addresscharacter identifying idle period, is the second word written to the UTXBUF after the TXWake bit has been set. The first data word written is suppressed while the address identifier is sent out and ignored thereafter. Writing the first don't care word to UTXBUF is necessary to shift the TXWAKE bit to WUT and generate an idle-line condition.
Figure 12-10. USART Transmitter Idle Generation
Example: One Stop Bit Mark XXXX Space Example: Two Stop Bits Mark XXXX Space SP: Stop Bit ST: Start Bit SP SP ST XXXXXXX 11-Bit Idle Period SP ST XXXXXXX 11-Bit Idle Period
12.3.5 Address-Bit Multiprocessor Format
In the address-bit multiprocessor format shown in Figure 12-11, characters contain an extra bit used as an address indicator. The first character in a block of data carries an address bit which indicates that the character is an address. The RXWake bit is set when a received character is an address character. It is transferred into the receive buffer (receive conditions are true). Usually, if the USART URXWIE bit is set, data characters are assembled by the receiver but are not transferred to the receiver buffer URXBUF, nor are interrupts generated. When a character that has an address bit set is received, the receiver is temporarily activated to transfer the character to URXBUF and to set the URXIFG. Error status flags are set as applicable. The application software processes the succeeding operation to optimize resource handling or reduce current consumption. The application software can validate the received address. If there is a match, the processor can read the remainder of the data block. If there is not a match, the processor waits for the next address character to arrive.
USART Peripheral Interface, UART Mode
12-9
Asynchronous Operation
Figure 12-11.Address-Bit Multiprocessor Format
Block of Frames
UTXD/URXD
Idle Periods of No Significance TXD/RXD Expanded
UTXD/URXD
ST
Address
1 SP ST
Data
0 SP
ST
Data
0 SP
First Frame Within Block is an Address. The ADDR/DATA Bit is 1
ADDR/DATA Bit is 0 for Data Within Block. Idle Time is of No Significance
In the address-bit multiprocessor mode, the address bit of a character can be controlled by writing to the TXWake bit. The value of the TXWake bit is loaded into the address bit of that character each time a character is transferred from transmit buffer UTXBUF to the transmitter. The TXWake bit is then cleared by the USART.
12-10
Interrupt and Enable Functions
12.4 Interrupt and Enable Functions
The USART peripheral interface serves two main interrupt sources for transmission and reception. Two interrupt vectors serve receive and transmit events. The interrupt control bits and flags and enable bits of the USART peripheral interface are located in the SFR registers. They are discussed in Table 12-1. See the peripheral file map in Appendix A for the exact bit locations.
Table 12-1.USART Interrupt Control and Enable Bits - UART Mode
Receive interrupt flag Receive interrupt enable Receive enable (see note) Transmit interrupt flag Transmit interrupt enable Transmit enable.(see note)
Note:
URXIFG URXIE URXE UTXIFG UTXIE UTXE
Initial state reset (by PUC/SWRST) Initial state reset (by PUC/SWRST) Initial state reset (by PUC) Initial state set (by PUC/SWRST) Initial state reset (by PUC/SWRST) Initial state reset (by PUC)
Different for SPI mode, see Chapter 13.
The USART receiver and transmitter operate independently, but use the same baud rate.
12.4.1 USART Receive Enable Bit
The receive enable bit URXE, shown in Figure 12-12, enables or disables receipt of the bit stream on the URXD data line. Disabling the USART receiver stops the receive operation after completion of receiving the character, or stops immediately if no receive operation is active. Start-bit detection is also disabled.
Figure 12-12. State Diagram of Receiver Enable
No Valid Start Bit URXE = 0 Not Completed URXE = 1 Valid Start Bit
URXE = 1 Receive Disable URXE = 0
Idle State (Receiver Enabled)
Receiver Collects Character
Handle Interrupt Conditions Character Received
URXE = 1 URXE = 0
Note: URXE Reenabled, UART Mode Because the receiver is completely disabled, reenabling the receiver is asynchronous to any data stream on the communication line. Synchronization can be performed by looking for an idle line condition before receiving a character.
USART Peripheral Interface, UART Mode
12-11
Interrupt and Enable Functions
12.4.2 USART Transmit Enable Bit
The transmit enable bit UTXE, shown in Figure 12-13, enables or disables a character transmission on the serial-data line. If this bit is reset, the transmitter is disabled but any active transmission does not halt until the data in the transmit shift register and the transmit buffer are transmitted. Data written to the transmit buffer before UTXE has been reset may be modified or overwritten--even after UTXE is reset--until it is shifted to the transmit shift register. For example, if software writes a byte to the transmit buffer and then resets UTXE, the byte written to the transmit buffer will be transmitted and may be modified or overwritten until it is transferred into the transmit shift register. However, after the byte is transferred to the transmit shift register, any subsequent writes to UTXBUF while UTXE is reset will not result in transmission, but UTXBUF will be updated with the new value.
Figure 12-13. State Diagram of Transmitter Enable
UTXE = 0 No Data Written to Transmit Buffer Not Completed
UTXE = 1 Transmit Disable UTXE = 0
UTXE = 1 Data Written to Idle State Transmit Buffer Transmission (Transmitter Active Enabled) UTXE = 1
Handle Interrupt Conditions Character Transmitted
UTXE = 0 And Last Buffer Entry Is Transmitted
When UTXE is reset and the current transmission is completed, new data written to the transmit buffer will not be transmitted. Once the UTXE bit is set, the data in the transmit buffer are immediately loaded into the transmit shift register and character transmission is started. Note: Writing to UTXBUF, UART Mode Data should never be written to transmit buffer UTXBUF when the buffer is not ready and when the transmitter is enabled (UTXE is set). Otherwise, the transmission will have errors.
Note: Write to UTXBUF/Reset of Transmitter, UART Mode Disabling the transmitter should be done only if all data to be transmitted has been moved to the transmit shift register.
MOV.B BIC.B #....,&UTXBUF #UTXE,&ME2 ; ; ; ; ; If BITCLK < MCLK then the transmitter might be stopped before the buffer is loaded into the transmitter shift register
12-12
Interrupt and Enable Functions
12.4.3 USART Receive Interrupt Operation
In the receive interrupt operation, shown in Figure 12-14, the receive interrupt flag URXIFG is set or is unchanged each time a character is received and loaded into the receive buffer:
-
Erroneous characters (parity, frame, or break error) do not set interrupt flag URXIFG when URXEIE is reset: URXIFG is unchanged. All types of characters (URXWIE = 0), or only address characters (URXWIE = 1), set the interrupt flag URXIFG. When URXEIE is set, erroneous characters can also set the interrupt flag URXIFG.
Figure 12-14. Receive Interrupt Operation
SYNC Valid Start Bit Receiver Collects Character URXSE From URXD Erroneous Character Will Not Set Flag URXIFG SYNC URXEIE (S) URXIFG URXWIE RXWake Each Character or Address Will Set Flag URXIFG Character Received or Break Detected Clear SWRST PUC URXBUF URXSE IRQA URXS
Clear URXIE
PE FE BRK
Request_ Interrupt_Service
URXIFG is reset by a system reset PUC signal, or with a software reset (SWRST). URXIFG is reset automatically if the interrupt is served (URXSE = 0) or the receive buffer URXBUF is read. A set receive interrupt flag URXIFG indicates that an interrupt event is waiting to be served. A set receive interrupt enable bit URXIE enables serving a waiting interrupt request. Both the receive interrupt flag URXIFG and the receive interrupt enable bit URXIE are reset with the PUC signal and a SWRST. Signal URXIFG can be accessed by the software, whereas signal URXS cannot. When both interrupt events--character receive action and receive start detection--are enabled by the software, the flag URXIFG indicates that a character was received but the start-detect interrupt was not. Because the interrupt software handler for the receive start detection resets the URXSE bit, this clears the URXS bit and prevents further interrupt requests from URXS. The URXIFG should already be reset since no set condition was active during URXIFG latch time.
USART Peripheral Interface, UART Mode
12-13
Interrupt and Enable Functions
12.4.4 USART Transmit Interrupt Operation
In the transmit interrupt operation, shown in Figure 12-15, the transmit interrupt flag UTXIFG is set by the transmitter to indicate that the transmitter buffer UTXBUF is ready to accept another character. This bit is automatically reset if the interrupt request service is started or a character is written into the UTXBUF. This flag asserts a transmitter interrupt if the local (UTXIE) and general interrupt enable (GIE) bits are set. The UTXIFG is set after a system reset PUC signal, or removal of a SWRST.
Figure 12-15. Transmit Interrupt Operation
Q UTXIE
Clear PUC or SWRST Set UTXIFG DQ SWRST Clear URXBUF Written Into Transmit Shift Register IRQA Request_ Interrupt_Service
VCC Character Moved From Buffer to Shift Register
The transmit interrupt enable UTXIE bit controls the ability of the UTXIFG to request an interrupt, but does not prevent the flag UTXIFG from being set. The UTXIE is reset with a PUC signal or a software reset (SWRST) bit. The UTXIFG bit is set after a system reset PUC signal or software reset (SWRST), but the UTXIE bit is reset to ensure full interrupt-control capability.
12-14
Control and Status Registers
12.5 Control and Status Registers
The USART control and status registers are byte structured and should be accessed using byte processing instructions (suffix B). Table 12-3 lists the registers and their access modes.
Table 12-2.Control and Status Registers
Register USART control Transmit control Receive control Modulation control Baud rate 0 Baud rate 1 Receive buffer Transmit buffer Short Form UCTL UTCTL URCTL UMCTL UBR0 UBR1 URXBUF UTXBUF Register Type Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read Address Initial State 070h 071h 072h 073h 074h 075h 076h 077h See section 12.5.1. See section 12.5.2. See section 12.5.3. Unchanged Unchanged Unchanged Unchanged Unchanged
All bits are random after a PUC signal, unless otherwise noted by the detailed functional description. The reset of the USART peripheral interface is performed by a PUC signal or a SWRST. After a PUC signal, the SWRST bit remains set and the USART interface remains in the reset condition until it is disabled by resetting the SWRST bit. The USART module operates in asynchronous or synchronous mode as defined by the SYNC bit. The bits in the control registers can have different functions in the two modes. All bits in this section are described with their functions in the asynchronous mode (SYNC = 0). Their functions in the synchronous mode are described in Chapter 13, USART Peripheral Interface, SPI Mode.
12.5.1 USART Control Register UCTL
The information stored in the USART control register (UCTL), shown in Figure 12-16, determines the basic operation of the USART module. The register bits select the communications protocol, communication format, and parity bit. All bits must be programmed according to the selected mode before resetting the SWRST bit to disable the reset.
Figure 12-16. USART Control Register UCTL
7 UCTL 070h
PENA PEV SP CHAR Listen SYNC MM
0
SWRST
rw-0
rw-0
rw-0
rw-0 rw-0
rw-0
rw-0
rw-1
USART Peripheral Interface, UART Mode
12-15
Control and Status Registers
Bit 0:
The USART state machines and operating flags are initialized to the reset condition (URXIFG = URXIE = UTXIE = 0, UTXIFG = 1) if the software reset bit is set. Until the SWRST bit is reset, all affected logic is held in the reset state. This implies that after a system reset the USART must be reenabled by resetting this bit. The receive and transmit enable flags URXE and UTXE are not altered by SWRST. The SWRST bit resets the following bits and flags: URXIE, UTXIE, URXIFG, RXWAKE, TXWAKE, RXERR, BRK, PE, OE, and FE The SWRST bit sets the following bits: UTXIFG, TXEPT
Bit 1:
Multiprocessor mode (address/idle-line wake up) Two multiprocessor protocols, idle-line and address-bit, are supported by the USART module. The choice of multiprocessor mode affects the operation of the automatic address decoding functions. MM = 0: Idle-line multiprocessor protocol MM = 1: Address-bit multiprocessor protocol The conventional asynchronous protocol uses MM-bit reset. Mode or function of USART module selected The SYNC bit selects the function of the USART peripheral interface module. Some of the USART control bits have different functions in UART and SPI mode. SYNC = 0: UART function is selected SYNC = 1: SPI function is selected The listen bit selects if the transmitted data is fed back internally to the receiver. Listen = 0: No feedback Listen = 1: Transmit signal is internally fed back to the receiver. This is commonly known as loopback mode. Character length This register bit selects the length of the character to be transmitted as either 7 or 8 bits. 7-bit characters do not use the eighth bit in URXBUF and UTXBUF. This bit is padded with 0. CHAR = 0: 7-bit data CHAR = 1: 8-bit data Number of stop bits This bit determines the number of stop bits transmitted. The receiver checks for one stop bit only. SP = 0: one stop bit SP = 1: two stop bits
Bit 2:
Bit 3:
Bit 4:
Bit 5:
12-16
Control and Status Registers
Bit 6:
Parity odd/even If the PENA bit is set (parity bit is enabled), the PEV bit defines odd or even parity according to the number of odd or even 1 bits (in both the transmitted and received characters), the address bit (address-bit multiprocessor mode), and the parity bit. PEV = 0: odd parity PEV = 1: even parity Parity enable If parity is disabled, no parity bit is generated during transmission or expected during reception. A received parity bit is not transferred to the URXBUF with the received data as it is not considered one of the data bits. In address-bit multiprocessor mode, the address bit is included in the parity calculation. PEN = 0: Parity disable PEN = 1: Parity enable
Bit 7:
Note: Mark and Space Definitions The mark condition is identical to the signal level in the idle state. Space is the opposite signal level: the start bit is always space.
12.5.2 Transmit Control Register UTCTL
The transmit control register (UTCTL), shown in Figure 12-17, controls the USART hardware associated with the transmit operation.
Figure 12-17. Transmitter Control Register UTCTL
7 UTCTL 071h
Unused CKPL SSEL1
0
SSEL0 URXSE TXWake Unused TXEPT
rw-0
rw-0
rw-0
rw-0 rw-0
rw-0
rw-0
rw-1
Bit 0:
The transmitter empty (TXEPT) flag is set when the transmitter shift register and UTXBUF are empty, and is reset when data is written to UTXBUF. It is set by a SWRST. Unused The TXWake bit controls the transmit features of the multiprocessor communication modes. Each transmission --started by loading the UTXBUF--uses the state of the TXWake bit to initialize the address-identification feature. It must not be cleared--the USART hardware clears this bit once it is transferred to the WUT; a SWRST also clears the TXWake bit.
Bit 1: Bit 2:
USART Peripheral Interface, UART Mode
12-17
Control and Status Registers
Bit 3:
The receive-start edge-control bit, if set, requests a receive interrupt service. For a successful interrupt service, the corresponding enable bits URXIE and GIE must be set. The advantage of this bit is that it starts the controller clock system, including MCLK, along with the interrupt service, and keeps it running by modifying the mode control bits. The USART module works with the selected MCLK even if the system is switched to a low-power mode with a disabled MCLK. Source select 0 and 1 The source select bit defines which clock source is used for baud-rate generation: SSEL1, SSEL0 0 External clock, UCLKI 1 ACLK 2, 3 MCLK Clock polarity CKPL The CKPL bit controls the polarity of the UCLKI signal. CKPL = 0: The UCLKI signal has the same polarity as the UCLK signal. CKPL = 1: The UCLKI signal has an inverted polarity to the UCLK signal. Unused
Bits 4, 5:
Bit 6:
Bit 7:
12.5.3 Receiver Control Register URCTL
The receiver-control register (URCTL), shown in Figure 12-18, controls the USART hardware associated with the receiver operation and holds error and wake-up conditions modified by the latest character written to the receive buffer (URXBUF). Once any one of the bits FE, PE, OE, BRK, RXERR, or RXWake is set, none are reset by receiving another character. The bits are reset by accessing the receive buffer, by a USART software reset (SWRST), by a system reset PUC signal, or by an instruction.
Figure 12-18. Receiver-Control Register URCTL
7 URCTL 072h
FE PE OE BRK
0
URXEIE URXWIE RXWake RXERR
rw-0 rw-0
rw-0 rw-0 rw-0
rw-0
rw-0
rw-0
Bit 0:
The receive error bit (RXERR) indicates that one or more error flags (FE, PE, OE, or BRK) is set. It is not reset when the error flags are cleared by instruction.
12-18
Control and Status Registers
Bit 1:
Receiver wake-up detect The RXWake bit is set when a received character is an address character and is transferred into the receive buffer. Address-bit multiprocessor mode: RXWake is set when the address bit is set in the character received. Idle-line multiprocessor mode: RXWake is set if an idle URXD line is detected (11 bits of mark level) in front of the received character. RXWake is reset by accessing the receive buffer (URXBUF), by a USART software reset, or by a system-reset PUC signal. The receive wake-up interrupt-enable bit (URXWIE) selects the type of character to set the interrupt flag (URXIFG): URXWIE = 0: Each character received sets the URXIFG URXWIE = 1: Only characters that are marked as address characters set the interrupt flag URXIFG. It operates identically in both multiprocessor modes. The wake-up interrupt enable feature depends on the receive erroneous-character feature. See also Bit 3, URXEIE. The receive erroneous-character interrupt-enable bit URXEIE selects whether an erroneous character is to set the interrupt flag URXIFG. URXEIE = 0: Each erroneous character received does not alter the interrupt flag URXIFG. URXEIE = 1: All characters can set the interrupt flag URXIFG as described in Table 12-4, depending on the conditions set by the URXWIE bit.
Bit 2:
Bit 3:
Table 12-3.Interrupt Flag Set Conditions
URXEIE 0 0 0 0 1 1 1 URXWIE X 0 1 1 0 1 1 Char. w/Error 1 0 0 0 X X X Char. Address X X 0 1 X 0 1 Description Flag URXIFG After a Character Is Received Unchanged Set Unchanged Set Set (Receives all characters) Unchanged Set
USART Peripheral Interface, UART Mode
12-19
Control and Status Registers
Bit 4:
The break detect bit (BRK) is set when a break condition occurs and the URXEIE bit is set. The break condition is recognized if the RXD line remains continuously low for at least 10 bits, beginning after a missing first stop bit. It is not cleared by receipt of a character after the break is detected, but is reset by a SWRST, a system reset, or by reading the URXBUF. The receive interrupt flag URXIFG is set if a break is detected. The overrun error flag bit OE is set when a character is transferred into the URXBUF before the previous character is read out. The previous character is overwritten and lost. OE is reset by a SWRST, a system reset, or by reading the URXBUF. The parity error flag bit PE is set when a character is received with a mismatch between the number of 1s and its parity bit, and is loaded into the receive buffer. The parity checker includes the address bit, used in the address-bit multiprocessor mode, in the calculation. The flag is disabled if parity generation and detection are not enabled. In this case the flag is read as 0. It is reset by a SWRST, a system reset, or by reading the URXBUF. The framing error flag bit FE is set when a character is received with a 0 stop bit and is loaded into the receive buffer. Only the first stop bit is checked when more than one is used. The missing stop bit indicates that the start-bit synchronization is lost and the character is incorrectly framed. FE is reset by a SWRST, a system reset, or by reading the URXBUF.
Bit 5:
Bit 6:
Bit 7:
Note: Receive Status Control Bits The receive status control bits FE, PE, OE, BRK, and RXWake are set by the hardware according to the conditions of the characters received. Once the bits are set, they remain set until the software resets them directly, or there is a reading of the receive buffer. False character interpretation or missinginterrupt capability can result in uncleared error bits.
12.5.4 Baud Rate Select and Modulation Control Registers
The baud-rate generator uses the content of the baud-rate select registers UBR0 and UBR1 shown in Figure 12-19, with the modulation control register to generate the serial data-stream bit timing.
Figure 12-19. USART Baud Rate Select Register
7 UBR0 074h
27 rw 26 rw 25 rw 24 rw 23 rw 22 rw 21 rw
0
20 rw
7 UBR1 075h
215 rw 214 rw 213 rw 212 rw 211 rw 210 rw 29 rw
0
28 rw
12-20
Control and Status Registers
Baud rate =
BRCLK UBR
)
1 n
S mi i+0
n-1
with UBR= [UBR1,UBR0] 3 UBR < 0FFFFh
The baud-rate control register range is: Note:
Unpredictable receive and transmission occur if UBR <3. The modulation control register, shown in Figure 12-20, ensures proper timing generation with the UBR0 and UBR01, even with crystal frequencies that are not integer multiples of the required baud rate.
Figure 12-20. USART Modulation Control Register
7 UMCTL 073h
m7 m6 m5 m4 m3 m2 m1
0
m0
rw
rw
rw
rw
rw
rw
rw
rw
The timing of the running bit is expanded by one clock cycle of the baud-ratedivider input clock if bit mi is set. Each time a bit is received or transmitted, the next bit in the modulation control register determines the present bit timing. The first bit time in the protocol--the start bit time--is determined by UBR plus m0; the next bit is determined by UBR plus m1, and so on. The modulation sequence is: m0 - m1 - m2 - m3 - m4 - m5 - m6 - m7 - m0 - m1 - m2 - .....
12.5.5 Receive-Data Buffer URXBUF
The receive-data buffer (URXBUF), shown in Figure 12-21, contains previous data from the receiver shift register. Reading URXBUF resets the receive-error bits, the RXWake bit, and the interrupt flag (URXIFG).
Figure 12-21. USART Receive Data Buffer URXBUF
7 URXBUF 076h
27 r 26 r 25 r 24 r 23 r 22 r 21 r
0
20 r
In seven-bit length mode, the MSB of the URXBUF is always reset. The receive data buffer is loaded with the recently-received character as described in Table 12-4, when receive and control conditions are true.
USART Peripheral Interface, UART Mode
12-21
Control and Status Registers
Table 12-4.Receive Data Buffer Characters
URXEIE 0 1 0 1 URXWIE 1 1 0 0 Load URXBUF With: Error-free address characters All address characters Error-free characters All characters PE 0 X 0 X FE 0 X 0 X BRK 0 X 0 X
12.5.6 Transmit Data Buffer UTXBUF
The transmit data buffer (UTXBUF), shown in Figure 12-22, contains current data to be transmitted.
Figure 12-22. Transmit Data Buffer UTXBUF
7 UTXBUF 077h
27 rw 26 rw 25 rw 24 rw 23 rw 22 rw 21 rw
0
20 rw
The UTXIFG flag indicates that the UTXBUF buffer is ready to accept another character for transmission. The transmission is initialized by writing data to UTXBUF. The transmission of this data is started immediately if the transmitter shift register is empty or is going to be empty. Note: Writing to UTXBUF Writing data to the transmit-data buffer must only be done if buffer UTXBUF is empty; otherwise, an unpredictable character can be transmitted.
12-22
Utilizing Features of Low-Power Modes
12.6 Utilizing Features of Low-Power Modes
There are several functions or features of the USART that support the ultra-low power architecture of the MSP430. These include:
-
Support system start up from any processor mode by sensing of UART frame-start condition Use the lowest input clock frequency for the required baud rate Support multiprocessor modes to reduce use of MSP430 resources
12.6.1 Receive-Start Operation From UART Frame
The most effective use of start detection in the receive path is achieved when the baud-rate clock runs from MCLK. In this configuration, the MSP430 can be put into a low-power mode with MCLK disabled. The receive-start condition is the negative edge from the signal on pin URXD. Each time the negative edge triggers the interrupt flag URXS, it requests a service when enable bits URXIE and GIE are set. This wakes the MSP430 and the system returns to active mode, supporting the USART transfer.
Figure 12-23. Receive-Start Conditions
SYNC Valid Start Bit Receiver Collects Character URXSE From URXD Erroneous Character Will Not Set Flag URXIFG URXEIE SYNC (S) URXIFG URXWIE RXWake Each Character or Address Will Set Flag URXIFG Character Received or Break Detected Clear SWRST PUC URXBUF Read URXSE IRQA URXS D Q
Clear URXIE
PE FE BRK
Request_ Interrupt_Service
Three character streams do not set the interrupt flag (URXIFG):
-
Erroneous characters (URXEIE = 0) Address characters (URXWIE = 1) Invalid start-bit detection
The interrupt software should handle these conditions.
USART Peripheral Interface, UART Mode
12-23
Utilizing Features of Low-Power Modes
12.6.1.1 Start Conditions
The URXD signal feeds into the USART module by first going into a deglitch circuit. Glitches cannot trigger the receive-start condition flag URXS, which prevents the module from being started from small glitches on the URXD line. Because glitches do not start the system or the USART module, current consumption is reduced in noisy environments. Figure 12-24 shows the accepted receive-start timing condition.
Figure 12-24. Receive-Start Timing Using URXS Flag, Start Bit Accepted
Majority Vote URXD URXS t URXS is Reset in the Interrupt Handler Using Control Bit URXSE
The UART stops receiving a character when the URXD signal exceeds the deglitch time t but the majority vote on the signal fails to detect a start bit, as shown in Figure 12-25. The software should handle this condition and return the system to the appropriate low-power mode. The interrupt flag URXIFG is not set.
Figure 12-25. Receive Start Timing Using URXS Flag, Start Bit Not Accepted
Majority Vote URXD URXS t URXS is Reset in The Interrupt Handler Using Control Bit URXSE
Glitches at the URXD line are suppressed automatically and no further activity occurs in the MSP430 as shown in Figure 12-26. The data for the deglitch time t is noted in the corresponding device specification.
Figure 12-26. Receive Start Timing Using URXS Flag, Glitch Suppression
Majority Vote URXD URXS t
The interrupt handler must reset the URXSE bit in control register UCTL to prevent further interrupt service requests from the URXS signal and to enable the basic function of the receive interrupt flag URXIFG.
12-24
Utilizing Features of Low-Power Modes
********************************************************** * Interrupt handler for frame start condition and * * Character receive * ********************************************************** IFG2 UTCTL UTXIFG URXSE URX_Int .EQU .EQU .EQU .EQU 3 71h 0 8 ; ; ; ; ; ; ; ; ; URXIFG and UTXIFG in address 3
BIT.B #URXIFG,&IFG2 JNE ST_COND ..... ..... BIC.B #URXSE,&UTCTL
test URXIFG signal to check if frame start condition
ST_COND
BIS.B #URXSE,&UTCTl ..... .....
; ; ; ; ; ; ;
clear ff/signal URXS, stop further interrupt requests Prepare FF_URXS for next frame start bits and set the conditions to run the clock needed for UART RX
Note: Break Detect (BRK) Bit With Halted UART Clock If the UART operates with the wake-up-on-start-condition mode and switches off the UCLK whenever a character is completely received, a communication line break cannot be detected automatically by the UART hardware. The break detection requires the baud-rate generator BRSCLK, but it is stopped upon the missing UCLK.
12.6.2 Maximum Utilization of Clock Frequency vs Baud Rate UART Mode
The current consumption increases linearly with the clock frequency. It should be kept to the minimum required to meet application conditions. Fast communication speed is needed for calibration and testing in manufacturing processes, alarm responses in critical applications, and response time to human requests for information. The MSP430 USART can generate baud rates up to one third of the clock frequency. An additional modulation of the baud-rate timing adjusts timing for individual bits within a frame. The timing is adjusted from bit to bit to meet timing requirements even when a noninteger division is needed. Baud rates up to 4800 baud can be generated from a 32,768 Hz crystal with maximum errors of 11 percent. Standard UARTs--even with the worst maximum error (-14.6 percent)--can obtain maximum baud rates of 75 baud.
USART Peripheral Interface, UART Mode
12-25
Baud Rate Considerations
12.6.3 Support of Multiprocessor Modes for Reduced Use of MSP430 Resources
Communication systems can use multiprocessor modes with multiplecharacter idle-line or address-bit protocols. The first character can be a target address, a message identifier, or can have another definition. This character is interpreted by the software and, if it is of any significance to the application, the succeeding characters are collected and further activities are defined. An insignificant first character would stop activity for the processing device. This application is supported by the wake-up interrupt feature in the receive operation, and sends wake-up conditions along with a transmission. Avoiding activity on insignificant characters reduces consumption of MSP430 resources and the system can remain in the most efficient power-conserving mode. In addition to the multiprocessor modes, rejecting erroneous characters saves MSP430 resources. This practice prevents interrupt handling of the erroneous characters. The processor waits in the most efficient power-conserving mode until a character is processed.
12.7 Baud Rate Considerations
The MSP430 baud-rate generator uses a divider and a modulator. A given crystal frequency and a required baud rate determines the required division factor N:
N=
BRCLK baud rate
The required division factor N usually has an integer part and a fraction. The divider in the baud rate generator realizes the integer portion of the division factor N, and the modulator meets the fractional part as closely as possible. The factor N is defined as:
N
1 + UBR ) n S mi
n-1 i+0
Where
N: UBR: i: n: mi :
Target division factor 16-bit representation of registers UBR1 and UBR0 Actual bit in the frame Number of bits in the frame Data of the actual modulation bit
Baud rate
+ BRCLK + N
BRCLK UBR
)
1 n
n*1 i+0
mi
12-26
Baud Rate Considerations
12.7.1 Bit Timing in Transmit Operation
The timing for each individual bit in one frame or character is the sum of the actual bit timings as shown in Figure 12-27. The baud-rate generation error shown in Figure 12-28 in relation to the required ideal timing, is calculated for each individual bit. The relevant error information is the error relative to the actual bit, not the overall relative error.
Figure 12-27. MSP430 Transmit Bit Timing
i BRCLK ti URXD t0 t1 t2 t3 t4 t5 t6 t7 D6 t8 D7 t9 t10 t11 t12 Mark Space [2nd Stop Bit, SP = 1] [Parity Bit, PE = 1] [Address Bit, MM = 1] [8th Data Bit, Char = 1] 0 1 2 3 4 5 6 7 8 9 10 11 12
ST D0
Figure 12-28. MSP430 Transmit Bit Timing Errors
i ttarget terror URXD tactual 0 t0 ST t0 1 t1 D0 t1 8 t8 D7 t8 t9 PA t9 t10 t11 9 t10 10 t11 Mark Space 11
Even small errors per bit (relative errors) can result in large cumulative errors. They must be considered to be cumulative, not relative. The error of an individual bit can be calculated by:
Error[%]
or,
+
S t actuali i+0
n-1
* St
n-1 i+0
target i
t baud rate
100%
Error [%]
With:
+
baud rate BRCLK
(i
) 1)
UBR
) S m * (i ) 1)
n-1 i+0 i
100%
baud rate: Required baud rate BRCLK: Input frequency - selected for UCLK, ACLK, or MCLK i = 0 for the start bit, 1 for the data bit D0, and so on UBR: Division factor in registers UBR1 and UBR0
USART Peripheral Interface, UART Mode
12-27
Baud Rate Considerations
Example 12-3. Error Example for 2400 Baud
The following data are assumed: Baud rate = BRCLK = UBR = m = 6Bh: 2400 32,768 Hz (ACLK) 13, since the ideal division factor is 13.67 m7 = 0, m6 = 1, m5 = 1, m4 = 0, m3 = 1, m2 = 0, m1 = 1 and m0 = 1 The LSB (m0) of the modulation register is used first.
baud rate BRCLK baud rate BRCLK baud rate BRCLK baud rate BRCLK baud rate BRCLK baud rate BRCLK baud rate BRCLK baud rate BRCLK baud rate BRCLK baud rate BRCLK baud rate BRCLK baud rate BRCLK
+ Data bit D0 Error [%] + Data bit D1 Error [%] + Data bit D2 Error [%] + Data bit D3 Error [%] + Data bit D4 Error [%] + Data bit D5 Error [%] + Data bit D6 Error [%] + Data bit D7 Error [%] + Parity bit Error [%] + Stop bit 1 Error [%] + Stop bit 2 Error [%] +
Start bit Error [%]
) 1) ((1 ) 1) ((2 ) 1) ((3 ) 1) ((4 ) 1) ((5 ) 1) ((6 ) 1) ((7 ) 1) ((8 ) 1) ((9 ) 1) ((10 ) 1) ((11 ) 1)
((0
) 1)-1 UBR ) 2)-2 UBR ) 2)-3 UBR ) 3)-4 UBR ) 3)-5 UBR ) 4)-6 UBR ) 5)-7 UBR ) 5)-8 UBR ) 6)-9 UBR ) 7)-10 UBR ) 7)-11 UBR ) 8)-12
UBR
+ 2.54% 100% + 5.08% 100% + 0.29% 100% + 2.83% 100% +*1.95% 100% + 0.59% 100% + 3.13% 100% + *1.66% 100% + 0.88% 100% + 3.42% 100% + *1.37% 100% + 1.17%
100%
12-28
Baud Rate Considerations
12.7.2 Typical Baud Rates and Errors
The standard baud rate data needed for the baud rate registers and the modulation register are listed in Table 12-6 for the 32,768-Hz watch crystal (ACLK) and MCLK, assumed to be 32 times the ACLK frequency. The error listed is calculated for the transmit and receive paths. In addition to the error for the receive operation, the synchronization error must be considered.
Table 12-5.Commonly Used Baud Rates, Baud Rate Data, and Errors
Divide by Baud Rate 75 110 150 300 600 1200 2400 4800 9600 19,200 38,400 76,800 115,200 ACLK (32,768 Hz) Max. TX Error % -0.1/0.3 0/0.5 0/0.4 -0.3/0.7 - 1/1 - 4/3 6/3 - 9/11 - 21/12 Max. RX Error % -0.1/0.3 0/0.5 0/0.4 -0.3/0.7 - 1/1 - 4/3 - 6/3 - 9/11 - 21/12 Synchr. RX Error % 2 3 2 2 2 2 4 7 15 MCLK (1,048,576 Hz) Max. TX Error% 0/0.1 0/0.1 0/0.1 -0.1/0 0/0.3 0/0.3 0/0.3 0/0.4 -0.4/1 -0.2/2 - 4/3 - 6/3 - 5/7 Max. RX Error % 2 3 2 2 2 2 2 2 2 2 2 4 7
ACLK 436.91 297.89 218.45 109.23 54.61 27.31 13.65 6.83 3.41
MCLK 13,981 9532.51 6990.5 3495.25 1747.63 873.81 436.91 218.45 109.23 54.61 27.31 13.65 9.10
UBR1 1 1 0 0 0 0 0 0 0
UBR0 B4 29 DA 6D 36 1B 0D 06 03
UMOD FF FF 55 22 D5 03 6B 6F 4A
UBR1 36 25 1B 0D 06 03 01 0 0 0 0 0 0
UBR0 9D 3C 4E A7 D3 69 B4 DA 6D 36 1B 0D 09
UMOD FF FF FF 00 FF FF FF 55 03 6B 03 6B 08
The maximum error is calculated for the receive and transmit modes. The receive-mode error is the accumulated time versus the ideal scanning time in the middle of each bit. The transmit error is the accumulated timing error versus the ideal time of the bit period. The MSP430 USART peripheral interface allows baud rates nearly as high as the clock rate. It has a low error accumulation as a result of modulating the individual bit timing. In practice, an error margin of 20% to 30% supports standard serial communication.
USART Peripheral Interface, UART Mode
12-29
Baud Rate Considerations
12.7.3 Synchronization Error
The synchronization error, shown in Figure 12-29, results from the asynchronous timing between the URXD pin data signal and the internal clock system. The receive signal is synchronized with the BRSCLK clock. The BRSCLK clock is sixteen to thirty-one times faster than the bit timing, as described. BRSCLK = BRCLK BRSCLK = BRCLK/2 BRSCLK = BRCLK/4 BRSCLK = BRCLK/8 BRSCLK = BRCLK/16 BRSCLK = BRCLK/32 BRSCLK = BRCLK/64 BRSCLK = BRCLK/128 BRSCLK = BRCLK/256 BRSCLK = BRCLK/512 BRSCLK = BRCLK/1024 BRSCLK = BRCLK/2048 for for for for for for for for for for for for N N N N N N N N N N N N 1F 3Fh 7Fh FFh 1FF 3FFh 7FFh FFFh 1FFFh 3FFFh 7FFFh FFFFh
20h 40h 80h 100 200 400 800h 1000h 2000h 4000h 8000h
Figure 12-29. Synchronization Error
i ttarget
BRSCLK URXD URXDS ST ST
t0 Synchronization Error 0.5x BLSCLK 0 t0 12345678 1 t1 9 10 11 12 13 14 1 2 3 4 5 6 7 8 9 10 11 12 13 14 1 2 3 4 5 6 7 2
D0 D0
t1
D2 D2
t2
tactual
Sample URXDS
Int(UBR/2)+m0 = Int (13/2)+1 = 6+1 = 7
UBR +m1 = 13+1 = 14
UBR +m2 = 13+0 = 13
Majority Vote Taken
Majority Vote Taken
Majority Vote Taken
12-30
Baud Rate Considerations
The target start-bit detection-baud-rate timing ttarget(0) is half the baud-rate timing tbaud rate because the bit is tested in the middle of its period. The target baud rate timing ttargeti for all of the other succeeding bits is the baud rate timing tbaud rate.
Error [%]
OR
+ +
t actual0
0.5
)t
target 0
t target0
)
n-1
i+1
S t actuali
* St
n-1 i+1
target i
t targeti
2
100%
Error [%]
Where:
baud rate BRCLK
m0
) int
UBR 2
)
i
UBR
) S m * 1-i
n-1 i+1 i
100%
baud rate is the required baud rate BRCLK is the input frequency--selected for UCLK, ACLK, or MCLK i = 0 for the start bit, 1 for data bit D0, and so on UBR is the division factor in registers UBR1 and BRB0
Example 12-4. Synchronization Error--2400 Baud
The following data are assumed: Baud rate = BRCLK = UBR = m = 6Bh: 2400 32,768 Hz (ACLK) 13, since the ideal division factor is 13.67 m7 = 0, m6 = 1, m5 = 1, m4 = 0, m3 = 1, m2 = 0, m1 = 1 and m0 = 1 The LSB (m0) of the modulation register is used first.
+ baud rate BRCLK Data bit D0 Error [%] + baud rate BRCLK
Start bit Error [%] Data bit D1 Error [%]
) 6) ) (0 [2x(1 ) 6) ) (1
[2x(1 UBR
) 0 -0)]-1 UBR ) 1)]-1-1
UBR 100%
+ 2.54% 100% + 5.08%
100%
+ Data bit D2 Error [%] + Data bit D3 Error [%] + Data bit D4 Error [%] + Data bit D5 Error [%] + Data bit D6 Error [%] + Data bit D7 Error [%] + Parity bit Error [%] + Stop bit 1 Error [%] + Stop bit 2 Error [%] +
baud rate BRCLK baud rate BRCLK baud rate BRCLK baud rate BRCLK baud rate BRCLK baud rate BRCLK baud rate BRCLK baud rate BRCLK baud rate BRCLK baud rate BRCLK
) 6) ) (2 [2x(1 ) 6) ) (3 [2x(1 ) 6) ) (4 [2x(1 ) 6) ) (5 [2x(1 ) 6) ) (6 [2x(1 ) 6) ) (7 [2x(1 ) 6) ) (8 [2x(1 ) 6) ) (9 [2x(1 ) 6) ) (10 [2x(1 ) 6) ) (11
[2x(1
) 1)]-1-2 UBR ) 2)]-1-3 UBR ) 2)]-1-4 UBR ) 3)]-1-5 UBR ) 4)]-1-6 UBR ) 4)]-1-7 UBR ) 5)]-1-8 UBR ) 6)]-1-9 UBR ) 6)]-1-10 UBR ) 7)]-1-11
+ 0.29% 100% + 2.83% 100% + -1.95% 100% + 0.59% 100% + 3.13% 100% + -1.66% 100% + 0.88% 100% + 3.42% 100% + -1.37% 100% + -1.17%
12-31
USART Peripheral Interface, UART Mode
12-32
Chapter 13
USART Peripheral Interface, SPI Mode
The universal synchronous/asynchronous receive/transmit (USART) serialcommunication peripheral supports two serial modes with one hardware configuration. These modes shift a serial-bit stream in and out of the MSP430 at a programmed rate or at a rate defined by an external clock. The first mode is the universal asynchronous-receive/transmit (UART) communication protocol (discussed in Chapter 12); the second is the serial peripheralinterface (SPI) protocol. Bit SYNC in control register UCTL selects the required mode: SYNC = 0: UART--asynchronous mode selected SYNC = 1: SPI--synchronous mode selected This chapter describes the SPI mode.
Topic
Page
13.1 USART Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2 13.2 USART Peripheral Interface, SPI Mode . . . . . . . . . . . . . . . . . . . . . . . . . 13-3 13.3 Synchronous Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4 13.4 Interrupt and Control Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-9 1.5 Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-15
USART Peripheral Interface, SPI Mode
13-1
13.1 USART Peripheral Interface
The USART peripheral interface connects to the CPU as a byte-peripheral module. It connects the MSP430 to the external system environment with three or four external pins. Figure 13-1 shows the USART peripheral-interface module
Figure 13-1. Block Diagram of USART
Receive Status Receive Buffer URXBUF SYNC RXE
Listen 0 1
MM 1 0
SYNC SOMI SYNC 0 STE
Receive Shift Register SSEL1 SSEL0 UCLKI ACLK MCLK MCLK 0 1 2 3 Baud-Rate Generator URXD
SYNC
Baud-Rate Register UBR SYNC UCLKS 1 0 UTXD
Baud-Rate Generator
WUT
Transmit Shift Register
SIMO
TXWake
Transmit Buffer UTXBUF
CKPH
SYNC
CKPL UCLK
UCLKI UCLKS
Clock Phase and Polarity
13-2
13.2 USART Peripheral Interface, SPI Mode
The USART peripheral interface is a serial channel that shifts a serial bit stream of 7 or 8 bits in and out of the MSP430. The SPI mode is chosen when control bit SYNC in the USART control register (UCTL) is set.
13.2.1 SPI Mode Features
The features of the SPI mode are:
-
Supports three-pin and four-pin SPI operations via SOMI, SIMO, UCLK, and STE Master or slave mode Separate shift registers for receive (URXBUF) and transmit (UTXBUF) Double buffers for receiving and transmitting Has clock-polarity and clock-phase control Has clock-frequency control in master mode Supports a character length of seven or eight bits per character
Figure 13-2 shows the USART module in SPI mode.
Figure 13-2. Block Diagram of USART--SPI Mode
SYNC = 1 Receive Status Receive Buffer URXBUF Listen 0 1 SSEL1 SSEL0 UCLKI ACLK MCLK MCLK 0 1 2 3 Baud-Rate Generator SYNC STE Baud-Rate Register SYNC UCLKS MSB First 1 0 Transmit Buffer UTXBUF CKPH SYNC CKPL UCLK Clock Phase and Polarity SIMO MM 1 0 SOMI
Receive Shift Register
MSB First
Baud-Rate Generator
Transmit Shift Register
(UCLKI) UCLKS
USART Peripheral Interface, SPI Mode
13-3
Synchronous Operation
13.3 Synchronous Operation
In USART synchronous mode, data and clock signals transmit and receive serial data. The master supplies the clock and data. The slaves use this clock to shift serial information in and out. The four-pin SPI mode also uses a control line to enable a slave to receive and transmit data. The line is controlled by the master. Three or four signals are used for data exchange:
-
SIMO
Slave in, master out The direction is defined by SIMODIR (SIMODIR=0, input direction) SIMODIR = [SYNC .and. MM .and. (STC .or. STE)] Output direction is selected when SPI + Master Mode is selected. When 4-pin SPI is selected (STC=0) input direction is forced by a low level on external STE pin. Slave out, master in The direction is defined by SOMIDIR (SIMODIR=0 input direction) SOMIDIR = [SYNC .and. .not.(MM)] .or. [STC .or. .not.(STE)] Output direction is selected when SPI + Slave Mode is selected. When 4-pin SPI is selected (STC=0) input direction is forced by a low level on external STE pin. USART clock. The master drives this signal and the slave uses it to receive and transmit data. The direction is defined by UCLKDIR (UCLKDIR=0 input direction) UCLKDIR = [SYNC .and. MM .and. (STC .or. STE)] Output direction is selected when SPI + Master Mode is selected. When 4-pin SPI is selected (STC=0) input direction is forced by a low level on external STE pin. Slave transmit enable. Used in four-pin mode to control more than one slave in a multiple master and slave system.
-
SOMI
-
UCLK
-
STE
The interconnection of the USART in synchronous mode to another device's serial port with one common transmit/receive shift register is shown in Figure 13-3, where MSP430 is master or slave. The operation of both devices is identical.
13-4
Synchronous Operation
Figure 13-3. MSP430 USART as Master, External Device With SPI as Slave
MASTER SIMO SIMO SLAVE
Receive Buffer URXBUF
Transmit Buffer UTXBUF Px.x STE STE SS Port.x SOMI
SPI Receive Buffer
Receive Shift Register MSB LSB
Transmit Shift Register MSB LSB
SOMI
Data Shift Register (DSR) MSB LSB COMMON SPI
UCLK MSP430 USART
SCLK
The master initiates the transfer by sending the UCLK signal. For the master, data is shifted out of the transmit shift register on one clock edge, and shifted into the receive shift register on the opposite edge. For the slave, the data shifting operation is the same and uses one common register for transmitting and receiving data. Master and slave send and receive data at the same time. Whether the data is meaningful or dummy data depends on the application software:
-
Master sends data and slave sends dummy data Master sends data and slave sends data Master sends dummy data and slave sends data
Figures 13-4 and 13-5 show an example of a serial synchronous data transfer for a character length of seven bits. The initial content of the receive shift register is 00. The following events occur in order: A) Slave writes 98h to the data shift register (DSR) and waits for the master to shift data out. B) Master writes B0h to UTXBUF, which is immediately transferred to the transmit shift register, and starts the transmission. C) First character is finished and sets the interrupt flags. D) Slave reads 58h from the receive buffer (right justified). E) Slave writes 54h to the DSR and waits for the master to shift out data. F) Master reads 4Ch from the receive buffer URXBUF (right justified). G) Master writes E8h to the transmit buffer UTXBUF and starts the transmission. Note: If USART is in slave mode, no UCLK is needed after D), until G). However, in master mode, two clocks are used internally (not on UCLK signal) to end transmit/receive of first character and prepare the transmit/receive of the next character.
USART Peripheral Interface, SPI Mode
13-5
Synchronous Operation
H) Second character is finished and sets the interrupt flag. I) Master receives 2Ah and slave receives 74h (right justified).
Figure 13-4. Serial Synchronous Data Transfer
CKPL = 0 CKPLH= 0 CKPL = 1 CKPLH= 0 SIMO From Master SOMI From Slave STE Master Interrupt UTXIFG Slave Interrupt URXIFG Shift Data Out Shift Data In AB 7 6 5 4 3 2 CD EF G 1 7 6 5 4 3 2 HI 1
Figure 13-5. Data Transfer Cycle
MSB A: 98h> DSR LSB S B: B0h> UTXBUF MSB LSB M 10011000 10110000
C,F: URXBUF
01001100 M
C,D: DSR
01011000
S
from Initial State E: 54h> DSR 01010100 S G:E8h> UTXBUF 11101000 M
H,I: URXBUF
00101010
M
H,I: DSR
01110100
S
In 7 bit mode, the MSB of RXBUF is always read as 0. S: Slave M: Master
13-6
Synchronous Operation
Figure 13-6 illustrates the USART module functioning as a slave in a three or four-pin SPI configuration.
Figure 13-6. MSP430 USART as Slave in Three-Pin or Four-Pin Configuration
MASTER SIMO SIMO SLAVE
SPI Receive Buffer Px.x STE STE SS Port.x SOMI
Transmit Buffer UTXBUF
Receive Buffer URXBUF
Data Shift Register DSR MSB LSB
SOMI
Transmit Shift Register MSB LSB
Receive Shift Register MSB LSB
SCLK COMMON SPI
UCLK MSP430 USART
13.3.1 Master SPI Mode
The master mode is selected when the master-mode bit (MM) in control register UCTL is set. The USART module controls the serial-communication network by providing UCLK at the UCLK pin. Data is output on the SIMO pin during the first UCLK period and latched from the SOMI pin in the middle of the corresponding UCLK period. The data written to the transmit buffer (UTXBUF) is moved to the transmit shift register as soon as the shift register is empty. This initiates the data transfer on the SIMO pin starting with the most-significant bit. At the same time, received data is shifted into the receive shift register and, upon receiving the selected number of bits, the data is transferred to the receive buffer (URXBUF) setting the receive interrupt flag (URXIFG). Data is shifted into the receive shift register starting with the most-significant bit. It is stored and right-justified in the receive buffer (URXBUF). When previous data is not read from the receive buffer (URXBUF), the overrun error bit (OE) is set. Note: USART Synchronous Master Mode, Receive Initiation The master writes data to the transmit buffer UTXBUF to receive a character. The receive starts when the transmit shift register is empty and the data is transferred to it. Receive and transmit operations always take place together, at opposite clock edges. The protocol can be controlled using the transmit-interrupt flag UTXIFG, or the receive-interrupt flag URXIFG. By using UTXIFG immediately after sending the shift-register data to the slave, the buffer data is transferred to the shift register and the transmission starts. The slave receive timing should ensure that there is a timely pick-up of the data. The URXIFG flag indicates when the data shifts out and in completely. The master can use URXIFG to ensure that the slave is ready to correctly receive the next data.
USART Peripheral Interface, SPI Mode
13-7
Synchronous Operation
13.3.1.1 Four-Pin SPI Master Mode
The signal on STE is used by the active master to prevent bus conflicts with another master. The STE pin is an input when the corresponding PnSEL bit (in the I/O registers) selects the module function. The master operates normally while the STE signal is high. Whenever the STE signal is low, for example, when another device makes a request to become master, the actual master reacts such that:
-
The pins that drive the SPI bus lines SIMO and UCLK are set to inputs. The error bit FE and the interrupt flag URXIFG in register URCTL are set.
The bus conflict is then removed: SIMO and UCLK do not drive the bus lines, and the error flag indicates the system integrity violation to the software. Pins SIMO and UCLK are forced to the input state while STE is in a low state, and they return to the conditions defined by the corresponding control bits when STE returns to a high state. In the three-pin mode, the STE input signal is not relevant.
13.3.2 Slave SPI Mode
The slave mode is selected when bit MM of the control register is reset and synchronous mode is selected. The UCLK pin is used as the input for the serial-shift clock supplied by an external master. The data-transfer rate is determined by this clock and not by the internal bit-rate generator. The data, loaded into the transmit shift register through the transmit buffer (UTXBUF) before the start of UCLK, is transmitted on the SOMI pin using the UCLK supplied from the master. Simultaneously, the serial data applied to the SIMO pin are shifted into the receive shift register on the opposite edge of the clock. The receive-interrupt flag URXIFG indicates when the data is received and transferred into the receive buffer. The overrun-error bit is set when the previously-received data is not read before the new data is written to the receive buffer.
13.3.2.1 Four-Pin SPI Slave Mode
In the four-pin SPI mode, the STE signal is used by the slave to enable the transmit and receive operations. It is applied from the SPI master. The receive and transmit operations are disabled when the STE signal is high, and enabled when it is low. Whenever the STE signal becomes high, any receive operation in progress is halted and then continues when the STE signal is low again. The STE signal enables one slave to access the data lines. The SOMI is input if STE is set high.
13-8
Interrupt and Control Functions
13.4 Interrupt and Control Functions
The USART peripheral interface serves two main interrupt sources for transmission and reception. Two interrupt vectors serve receive and transmit interrupt events. The interrupt control bits and flags and enable bits of the USART peripheral interface are located in the SFR address range. The bit functions are described below in Table 13-1. See the peripheral-file map in Appendix A for the exact bit locations.
Table 13-1.USART Interrupt Control and Enable Bits--SPI Mode
Receive interrupt flag Receive interrupt enable Receive/transmit enable (see Note) Transmit interrupt flag Transmit interrupt enable
Note:
URXIFG URXIE USPIIE UTXIFG UTXIE
Initial state reset (by PUC/SWRST) Initial state reset (by PUC/SWRST) Initial state reset (by PUC) Initial state set (by PUC/SWRST) Initial state reset (by PUC/SWRST)
Different for UART mode, see Chapter 12.
The USART receiver and transmitter operate in parallel and use the same baud-rate generator in synchronous master mode. In synchronous slave mode, the external clock applied to UCLK is used for the receiver and the transmitter. The receiver and transmitter are enabled and disabled together with the USPIIE bit.
13.4.1 USART Receive/Transmit Enable Bit, Receive Operation
The receive/transmit enable bit (USPIIE) enables or disables collection of the bit stream on the URXD/SOMI data line. Disabling the USART receiver (USPIIE = 0) stops the receive operation after completion, or stops a pending operation if no receive operation is active. In synchronous mode, UCLK does not shift any data into the receiver shift register.
13.4.1.1 Receive/Transmit Enable Bit--MSP430 as Master
The receive operation functions identically for three-pin and four-pin modes, as shown in Figure 13-7, when the MSP430 USART is selected to be the SPI master.
USART Peripheral Interface, SPI Mode
13-9
Interrupt and Control Functions
Figure 13-7. State Diagram of Receiver Enable Operation--MSP430 as Master
USPIIE = 0 USPIIE = 1 Receive Disable USPIIE = 0 SWRST PUC USPIIE = 0 No Data Written to UTXBUF Not Completed
Idle State (Receiver Enabled)
USPIIE = 1
Receiver Collects Character
Handle Interrupt Conditions Character Received
USPIIE = 1
13.4.1.2 Receive/Transmit Enable Bit--MSP430 as Slave, Three-Pin Mode
The receive operation functions differently for three-pin and four-pin modes when the MSP430 USART module is selected to be the SPI slave. In the three-pin mode, shown in Figure 13-8, no external SPI receive-control signal stops an active receive operation. A PUC signal, a software reset (SWRST), or a receive/transmit enable (USPIIE) signal can stop a receive operation and reset the USART.
Figure 13-8. State Diagram of Receive/Transmit Enable--MSP430 as Slave, Three-Pin Mode
USPIIE = 0 No Clock at UCLK Not Completed
USPIIE = 1 Receive Disable USPIIE = 0 SWRST PUC
Idle State (Receive Enabled)
USPIIE = 1 External Clock Present USPIIE = 1
Receiver Collects Character
Handle Interrupt Conditions Character Received
USPIIE = 0
Note: USPIIE Re-Enabled, SPI Mode After the receiver is completely disabled, a reenabling of the receiver is asynchronous to any data stream on the communication line. Synchronization to the data stream is handled by the software protocol in three-pin SPI mode.
13.4.1.3 Receive/Transmit Enable Bit--MSP430 as Slave, Four-Pin Mode
In the four-pin mode, shown in Figure 13-9, the external SPI receive-control signal applied to pin STE stops a started receive operation. A PUC signal, a software reset (SWRST), or a receive/transmit enable (USPIIE) can stop a receive operation and reset the operation-control state machine. Whenever the STE signal is set to high, the receive operation is halted.
13-10
Interrupt and Control Functions
Figure 13-9. State Diagram of Receive Enable--MSP430 as Slave, Four-Pin Mode
USPIIE = 0 USPIIE = 1 and STE = 0 Receive Disable USPIIE = 0 SWRST PUC USPIIE = 0 No Clock at UCLK Not Completed USPIIE = 1 Receiver Collects Character Handle Interrupt Conditions Character Received
Idle State (Receive Enabled)
USPIIE = 1 External Clock Present USPIIE = 1
13.4.2 USART Receive/Transmit Enable Bit, Transmit Operation
The receive/transmit enable bit USPIIE, shown in Figures 13-10 and 13-11, enables or disables the shifting of a character on the serial data line. If this bit is reset, the transmitter is disabled, but any active transmission does not halt until all data previously written to the transmit buffer is transmitted. If the transmission is completed, any further write operation to the transmitter buffer does not transmit. When the UTXBUF is ready, any pending request for transmission remains, which results in an immediate start of transmission when USPIIE is set and the transmitter is empty. A low state on the STE signal removes the active master (four-pin mode) from the bus. It also indicates that another master is requesting the active-master function.
13.4.2.1 Receive/Transmit Enable--MSP430 as Master
Figure 13-10 shows the transmit-enable activity when the MSP430 is master.
Figure 13-10. State Diagram of Transmit Enable--MSP430 as Master
USPIIE = 0 No Data Written to Transfer Buffer Not Completed USPIIE = 1
Transmit Disable
USPIIE = 1, Data Written to USPIIE = 1 Idle State Transmit Buffer Transmission (Transmitter Active Enabled) USPIIE = 0 SWRST USPIIE = 1
Handle Interrupt Conditions Character Transmitted
PUC USPIIE = 0 And Last Buffer Entry Is Transmitted
USART Peripheral Interface, SPI Mode
13-11
Interrupt and Control Functions
13.4.2.2 Receive/Transmit Enable, MSP430 is Slave
Figure 13-11 shows the receive/transmit-enable-bit activity when the MSP430 is slave.
Figure 13-11.State Diagram of Transmit Enable--MSP430 as Slave
USPIIE = 0 No Clock at UCLK Not Completed USPIIE = 1
USPIIE = 1 Transmit Disable USPIIE = 0 SWRST
Idle State (Transmitter Enabled)
Transmission Active External Clock Present USPIIE = 1
USPIIE = 1
Handle Interrupt Conditions Character Transmitted
PUC
USPIIE = 0
When USPIIE is reset, any data can be written regularly into the transmit buffer, but no transmission is started. Once the USPIIE bit is set, the data in the transmit buffer are immediately loaded into the transmit shift register and character transmission is started. Note: Writing to UTXBUF, SPI Mode Data should never be written to transmit buffer UTXBUF when the buffer is not ready (UTXIFG = 0) and the transmitter is enabled (USPIIE is set). If data is written, character shifting can be random.
Note: Write to UTXBUF/Reset of Transmitter, SPI Mode Disabling of the transmitter should be done only if all data to be transmitted have been moved to the transmit shift register.
MOV.B BIC.B #....,&UTXBUF #USPIIE,&ME2 ; ; ; ; ; If BITCLK < MCLK then the transmitter might be stopped before the buffer is loaded into the transmitter shift register
13-12
Interrupt and Control Functions
13.4.3 USART Receive-Interrupt Operation
In the receive-interrupt operation shown in Figure 13-12, the receive-interrupt flag URXIFG is set each time a character is received and loaded into the receive buffer.
Figure 13-12. Receive Interrupt Operation
SYNC Valid Start Bit Receiver Collects Character URXSE From URXD URXS SYNC = 1
Clear URXIE
PE FE BRK URXEIE URXWIE RXWake
SYNC (S) URXIFG Clear Character Received or Master Overrun
Request_ Interrupt_Service
SWRST PUC URXBUF Read USPIIE IRQA
URXIFG is reset by a system reset PUC signal, or by a software reset (SWRST). URXIFG is reset automatically if the interrupt is served or the receive buffer URXBUF is read. The receive interrupt enable bit (USPIIE), if set, enables a CPU interrupt request as shown in Figure 13-13. The receive interrupt flag bits URXIFG and USPIIE are reset with a PUC signal or a SWRST.
Figure 13-13. Receive Interrupt State Diagram
Wait For Next Start USPIIE = 1 Receive Character Completed URXIFG = 0 SWRST = 1 PUC USPIIE = 0 USPIIE = 1 and GIE = 1 and Priority Valid Interrupt Service Started, GIE = 0 URXIFG = 0
URXIFG = 1
Priority Too GIE = 0 Low
USART Peripheral Interface, SPI Mode
13-13
Interrupt and Control Functions
13.4.4 Transmit-Interrupt Operation
In the transmit-interrupt operation shown in Figure 13-14, the transmitinterrupt flag UTXIFG is set by the transmitter to indicate that the transmitter buffer UTXBUF is ready to accept another character. This bit is automatically reset if the interrupt-request service is started or a character is written to the UTXBUF. This flag activates a transmitter interrupt if bits USPIIE and GIE are set. The UTXIFG is set after a system reset PUC signal, or removal of SWRST.
Figure 13-14. Transmit-Interrupt Operation
Q USPIIE SYNC = 1
Clear PUC or SWRST Set UTXIFG DQ SWRST Clear UTXBUF Written Into Transmit Shift Register IRQA Request_ Interrupt_Service
VCC Character Moved From Buffer to Shift Register
The transmit-interrupt enable bit UTXIE controls the ability of the UTXIFG to request an interrupt, but does not prevent the UTXIFG flag from being set. The USPIIE is reset with a PUC signal or a SWRST. The UTXIFG bit is set after a system reset PUC signal or a SWRST, but the USPIIE bit is reset to ensure full interrupt-control capability.
13-14
Control and Status Registers
13.5 Control and Status Registers
The USART registers, shown in Table 13-2, are byte structured and should be accessed using byte instructions.
Table 13-2.USART Control and Status Registers
Register USART control Transmit control Receive control Modulation control Baud Rate 0 Baud Rate 1 Receive buffer Transmit buffer Short Form UCTL UTCTL URCTL UMCTL UBR0 UBR1 URXBUF UTXBUF Register Type Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read Address 070h 071h 072h 073h 074h 075h 076h 077h Initial State See Section 13.5.1 See Section 13.5.2 See Section 13.5.3 Unchanged Unchanged Unchanged Unchanged Unchanged
All bits are random following the PUC signal, unless otherwise noted by the detailed functional description. Reset of the USART module is performed by the PUC signal or a SWRST. After a PUC signal, the SWRST bit remains set and the USART module remains in the reset condition. It is disabled by resetting the SWRST bit. The SPI mode is disabled after the PUC signal. The USART module operates in asynchronous or synchronous mode as defined by the SYNC bit. The bits in the control registers can have different functions in the two modes. All bits are described with their function in the synchronous mode--SYNC = 1. Their function in the asynchronous mode is described in Chapter 12.
13.5.1 USART Control Register
The information stored in the control register, shown in Figure 13-15, determines the basic operation of the USART module. The register bits select the communication mode and the number of bits per character. All bits should be programmed to the desired mode before resetting the SWRST bit.
Figure 13-15. USART Control Register
7 UCTL 070h
Unused Unused Unused CHAR Listen SYNC MM
0
SWRST
rw-0
rw-0
rw-0
rw-0 rw-0
rw-0
rw-0
rw-1
USART Peripheral Interface, SPI Mode
13-15
Control and Status Registers
Bit 0:
The USART state machines and operating flags are initialized to the reset condition (URXIFG=USPIIE=0, UTXIFG=1) if the software reset bit is set. Until the SWRST bit is reset, all affected logic is held in the reset state. This implies that after a system reset the USART must be reenabled by resetting this bit. Master mode is selected when the MM bit is set. The USART module slave mode is selected when the MM bit is reset. Peripheral module mode select The SYNC bit sets the function of the USART peripheralinterface module. Some of the USART control bits have different functions in UART and SPI modes. SYNC = 0: UART function is selected SYNC = 1: SPI function is selected The listen bit determines the transmitted data to feed back internally to the receiver. This is commonly called loopback mode. Character length This register bit sets the length of the character to be transmitted as either seven or eight bits. CHAR = 0: 7-bit data CHAR = 1: 8-bit data Unused Unused Unused
Bit 1: Bit 2:
Bit 3:
Bit 4:
Bit 5: Bit 6: Bit 7:
13.5.2 Transmit Control Register UTCTL
The transmit control register (UTCTL), shown in Figure 13-16, controls the USART hardware associated with transmitter operations.
Figure 13-16. Transmit Control Register UTCTL
7 UTCTL 071h
CKPH CKPL SSEL1 SSEL0 Unused Unused STC
0
TXEPT
rw-0
rw-0
rw-0
rw-0 rw-0
rw-0
rw-0
rw-1
Bit 0:
Master mode: The transmitter-empty flag TXEPT is set when the transmitter shift register and UTXBUF are empty, and reset when data are written to UTXBUF. It is set again by a SWRST. Slave mode: The transmitter-empty flag TXEPT is not set when the transmitter shift register and UTXBUF are empty.
Bit 1:
The slave transmit-control bit STC selects if the STE pin is used for master and slave mode:
13-16
Control and Status Registers
STC = 0:
STC = 1: Bit 2: Bit 3: Bits 4, 5: Unused Unused
The four-pin mode of SPI is selected. The STE signal is used by the master to avoid bus conflicts, or is used in slave mode to control transmit and receive enable. The three-pin SPI mode is selected. STE is not used in master or slave mode.
Source select 0 and 1 The source-select bits define which clock source is used for baud-rate generation only when master mode is selected: SSEL1,SSEL0 0 External clock UCLK selected 1 Auxiliary clock ACLK selected 2, 3 MCLK In master mode (MM = 1), an external clock at UCLK cannot be selected since the master supplies the UCLK signal for any slave. In slave mode, bits SSEL1 and SSEL0 are not relevant. The external clock UCLK is always used. Clock polarity CKPL and clock phase CKPH The CKPL bit controls the polarity of the SPICLK signal. CKPL = 0: The inactive level is low; data is output with the rising edge of UCLK; input data is latched with the falling edge of UCLK. CKPL = 1: The inactive level is high; data is output with the falling edge of UCLK; input data is latched with the rising edge of SPICLK. The CKPH bit controls the polarity of the SPICLK signal as shown in Figure 13-17. CKPH = 0: Normal UCLK clocking scheme CKPH = 1: UCLK is delayed by one half cycle
Bits 6, 7:
Figure 13-17. USART Clock Phase and Polarity
CKPL CKPH 0 0 0 1 1 0 1 1 x x 0 Cycle# UCLK UCLK UCLK UCLK LSB LSB 1 2 3 4 5 6 7 8
SIMO/ MSB SOMI * SIMO/ 1 SOMI * MSB Data to TXBUF Receive Sample Points
*Previous Data Bit
USART Peripheral Interface, SPI Mode
13-17
Control and Status Registers
When operating with the CKPH bit set, the USART (synchronous mode) makes the first bit of data available after the transmit shift register is loaded and before the first edge of the UCLK. In this mode, data is latched on the first edge of UCLK and transmitted on the second edge.
13.5.3 Receive Control Register URCTL
The receive control register (URCTL), shown in Figure 13-18, controls the USART hardware associated with the receiver operation and holds error conditions.
Figure 13-18. Receive Control Register URCTL
7 URCTL 072h
FE Undef. OE Undef. Unused Unused Undef.
0
Undef.
rw-0
rw-0
rw-0 rw-0
rw-0
rw-0
rw-0 rw-0
Bit 0: Bit 1: Bit 2: Bit 3: Bit 4: Bit 5:
Undefined, driven by USART hardware Undefined, driven by USART hardware Unused Unused Undefined, driven by USART hardware The overrun-error-flag bit (OE) is set when a character is transferred to URXBUF before the previous character is read. The previous character is overwritten and lost. OE is reset by a SWRST, a system reset, by reading the URXBUF, or by an instruction. Undefined, driven by USART hardware Frame error. The FE bit is set when four-pin mode is selected and a bus conflict stops an active master by applying a negative transition signal to pin STE. FE is reset by a SWRST, a system reset, by reading the URXBUF, or by an instruction.
Bit 6: Bit 7:
13.5.4 Baud Rate Select and Modulation Control Registers
The baud-rate generator uses the content of baud-rate select registers UBR1 and UBR0, shown in Figure 13-19, to generate the serial-data-stream bit timing. The smallest division factor is two.
Figure 13-19. USART Baud-Rate Select Register
7 UBR0 074h
27 rw 26 rw 25 rw 24 rw 23 rw 22 rw 21 rw
0
20 rw
7 UBR1 075h
215 rw 214 rw 213 rw 212 rw 211 rw 210 rw 29 rw
0
28 rw
13-18
Control and Status Registers
Baud rate =
BRCLK UBR
)
1 n
Smi i
n
with UBR= [UBR1,UBR0]
The maximum baud rate that can be selected for transmission in master mode is half of the clock-input frequency of the baud-rate generator. In slave mode, the rate is determined by the external clock applied to UCLK. The modulation control register, shown in Figure 13-20, is not used for serial synchronous communication. It is best kept in reset mode (bits m0 to m7 = 0).
Figure 13-20. USART Modulation Control Register
7 UMCTL 073h
m7 m6 m5 m4 m3 m2 m1
0
m0
rw
rw
rw
rw
rw
rw
rw
rw
13.5.5 Receive Data Buffer URXBUF
The receive data buffer (URXBUF), shown in Figure 13-21, contains previous data from the receiver shift register. URXBUF is cleared with a SWRST or a PUC signal. Reading URXBUF resets the receive-error bits and the receiveinterrupt flag URXIFG.
Figure 13-21. Receive Data Buffer URXBUF
7 URXBUF 076h
27 rw 26 rw 25 rw 24 rw 23 rw 22 rw 21 rw
0
20 rw
The MSB of the URXBUF is always reset in seven-bit-length mode.
13.5.6 Transmit Data Buffer UTXBUF
The transmit data buffer (UTXBUF), shown in Figure 13-22, contains current data for the transmitter to transmit.
Figure 13-22. Transmit Data Buffer UTXBUF
7 UTXBUF 077h
27 rw 26 rw 25 rw 24 rw 23 rw 22 rw 21 rw
0
20 rw
The UTXIFG bit indicates that UTXBUF is ready to accept another character for transmission. In master mode, the transmission is initialized by writing data to UTXBUF. The transmission of this data is started immediately if the transmit shift register is empty. When seven-bit character-length is used, the data moved into the transmit buffer must be left-justified since the MSB is shifted out first.
USART Peripheral Interface, SPI Mode
13-19
13-20
Chapter 14
Liquid Crystal Display Drive
This chapter describes the MSP430x3xx liquid crystal display (LCD) driver.
Topic
Page
14.1 LCD Drive Basics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-2 14.2 LCD Controller/Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-7 14.3 Code Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-21
Liquid Crystal Display Drive
14-1
LCD Drive Basics
14.1 LCD Drive Basics
LCDs must be driven with ac voltages. DC voltage signals applied to LCD segments can harm and even destroy an LCD. The LCD controller/driver on the MSP430 devices simplifies the use of LCD displays by creating the ac voltage signals automatically.
Static LCDs have one pin for each segment and one pin for the ground plane, so one can see how the pin-counts of large LCDs with many segments could easily become cumbersome. For example, an 80-segment, static LCD requires 81 pins. To reduce pin-counts, LCDs are often multiplexed. This means the individual LCD segments are arranged in a matrix of the segment pins and common pins, such that each LCD segment has a unique combination of a segment pin and a common pin for activation, but each segment pin can be used for more than one segment. For example, a 2-MUX LCD contains one segment pin for every two segments and 2 common layers, each with a pin. The two segments that share any pin are connected to different common layers for individual control. The table below shows a possible pin configuration for a 2-MUX, 16-segment LCD. There are 10 total pins.
Pin 1 Pin 2 Pin 3 Pin 4 Pin 5 Pin 6 Pin 7 Pin 8 segment 1 segment 3 segment 5 segment 7 segment 9 segment 11 segment 13 segment 15 common pin 0 segment 2 segment 4 segment 6 segment 8 segment 10 segment 12 segment 14 segment 16 common pin 1
LCDs with more common planes realize greater pin-count reductions. For example, a possible pin configuration of a 4-MUX, 16-segment LCD is shown below. This LCD has 8 total pins for a reduction of 2 pins over the 2-MUX configuration above. 2 pins is generally not significant, however, in the case of a 132-segment LCD for example, the required pins for a 2-MUX version would be 68 (132/2 +2), whereas the required pins for a 4-MUX version would be 37 (132/4 +4).
Pin 1 Pin 2 Pin 3 Pin 4 segment 1 segment 5 segment 9 segment 13 common pin 0 segment 2 segment 6 segment 10 segment 14 common pin 1 segment 3 segment 7 segment 11 segment 15 common pin 2 segment 4 segment 8 segment 12 segment 16 common pin 3
14-2
LCD Drive Basics
Because of the multiplexing of segments with segment pins, the required drive signals for the segment pins and common pins can be complicated. Each segment and common pin of a multiplexed LCD requires a time-division-multiplexed signal in order to only turn on the desired segments and to avoid having a dc voltage on any segment. Some examples of segment and common signals are shown below. Fortunately for the user, the MSP430 creates all these signals automatically. With static LCDs, each segment pin drives one segment. Figure 14-1 shows some example waveforms with a typical pin assignment.
Figure 14-1. Static Wave-Form Drive
VDD COM0 GND fframe VDD GND VDD SP2 GND VDD SP2 SP7 SP3 SP5 SP4 SP = Segment Pin Resulting Voltage for Segment a (COM0-SP1), Segment Is On. 0V -VDD SP8 Resulting Voltage for Segment b (COM0-SP2), Segment Is Off. 0V
SP1 COM0
SP6
SP1
a b
Liquid Crystal Display Drive
14-3
LCD Drive Basics
With 2-MUX LCDs, each segment pin drives two segments (see Figure 14-2).
Figure 14-2. Two-MUX Wave-Form Drive
COM1 VDD -V3 = VDD/2 GND VDD -V3 = VDD/2 GND VDD SP1 GND SP2
b
COM0 fframe COM1 COM0
VDD GND VDD VDD/2 0V VDD/2 -VDD VDD VDD/2 0V VDD/2 -VDD
SP1 Resulting Voltage for Segment h (COM0-SP2), Segment Is On.
h
SP4 SP3
SP2
SP = Segment Pin Resulting Voltage for Segment b (COM1-SP2), Segment Is Off.
14-4
LCD Drive Basics
With three-MUX LCDs, each segment line drives three segments.
Figure 14-3. Three-MUX Wave-Form Drive
COM2 COM0 fframe COM1 COM1 VDD -V2 = 2/3VDD -V4 = 1/3VDD GND VDD -V2 = 2/3VDD -V4 = 1/3VDD GND VDD -V2 = 2/3VDD -V4 = 1/3VDD GND VDD -V2 = 2/3VDD -V4 = 1/3VDD GND VDD e d SP1 SP3 SP2 SP3 GND VDD VDD SP2 GND
COM0
COM2
SP1
SP = Segment Pin Resulting Voltage for Segment e (COM0-SP1), Segment Is Off.
0V -VDD VDD
Resulting Voltage for Segment d (COM0-SP2), Segment Is On.
0V -VDD
Liquid Crystal Display Drive
14-5
LCD Drive Basics
With 4-MUX LCDs, each segment pin drives four segments.
Figure 14-4. Four-MUX Wave-Form Drive
COM3 COM0 COM2 COM1 fframe VDD -V2 = 2/3 VDD -V4 = 1/3 VDD GND VDD -V2 = 2/3 VDD -V4 = 1/3 VDD GND VDD -V2 = 2/3 VDD -V4 = 1/3 VDD GND VDD -V2 = 2/3 VDD -V4 = 1/3 VDD GND VDD -V2 = 2/3 VDD -V4 = 1/3 VDD GND VDD -V2 = 2/3 VDD -V4 = 1/3 VDD GND VDD 0V -VDD VDD 0V -VDD
COM1
COM0
COM2
COM3
SP1 e c SP2 SP1 SP2
SP = Segment Pin Resulting Voltage for Segment e (COM1-SP1), Segment Is Off.
Resulting Voltage for Segment c (COM1-SP2), Segment Is On.
14-6
LCD Controller/Driver
14.2 LCD Controller/Driver
The LCD controller/driver peripheral, shown in Figure 14-5, contains all the functional blocks and generates the segment and common signals required to drive an LCD.
Figure 14-5. LCD Controller/Driver Block Diagram
S29/O29/ CMPI S28/O28
Mux Group 7 Display Memory 15x8 Bit Mux Group 1 Mux
DCTL
Segment Output Control DCTL Seg 2 S2/O2
Seg 1
S1
Mux
ADR 31h - 3Fh
Seg 0
S0
Group 1-7 LCD LCDM2 Control and 7 Mode Group 1-7 Register PUC ADR: 30h LCDM0 LCDM3 LCDM4 7 Group1-7 Common Output Control COM3 COM2 COM1 COM0
LCDM1 Analog Voltage Multiplexer fLCD OscOff Timing Generator
R33 R23 R13 R03
Liquid Crystal Display Drive
14-7
LCD Controller/Driver
14.2.1 LCD Controller/Driver Features
The LCD controller/driver features are:
-
Display memory Automatic signal generation Support for 4 types of LCDs:
-
J J J J
Static 2 MUX, 1/2 bias 3 MUX, 1/3 bias 4 MUX, 1/3 bias
Multiple frame frequencies Unused segment outputs may be used as general-purpose outputs. Unused display memory may be used as normal memory Operates using the basic timer with the auxiliary clock (ACLK).
The LCD-line frame frequencies include: 1f f frame Static mode: LCD 2 2 MUX: 3 MUX: 4 MUX:
+ f frame + 1 4 f frame + 1 6 f frame + 1 8
f LCD f LCD f LCD
14.2.2 LCD Timing Generation
The LCD controller uses the fLCD signal from the Basic Timer1 (discussed in Chapter 10) to generate the timing for common and segment lines. The frequency fLCD of signal is generated from ACLK. Using a 32,768-Hz crystal, the fLCD frequency can be 1024 Hz, 512 Hz, 256 Hz, or 128 Hz. Bits FRFQ1 and FRFQ0 allow the correct selection of frame frequency. The proper frequency fLCD depends on the LCD's requirement for framing frequency and LCD multiplex rate, and is calculated by: fLCD = 2 x MUX rate x fFraming A 3 MUX example follows: LCD data sheet: fFraming = 100 Hz .... 30 Hz FRFQ: fLCD = 6 x fFraming fLCD = 6 x 100 Hz = 600 Hz ... 6 x 30 Hz = 180 Hz Select fLCD: 1024 Hz, 512 Hz, 256 Hz, or 128 Hz fLCD = 32,768/128 = 256 Hz FRFQ1 = 1; FRFQ0 = 0
14-8
LCD Controller/Driver
14.2.3 LCD Voltage Generation
The voltages required for the LCD signals are supplied externally and are applied to pins R33, R23, R13, and R03 (see Figure 14-6). Generally, the voltages are generated with an equal-weighted resistor ladder. Note that pins R33 and R03 are not present on all MSP430 devices. Check the datasheet for the presence of these pins. When pins R33 and R03 are not preset, voltage V1 is tied to VCC and voltage V5 is tied to VSS internally. When these pins are present, they provide two advantages to the user. First, R33 is a switched-VCC output. This allows the power to the resistor ladder to be turned off reducing current consumption. Also, when these pins are present, R03 is not tied internally to VSS. This allows the user to control the offset of the LCD voltages thereby providing for temperature compensation or contrast adjustment. If this not desired, the user may simply connect R03 to VSS.
Figure 14-6. External LCD Module Analog Voltage
Analog Levels VCC Segn COMn Voltage Connections For the Different Modes: 3Mux Static 2Mux 4Mux VCC R R23 V2 VSS (R23 Open) R R13 V4 VSS R
VA VB
VC VD
Ron
R33 V1
V3 Analog MUX
R LCD Phases LCDM0 LCDM3 LCDM4 OscOff OscOff X 1 0 0 0 LCDM4 LCDM3 LCDM0 0 X X X X X 1 0 0 1 1 0 1 X 1 VA 0 0 V5/V1 V5/V1 V5/V1 R03 V5 VSS
R
VB 0 0 V1/V5 V1/V5 V2/V4
VD VC 0 0 0 0 V5/V1 V1/V5 V3/V3 V1/V5 V4/V2 V1/V5
RON OFF OFF ON ON ON
Indicates the position of the Ron switch, controlled by the LCDM0 bit. Supply pins for V1 and V5 are optional. Devices without R33 and R03 pins have V1 tied to VCC and V5 tied to VSS. In this case, the resistor ladder should also be tied to VCC and VSS.
Liquid Crystal Display Drive
14-9
LCD Controller/Driver
14.2.4 LCD Outputs
The LCD outputs use transmission gates to transfer the analog voltage to the output pin where they are used to drive liquid crystal displays. Groups of LCD outputs can be configured to operate as digital outputs as shown in Figure 14-7.
Figure 14-7. Schematic of LCD Output
Analog Levels VC VD Control COM0-3 VA VB Control Segment/COM0-3 VA VB Control Segment/COM0-3 (LCDM5, 6, 7) Out2 Data (LCD RAM, Bit 0 to Bit 3 Bit 4 to Bit 7) Outn Seg2 Segn S2/O2 Sn/On Seg0 Seg1 Analog Switches COM0 COM3
NOTE: The signals VA,VB,VC, and VD are from the LCD analog voltage generator.
14-10
LCD Controller/Driver
14.2.4.1 LCD Port as General-Purpose Outputs
The logic level of an Oxx output is defined by the 4 display memory bits assigned to the pin (see Figure 14-8). All 4 bits must have the same value or the output will not be static. For example, if pin S10/O10 is used as a generalpurpose output, Its state is defined by bits 0-3 at memory address 036h and the bits must have the same value.
Figure 14-8. Segment Line or Output Line
Segment Information From Display Memory A 3 2 1 0 Segment Information From Display Memory 3 2 1 0 A 0 G 3 B
Parallel-Serial Conversion
G0 B 3
Parallel-Serial Conversion
Analog Levels Segn
Analog Mux
1
0
Analog Levels Segn Oxx
Sxx
Segment/Port Control
Sxx/Oxx
Sxx/Oxx
Liquid Crystal Display Drive
14-11
Mixed LCD and Port Mode Application
14.2.4.2 Mixed LCD and Port Mode Application
Figure 14-9 illustrates the mixed mode using a four-MUX LCD drive for 13 digits and one port group as digital outputs. In the example below, digital outputs O26 - O29 are defined to be general-purpose outputs by bits LCDM5, LCDM6, and LCDM7 in the LCDCTL register. In this example, the value of the LCDMx bits is 06h.
Figure 14-9. Mixed LCD and Port Mode Application
a f e d
MDB BIT COM 0003Fh 0003Eh 0003Dh 0003Ch 0003Bh 0003Ah 00039h 00038h 00037h 00036h 00035h 00034h 00033h 00032h 00031h 00030h MAB O26 7 3 6 2 5 1 4 0 3 3 2 2 1 1 0 0 S25
a b c h
S24 S1
g
f e
g
b c
d
S0
h
O29
O29 O29 O29 O29 O28 O28 O27 O27 O27 O27 O26 O26 h h h h h h h h h h h h h 1 g g g g g g g g g g g g g 1 f f f f f f f f f f f f f 0 e e e e e e e e e e e e e 1 d d d d d d d d d d d d d 1 c c c c c c c c c c c c c 1
O28 O28 O26 O26 b b b b b b b b b b b b b X a a a a a a a a a a a a a 1 Digit 13 Digit 12 Digit 11 Digit 10 Digit 9 Digit 8 Digit 7 Digit 6 Digit 5 Digit 4 Digit 3 Digit 2 Digit 1 LCDCTL O27 O28
14-12
LCD Port--Timer/Port Comparator Input
14.2.4.3 LCD Port--Timer/Port Comparator Input
The comparator input associated with the Timer/Port module is typically shared with one segment line as shown in Figure 14-10. The LCD segment function is selected for this pin after the PUC signal is active. The comparator input is selected once the CPON bit--located in the Timer/Port module--has been set. Once the CPON bit is set, the comparator input remains selected for the pin until it is deselected by a PUC signal. Therefore, this pin is not available for the LCD function if it is used for the comparator function. Additionally, once selected for the CMPI function, it can not be switched back to the LCD function without a PUC (power-up clear).
Figure 14-10. Schematic of LCD Pin - Timer/Port Comparator
LCD Module Sxx/Oxx
0
Sxx/Oxx/CMPI
CPON PUC CPON 1 CMP 0
S R
1
CMPI
+ _
CPON VCC/4 1 VCC
VSS VSS Timer/Port Module - Schematic detail CIN
NOTE: The comparator is selected with the CPON bit. It remains selected, consumes current, and the comparator reference consumes current as long as the CPON bit is set.
Liquid Crystal Display Drive
14-13
LCD Port--Timer/Port Comparator Input
14.2.5 LCD Control Register
The LCD control register contents define the mode and operating conditions. The LCD module is byte structured and should be accessed using byte instructions (suffix .B). All LCD control register bits are reset with a PUC signal.
Figure 14-11.LCD Control and Mode Register
7 LCDCTL 030h LCDM7 rw-0 LCDM6 rw-0 LCDM5 rw-0 LCDM4 rw-0 LCDM3 rw-0 LCDM2 rw-0 LCDM1 rw-0 0 LCDM0 rw-0
LCDM0:
LCDM0 = 0: The timing generator is switched off. Common and segment lines are low. Ron is off. Outputs selected as port output lines are not affected. LCDM0 = 1: Common and segment lines active. Ron is on. Outputs selected as port output lines are not affected.
LCDM1: LCDM2 to 4:
Not used These three bits select the display mode as described in Table 14-1.
14-14
LCD Port--Timer/Port Comparator Input
Table 14-1.LCDM Selections
LCDM4 X LCDM3 X LCDM2 0 Display Mode All segments are deselected. The port outputs remain stable. This supports flashing LCD applications. Static mode 2 MUX mode 3 MUX mode 4 MUX mode
0 0 1 1
0 1 0 1
1 1 1 1
The primary function of the LCDM2 bit is to support flashing or blinking the LCD. The LCDM2 bit is logically ANDed with each segment's display memory value to turn each LCD segment on or off (see Figure 14-12). When LCDM2=1, each LCD segment is on or off according to the LCD display memory. When LCDM2=0, each LCD segment is off, therefore blanking the LCD.
Figure 14-12. Information Control
S0, S1: Segment Information LCDM2 S2 - S29: Segment Information LCDM2 Groupn (1-7) To Output Control
To Output Control
LCDM5 to 7:
These three bits select groups of outputs to be used for LCD segment drive or as general-purpose outputs, as described in Table 14-2. The pins selected as general-purpose outputs reflect the state of the corresponding display memory bits and no longer function as part of the LCD segment lines
Table 14-2.LCDM Signal Outputs for Port Functions
LCDM7 0 0 0 0 1 1 1 1 LCDM6 0 0 1 1 0 0 1 1 LCDM5 0 1 0 1 0 1 0 1 Group0 S0-S1 S0-S1 S0-S1 S0-S1 S0-S1 S0-S1 S0-S1 S0-S1 Group1 O2-O5 S2-S5 S2-S5 S2-S5 S2-S5 S2-S5 S2-S5 S2-S5 Group2 O6-O9 O6-O9 S6-S9 S6-S9 S6-S9 S6-S9 S6-S9 S6-S9 Group3 O10O13 O10O13 O10O13 S10S13 S10S13 S10S13 S10S13 S10S13 Group4 O14O17 O14O17 O14O17 O14O17 S14S17 S14S17 S14S17 S14S17 Group5 O18O21 O18O21 O18O21 O18O21 O18O21 S18S21 S18S21 S18S21 Group6 O22O25 O22O25 O22O25 O22O25 O22O25 O22O25 S22S25 S22S25 Group7 O26O29 O26O29 O26O29 O26O29 O26O29 O26O29 O26O29 S26S29 reset
condition
S = LCD segment function O = GP output function
Liquid Crystal Display Drive
14-15
LCD Port--Timer/Port Comparator Input
14.2.6 LCD Memory
The LCD memory map is shown in Figure 14-13. Each individual memory bit corresponds to one LCD segment. To turn on an LCD segment the memory bit is simply set. To turn off an LCD segment, the memory is reset. The mapping of each LCD segment in an application depends on the connections between the '430 and the LCD and on the LCD pin-out. Examples for each of the four modes follow including an LCD with pin out, the '430-to-LCD connections, and the resulting data mapping.
Figure 14-13. Display Memory Bits Attached to Segment Lines
Associated Common Pin Address 03Fh 03Eh 03Dh 03Ch 03Bh 03Ah 039h 038h 037h 036h 035h 034h 033h 032h 031h 3 7 ---------------2 1 0 3 2 1 0 0 ---------------Associated '430 Segment Pin n 28 29, 28 26 27, 26 24 25, 24 22 23, 22 20 21, 20 18 19, 18 16 17, 16 14 15, 14 12 13, 12 10 11, 10 8 9, 8 6 7, 6 4 5, 4 2 3, 2 0 1, 0
----------------
----------------
----------------
----------------
---------------Sn
----------------
Sn+1
14.2.6.1 Example Using the Static Drive Mode
The static drive mode uses one common line, COM0. In this mode, only bit 0 and bit 4 are used for segment information. The other bits can be used like any other memory. Figure 14-14 shows an example static LCD, pin-out, LCD-to-'430 connections, and the resulting data mapping. Note this is only an example. Segment mapping in a user's application completely depends on the LCD pin-out and on the '430-to-LCD connections.
14-16
LCD Port--Timer/Port Comparator Input
Figure 14-14. Example With the Static Drive Mode
LCD a f e d Pinout and Connections
Connections '430 Pins S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 S22 S23 S24 S25 S26 S27 S28 S29 NC NC COM0 COM1 COM2 COM3 LCD Pinout PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 NC NC NC COM0 1a 1b 1c 1d 1e 1f 1g 1h 2a 2b 2c 2d 2e 2f 2g 2h 3a 3b 3c 3d 3e 3f 3g 3h 4a 4b 4c 4d 4e 4f 4g 4h COM0
a b c h e d f g c h b e d f g
a b c h e d f g
a b c h
g
Display Memory COM MAB 03Fh 03Eh 03Dh 03Ch 03Bh 03Ah 039h 038h 037h 036h 035h 034h 033h 032h 031h A 3 ---------------3 2 ---------------2 1 ---------------1 0 f d b h f d b h f d b h f d b 0 3 ---------------3 2 ---------------2 1 ---------------1 0 e c a g e c a g e c a g e c a 0 n = 28 26 24 22 20 18 16 14 12 10 8 6 4 2 0 A 0 G 3 B Digit 4
Digit 3
Digit 2
Digit 1
G0 B 3
Parallel-Serial Conversion
Sn+1
Sn
14.2.6.2 Example Using Two-MUX, 1/2-Bias Drive Mode
The two-MUX drive mode uses COM0 and COM1. In this mode, bits 0, 1, 4, and 5 are used for segment information. The other bits can be used like any other memory.
Liquid Crystal Display Drive
14-17
LCD Port--Timer/Port Comparator Input
Figure 14-15 shows an example two-MUX LCD, pin-out, LCD-to-'430 connections, and the resulting data mapping. Note this is only an example. Segment mapping in a user's application completely depends on the LCD pin-out and on the '430-to-LCD connections.
Figure 14-15. Example With the Two-MUX Mode
LCD a f e d DIGIT8 Pinout and Connections
Connections '430 Pins PIN S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 S22 S23 S24 S25 S26 S27 S28 S29 NC NC COM0 COM1 COM2 COM3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 NC NC LCD Pinout COM0 COM1 1f 1h 1d 1e 2f 2h 2d 2e 3f 3h 3d 3e 4f 4h 4d 4e 5f 5h 5d 5e 6f 6h 6d 6e 7f 7h 7d 7e 8f 8h 8d 8e COM0 1a 1b 1c 1g 2a 2b 2c 2g 3a 3b 3c 3g 4a 4b 4c 4g 5a 5b 5c 5g 6a 6b 6c 6g 7a 7b 7c 7g 8a 8b 8c 8g COM1
a b c h e d DIGIT1 Display Memory COM MAB 03Fh 03Eh 03Dh 03Ch 03Bh 03Ah 039h 038h 037h 036h 035h 034h 033h 032h 031h A 3 ---------------3 2 ---------------2 1 b g b g b g b g b g b g b g b 1 0 h e h e h e h e h e h e h e h 0 3 ---------------3 2 ---------------2 1 a c a c a c a c a c a c a c a 1 0 f d f d f d f d f d f d f d f 0 n = 28 26 24 22 20 18 16 14 12 10 8 6 4 2 0 A 0 G 3 B 1/2 Digit 8 Digit 7 Digit 6 Digit 5 Digit 4 Digit 3 Digit 2 Digit 1 ParallelSerial Conversion f g c h b
g
G0 B 3
Sn+1
Sn
14-18
LCD Port--Timer/Port Comparator Input
14.2.6.3 Example Using Three-MUX, 1/3-Bias Drive Mode
The three-MUX drive mode uses COM0, COM1, and COM2. In this mode, bits 0, 1, 2, 4, 5, and 6 are used for segment information. The other bits can be used like any other memory. Figure 14-16 shows an example three-MUX LCD, pin-out, LCD-to-'430 connections, and the resulting data mapping. Note this is only an example. Segment mapping in a user's application completely depends on the LCD pin-out and on the '430-to-LCD connections.
Figure 14-16. Example With the 3-MUX Mode
LCD y a f e d DIGIT10 Pinout and Connections
Connections '430 Pins PIN S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 S22 S23 S24 S25 S26 S27 S28 S29 COM0 COM1 COM2 COM3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 NC LCD Pinout COM0 COM1 COM2 1y 1e 1f 1a 1d 1g 1b 1h 1c 2y 2e 2f 2a 2d 2g 2b 2h 2c 3y 3e 3f 3a 3d 3g 3b 3h 3c 4y 4e 4f 4a 4d 4g 4b 4h 4c 5y 5e 5f 5a 5d 5g 5b 5h 5c 6y 6e 6f 6a 6d 6g 6b 6h 6c 7y 7e 7f 7a 7d 7g 7b 7h 7c 8y 8e 8f 8a 8d 8g 8b 8h 8c 9y 9e 9f 9a 9d 9g 9b 9h 9c 10y 10e 10f 10a 10d 10g 10b 10h 10c COM0 COM1 COM2 COM MAB 03Fh 03Eh 03Dh 03Ch 03Bh 03Ah 039h 038h 037h 036h 035h 034h 033h 032h 031h A B G 3 ---------------3 2 b y a b y a b y a b y a b y a 2
y b c h e d f g
a b c h DIGIT1
g
Display Memory
1 c f g c f g c f g c f g c f g 1 0 h e d h e d h e d h e d h e d 0 3 ---------------3 2 a b y a b y a b y a b y a b y 2 1 g c f g c f g c f g c f g c f 1 0 d h e d h e d h e d h e d h e 0 n = 28 Digit 10 26 Digit 9 24 22 Digit 8 20 Digit 7 18 16 Digit 6 14 Digit 5 12 10 Digit 4 8 Digit 3 6 4 Digit 2 2 Digit 1 0 A Parallel0 Serial G 3 B Conversion
0 3
Sn+1
Sn
Liquid Crystal Display Drive
14-19
LCD Port--Timer/Port Comparator Input
14.2.6.4 Example Using Four-MUX, 1/3-Bias Drive Mode
The four-MUX drive mode uses all four common lines. In this mode, bits 0 through 7 are used for segment information. Figure 14-17 shows an example four-MUX LCD, pin-out, LCD-to-'430 connections, and the resulting data mapping. Note this is only an example. Segment mapping in a user's application completely depends on the LCD pin-out and on the '430-to-LCD connections.
Figure 14-17. Example With the Four-MUX Mode
LCD
a f e d g c h b e d f g c h a b
DIGIT15 Pinout and Connections
Connections
'430 Pins PIN S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 S22 S23 S24 S25 S26 S27 S28 S29 COM0 COM1 COM2 COM3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 LCD Pinout COM0 COM1 COM2 COM3 1d 1h 2d 2h 3d 3h 4d 4h 5d 5h 6d 6h 7d 7h 8d 8h 9d 9h 10d 10h 11d 11h 12d 12h 13d 13h 14d 14h 15d 15h COM0 1e 1c 2e 2c 3e 3c 4e 4c 5e 5c 6e 6c 7e 7c 8e 8c 9e 9c 10e 10c 11e 11c 12e 12c 13e 13c 14e 14c 15e 15c COM1 COM2 COM3 1g 1b 2g 2b 3g 3b 4g 4b 5g 5b 6g 6b 7g 7b 8g 8b 9g 9b 10g 10b 11g 11b 12g 12b 13g 13b 14g 14b 15g 15b 1f 1a 2f 2a 3f 3a 4f 4a 5f 5a 6f 6a 7f 7a 8f 8a 9f 9a 10f 10a 11f 11a 12f 12a 13f 13a 14f 14a 15f 15a
DIGIT1 Display Memory
COM MAB 03Fh 03Eh 03Dh 03Ch 03Bh 03Ah 039h 038h 037h 036h 035h 034h 033h 032h 031h A B G 3 a a a a a a a a a a a a a a a 3 0 3 2 b b b b b b b b b b b b b b b 2 1 c c c c c c c c c c c c c c c 1 0 h h h h h h h h h h h h h h h 0 3 f f f f f f f f f f f f f f f 3 2 g g g g g g g g g g g g g g g 2 1 e e e e e e e e e e e e e e e 1 0 d d d d d d d d d d d d d d d 0 n = 28 Digit 15 26 Digit 14 24 Digit 13 22 Digit 12 20 Digit 11 18 Digit 10 16 Digit 9 14 Digit 8 12 Digit 7 10 Digit 6 8 6 4 2 0 Digit 5 Digit 4 Digit 3 Digit 2 Digit 1
0 G 3
A ParallelSerial B Conversion
Sn+1
Sn
14-20
Code Examples
14.3 Code Examples
Code examples for the four modes follow.
14.3.1 Example Code for Static LCD
; ; ; a b c d e f g h ; : ; .sect "lcd1mux",0f000h All eight segments of a digit are often located in four display memory bytes with the static display method. .EQU 001h .EQU 010h .EQU 002h .EQU 020h .EQU 004h .EQU 040h .EQU 008h .EQU 080h The register content of Rx should be displayed. The Table represents the 'on'-segments according to the content of Rx. ........... ; LCD1 .EQU 00031h ........... ........... LCD15 .EQU 0003Fh ; ........... MOV.B Table (Rx),RY
MOV.B Ry,&LCDn
RRA Ry MOV.B Ry,&LCDn+1
RRA Ry MOV.B Ry,&LCDn+2
RRA Ry MOV.B Ry,&LCDn+3
; ; ; ; ; ' ; ; ; ; ; ; ; ' ; ; ; '
Load segment information into temporary memory. (Ry) = 0000 0000 hfdb geca Note: All bits of an LCD memory byte are written (Ry) = 0000 0000 0hfd bgec Note: All bits of an LCD memory byte are written (Ry) = 0000 0000 00hf dbge Note: All bits of an LCD memory byte are written (Ry) = 0000 0000 000h fdbg Note: All bits of an LCD memory byte are written
........... ........... ; Table .BYTE a+b+c+d+e+f .BYTE b+c; ........... ........... .BYTE ........... ; displays "0" ; displays "1"
Liquid Crystal Display Drive
14-21
Code Examples
14.3.2 Example Code for Two MUX, 1/2-Bias LCD
; ; ; a b c d e f g h ; ; ; ; .sect "lcd2mux",0f000h All eight segments of a digit are often located in two display memory bytes with the 2MUX display rate .EQU 002h .EQU 020h .EQU 008h .EQU 004h .EQU 040h .EQU 001h .EQU 080h .EQU 010h The register content of Rx should be displayed. The Table represents the 'on'-segments according to the content of Rx. ........... ; LCD1 .EQU 00031h ........... ........... LCD15 .EQU 0003Fh ; ........... ........... MOV.B Table(Rx),Ry ; Load segment information into ; temporary memory. ; (Ry) = 0000 0000 gebh cdaf MOV.B Ry,&LCDn ; Note: ; All bits of an LCD memory byte ; are written RRA Ry ; (Ry) = 0000 0000 0geb hcda RRA Ry ; (Ry) = 0000 0000 00ge bhcd MOV.B Ry,&LCDn+1 ; Note: ; All bits of an LCD memory byte ; are written ........... ........... ........... Table .BYTE a+b+c+d+e+f ; displays "0" ........... .BYTE a+b+c+d+e+f+g+h ; displays "8" ........... ........... .BYTE ........... ;
14-22
Code Examples
14.3.3 Example Code for Three MUX, 1/3-Bias LCD
.sect "lcd3mux",0f000h ; The 3MUX rate can easily support nine segments for each ; digit. The nine segments of a digit are located in ; 1 1/2 display memory bytes. ; a .EQU 0040h b .EQU 0400h c .EQU 0200h d .EQU 0010h e .EQU 0001h f .EQU 0002h g .EQU 0020h h .EQU 0100h Y .EQU 0004h ; The LSDigit of register Rx should be displayed. ; The Table represents the 'on'-segments according to the ; LSDigit of register of Rx. ; The register Ry is used for temporary memory ; LCD1 .EQU 00031h ........... LCD15 .EQU 0003Fh ........... ........... ODDDIG RLA Rx ; LCD in 3MUX has 9 segments per ; digit; word table required for ; displayed characters. MOV Table(Rx),Ry ; Load segment information to ; temporary mem. ; (Ry) = 0000 0bch 0agd 0yfe MOV.B Ry,&LCDn ; write 'a, g, d, y, f, e' of ; Digit n (LowByte) SWPB Ry ; (Ry) = 0agd 0yfe 0000 0bch BIC.B #07h,&LCDn+1 ; write 'b, c, h' of Digit n ; (HighByte) BIS.B Ry,&LCDn+1 ..... EVNDIG RLA Rx ; LCD in 3MUX has 9 segments per ; digit; word table required for ; displayed characters. MOV Table(Rx),Ry ; Load segment information to ; temporary mem. ; (Ry) = 0000 0bch 0agd 0yfe RLA Ry ; (Ry) = 0000 bch0 agd0 yfe0 RLA Ry ; (Ry) = 000b ch0a gd0y fe00 RLA Ry ; (Ry) = 00bc h0ag d0yf e000 RLA Ry ; (Ry) = 0bch 0agd 0yfe 0000 BIC.B #070h,&LCDn+1 BIS.B Ry,&LCDn+1 ; write 'y, f, e' of Digit n+1 ; (LowByte) SWPB Ry ; (Ry) = 0yfe 0000 0bch 0agd MOV.B Ry,&LCDn+2 ; write 'b, c, h, a, g, d' of ; Digit n+1 (HighByte) ........... Table .WORD a+b+c+d+e+f ; displays "0" .WORD b+c ; displays "1" ........... ........... .WORD a+e+f+g ; displays "F"
Liquid Crystal Display Drive
14-23
Code Examples
14.3.4 Example Code for Four MUX, 1/3-Bias LCD
; ; ; a b c d e f g h ; ; ; ; ; .sect "lcd4mux",0f000h The 4MUX rate is the most easy-to-handle display rate. All eight segments of a digit can often be located in one display memory byte .EQU 080h .EQU 040h .EQU 020h .EQU 001h .EQU 002h .EQU 008h .EQU 004h .EQU 010h The LSDigit of register Rx should be displayed. The Table represents the 'on'-segments according to the content of Rx.
........... .EQU 00031h ; Address of LC Display Memory ........... ........... LCD15 .EQU 0003Fh ........... ........... ........... MOV.B Table(Rx),&LCD n ; n = 1 ..... 15 ; all eight segments are ; written to the display ; memory ........... ........... LCD1 Table .BYTE a+b+c+d+e+f .BYTE b+c ........... ........... .BYTE b+c+d+e+g .BYTE a+d+e+f+g .BYTE a+e+f+g ; displays "0" ; displays "1"
; displays "d" ; displays "E" ; displays "F"
14-24
Chapter 15
ADC12+2 A-to-D Converter
The ADC12+2 features include:
-
Eight analog or digital input channels A programmable current source on four analog pins Ratiometric or absolute measurement Built-in sample-and-hold End-of-conversion interrupt flag ADAT register that holds conversion results until the next start of conversion Low-power consumption Stand-alone conversion without CPU processing overhead Programmable 12-bit or 14-bit resolution Four programmable ranges that give 14-bit dynamic range Fast-conversion time Large supply-voltage range Monotonic conversion
Topic
Page
15.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-2 15.2 Analog-to-Digital Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-4 15.3 ADC12+2 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-13
ADC12+2 A-to-D Converter
15-1
Introduction
15.1 Introduction
The 12+2-bit ADC is a peripheral module accessed using word instructions. Conversion results are contained in the ADAT register. The converted bits are visible during a conversion and are immediately available to be read at the end of conversion in the ADAT register. The conversion result is not cleared until the next conversion is initiated by setting the SOC bit in the ACTL register. The SOC bit clears the ADAT register for the new result and starts the ADC12+2 clock for another conversion. Figure 15-1 shows the ADC12+2 module configuration.
Figure 15-1. ADC12+2 Module Configuration
SVCC ACTL.1, ACTL.12 AVCC ACTL.2-5 A0 A1 A2 A3 A4 A5 A6 A7 0 MDB.1 1 MDB.2 2 MDB.3 3 MDB.4 4 MDB.5 5 MDB.6 6 MDB.7 7 MDB.8 To MDB.15 AEN.x GND ACTL.0 AEN.7 AEN AEN.0 AIN Register MDB.0
Rext AGND
Analog-To-Digital Converter RC-Type
ADAT
ACTL
ACTL.14 MDB, 16 Bit
15-2
Introduction
The ADC12+2 module has eight individually-configurable input channels. A conversion can be made on any one of these channels at any time. Four of the channels, A0, A1, A2, and A3, may also be configured as current source outputs whose values can be programmed by external resistor Rext. Any of the current source outputs can be turned on (one at a time) to drive external sensors in order to make ratiometric measurements. Absolute measurements can also be made by applying an external reference to pins SVCC or AVDD. Additionally, the eight channels can be configured as digital inputs. Each input channel is individually configurable, so each input may be either an analog or a digital input. The selection is made with the bits in the AEN register. When used as digital inputs, the values of the digital input signals are read from the AIN register. Note: When sensitive analog conversion takes place, any digital activity on adjacent channels may cause crosstalk and interference, giving noisy or incorrect conversion results. The converter has two modes of operation: 12-bit, and 12+2-bit conversion, depending on the status of ACTL register bit 11. When the range of the input signal is known the input range may be preselected and the converter can be used in 12-bit mode. The converter samples the input and then converts it to 12 bits of resolution within any one of the four ranges (see subsection 15.2.3). In 12+2-bit mode (setting ACTL register bit 11), the range is automatically selected by the converter to resolve to 14 bits. The input is sampled twice: once for the 2-bit range selection, and once again for the remaining 12-bits of the conversion, to give a 12+2-bit result. In both modes, when a conversion is completed, the interrupt flag (EOC) is set automatically. The EOC signal disables the ADC clock to conserve power until the SOC bit is set again. Note: ADC, Start-of-Conversion A conversion must always be completed before the next conversion is initiated. Otherwise, unpredictable conversion data will result. When powered-down (Pd bit in ACTL register), the ADC current consumption is stopped. This is valid while SVCC is not externally driven. Upon a conversion start-up or a power-up signal the converter wakes up, but it can take up to 6 s to reach steady-state conditions.
ADC12+2 A-to-D Converter
15-3
Analog-to-Digital Operation
15.2 Analog-to-Digital Operation
The following sections describe the ADC12+2 and operation.
15.2.1 A/D Conversion
After power-up, the ACTL register must be programmed to make a ratiometric or absolute measurement and to manually or automatically select a range. In manual (12-bit) mode, once the range bits are selected they cannot be changed during the conversion, as this invalidates the results. Setting the SOC bit in the ACTL register activates the ADC clock to begin a new conversion. The conversion is based on a successive approximation technique that uses a resistor array to resolve the M MSBs first, and uses a switched capacitor array to resolve the remaining L LSBs. The resistor array, consisting of 2M individually and equally weighted resistors, forms a DAC; the capacitor array, consisting of L capacitors, forms an A/D charge redistribution. The capacitors are binary-weighted. The number of capacitors corresponds to the converter range, or to the digital-output code L bits. The sequence, shown in Figure 15-2, starts by selecting the applicable analog channel and sampling the analog-input voltage onto the top plates of the capacitor array. The analog multiplexer is then disconnected from the ADC and the analog input does not need to be present after this sample period. A successive approximation is performed on the resistor string to find the tap that corresponds to a voltage within 2L LSBs of VIN. This yields the VH and VL voltages across one element of the resistor array, and resolves the M MSBs. The capacitor array then resolves the difference voltage (VH-VL) to L bits of resolution using a similar successive approximation search on the capacitor array, starting with the MSB capacitor. This switching procedure continues with the MSB or largest capacitor to the smallest (LSB) capacitor in the capacitor array, whereby the initial charge is redistributed among the capacitors. The particular setting of the switches (both in the resistor array and in those connected to the bottom plates of the capacitors) has then induced a change on the top plate that is as close to the input voltage (VIN) as possible. The switch settings then correspond to the binary code [12-bit or 12+2-bit] that represents the fraction VIN/VREF. The top plate voltage is monitored by a comparator with built-in input-offset cancellation circuitry that senses whether the input voltage is less or greater than the voltage on the top plate. It generates a digital output that determines the direction of the successive approximation search. When this sequence is completed, the top plate voltage is as close to zero as the converter resolution allows, and the LSB is determined. An EOC signal is then sent to indicate that the conversion result is available from the ADAT register.
15-4
Analog-to-Digital Operation
Figure 15-2. ADC12+2 Schematic
AVCC SVCC Switch SVCC
ACTL.1 (SVCC on) ACTL.12(Pd) AVCC/2 Generator C C 2C 4C 8C PD
REXT
- +
Rext Isource Pd
_ +
D 0.75 SVCC C ACTL 6,7
2M 2M 2M
Range MUX 2(L-1)C Resistor VH Capacitor Array Decoder VL Delay ADCLK/12 M 2 L
B 2M A
1:4
ACTL 8 (Off)
AGND
ACTL.9, 10 ACTL.11 SAR ACTL.0 8:1 Input :12 ACTL 2.4 ACTL .5 Input MUX A7 Input Buffer AIN 8 MDB 0-7 A0 SAR.13 AEN.0-7 8 Input Buffer Enable AEN 8 MDB 0-7 SAR.0 :1, :2 :3, :4 ACTL.14 ACTL 14 ACTL 13 MCLK ACTL.0 EOC
A0 A1 A2 A3 A4 A5 A6 A7
Output Buffer ADAT 12/14 MDB, 16 Bit
Control Register ACTL 16
15.2.1.1 A/D Conversion Timing
After the ADC12+2 module is activated (Pd bit is reset), at least 6 s must elapse before a new conversion is attempted in order to allow the correct internal biases to be established. The ADC always runs at one-twelfth the clock rate of the ADCLK. ADCLK is always MCLK divided by 1, 2, 3, or 4. The ADCLK frequency must be chosen to meet the conversion time defined in the electrical characteristics (see device's data sheet). The ADCLK frequency is selected with two bits (ADCLK) in control register ACTL. If the ADCLK is too fast, an accurate conversion to 12 bits cannot be guaranteed due to the internal time constants associated with analog input sampling and the conversion network. Also, if the ADCLK is too slow, an accurate conversion to 12 bits cannot be guaranteed, due to charge loss within the ADC-capacitor array, even if the input signal is valid and steady for the required acquisition time. Sampling the analog input signal takes 12 ADCLK pulses, and the 12-bit conversion takes 84 (12 x 7) additional ADCLK cycles. Therefore, a 12-bit conversion with a preselected range takes 96 ADCLK cycles. This is illustrated in Figure 15-3.
ADC12+2 A-to-D Converter
15-5
Analog-to-Digital Operation
Figure 15-3. ADC12+2 Timing, 12-Bit Conversion
ADCLK/12 PD Start Of Conversion SOC ADC Activated
Sample End Of Conversion
EOC SAR.0-11 A2D Mode, Range, Channel Selected Input Valid Converting N Bits
Data Valid and Latched
In 12+2-bit mode, the analog input signal is sampled twice, each sampling taking twelve ADCLK clock pulses. After the first sampling of the input signal, the range conversion occurs and takes 24 ADCLK clocks. After the second sampling of the input signal (the second sampling occurs automatically), the 12-bit conversion occurs and takes 84 (12 x 7) additional ADCLK clock cycles. Altogether, the 12+2-bit conversion takes 132 ADCLK cycles as illustrated in Figure 15-4.
Figure 15-4. ADC12+2 Timing, 12+2-Bit Conversion
Power-Up Time ADCLK/12 PD Start Of Conversion SOC ADC Activated 12/ADCLK
Sample End Of Conversion EOC SAR.0-13 A2D Mode, Range, Channel Selected Input Valid Convert 2 Bits Input Valid Converting 12 Bits Data Valid and Latched
The input signal must be valid and steady during the sampling period for an accurate conversion (Figure 15-5). To ensure that supply glitching and ground bounce errors or crosstalk interferences do not corrupt the results, avoid digital activity on channels adjacent to the analog input during the conversion.
15-6
III III III III III III III III III III III III III III III
Power-Up Time
12/ADCLK
New Conversion
New Conversion
Analog-to-Digital Operation
Figure 15-5. ADC, Input Sampling Timing
Power-Up Time ADCLK PD Start Of Conversion SOC ADCLK/12 Sample Sampling Input ADC-Activated 1/ADCLK
EOC SAR.0-13 A2D Mode, Range, Channel Selected Input Valid Converting Converting N Bits N Bits
Sampling Input INPUT
The ADC12+2 uses the charge redistribution method and thus the internal switching of the inputs for sampling causes displacement currents to flow in and out of the analog inputs. These current spikes or transients occur at the leading and falling edges of the internal sample pulse. They quickly decay and settle before causing any problems, because the time constant is less than that of the effective internal RC. Internally, the analog inputs see a nominal RC consisting of a nominal 40-pF (C-array) capacitor in series with a nominal 2-k resistor (Ron of switches). However, if the external dynamic-source impedance is large, these transients might not settle within the allocated sampling time to within 12 or 12+2 bits of accuracy.
15.2.2 A/D Interrupt
When an A/D conversion is complete, the EOC signal goes high, setting the interrupt flag ADIFG. The ADIFG flag is located in the SFR registers in IFG2.2. The flag is automatically reset when the interrupt is serviced. Two additional bits control the generation of a CPU interrupt: The ADIE bit in the SFR register (IE2.2) and the GIE bit. The ADIE bit is an individual bit to enable or disable the A/D interrupt--its initial state is reset. The GIE bit is the global interrupt enable bit. When both bits are set, a CPU interrupt is generated at the end of an A/D conversion.
15.2.3 A/D Ranges
One of four ranges can be selected manually to yield 12 bits of resolution within any given range. The range is defined with bits ACTL.9 and ACTL.10 prior to conversion. The converter can also find the appropriate range automatically, resulting in an overall 12+2-bit conversion.
ADC12+2 A-to-D Converter
15-7
Analog-to-Digital Operation
The ranges are: 0.00 x VREF VIN < 0.25 x VREF 0.25 x VREF VIN < 0.50 x VREF 0.50 x VREF VIN < 0.75 x VREF 0.75 x VREF VIN < 1.00 x VREF Where: VREF is the voltage at the SVCC pin, either applied externally or derived by closing the SVCC switch with bit 12 of the ACTL register. After the proper range is selected, the input channel, selected by the applicable bits in the control register, is connected to the converter input. The ADC processes the signal at the selected input channel, and the software can then access the conversion result through the ADAT register. The digital code (decimal) expected within any one range is: Range A Range B Range C Range D
N typ
Where:
+ INT
VIN 2 14 - 2 13 VREF
ACTL.10 - 2 12
ACTL.9
ACTL.10 and ACTL.9 are bits 10 and 9 (respectively) in the ACTL register. Thus, for a 12-bit conversion, the ranges are: 0000h N 0FFFh 0000h N 0FFFh 0000h N 0FFFh 0000h N 0FFFh and for a 12+2-bit conversion: 0000h N 3FFFh Note: ADC12+2 Offset Voltage Any offset voltage (Vio) due to voltage drops at the bottom or top of the resistor array, caused by parasitic impedances to the SVCC pin or the ground AGND pin, distorts the digital code output and formula. Range A Range B Range C Range D
15.2.4 A/D Current Source
When the ADC12+2 is used in sensor applications in conjunction with resistive elements, current sources may be required so that the input signal can be referred back to the supply voltage or voltage reference. This allows a ratiometric measurement independent of the accuracy of the reference. One of four analog channels can be used for the current-source output, as shown in Figure 15-6. The current-source (Isource) output can be programmed by an external resistor (Rext) and is then available on pins A0, A1, A2, and A3, with the value: Isource = (0.25 x SVCC)/Rext
15-8
Analog-to-Digital Operation
Where: SVCC is the voltage at pin SVCC, and Rext is the external resistor between pins SVCC and Rext. Therefore, for ratiometric measurements, the voltage (Vin), developed across the channel input with the resistive elements (channels A0, A1, A2, and A3 only) is: Vin = (0.25 x SVCC) x (Rsens/Rext) Where: Rsens is the external resistive element.
Figure 15-6. A/D Current Source
AVCC SVCC Switch SVCC Rext ACTL.1 (SVCC on) ACTL.12(Pd)
Rext Isource Pd
D 0.75 SVCC + C ACTL 6,7
_
2M 2M 2M
Resistor
B 2M A
Decode
1:4
ACTL 8 (Off)
AGND Rsens A0 A1 A2 A3 A4 A5 A6 A7
8:1
Input
ACTL 2.4 Input
15.2.5 Analog Inputs and Multiplexer
The analog inputs and the multiplexer are described in the following sections.
15.2.5.1 Analog Inputs
The analog-input signal is sampled onto an internal capacitor and held during conversion. The charge is supplied by the input source, and the charging time is defined to be twelve ADCLK clocks. Therefore, the external source resistances and dynamic impedances must be limited so that the RC time constant is short enough to allow the analog inputs to completely settle to 12-bit accuracy within the allocated sampling time. This time constant is typically less than 0.8/fADCLK. High source impedances have an adverse affect on the accuracy of the converter, not only due to RC-settling behavior, but also due to input voltage drops as a result of leakage current or averaged dc-input currents (input
ADC12+2 A-to-D Converter
15-9
Analog-to-Digital Operation
switching currents). Typically, for a 12-bit converter, the error in LSBs due to leakage current is: Error (LSBs) = 4 x (A of leakage current) x (k of source resistance)/(volt of VREF). Example: 50-nA leakage, 10-k source resistance, 3-V VREF results in 0.7 LSBs of error. This also applies to the output impedance of the voltage-reference source VREF. The impedance must be low enough to enable the transients to settle within (0.2/ADCLK) seconds and to generate leakage-current-induced errors of << 1LSB.
15.2.5.2 Analog Multiplexer
The analog multiplexer selects one of eight single-ended input channels, as determined by the ACTL register bits. It is based on a T-switch to minimize the coupling between channels, which corrupts the analog input. Channels that are not selected are isolated from the ADC and the intermediate node connected to the analog ground (AGND) so that the stray capacitance is grounded to eliminate crosstalk.
Figure 15-7. Analog Multiplexer
R 100 ACTL.9,10 Input
0V 0V 0V ESD Protection 0V
Crosstalk exists because there is always parasitic coupling capacitance across and between switches. This can take several forms, such as coupling from the input to the output of an off switch, or coupling from an off-analog input channel to the output of an adjacent on output channel, causing errors. Thus, for high-accuracy conversions, crosstalk interference must be minimized through shielding and other well-known printed-circuit board (PCB) layout techniques.
15.2.6 A/D Grounding and Noise Considerations
As with any high-resolution converter ( 12 bits), care and special attention must be given to the printed-circuit board layout and the grounding scheme to eliminate ground loops and any unwanted parasitic components/effects and noise. Many common techniques are documented in application notes that address these issues. Ground loops can be formed when the ADC12+2 resistor-divider return current flows through traces that are common to other analog or digital
15-10
Analog-to-Digital Operation
circuitry. This current can generate small unwanted offset voltages that can add to or subtract from the ADC reference or input voltages. One way to avoid ground loops is to use a star-connection scheme for the AGND; in this way, the ground or reference currents do not flow through any common input leads, eliminating any voltage errors (see Figure 15-8).
Figure 15-8. A/D Grounding and Noise Considerations
A/D + VREF - SVCC RTOP (Internal) AVCC 22 F Tantalum 0.1 F Ceramic
RBOT (Internal) + - DVCC Vin A0. . . 7 22 F Tantalum AGND 0.1 F Ceramic
VIN
DGND
The digital ground (DGND) and the analog ground (AGND) can also be starconnected together. However, if separate supplies are used, two reversebiased diodes limit the voltage difference to less than 700 mV (see Figure 15-8). Power-supply rippling and noise spikes from digital switching or switching power supplies can cause conversion errors. Normally, the internal ADC noise is very small and the total input-referred noise is far less than one LSB, so the output code is fairly stable. However, as noise couples into the device through the supply and ground, the noise margin is reduced, and code uncertainty and jitter can result. Several readings might be required to average out the noise effects. Another consequence of noise is that, as one of the reference voltages SVCC or VREF is reduced, the absolute value of the LSB is also reduced. Therefore, the noise becomes even more dominant. Thus, a clean, noise-free design becomes even more important to achieve the desired accuracy. In addition to physical layout techniques, adding carefully-placed bypass capacitors returned to the respective ground planes helps to stabilize the supply current and minimize the noise.
ADC12+2 A-to-D Converter
15-11
Analog-to-Digital Operation
15.2.7 A/D Converter Input and Output Pins
The following sections describe the various ADC12+2 pins.
15.2.7.1 Input Pins
There are two different types of input signals: analog signals A0 through A7, and signals ISOURCE and SVCC. The input signals coming from channels A0 to A7 are configurable as ADC analog signals or as digital inputs (see Figure 15-9). Pin SVCC is used as an output or input. It is an input when the internal SVCC switch is off and the VREF is applied externally. It is an output when the internal SVCC switch is on.
Figure 15-9. ADC12+2 Input Register, Input Enable Register
ACTL.2-5 AEN REG A0 A1 A2 A3 A4 A5 A6 A7 0 1 2 3 4 5 6 7 AIN Register From/To ADC MDB.8 To MDB.15 A0x A1x A2x A3x A4x A5x A6x A7x MDB.0 MDB.1 MDB.2 MDB.3 AEN.4 MDB.4 AEN.5 MDB.5 AEN.6 MDB.6 AEN.7 MDB.7 AEN.0 AEN.1 AEN.2 AEN.3
16 MDB
15-12
ADC12+2 Control Registers
15.2.7.2 Output Pins
There are two different types of output signals: outputs A0, A1, A2, A3, and output SVCC. Current flows out of one of the analog pins A0, A1, A2, A3 if the current source function is selected. An external resistor between Rext and SVCC determines the amount of current. The SVCC pin outputs a voltage just below AVCC when the SVCC switch is on.
15.2.7.3 Supply Pins
There are four supply pins to split the digital and analog current paths: AVCC, DVCC, AGND, and DGND. Some of the MSP430 family members may have all four supply pins bonded out, while others may have analog and digital VCC and/or GND rails internally connected. Check the specific device's data sheet for configuration.
15.3 ADC12+2 Control Registers
The four ADC12+2 control registers are described in Table 15-1.
Table 15-1.ADC12+2 Control Registers
Register Input Input enable ADC control Reserved ADC Data ADAT Read 0118h Short Form AIN AEN ACTL Register Type Read only Read/write Read/write Address 0110h 0112h 0114h Initial State --- Reset See Figure 15-13 0116h ---
15.3.1 Input Register AIN
When any of the inputs A0 to A7 are configured as digital inputs, the digital values are read from the AIN register. Input register AIN is a read-only register connected to the 16-bit MDB; however, only the register low byte is implemented. MDB.0 to MDB.7 correspond to A0 to A7 as shown in Figure 15-10. The register high byte is read as 00h.
Figure 15-10. Input Register AIN
MDB. 15 MDB. 8 MDB. 7 MDB. 0
AIN 110h r0
0
0
0
0
0
0
0
0
AIN .7
AIN .6
AIN .5
AIN .4
AIN .3
AIN .2
AIN .1
AIN .0
r0
r0
r0
r0
r0
r0
r0
r A7x
r
r
r
r
r
r
r A0x
A6x A5x A4x A3x A2x A1x
The signal at the corresponding input is logically ANDed with the applicable enable signal (see Figure 15-9). Unselected (disabled) bits are read as 0.
ADC12+2 A-to-D Converter
15-13
ADC12+2 Control Registers
15.3.2 Input Enable Register AEN
Input enable register AEN, shown in Figure 15-11, is a read/write register connected to the 16-bit MDB; however, only the register low byte is implemented. MDB.0 to MDB.7 correspond to A0 to A7. The register high byte is read as 00h.
Figure 15-11.Input Enable Register AEN
MDB. 15 MDB. 8 MDB. 7 MDB. 0
AIN 112h r0
0
0
0
0
0
0
0
0
AIN .7
AIN .6
AIN .5
AIN .4
AIN .3
AIN .2
AIN .1
AIN .0
r0
r0
r0
r0
r0
r0
r0
rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0
The input enable register bits control the definition of the individual bit: AEN.x = 0: AEN.x = 1: Analog input. The bit read while accessing the AIN register is 0. Digital input. The bit read while accessing the AIN register represents the logic level at the applicable pin.
The initial state of all AEN bits is reset.
15.3.3 ADC12+2 Data Register ADAT
The ADC data register (ADAT), shown in Figure 15-12, holds the result of the analog-to-digital conversion. The register data at the end of a conversion are correct until another conversion begins by setting the SOC bit.
Figure 15-12. ADC12+2 Data Register ADAT
MDB. 15 MDB. 0
ADAT 0118h r0
0
0
0
0
MSB
LSB
ACTL.11 = 0
r0
r0
r0
r
r
r
r
r
r
r
r
r
r
r
r MDB. 0
MDB. 15
ADAT 0118h r0
0
0
RA1
RA0 MSB
LSB
ACTL.11 = 1
r0
r
r
r
r
r
r
r
r
r
r
r
r
r
r
15-14
ADC12+2 Control Registers
15.3.4 ADC12+2 Control Register ACTL
The ADC12+2 control register (ACTL) is illustrated in Figure 15-13.
Figure 15-13. ADC12+2 Control Register ACTL
MDB. 15 MDB. 0
ACTL 0114h r0
0
ADCLK
Pd
Range Select
Current Source
AD Input Select
Vref
SOC
rw-0 rw-0 rw-1 rw-0 rw-0 rw-0
rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 (w)r-0
Bit 0:
Start of conversion Setting this bit starts the ADC conversion. It is automatically reset. Source of VREF ACTL.1 = 0 : Switch SVCC is off. The ADC reference voltage must be supplied from an external source. ACTL.1 = 1 : Switch SVCC is on. The SVCC pin is connected to VCC internally and configured as an output. The ADC reference voltage must not be supplied from an external source.
Bit 1:
Bits 2-5: A/D input selection These bits select the channel for conversion as described in Table 15-2. Channels should be changed only after completing a conversion. Changing the channel while a conversion is active invalidates the conversion in progress.
Table 15-2.A/D Input Selection
ACTL.5 0 0 0 0 0 0 0 0 1 ACTL.4 0 0 0 0 1 1 1 1 X ACTL.3 0 0 1 1 0 0 1 1 X ACTL.2 0 1 0 1 0 1 0 1 X Channel A0 A1 A2 A3 A4 A5 A6 A7 NONE
Bits 6-8: A/D current source output selection These bits select the channel for current source output as described in Table 15-3. Channels should be changed only after completing a conversion. Changing the channel while a conversion is active invalidates the conversion in progress.
ADC12+2 A-to-D Converter
15-15
ADC12+2 Control Registers
Table 15-3.A/D Current Source Selection
ACTL.8 0 0 0 0 1 ACTL.7 0 0 1 1 X ACTL.6 0 1 0 1 X Channel A0 A1 A2 A3 NONE
Bits 9-11: Range selection These bits select the range for 12-bit mode conversion as described in Table 15-4. They must not be changed after a conversion starts. Any manipulation of these bits during conversion results in incorrect conversion data. Their states are ignored when 12+2-bit mode is selected.
Table 15-4.Range Selection
ACTL.11 0 0 0 0 1 ACTL.10 0 0 1 1 X ACTL.9 0 1 0 1 X Range A B C D Auto
Bit 11:
Conversion mode ACTL.11 = 0 : 12-bit mode selected. The range selection bits ACTL.9 and ACTL.10 must be used for manual range selection. ACTL.11 = 1 : 12+2-bit mode selected. The automatic range selection is active. The state of the range selection bits ACTL.9 and ACTL.10 is don't care. Power down (Pd) ACTL.12 = 0: ADC12+2 is powered. Note, the ADC12+2 needs about 6 s to stabilize after bit Pd is reset. ACTL.12 = 1: SVCC switch is off. Comparator is powered down. Current source is off.
Bit 12:
Bit 13, 14: ADCLK The ADC12+2 clock is selected as described in Table 15-5.
Table 15-5.ADCLK Clock Frequency
ACTL.14 0 0 1 1 ACTL.13 0 1 0 1 ADCLK MCLK MCLK/2 MCLK/3 MCLK/4
Bit 15:
Reserved
15-16
Appendix A
Peripheral File Map
This appendix summarizes the MSP430x3xx peripheral file (PF) and controlbit information into a single location for reference. Each PF register is presented as a row of boxes containing the control or status bits belonging to the register. The register symbol (e.g. P0IN) and the PF hex address are to the left of each register.
Topic
A.1 A.2 A.3 A.4 A.5 A.6 A.7 A.8 A.9
Page
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-2 Special Function Register of MSP430x3xx Family, Byte Access . . . A-2 Digital I/O, Byte Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-3 LCD Registers, Byte Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-5 8-Bit Timer/Counter, Basic Timer, Timer/Port, Byte Access . . . . . . . A-6 FLL Registers, Byte Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-6 EPROM Control Register and Crystal Buffer, Byte Access . . . . . . . . A-7 USART, UART Mode (Sync=0), Byte Access . . . . . . . . . . . . . . . . . . . . . A-7 USART SPI Mode (Sync=1), Byte Access . . . . . . . . . . . . . . . . . . . . . . . . A-8
A.10 ADC12+2, Word Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-9 A.11 Watchdog/Timer, Word Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-10 A.12 Hardware Multiplier, Word Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-10 A.13 Timer_A Registers, Word Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-11
Peripheral File Map
A-1
Overview
A.1 Overview
Bit accessibility and/or hardware definitions are indicated following each bit symbol:
-
rw: r: r0: r1: w: w0: w1: (w): h0: h1: -0,-1: -(0),-(1):
Read/write Read only Read as 0 Read as 1 Write only Write as 0 Write as 1 No register bit implemented; writing a 1 results in a pulse. The register bit is always read as 0. Cleared by hardware Set by hardware Condition after PUC signal active Condition after POR signal active
The tables in the following sections describe byte access to each peripheral file according to the previously-described definitions.
A.2 Special Function Register of MSP430x3xx Family, Byte Access
000Fh
Module enable 2, ME2 0005h Module enable 1, ME1 0004h Interrupt flag 2, IFG2 0003h Interrupt flag 1, IFG1 0002h Interrupt enable 2, IE2 0001h Interrupt enable 1, IE1 0000h BTIE rw-0 BTIFG rw NMIIFG rw-0 P0IFG.1 rw-0 TPIE rw-0 P0IE.1 rw-0 ADIFG rw-0 P0IFG.0 rw-0 ADIE TPIE rw-0 P0IE.0 rw-0
UTXE rw-0
URXE USPIIE rw-0
UTXIFG rw-0 OFIFG rw-1 UTXIE rw-0 OFIE rw-0
URXIFG rw-0 WDTIFG rw-0 URXIE rw-0 WDTIE rw-0
ADIE - ADC12+2 interrupt enable (32x devices) TPIE - Timer/Port interrupt enable (31x devices) TPIE - Timer/Port interrupt enable (32x, 33x devices) Note: SFR bits are not implemented on devices without the corresponding peripheral.
A-2
Digital I/O, Byte Access
A.3 Digital I/O, Byte Access
Bit # Function select, P4SEL 001Fh Direction register, P4DIR 001Eh Output register, P4OUT 001Dh Input register, P4IN 001Ch Function select, P3SEL 001Bh Direction register, P3DIR 001Ah Output register, P3OUT 0019h Input register, P3IN 0018h 0017h 0016h Interrupt enable, P0IE 0015h Interrupt edge select, P0IES 0014h Interrupt flags, P0IFG 0013h Direction register, P0DIR 0012h Output register, P0OUT 0011h Input register, P0IN 0010h P0IE.7 rw-0 P0IES.7 rw P0IFG.7 rw-0 P0DIR.7 rw-0 P0OUT.7 rw P0IN.7 r P0IE.6 rw-0 P0IES.6 rw P0IFG.6 rw-0 P0DIR.6 rw-0 P0OUT.6 rw P0IN.6 r P0IE.5 rw-0 P0IES.5 rw P0IFG.5 rw-0 P0DIR.5 rw-0 P0OUT.5 rw P0IN.5 r P0IE.4 rw-0 P0IES.4 rw P0IFG.4 rw-0 P0DIR.4 rw-0 P0OUT.4 rw P0IN.4 r P0IE.3 rw-0 P0IES.3 rw P0IFG.3 rw-0 P0DIR.3 rw-0 P0OUT.3 rw P0IN.3 r P0IE.2 rw-0 P0IES.2 rw P0IFG.2 rw-0 P0DIR.2 rw-0 P0OUT.2 rw P0IN.2 r r0 P0IES.1 rw r0 P0DIR.1 rw-0 P0OUT.1 rw P0IN.1 r r0 P0IES.0 rw r0 P0DIR.0 rw-0 P0OUT.0 rw P0IN.0 r 7 P4SEL.7 rw-0 P4DIR.7 rw-0 P4OUT.7 rw P4IN.7 r P3SEL.7 rw-0 P3DIR.7 rw-0 P3OUT.7 rw P3IN.7 r 6 P4SEL.6 rw-0 P4DIR.6 rw-0 P4OUT.6 rw P4IN.6 r P3SEL.6 rw-0 P3DIR.6 rw-0 P3OUT.6 rw P3IN.6 r 5 P4SEL.5 rw-0 P4DIR.5 rw-0 P4OUT.5 rw P4IN.5 r P3SEL.5 rw-0 P3DIR.5 rw-0 P3OUT.5 rw P3IN.5 r 4 P4SEL.4 rw-0 P4DIR.4 rw-0 P4OUT.4 rw P4IN.4 r P3SEL.4 rw-0 P3DIR.4 rw-0 P3OUT.4 rw P3IN.4 r 3 P4SEL.3 rw-0 P4DIR.3 rw-0 P4OUT.3 rw P4IN.3 r P3SEL.3 rw-0 P3DIR.3 rw-0 P3OUT.3 rw P3IN.3 r 2 P4SEL.2 rw-0 P4DIR.2 rw-0 P4OUT.2 rw P4IN.2 r P3SEL.2 rw-0 P3DIR.2 rw-0 P3OUT.2 rw P3IN.2 r 1 P4SEL.1 rw-0 P4DIR.1 rw-0 P4OUT.1 rw P4IN.1 r P3SEL.1 rw-0 P3DIR.1 rw-0 P3OUT.1 rw P3IN.1 r 0 P4SEL.0 rw-0 P4DIR.0 rw-0 P4OUT.0 rw P4IN.0 r P3SEL.0 rw-0 P3DIR.0 rw-0 P3OUT.0 rw P3IN.0 r
These interrupt enable bits and flags are included in the SFR frame.
Peripheral File Map
A-3
Digital I/O, Byte Access (Continued)
A.3 Digital I/O, Byte Access (Continued)
Bit # 002Fh Function select, P2SEL 002Eh Interrupt enable, P2IE 002Dh Interrupt edge select, P2IES 002Ch Interrupt flags, P2IFG 002Bh Direction register, P2DIR 002Ah Output register, P2OUT 0029h Input register, P2IN 0028h 0027h Function select, P1SEL 0026h Interrupt enable, P1IE 0025h Interrupt edge select, P1IES 0024h Interrupt flags, P1IFG 0023h Direction register, P1DIR 0022h Output register, P1OUT 0021h Input register, P1IN 0020h P1SEL.7 rw-0 P1IE.7 rw-0 P1IES.7 rw P1IFG.7 rw-0 P1DIR.7 rw-0 P1OUT.7 rw P1IN.7 r P1SEL.6 rw-0 P1IE.6 rw-0 P1IES.6 rw P1IFG.6 rw-0 P1DIR.6 rw-0 P1OUT.6 rw P1IN.6 r P1SEL.5 rw-0 P1IE.5 rw-0 P1IES.5 rw P1IFG.5 rw-0 P1DIR.5 rw-0 P1OUT.5 rw P1IN.5 r P1SEL.4 rw-0 P1IE.4 rw-0 P1IES.4 rw P1IFG.4 rw-0 P1DIR.4 rw-0 P1OUT.4 rw P1IN.4 r P1SEL.3 rw-0 P1IE.3 rw-0 P1IES.3 rw P1IFG.3 rw-0 P1DIR.3 rw-0 P1OUT.3 rw P1IN.3 r P1SEL.2 rw-0 P1IE.2 rw-0 P1IES.2 rw P1IFG.2 rw-0 P1DIR.2 rw-0 P1OUT.2 rw P1IN.2 r P1SEL.1 rw-0 P1IE.1 rw-0 P1IES.1 rw P1IFG.1 rw-0 P1DIR.1 rw-0 P1OUT.1 rw P1IN.1 r P1SEL.0 rw-0 P1IE.0 rw-0 P1IES.0 rw P1IFG.0 rw-0 P1DIR.0 rw-0 P1OUT.0 rw P1IN.0 r P2SEL.7 rw-0 P2IE.7 rw-0 P2IES.7 rw P2IFG.7 rw-0 P2DIR.7 rw-0 P2OUT.7 rw P2IN.7 r P2SEL.6 rw-0 P2IE.6 rw-0 P2IES.6 rw P2IFG.6 rw-0 P2DIR.6 rw-0 P2OUT.6 rw P2IN.6 r P2SEL.5 rw-0 P2IE.5 rw-0 P2IES.5 rw P2IFG.5 rw-0 P2DIR.5 rw-0 P2OUT.5 rw P2IN.5 r P2SEL.4 rw-0 P2IE.4 rw-0 P2IES.4 rw P2IFG.4 rw-0 P2DIR.4 rw-0 P2OUT.4 rw P2IN.4 r P2SEL.3 rw-0 P2IE.3 rw-0 P2IES.3 rw P2IFG.3 rw-0 P2DIR.3 rw-0 P2OUT.3 rw P2IN.3 r P2SEL.2 rw-0 P2IE.2 rw-0 P2IES.2 rw P2IFG.2 rw-0 P2DIR.2 rw-0 P2OUT.2 rw P2IN.2 r P2SEL.1 rw-0 P2IE.1 rw-0 P2IES.1 rw P2IFG.1 rw-0 P2DIR.1 rw-0 P2OUT.1 rw P2IN.1 r P2SEL.0 rw-0 P2IE.0 rw-0 P2IES.0 rw P2IFG.0 rw-0 P2DIR.0 rw-0 P2OUT.0 rw P2IN.0 r 7 6 5 4 3 2 1 0
A-4
LCD Registers, Byte Access
A.4 LCD Registers, Byte Access
Bit # - LCD memory 15 003Fh LCD memory 14 003Eh LCD memory 13 003Dh LCD memory 12 003Ch LCD memory 11 003Bh LCD memory 10 003Ah LCD memory 9 0039h LCD memory 8 0038h LCD memory 7 0037h LCD memory 6 0036h LCD memory 5 0035h LCD memory 4 0034h LCD memory 3 0033h LCD memory 2 0032h LCD memory 1 0031h LCD control & mode, LCDC 0030h Note: 7 S29C3 rw S27C3 rw S25C3 rw S23C3 rw S21C3 rw S19C3 rw S17C3 rw S15C3 rw S13C3 rw S11C3 rw S9C3 rw S7C3 rw S5C3 rw S3C3 rw S1C3 rw LCDM7 rw-0 6 S29C2 rw S27C2 rw S25C2 rw S23C2 rw S21C2 rw S19C2 rw S17C2 rw S15C2 rw S13C2 rw S11C2 rw S9C2 rw S7C2 rw S5C2 rw S3C2 rw S1C2 rw LCDM6 rw-0 5 S29C1 rw S27C1 rw S25C1 rw S23C1 rw S21C1 rw S19C1 rw S17C1 rw S15C1 rw S13C1 rw S11C1 rw S9C1 rw S7C1 rw S5C1 rw S3C1 rw S1C1 rw LCDM5 rw-0 4 S29C0 rw S27C0 rw S25C0 rw S23C0 rw S21C0 rw S19C0 rw S17C0 rw S15C0 rw S13C0 rw S11C0 rw S9C0 rw S7C0 rw S5C0 rw S3C0 rw S1C0 rw LCDM4 rw-0 3 S28C3 rw S26C3 rw S24C3 rw S22C3 rw S20C3 rw S18C3 rw S16C3 rw S14C3 rw S12C3 rw S10C3 rw S8C3 rw S6C3 rw S4C3 rw S2C3 rw S0C3 rw LCDM3 rw-0 2 S28C2 rw S26C2 rw S24C2 rw S22C2 rw S20C2 rw S18C2 rw S16C2 rw S14C2 rw S12C2 rw S10C2 rw S8C2 rw S6C2 rw S4C2 rw S2C2 rw S0C2 rw LCDM2 rw-0 1 S28C1 rw S26C1 rw S24C1 rw S22C1 rw S20C1 rw S18C1 rw S16C1 rw S14C1 rw S12C1 rw S10C1 rw S8C1 rw S6C1 rw S4C1 rw S2C1 rw S0C1 rw LCDM1 rw-0 0 S28C0 rw S26C0 rw S24C0 rw S22C0 rw S20C0 rw S18C0 rw S16C0 rw S14C0 rw S12C0 rw S10C0 rw S8C0 rw S6C0 rw S4C0 rw S2C0 rw S0C0 rw LCDM0 rw-0
The LCD memory bits are named with the MSP430 convention. The first part of the bit name indicates the corresponding segment line and the second indicates the corresponding common line. Example for a segment using S4 and Com3: S4C3
Peripheral File Map
A-5
8-Bit Timer/Counter, Basic Timer, Timer/Port, Byte Access
A.5 8-Bit Timer/Counter, Basic Timer, Timer/Port, Byte Access
Bit # - Timer/Port enable reg., TPE 04Fh Timer/Port data reg., TPD 04Eh Timer/Port counter1, TPCNT2 04Dh Timer/Port counter1, TPCNT1 04Ch Timer/Port control reg., TPCTL 04Bh 7 TPSSEL3 rw-0 B16 rw-0 27 rw 27 rw TPSSEL1 rw-0 6 TPSSEL2 rw-0 CPON rw-0 26 rw 26 rw TPSSEL0 rw-0 5 TPE.5 rw-0 TPD.5 rw-0 25 rw 25 rw ENB rw-0 4 TPE.4 rw-0 TPD.4 rw-0 24 rw 24 rw ENA rw-0 3 TPE.3 rw-0 TPD.3 rw-0 23 rw 23 rw EN1 r-0 2 TPE.2 rw-0 TPD.2 rw-0 22 rw 22 rw RC2FG rw-0 1 TPE.1 rw-0 TPD.1 rw-0 21 rw 21 rw RC1FG rw-0 0 TPE.0 rw-0 TPD.0 rw-0 20 rw 20 rw EN1FG rw-0
Counter data, 8-Bit Basic Timer, BTCNT2 0047h Counter data, 8-Bit Basic Timer, BTCNT1 0046h 0045h Counter data, 8-Bit Timer/Counter, TCDAT 0044h Preload register, 8-Bit Timer/Counter, TCPLD 0043h Control register, 8-Bit Timer/Counter, TCCTL 0042h 0041h Basic Timer, BTCTL 0040h
27 rw 27 rw
26 rw 26 rw
25 rw 25 rw
24 rw 24 rw
23 rw 23 rw
22 rw 22 rw
21 rw 21 rw
20 rw 20 rw
TCDAT.7 rw TCPLD.7 rw SSEL1 rw-0
TCDAT.6 rw TCPLD.6 rw SSEL0 rw-0
TCDAT.5 rw TCPLD.5 rw ISCTL rw-0
TCDAT.4 rw TCPLD.4 rw TXEN rw-0
TCDAT.3 rw TCPLD.3 rw ENCNT rw-0
TCDAT.2 rw TCPLD.2 rw RXACT rw-0
TCDAT.1 rw TCPLD.1 rw TXD rw-0
TCDAT.0 rw TCPLD.0 rw RXD r(-1)
SSEL rw
Hold rw
DIV rw
FRFQ1 rw
FRFQ0 rw
IP2 rw
IP1 rw
IP0 rw
A.6
FLL Registers, Byte Access
Bit # - 7 M rw-0 29 rw-0 0 r 6 26 rw-0 28 rw-0 0 r 5 25 rw-0 27 rw-0 0 r 4 24 rw-1 26 rw-0 FN_4 rw-0 3 23 rw-1 25 rw-0 FN_3 rw-0 2 22 rw-1 24 rw-0 FN_2 rw-0 1 21 rw-1 23 rw-0 21 rw-0 0 20 rw-1 22 rw-0 20 rw-0
Frequency control, SCFQCTL 0052h Frequency integrator, SCFI1 0051h Frequency integrator, SCFI0 0050h
A-6
EPROM Control Register and Crystal Buffer, Byte Access
A.7 EPROM Control Register and Crystal Buffer, Byte Access
Bit # - EPROM control register EPCTL 0054h Crystal buffer control register CBCTL 0053h 7 r-0 6 r-0 5 r-0 4 r-0 3 r-0 2 r-0 CBSEL1 w-(0) 1 VPPS rw-0 CBSEL0 w-(0) 0 EXE rw-0 CBE w-(0)
NonEPROM devices may use this register for other control purposes. Devices without XBUF may use this register for other control purposes.
A.8 USART, UART Mode (Sync=0), Byte Access
Bit # - USART Transmit buffer UTXBUF 077h USART Receive buffer URXBUF 076h USART Baud rate UBR1 075h USART Baud rate UBR0 074h USART Modulation control UMCTL 073h USART Receive control URCTL 072h USART Transmit control UTCTL 071h USART USART control UCTL 070h 7 27 rw 27 r 215 rw 27 rw m7 rw FE rw-0 Unused rw-0 PENA rw-0 6 26 rw 26 r 214 rw 26 rw m6 rw PE rw-0 CKPL rw-0 PEV rw-0 5 25 rw 25 r 213 rw 25 rw m5 rw OE rw-0 SSEL1 rw-0 SP rw-0 4 24 rw 24 r 212 rw 24 rw m4 rw BRK rw-0 SSEL0 rw-0 CHAR rw-0 3 23 rw 23 r 211 rw 23 rw m3 rw URXEIE rw-0 URXSE rw-0 Listen rw-0 2 22 rw 22 r 210 rw 22 rw m2 rw URXWIE rw-0 TXWAKE rw-0 SYNC rw-0 1 21 rw 21 r 29 rw 21 rw m1 rw RXWake rw-0 Unused rw-0 MM rw-0 0 20 rw 20 r 28 rw 20 rw m0 rw RXERR rw-0 TXEPT rw-1 SWRST rw-1
Peripheral File Map
A-7
USART, SPI Mode (Sync=1), Byte Access
A.9 USART, SPI Mode (Sync=1), Byte Access
Bit # - USART Transmit buffer UTXBUF 077h USART Receive buffer URXBUF 076h USART Baud rate UBR1 075h USART Baud rate UBR0 074h USART Modulation control UMCTL 073h USART Receive control URCTL 072h USART Transmit control UTCTL 071h USART USART control UCTL 070h 7 27 rw 27 r 215 rw 27 rw m7 rw FE rw-0 CKPH rw-0 Unused rw-0 6 26 rw 26 r 214 rw 26 rw m6 rw Undef. rw-0 CKPL rw-0 Unused rw-0 5 25 rw 25 r 213 rw 25 rw m5 rw OE rw-0 SSEL1 rw-0 Unused rw-0 4 24 rw 24 r 212 rw 24 rw m4 rw Undef. rw-0 SSEL0 rw-0 CHAR rw-0 3 23 rw 23 r 211 rw 23 rw m3 rw Unused rw-0 Unused rw-0 Listen rw-0 2 22 rw 22 r 210 rw 22 rw m2 rw Unused rw-0 Unused rw-0 SYNC rw-0 1 21 rw 21 r 29 rw 21 rw m1 rw Undef. rw-0 STC rw-0 MM rw-0 0 20 rw 20 r 28 rw 20 rw m0 rw Undef. rw-0 TXEPT rw-1 SWRST rw-1
A-8
ADC12+2, Word Access
A.10 ADC12+2, Word Access
Bit # - 11Fh 15 14 13 12 11 10 9 8
ADC12+2, Data register ADAT 118h Reserved 116h ADC12+2, Control register ACTL 114h ADC12+2, Input enable register AEN 112h ADC12+2, Input data register AIN 110h
r0
r0
R1 r0
R0 r0
211 r
210 r
29 r
28 r
ACTL.15 r0 r0
ACTL.14 rw-0 r0
ACTL.13 rw-0 r0
ACTL.12 rw-1 r0
ACTL.11 rw-0 r0
ACTL.10 rw-0 r0
ACTL.9 rw-0 r0
ACTL.8 rw-0 r0
r0
r0
r0
r0
r0
r0
r0
r0
The bits ADAT.12 and ADAT.13 are read as 0 when ACTL.11 = 0; otherwise, signals R0 and R1 are read. Bit # - 11Eh 7 6 5 4 3 2 1 0
ADC12+2, Data register ADAT 118h Reserved 116h ADC12+2, Control register ACTL 114h ADC12+2, Input enable register AEN 112h ADC12+2, Input data register AIN 110h
27 r
26 r
25 r
24 r
23 r
22 r
21 r
20 r
ACTL.7 rw-0 AEN.7 rw-0 AIN.7 r
ACTL.6 rw-0 AEN.6 rw-0 AIN.6 r
ACTL.5 rw-0 AEN.5 rw-0 AIN.5 r
ACTL.4 rw-0 AEN.4 rw-0 AIN.4 r
ACTL.3 rw-0 AEN.3 rw-0 AIN.3 r
ACTL.2 rw-0 AEN.2 rw-0 AIN.2 r
ACTL.1 rw-0 AEN.1 rw-0 AIN.1 r
ACTL.0 (w)r0 AEN.0 rw-0 AIN.0 r
Peripheral File Map
A-9
Watchdog/Timer, Word Access
A.11 Watchdog/Timer, Word Access
Bit # - Watchdog Timer, Control register WDTCTL 120h Bit # - Watchdog Timer, Control register WDTCTL 120h 15 <-------------------------- <-------------------------- Read as 069h Written as 05Ah 8 -----------------------> ------------------------>
7 HOLD rw-0
6 NMIES rw-0
5 NMI rw-0
4 TMSEL rw-0
3 CNTCL (w),r0
2 SSEL rw-0
1 IS1 rw-0
0 IS0 rw-0
A.12 Hardware Multiplier, Word Access
Bit # - Sum extend, SumExt 013Eh Result-high word ResHI 013Ch Result-low word ResLO 013Ah Second operand OP2 0138h MPYS+ACC MACS 0136h MPY+ACC MAC 0134h Multiply signed MPYS 0132h Multiply unsigned MPY 0130h 15 r 215 rw 215 rw 215 rw 215 rw 215 rw 215 rw 215 rw 14 r 214 rw 214 rw 214 rw 214 rw 214 rw 214 rw 214 rw 13 r 213 rw 213 rw 213 rw 213 rw 213 rw 213 rw 213 rw 12 r 212 rw 212 rw 212 rw 212 rw 212 rw 212 rw 212 rw 11 r 211 rw 211 rw 211 rw 211 rw 211 rw 211 rw 211 rw 10 r 210 rw 210 rw 210 rw 210 rw 210 rw 210 rw 210 rw 9 r 29 rw 29 rw 29 rw 29 rw 29 rw 29 rw 29 rw 8 r 28 rw 28 rw 28 rw 28 rw 28 rw 28 rw 28 rw
Bit # - Sum extend, SumExt 013Eh Result-high word ResHI 013Ch Result-low word ResLO 013Ah Second operand OP2 0138h MPYS+ACC MACS 0136h MPY+ACC MAC 0134h Multiply signed MPYS 0132h Multiply unsigned MPY 0130h
7 r 27 rw 27 rw 27 rw 27 rw 27 rw 27 rw 27 rw
6 r 26 rw 26 rw 26 rw 26 rw 26 rw 26 rw 26 rw
5 r 25 rw 25 rw 25 rw 25 rw 25 rw 25 rw 25 rw
4 r 24 rw 24 rw 24 rw 24 rw 24 rw 24 rw 24 rw
3 r 23 rw 23 rw 23 rw 23 rw 23 rw 23 rw 23 rw
2 r 22 rw 22 rw 22 rw 22 rw 22 rw 22 rw 22 rw
1 r 21 rw 21 rw 21 rw 21 rw 21 rw 21 rw 21 rw
0 r 20 rw 20 rw 20 rw 20 rw 20 rw 20 rw 20 rw
The Sum Extend register SumExt holds a 16x16-bit multiplication (MPYS) sign result, or the overflow of the multiply and accumulate (MAC) operation, or the sign of the signed multiply and accumulate (MACS) operation. Overflow and underflow of the MACS operation must be handled by software.
A-10
Timer_A Registers, Word Access
A.13 Timer_A Registers, Word Access
Bit # - 017Eh 017Ch Cap/com register CCR4 017Ah Cap/com register CCR3 0178h Cap/com register CCR2 0176h Cap/com register CCR1 0174h Cap/com register CCR0 0172h Timer_A register TAR 0170h 016Eh 016Ch Cap/com control CCTL4, 016Ah Cap/com control CCTL3, 0168h Cap/com control CCTL2, 0166h Cap/com control CCTL1, 0164h Cap/com control CCTL0, 0162h Timer_A control TACTL 0160h CM41 rw-(0) CM31 rw-(0) CM21 rw-(0) CM11 rw-(0) CM01 rw-(0) Unused rw-(0) CM40 rw-(0) CM30 rw-(0) CM20 rw-(0) CM10 rw-(0) CM00 rw-(0) Unused rw-(0) CCIS41 rw-(0) CCIS31 rw-(0) CCIS21 rw-(0) CCIS11 rw-(0) CCIS01 rw-(0) Unused rw-(0) CCIS40 rw-(0) CCIS30 rw-(0) CCIS20 rw-(0) CCIS10 rw-(0) CCIS00 rw-(0) Unused rw-(0) SCS4 rw-(0) SCS3 rw-(0) SCS2 rw-(0) SCS1 rw-(0) SCS0 rw-(0) Unused rw-(0) SCCI4 rw-(0) SCCI3 rw-(0) SCCI2 rw-(0) SCCI1 rw-(0) SCCI0 rw-(0) SSEL2 rw-(0) Unused r0 Unused r0 Unused r0 Unused r0 Unused r0 SSEL1 rw-(0) CAP4 rw-(0) CAP3 rw-(0) CAP2 rw-(0) CAP1 rw-(0) CAP0 rw-(0) SSEL0 rw-(0) 215 rw-(0) 215 rw-(0) 215 rw-(0) 215 rw-(0) 215 rw-(0) 215 rw-(0) 214 rw-(0) 214 rw-(0) 214 rw-(0) 214 rw-(0) 214 rw-(0) 214 rw-(0) 213 rw-(0) 213 rw-(0) 213 rw-(0) 213 rw-(0) 213 rw-(0) 213 rw-(0) 212 rw-(0) 212 rw-(0) 212 rw-(0) 212 rw-(0) 212 rw-(0) 212 rw-(0) 211 rw-(0) 211 rw-(0) 211 rw-(0) 211 rw-(0) 211 rw-(0) 211 rw-(0) 210 rw-(0) 210 rw-(0) 210 rw-(0) 210 rw-(0) 210 rw-(0) 210 rw-(0) 29 rw-(0) 29 rw-(0) 29 rw-(0) 29 rw-(0) 29 rw-(0) 29 rw-(0) 28 rw-(0) 28 rw-(0) 28 rw-(0) 28 rw-(0) 28 rw-(0) 28 rw-(0) 15 14 13 12 11 10 9 8
Registers are reserved on devices with Timer_A3.
Peripheral File Map
A-11
Timer_A Registers, Word Access (Continued)
A.13 Timer_A Registers, Word Access (Continued)
Bit # - 017Eh 017Ch Cap/com register CCR4 017Ah Cap/com register CCR3 0178h Cap/com register CCR2 0176h Cap/com register CCR1 0174h Cap/com register CCR0 0172h Timer_A register TAR 0170h 016Eh 016Ch Cap/com control CCTL4, 016Ah Cap/com control CCTL3, 0168h Cap/com control CCTL2, 0166h Cap/com control CCTL1, 0164h Cap/com control CCTL0, 0162h Timer_A control TACTL 0160h
OutMod42 OutMod41 OutMod40
7
6
5
4
3
2
1
0
27 rw-(0) 27 rw-(0) 27 rw-(0) 27 rw-(0) 27 rw-(0) 27 rw-(0)
26 rw-(0) 26 rw-(0) 26 rw-(0) 26 rw-(0) 26 rw-(0) 26 rw-(0)
25 rw-(0) 25 rw-(0) 25 rw-(0) 25 rw-(0) 25 rw-(0) 25 rw-(0)
24 rw-(0) 24 rw-(0) 24 rw-(0) 24 rw-(0) 24 rw-(0) 24 rw-(0)
23 rw-(0) 23 rw-(0) 23 rw-(0) 23 rw-(0) 23 rw-(0) 23 rw-(0)
22 rw-(0) 22 rw-(0) 22 rw-(0) 22 rw-(0) 22 rw-(0) 22 rw-(0)
21 rw-(0) 21 rw-(0) 21 rw-(0) 21 rw-(0) 21 rw-(0) 21 rw-(0)
20 rw-(0) 20 rw-(0) 20 rw-(0) 20 rw-(0) 20 rw-(0) 20 rw-(0)
rw-(0)
OutMod32
rw-(0)
OutMod31
rw-(0)
OutMod30
CCIE4 rw-(0) CCIE3 rw-(0) CCIE2 rw-(0) CCIE1 rw-(0) CCIE0 rw-(0) MC0 rw-(0)
CCI4 r CCI3 r CCI2 r CCI1 r CCI0 r Unused rw-(0)
OUT4 rw-(0) OUT3 rw-(0) OUT2 rw-(0) OUT1 rw-(0) OUT0 rw-(0) CLR rw-(0)
COV4 rw-(0) COV3 rw-(0) COV2 rw-(0) COV1 rw-(0) COV0 rw-(0) TAIE rw-(0)
CCIFG4 rw-(0) CCIFG3 rw-(0) CCIFG2 rw-(0) CCIFG1 rw-(0) CCIFG0 rw-(0) TAIFG rw-(0)
rw-(0)
OutMod22
rw-(0)
OutMod21
rw-(0)
OutMod20
rw-(0)
OutMod12
rw-(0)
OutMod11
rw-(0)
OutMod10
rw-(0)
OutMod02
rw-(0)
OutMod01
rw-(0)
OutMod00
rw-(0) ID1 rw-(0)
rw-(0) ID0 rw-(0)
rw-(0) MC1 rw-(0)
Registers are reserved on devices with Timer_A3. Bit # - Timer_A interrupt vector TAIV 12Eh 15 0 r0 14 0 r0 13 0 r0 12 0 r0 11 0 r0 10 0 r0 9 0 r0 8 0 r0
Bit # - Timer_A interru t vector interrupt TAIV 12Eh
7 0 r0
6 0 r0
5 0 r0
4 0 r0
3 r-(0)
2 TAIV r-(0)
1 r-(0)
0 0 r0
TAIV Vector, Timer_A5 (five capture/compare blocks integrated) 0: No interrupt pending 2: CCIFG1 flag set, interrupt flag of capture/compare block 1 4: CCIFG2 flag set, interrupt flag of capture/compare block 2 (CCIFG1=0) 6: CCIFG3 flag set, interrupt flag of capture/compare block 3 (CCIFG1=CCIFG2=0) 8: CCIFG3 flag set, interrupt flag of capture/compare block 3 (CCIFG1=CCIFG2=CCIFG3=0) 10: TAIFG flag set, interrupt flag of Timer_A register/counter (CCIFG1=CCIFG2=CCIFG3=CCIFG4=0) TAIV Vector, Timer_A3 (three capture/compare blocks integrated) 0: No interrupt pending 2: CCIFG1 flag set, interrupt flag of capture/compare block 1 4: CCIFG2 flag set, interrupt flag of capture/compare block 2 (CCIFG1=0) 6: Reserved 8: Reserved 10: TAIFG flag set, interrupt flag of Timer_A register/counter (CCIFG1=CCIFG2=CCIFG3=CCIFG4=0)
A-12
Appendix B
Instruction Set Description
The MSP430 core CPU architecture evolved from a reduced instruction set with highly-transparent instruction formats. Using these formats, core instructions are implemented into the hardware. Emulated instructions are also supported by the assembler. Emulated instructions use the core instructions with the built-in constant generators CG1 and CG2 and/or the program counter (PC). The core and emulated instructions are described in detail in this section. The emulated instruction mnemonics are listed with examples. Program memory words used by an instruction vary from one to three words, depending on the combination of addressing modes.
Topic
B.1 B.2
Page
Instruction Set Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-2 Instruction Set Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-8
Instruction Set Description
B-1
Instruction Set Overview
B.1 Instruction Set Overview
The following list gives an overview of the instruction set. Status Bits V * * * 0 - - 0 - - - - - - * * * * * - - * * * N * * * * - - * - - - - 0 - * * * * * - - * * * Z * * * * - - * - - - - - 0 * * * * * - - * * * C * * * * - - * - - - 0 - - * * * * * - - * * *
* ADC[.W];ADC.B ADD[.W];ADD.B ADDC[.W];ADDC.B AND[.W];AND.B BIC[.W];BIC.B BIS[.W];BIS.B BIT[.W];BIT.B * BR CALL * CLR[.W];CLR.B * CLRC * CLRN * CLRZ CMP[.W];CMP.B * DADC[.W];DADC.B DADD[.W];DADD.B * DEC[.W];DEC.B * DECD[.W];DECD.B * DINT * EINT * INC[.W];INC.B * INCD[.W];INCD.B * INV[.W];INV.B JC/JHS JEQ/JZ JGE JL JMP JN JNC/JLO JNE/JNZ
dst dst + C -> dst src,dst src + dst -> dst src,dst src + dst + C -> dst src,dst src .and. dst -> dst src,dst .not.src .and. dst -> dst src,dst src .or. dst -> dst src,dst src .and. dst dst Branch to ....... dst PC+2 -> stack, dst -> PC dst Clear destination Clear carry bit Clear negative bit Clear zero bit src,dst dst - src dst dst + C -> dst (decimal) src,dst src + dst + C -> dst (decimal) dst dst - 1 -> dst dst dst - 2 -> dst Disable interrupt Enable interrupt dst Increment destination, dst +1 -> dst dst Double-Increment destination, dst+2->dst dst Invert destination Label Jump to Label if Carry-bit is set Label Jump to Label if Zero-bit is set Label Jump to Label if (N .XOR. V) = 0 Label Jump to Label if (N .XOR. V) = 1 Label Jump to Label unconditionally Label Jump to Label if Negative-bit is set Label Jump to Label if Carry-bit is reset Label Jump to Label if Zero-bit is reset
-- -- -- -- -- -- -- -- -- -- - ---
-- -- -- --
B-2
Instruction Set Overview
Status Bits V - - - - * N - - - - * Z - - - - * C - - - - *
MOV[.W];MOV.B * NOP * POP[.W];POP.B PUSH[.W];PUSH.B RETI
* RET * RLA[.W];RLA.B * RLC[.W];RLC.B RRA[.W];RRA.B RRC[.W];RRC.B * SBC[.W];SBC.B * SETC * SETN * SETZ SUB[.W];SUB.B SUBC[.W];SUBC.B SWPB SXT * TST[.W];TST.B XOR[.W];XOR.B
src,dst src -> dst No operation dst Item from stack, SP+2 SP src SP - 2 SP, src @SP Return from interrupt TOS SR, SP + 2 SP TOS PC, SP + 2 SZP Return from subroutine TOS PC, SP + 2 SP dst Rotate left arithmetically dst Rotate left through carry dst MSB MSB ....LSB C dst C MSB .........LSB C dst Subtract carry from destination Set carry bit Set negative bit Set zero bit src,dst dst + .not.src + 1 dst src,dst dst + .not.src + C dst dst swap bytes dst Bit7 Bit8 ........ Bit15 dst Test destination src,dst src .xor. dst dst
-- -- * * 0 * * - - - * * - 0 0 * * * * * * - 1 - * * - * * * * * * * * - - 1 * * - * * * * * * * * 1 - - * * - * 1 *
Note: Asterisked Instructions Asterisked (*) instructions are emulated. They are replaced with core instructions by the assembler.
Instruction Set Description
B-3
Instruction Set Overview
B.1.1 Instruction Formats
The following sections describe the instruction formats.
B.1.1.1 Double-Operand Instructions (Core Instructions)
The instruction format using double operands, as shown in Figure B-1, consists of four main fields to form a 16-bit code:
-
operational code field, four bits source field, six bits byte operation identifier, one bit destination field, five bits
[op-code] [source register + As] [BW] [dest. register + Ad]
The source field is composed of two addressing bits and a four-bit register number (0....15). The destination field is composed of one addressing bit and a four-bit register number (0....15). The byte identifier B/W indicates whether the instruction is executed as a byte (B/W = 1) or as a word instruction (B/W = 0).
Figure B-1.Double-Operand Instructions
15 OP-Code Operational Code Field 12 11 8 7 Ad 6 B/W 5 As 4 3 Destination Register 0
Source Register
Status Bits V * * 0 - - 0 * * - * * * N * * * - - * * * - * * * Z * * * - - * * * - * * * C * * * - - * * * - * * *
ADD[.W]; ADDC[.W]; AND[.W]; BIC[.W]; BIS[.W]; BIT[.W]; CMP[.W]; DADD[.W]; MOV[.W]; SUB[.W]; SUBC[.W]; XOR[.W];
ADD.B ADDC.B AND.B BIC.B BIS.B BIT.B CMP.B DADD.B MOV.B SUB.B SUBC.B XOR.B
src,dst src,dst src,dst src,dst src,dst src,dst src,dst src,dst src,dst src,dst src,dst src,dst
src + dst -> dst src + dst + C -> dst src .and. dst -> dst .not.src .and. dst -> dst src .or. dst -> dst src .and. dst dst - src src + dst + C -> dst (dec) src -> dst dst + .not.src + 1 -> dst dst + .not.src + C -> dst src .xor. dst -> dst
Note: Operations Using the Status Register (SR) for Destination All operations using Status Register SR for destination overwrite the SR contents with the operation result; as described in that operation, the status bits are not affected. Example: ADD #3,SR ; Operation: (SR) + 3 --> SR
B-4
Instruction Set Overview
B.1.1.2 Single Operand Instructions (Core Instructions)
The instruction format using a single operand, as shown in Figure B-2, consists of two main fields to form a 16-bit code:
-
operational code field, nine bits with four MSBs equal to 1h byte operation identifier, one bit [B/W] destination field, six bits [destination register + Ad]
The destination field is composed of two addressing bits and the four-bit register number (0....15). The destination field bit position is the same as that of the two operand instructions. The byte identifier (B/W) indicates whether the instruction is executed as a byte (B/W = 1) or as a word (B/W = 0).
Figure B-2.Single-Operand Instructions
15 0 0 0 12 1 11 X 10 X 9 X X 7 X 6 B/W 5 Ad 4 3 0 Destination Register
Operational Code Field
Destination Field
Status Bits RRA[.W]; RRA.B RRC[.W]; RRC.B PUSH[.W]; PUSH.B SWPB CALL RETI SXT dst dst dst dst dst dst dst MSB MSB ...LSB C C MSB ........LSB C SP - 2 SP, src @SP swap bytes PC2 + @SP, dst PC TOS SR, SP + 2 SP TOS PC, SP + 2 SP Bit 7 Bit 8 ........ Bit 15 V 0 * - - - * N * * - - - * Z * * - - - * * C * * - - - * *
0*
B.1.2 Conditional and Unconditional Jumps (Core Instructions)
The instruction format for conditional and unconditional jumps, as shown in Figure B-3, consists of two main fields to form a 16-bit code:
-
operational code (op-code) field, six bits jump offset field, ten bits
The operational-code field is composed of the op-code ( three bits), and three bits according to the following conditions.
Figure B-3.Conditional and Unconditional Jump Instructions
15 0 0 13 1 12 X X 10 X 9 X Sign X X X X X X X X 0 X
OP-Code Jump-On Code Operational Code Field
Offset Jump Offset Field
Conditional jumps jump to addresses in the range of -511 to +512 words relative to the current address. The assembler computes the signed offsets and inserts them into the op-code.
Instruction Set Description
B-5
Instruction Set Overview
JC/JHS JEQ/JZ JGE JL JMP JN JNC/JLO JNE/JNZ
Label Label Label Label Label Label Label Label
Jump to label if carry bit is set Jump to label if zero bit is set Jump to label if (N .XOR. V) = 0 Jump to label if (N .XOR. V) = 1 Jump to label unconditionally Jump to label if negative bit is set Jump to label if carry bit is reset Jump to label if zero bit is reset
Note: Conditional and Unconditional Jumps Conditional and unconditional jumps do not affect the status bits. A jump that is taken alters the PC with the offset: PCnew = PCold + 2 + 2*offset A jump that is not taken continues the program with the ascending instruction.
B.1.3 Emulated Instructions
The following instructions can be emulated with the reduced instruction set without additional code words. The assembler accepts the emulated instruction mnemonic, and inserts the applicable core instruction op-code.
B-6
Instruction Set Overview
The following list describes the emulated instruction short form. Mnemonic Description Status Bits VNZC * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * Emulation
Arithmetical instructions ADC[.W] dst Add carry to destination ADC.B dst Add carry to destination DADC[.W] dst Add carry decimal to destination DADC.B dst Add carry decimal to destination DEC[.W] dst Decrement destination DEC.B dst Decrement destination DECD[.W] dst Double-decrement destination DECD.B dst Double-decrement destination INC[.W] dst Increment destination INC.B dst Increment destination INCD[.W] dst Increment destination INCD.B dst Increment destination SBC[.W] dst Subtract carry from destination SBC.B dst Subtract carry from destination Logical instructions INV[.W] dst INV.B dst RLA[.W] dst RLA.B dst RLC[.W] dst RLC.B dst
ADDC ADDC.B DADD DADD.B SUB SUB.B SUB SUB.B ADD ADD.B ADD ADD.B SUBC SUBC.B
#0,dst #0,dst #0,dst #0,dst #1,dst #1,dst #2,dst #2,dst #1,dst #1,dst #2,dst #2,dst #0,dst #0,dst
Invert destination Invert destination Rotate left arithmetically Rotate left arithmetically Rotate left through carry Rotate left through carry
* * * * * *
* * * * * *
* * * * * *
* * * * * *
XOR #0FFFFh,dst XOR.B #0FFFFh,dst ADD dst,dst ADD.B dst,dst ADDC dst,dst ADDC.B dst,dst
Data instructions (common use) CLR[.W] Clear destination CLR.B Clear destination CLRC Clear carry bit CLRN Clear negative bit CLRZ Clear zero bit POP dst Item from stack SETC Set carry bit SETN Set negative bit SETZ Set zero bit TST[.W] dst Test destination TST.B dst Test destination Program flow instructions BR dst Branch to ....... DINT Disable interrupt EINT Enable interrupt NOP No operation RET Return from subroutine
- - - - - - - - - 0 0
- - - 0 - - - 1 - * *
- - - - 0 - - - 1 * *
- - 0 - - - 1 - - 1 1
MOV MOV.B BIC BIC BIC MOV BIS BIS BIS CMP CMP.B
#0,dst #0,dst #1,SR #4,SR #2,SR @SP+,dst #1,SR #4,SR #2,SR #0,dst #0,dst
- - - - -
- - - - -
- - - - -
- - - - -
MOV BIC BIS MOV MOV
dst,PC #8,SR #8,SR #0h,#0h @SP+,PC
Instruction Set Description
B-7
Instruction Set Overview
B.2 Instruction Set Description
This section catalogues and describes all core and emulated instructions in alphabetical order. Some examples serve as explanations and others as application hints. The suffix .W or no suffix in the instruction mnemonic results in a word operation. The suffix .B at the instruction mnemonic results in a byte operation.
B-8
Instruction Set Overview
ADC[.W] ADC.B Syntax
Add carry to destination Add carry to destination ADC ADC.B dst dst or ADC.W dst
Operation Emulation
dst + C -> dst ADDC ADDC.B #0,dst #0,dst
Description
The carry bit (C) is added to the destination operand. The previous contents of the destination are lost. N: Set if result is negative, reset if positive Z: Set if result is zero, reset otherwise C: Set if dst was incremented from 0FFFFh to 0000, reset otherwise Set if dst was incremented from 0FFh to 00, reset otherwise V: Set if an arithmetic overflow occurs, otherwise reset OscOff, CPUOff, and GIE are not affected. The 16-bit counter pointed to by R13 is added to a 32-bit counter pointed to by R12. ADD @R13,0(R12) ; Add LSDs ADC 2(R12) ; Add carry to MSD The 8-bit counter pointed to by R13 is added to a 16-bit counter pointed to by R12. ADD.B @R13,0(R12) ; Add LSDs ADC.B 1(R12) ; Add carry to MSD
Status Bits
Mode Bits Example
Example
Instruction Set Description
B-9
Instruction Set Overview
ADD[.W] ADD.B Syntax
Add source to destination Add source to destination ADD ADD.B src,dst src,dst or ADD.W src,dst
Operation Description
src + dst -> dst The source operand is added to the destination operand. The source operand is not affected. The previous contents of the destination are lost. N: Z: C: V: Set if result is negative, reset if positive Set if result is zero, reset otherwise Set if there is a carry from the result, cleared if not Set if an arithmetic overflow occurs, otherwise reset
Status Bits
Mode Bits Example
OscOff, CPUOff, and GIE are not affected. R5 is increased by 10. The jump to TONI is performed on a carry. ADD JC ...... #10,R5 TONI
; Carry occurred ; No carry
Example
R5 is increased by 10. The jump to TONI is performed on a carry. ADD.B JC ...... #10,R5 TONI ; Add 10 to Lowbyte of R5 ; Carry occurred, if (R5) 246 [0Ah+0F6h] ; No carry
B-10
Instruction Set Overview
ADDC[.W] ADDC.B Syntax
Add source and carry to destination Add source and carry to destination ADDC ADDC.B src,dst src,dst or ADDC.W src,dst
Operation Description
src + dst + C -> dst The source operand and the carry bit (C) are added to the destination operand. The source operand is not affected. The previous contents of the destination are lost. N: Z: C: V: Set if result is negative, reset if positive Set if result is zero, reset otherwise Set if there is a carry from the MSB of the result, reset otherwise Set if an arithmetic overflow occurs, otherwise reset
Status Bits
Mode Bits Example
OscOff, CPUOff, and GIE are not affected. The 32-bit counter pointed to by R13 is added to a 32-bit counter, eleven words (20/2 + 2/2) above the pointer in R13. ADD ADDC ... @R13+,20(R13) @R13+,20(R13) ; ADD LSDs with no carry in ; ADD MSDs with carry ; resulting from the LSDs
Example
The 24-bit counter pointed to by R13 is added to a 24-bit counter, eleven words above the pointer in R13. ADD.B ADDC.B ADDC.B ... @R13+,10(R13) @R13+,10(R13) @R13+,10(R13) ; ADD LSDs with no carry in ; ADD medium Bits with carry ; ADD MSDs with carry ; resulting from the LSDs
Instruction Set Description
B-11
Instruction Set Overview
AND[.W] AND.B Syntax
Source AND destination Source AND destination AND AND.B src,dst src,dst or AND.W src,dst
Operation Description
src .AND. dst -> dst The source operand and the destination operand are logically ANDed. The result is placed into the destination. N: Z: C: V: Set if result MSB is set, reset if not set Set if result is zero, reset otherwise Set if result is not zero, reset otherwise ( = .NOT. Zero) Reset
Status Bits
Mode Bits Example
OscOff, CPUOff, and GIE are not affected. The bits set in R5 are used as a mask (#0AA55h) for the word addressed by TOM. If the result is zero, a branch is taken to label TONI. MOV AND JZ ...... ; ; ; ; ; AND JZ #0AA55h,R5 R5,TOM TONI ; Load mask into register R5 ; mask word addressed by TOM with R5 ; ; Result is not zero
or
#0AA55h,TOM TONI
Example
The bits of mask #0A5h are logically ANDed with the low byte TOM. If the result is zero, a branch is taken to label TONI. AND.B JZ ...... #0A5h,TOM TONI ; mask Lowbyte TOM with R5 ; ; Result is not zero
B-12
Instruction Set Overview
BIC[.W] BIC.B Syntax
Clear bits in destination Clear bits in destination BIC BIC.B src,dst src,dst or BIC.W src,dst
Operation Description
.NOT.src .AND. dst -> dst The inverted source operand and the destination operand are logically ANDed. The result is placed into the destination. The source operand is not affected. N: Z: C: V: Not affected Not affected Not affected Not affected
Status Bits
Mode Bits Example
OscOff, CPUOff, and GIE are not affected. The six MSBs of the RAM word LEO are cleared. BIC #0FC00h,LEO ; Clear 6 MSBs in MEM(LEO)
Example
The five MSBs of the RAM byte LEO are cleared. BIC.B #0F8h,LEO ; Clear 5 MSBs in Ram location LEO
Example
The port pins P0 and P1 are cleared. P0OUT P0_0 P0_1 BIC.B .equ .equ .equ 011h; Definition of port address 01h 02h ;Set P0.0 and P0.1 to low
#P0_0+P0_1,&P0OUT
Instruction Set Description
B-13
Instruction Set Overview
BIS[.W] BIS.B Syntax
Set bits in destination Set bits in destination BIS BIS.B src,dst src,dst or BIS.W src,dst
Operation Description
src .OR. dst -> dst The source operand and the destination operand are logically ORed. The result is placed into the destination. The source operand is not affected. N: Z: C: V: Not affected Not affected Not affected Not affected
Status Bits
Mode Bits Example
OscOff, CPUOff, and GIE are not affected. The six LSBs of the RAM word TOM are set. BIS #003Fh,TOM; set the six LSBs in RAM location TOM
Example
Start an A/D- conversion ASOC ACTL BIS .equ .equ 1 114h ; Start of conversion bit ; ADC control register ; Start A/D-conversion
#ASOC,&ACTL
Example
The three MSBs of RAM byte TOM are set. BIS.B #0E0h,TOM ; set the 3 MSBs in RAM location TOM
Example
Port pins P0 and P1 are set to high. P0OUT P0 P1 BIS.B .equ .equ .equ 011h 01h 02h
#P0+P1,&P0OUT
B-14
Instruction Set Overview
BIT[.W] BIT.B Syntax Operation Description Status Bits
Test bits in destination Test bits in destination BIT src .AND. dst The source and destination operands are logically ANDed. The result affects only the status bits. The source and destination operands are not affected. N: Z: C: V: Set if MSB of result is set, reset otherwise Set if result is zero, reset otherwise Set if result is not zero, reset otherwise (.NOT. Zero) Reset src,dst or BIT.W src,dst
Mode Bits Example
OscOff, CPUOff, and GIE are not affected. If bit 9 of R8 is set, a branch is taken to label TOM. BIT JNZ ... #0200h,R8 TOM ; bit 9 of R8 set? ; Yes, branch to TOM ; No, proceed
Example
Determine which A/D channel is configured by the MUX. ACTL BIT jnz .equ #4,&ACTL END 114h ; ADC control register ; Is channel 0 selected? ; Yes, branch to END
Example
If bit 3 of R8 is set, a branch is taken to label TOM. BIT.B JC #8,R8 TOM
Example
A serial communication receive bit (RCV) is tested. Because the carry bit is equal to the state of the tested bit while using the BIT instruction to test a single bit, the carry bit is used by the subsequent instruction; the read information is shifted into register RECBUF. ; ; Serial communication with LSB is shifted first: ; xxxx xxxx xxxx xxxx BIT.B #RCV,RCCTL ; Bit info into carry RRC RECBUF ; Carry -> MSB of RECBUF ; cxxx xxxx ...... ; repeat previous two instructions ...... ; 8 times ; cccc cccc ;^ ^ ; MSB LSB ; Serial communication with MSB is shifted first: BIT.B #RCV,RCCTL ; Bit info into carry RLC.B RECBUF ; Carry -> LSB of RECBUF ; xxxx xxxc ...... ; repeat previous two instructions ...... ; 8 times ; cccc cccc ;| LSB ; MSB
Instruction Set Description
B-15
Instruction Set Overview
* BR, BRANCH Syntax Operation Emulation Description
Branch to .......... destination BR dst -> PC MOV dst,PC dst
An unconditional branch is taken to an address anywhere in the 64K address space. All source addressing modes can be used. The branch instruction is a word instruction. Status bits are not affected. Examples for all addressing modes are given. BR #EXEC ;Branch to label EXEC or direct branch (e.g. #0A4h) ; Core instruction MOV @PC+,PC ; Branch to the address contained in EXEC ; Core instruction MOV X(PC),PC ; Indirect address ; Branch to the address contained in absolute ; address EXEC ; Core instruction MOV X(0),PC ; Indirect address ; Branch to the address contained in R5 ; Core instruction MOV R5,PC ; Indirect R5 ; Branch to the address contained in the word ; pointed to by R5. ; Core instruction MOV @R5,PC ; Indirect, indirect R5 ; Branch to the address contained in the word pointed ; to by R5 and increment pointer in R5 afterwards. ; The next time--S/W flow uses R5 pointer--it can ; alter program execution due to access to ; next address in a table pointed to by R5 ; Core instruction MOV @R5,PC ; Indirect, indirect R5 with autoincrement ; Branch to the address contained in the address ; pointed to by R5 + X (e.g. table with address ; starting at X). X can be an address or a label ; Core instruction MOV X(R5),PC ; Indirect, indirect R5 + X
Status Bits Example
BR
EXEC
BR
&EXEC
BR
R5
BR
@R5
BR
@R5+
BR
X(R5)
B-16
Instruction Set Overview
CALL Syntax Operation
Subroutine CALL dst SP - 2 PC tmp dst -> tmp -> SP -> @SP -> PC dst is evaluated and stored PC updated to TOS dst saved to PC
Description
A subroutine call is made to an address anywhere in the 64K address space. All addressing modes can be used. The return address (the address of the following instruction) is stored on the stack. The call instruction is a word instruction. Status bits are not affected. Examples for all addressing modes are given. CALL #EXEC ; Call on label EXEC or immediate address (e.g. #0A4h) ; SP-2 SP, PC+2 @SP, @PC+ PC ; Call on the address contained in EXEC ; SP-2 SP, PC+2 @SP, X(PC) PC ; Indirect address ; Call on the address contained in absolute address ; EXEC ; SP-2 SP, PC+2 @SP, X(PC) PC ; Indirect address ; Call on the address contained in R5 ; SP-2 SP, PC+2 @SP, R5 PC ; Indirect R5 ; Call on the address contained in the word ; pointed to by R5 ; SP-2 SP, PC+2 @SP, @R5 PC ; Indirect, indirect R5 ; Call on the address contained in the word ; pointed to by R5 and increment pointer in R5. ; The next time--S/W flow uses R5 pointer-- ; it can alter the program execution due to ; access to next address in a table pointed to by R5 ; SP-2 SP, PC+2 @SP, @R5 PC ; Indirect, indirect R5 with autoincrement ; Call on the address contained in the address pointed ; to by R5 + X (e.g. table with address starting at X) ; X can be an address or a label ; SP-2 SP, PC+2 @SP, X(R5) PC ; Indirect indirect R5 + X
Status Bits Example
CALL
EXEC
CALL
&EXEC
CALL
R5
CALL
@R5
CALL
@R5+
CALL
X(R5)
Instruction Set Description
B-17
Instruction Set Overview
* CLR[.W] * CLR.B Syntax
Clear destination Clear destination CLR CLR.B 0 -> dst MOV MOV.B #0,dst #0,dst dst dst or CLR.W dst
Operation Emulation
Description Status Bits Example
The destination operand is cleared. Status bits are not affected. RAM word TONI is cleared. CLR TONI ; 0 -> TONI
Example
Register R5 is cleared. CLR R5
Example
RAM byte TONI is cleared. CLR.B TONI ; 0 -> TONI
B-18
Instruction Set Overview
* CLRC Syntax Operation Emulation Description Status Bits
Clear carry bit CLRC 0 -> C BIC #1,SR
The carry bit (C) is cleared. The clear carry instruction is a word instruction. N: Z: C: V: Not affected Not affected Cleared Not affected
Mode Bits Example
OscOff, CPUOff, and GIE are not affected. The 16-bit decimal counter pointed to by R13 is added to a 32-bit counter pointed to by R12. CLRC DADD DADC ; C=0: defines start @R13,0(R12) ; add 16-bit counter to low word of 32-bit counter 2(R12) ; add carry to high word of 32-bit counter
Instruction Set Description
B-19
Instruction Set Overview
* CLRN Syntax Operation
Clear negative bit CLRN 0N or (.NOT.src .AND. dst -> dst) BIC #4,SR
Emulation Description
The constant 04h is inverted (0FFFBh) and is logically ANDed with the destination operand. The result is placed into the destination. The clear negative bit instruction is a word instruction. N: Z: C: V: Reset to 0 Not affected Not affected Not affected
Status Bits
Mode Bits Example
OscOff, CPUOff, and GIE are not affected. The Negative bit in the status register is cleared. This avoids special treatment with negative numbers of the subroutine called. CLRN CALL ...... ...... JN ...... ...... ...... RET
SUBR
SUBR
SUBRET
; If input is negative: do nothing and return
SUBRET
B-20
Instruction Set Overview
* CLRZ Syntax Operation
Clear zero bit CLRZ 0Z or (.NOT.src .AND. dst -> dst) BIC #2,SR
Emulation Description
The constant 02h is inverted (0FFFDh) and logically ANDed with the destination operand. The result is placed into the destination. The clear zero bit instruction is a word instruction. N: Z: C: V: Not affected Reset to 0 Not affected Not affected
Status Bits
Mode Bits Example
OscOff, CPUOff, and GIE are not affected. The zero bit in the status register is cleared. CLRZ
Instruction Set Description
B-21
Instruction Set Overview
CMP[.W] CMP.B Syntax
Compare source and destination Compare source and destination CMP CMP.B src,dst src,dst or CMP.W src,dst
Operation
dst + .NOT.src + 1 or (dst - src) The source operand is subtracted from the destination operand. This is accomplished by adding the 1s complement of the source operand plus 1. The two operands are not affected and the result is not stored; only the status bits are affected. N: Z: C: V: Set if result is negative, reset if positive (src >= dst) Set if result is zero, reset otherwise (src = dst) Set if there is a carry from the MSB of the result, reset otherwise Set if an arithmetic overflow occurs, otherwise reset
Description
Status Bits
Mode Bits Example
OscOff, CPUOff, and GIE are not affected. R5 and R6 are compared. If they are equal, the program continues at the label EQUAL. CMP JEQ R5,R6 EQUAL ; R5 = R6? ; YES, JUMP
Example
Two RAM blocks are compared. If they are not equal, the program branches to the label ERROR. MOV CMP JNZ DEC JNZ #NUM,R5 &BLOCK1,&BLOCK2 ERROR R5 L$1 ; number of words to be compared ; Are Words equal? ; No, branch to ERROR ; Are all words compared? ; No, another compare
L$1
Example
The RAM bytes addressed by EDE and TONI are compared. If they are equal, the program continues at the label EQUAL. CMP.B EDE,TONI JEQ EQUAL ; MEM(EDE) = MEM(TONI)? ; YES, JUMP
Example
Check two keys connected to port pins P0 and P1. If key1 is pressed, the program branches to label MENU1; if key2 is pressed, the program branches to MENU2. P0IN KEY1 KEY2 .EQU .EQU .EQU CMP.B JEQ CMP.B JEQ 010h 01h 02h #KEY1,&P0IN MENU1 #KEY2,&P0IN MENU2
B-22
Instruction Set Overview
* DADC[.W] * DADC.B Syntax
Add carry decimally to destination Add carry decimally to destination DADC DADC.B dst dst or DADC.W src,dst
Operation Emulation
dst + C -> dst (decimally) DADD DADD.B #0,dst #0,dst
Description Status Bits
The carry bit (C) is added decimally to the destination. N: Set if MSB is 1 Z: Set if dst is 0, reset otherwise C: Set if destination increments from 9999 to 0000, reset otherwise Set if destination increments from 99 to 00, reset otherwise V: Undefined OscOff, CPUOff, and GIE are not affected. The four-digit decimal number contained in R5 is added to an eight-digit decimal number pointed to by R8. CLRC DADD DADC R5,0(R8) 2(R8) ; Reset carry ; next instruction's start condition is defined ; Add LSDs + C ; Add carry to MSD
Mode Bits Example
Example
The two-digit decimal number contained in R5 is added to a four-digit decimal number pointed to by R8. CLRC DADD.B DADC R5,0(R8) 1(R8) ; Reset carry ; next instruction's start condition is defined ; Add LSDs + C ; Add carry to MSDs
Instruction Set Description
B-23
Instruction Set Overview
DADD[.W] DADD.B Syntax
Source and carry added decimally to destination Source and carry added decimally to destination DADD DADD.B src,dst src,dst or DADD.W src,dst
Operation Description
src + dst + C -> dst (decimally) The source operand and the destination operand are treated as four binary coded decimals (BCD) with positive signs. The source operand and the carry bit (C) are added decimally to the destination operand. The source operand is not affected. The previous contents of the destination are lost. The result is not defined for non-BCD numbers. N: Set if the MSB is 1, reset otherwise Z: Set if result is zero, reset otherwise C: Set if the result is greater than 9999 Set if the result is greater than 99 V: Undefined OscOff, CPUOff, and GIE are not affected. The eight-digit BCD number contained in R5 and R6 is added decimally to an eight-digit BCD number contained in R3 and R4 (R6 and R4 contain the MSDs). CLRC DADD DADD JC ; CLEAR CARRY R5,R3 ; add LSDs R6,R4 ; add MSDs with carry OVERFLOW ; If carry occurs go to error handling routine
Status Bits
Mode Bits Example
Example
The two-digit decimal counter in the RAM byte CNT is incremented by one. CLRC DADD.B or SETC DADD.B ; DADC.B ; clear Carry ; increment decimal counter
#1,CNT
#0,CNT
CNT
B-24
Instruction Set Overview
* DEC[.W] * DEC.B Syntax
Decrement destination Decrement destination DEC DEC.B dst dst or DEC.W dst
Operation Emulation Emulation Description
dst - 1 -> dst SUB SUB.B #1,dst #1,dst
The destination operand is decremented by one. The original contents are lost. N: Z: C: V: Set if result is negative, reset if positive Set if dst contained 1, reset otherwise Reset if dst contained 0, set otherwise Set if an arithmetic overflow occurs, otherwise reset. Set if initial value of destination was 08000h, otherwise reset. Set if initial value of destination was 080h, otherwise reset.
Status Bits
Mode Bits
OscOff, CPUOff, and GIE are not affected.
Instruction Set Description
B-25
Instruction Set Overview
Example
R10 is decremented by 1 DEC R10 ; Decrement R10
; Move a block of 255 bytes from memory location starting with EDE to memory location starting with ;TONI. Tables should not overlap: start of destination address TONI must not be within the range EDE ; to EDE+0FEh ; MOV #EDE,R6 MOV #255,R10 L$1 MOV.B @R6+,TONI-EDE-1(R6) DEC R10 JNZ L$1 ; Do not transfer tables using the routine above with the overlap shown in Figure B-4.
Figure B-4.Decrement Overlap
EDE
TONI EDE+254
TONI+254
Example
Memory byte at address LEO is decremented by one. DEC.B LEO ; Decrement MEM(LEO)
; Move a block of 255 bytes from memory location starting with EDE to memory location starting with ; TONI. Tables should not overlap: start of destination address TONI must not be within the range EDE ; to EDE+0FEh ; MOV #EDE,R6 MOV.B #255,LEO L$1 MOV.B @R6+,TONI-EDE-1(R6) DEC.B LEO JNZ L$1
B-26
Instruction Set Overview
* DECD[.W] * DECD.B Syntax
Double-decrement destination Double-decrement destination DECD DECD.B dst dst or DECD.W dst
Operation Emulation Emulation Description Status Bits
dst - 2 -> dst SUB SUB.B #2,dst #2,dst
The destination operand is decremented by two. The original contents are lost. N: Z: C: V: Set if result is negative, reset if positive Set if dst contained 2, reset otherwise Reset if dst contained 0 or 1, set otherwise Set if an arithmetic overflow occurs, otherwise reset. Set if initial value of destination was 08001 or 08000h, otherwise reset. Set if initial value of destination was 081 or 080h, otherwise reset.
Mode Bits Example
OscOff, CPUOff, and GIE are not affected. R10 is decremented by 2. DECD R10 ; Decrement R10 by two
; Move a block of 255 words from memory location starting with EDE to memory location ; starting with TONI ; Tables should not overlap: start of destination address TONI must not be within the ; range EDE to EDE+0FEh ; MOV #EDE,R6 MOV #510,R10 L$1 MOV @R6+,TONI-EDE-2(R6) DECD R10 JNZ L$1 Example Memory at location LEO is decremented by two. DECD.B LEO ; Decrement MEM(LEO)
Decrement status byte STATUS by two. DECD.B STATUS
Instruction Set Description
B-27
Instruction Set Overview
* DINT Syntax Operation
Disable (general) interrupts DINT 0 GIE or (0FFF7h .AND. SR SR BIC #8,SR
/
.NOT.src .AND. dst -> dst)
Emulation Description
All interrupts are disabled. The constant 08h is inverted and logically ANDed with the status register (SR). The result is placed into the SR. N: Z: C: V: Not affected Not affected Not affected Not affected
Status Bits
Mode Bits Example
GIE is reset. OscOff and CPUOff are not affected. The general interrupt enable (GIE) bit in the status register is cleared to allow a nondisrupted move of a 32-bit counter. This ensures that the counter is not modified during the move by any interrupt. DINT NOP MOV MOV EINT ; All interrupt events using the GIE bit are disabled COUNTHI,R5 ; Copy counter COUNTLO,R6 ; All interrupt events using the GIE bit are enabled
Note: Disable Interrupt If any code sequence needs to be protected from interruption, the DINT should be executed at least one instruction before the beginning of the uninterruptible sequence, or should be followed by an NOP.
B-28
Instruction Set Overview
* EINT Syntax Operation
Enable (general) interrupts EINT 1 GIE or (0008h .OR. SR -> SR / .NOT.src .OR. dst -> dst) BIS #8,SR
Emulation Description
All interrupts are enabled. The constant #08h and the status register SR are logically ORed. The result is placed into the SR. N: Z: C: V: Not affected Not affected Not affected Not affected
Status Bits
Mode Bits Example
GIE is set. OscOff and CPUOff are not affected. The general interrupt enable (GIE) bit in the status register is set.
; Interrupt routine of port P0.2 to P0.7 ; The interrupt level is the lowest in the system ; P0IN is the address of the register where all port bits are read. P0IFG is the address of ; the register where all interrupt events are latched. ; PUSH.B &P0IN BIC.B @SP,&P0IFG ; Reset only accepted flags EINT ; Preset port 0 interrupt flags stored on stack ; other interrupts are allowed BIT #Mask,@SP JEQ MaskOK ; Flags are present identically to mask: jump ...... MaskOK BIC #Mask,@SP ...... INCD SP ; Housekeeping: inverse to PUSH instruction ; at the start of interrupt subroutine. Corrects ; the stack pointer. RETI Note: Enable Interrupt The instruction following the enable interrupt instruction (EINT) is always executed, even if an interrupt service request is pending when the interrupts are enable.
Instruction Set Description
B-29
Instruction Set Overview
* INC[.W] * INC.B Syntax
Increment destination Increment destination INC INC.B dst dst or INC.W dst
Operation Emulation Description Status Bits
dst + 1 -> dst ADD #1,dst
The destination operand is incremented by one. The original contents are lost. N: Set if result is negative, reset if positive Z: Set if dst contained 0FFFFh, reset otherwise Set if dst contained 0FFh, reset otherwise C: Set if dst contained 0FFFFh, reset otherwise Set if dst contained 0FFh, reset otherwise V: Set if dst contained 07FFFh, reset otherwise Set if dst contained 07Fh, reset otherwise OscOff, CPUOff, and GIE are not affected. The item on the top of a software stack (not the system stack) for byte data is removed. SSP ; .EQU INC R4 SSP ; Remove TOSS (top of SW stack) by increment ; Do not use INC.B since SSP is a word register
Mode Bits Example
Example
The status byte of a process STATUS is incremented. When it is equal to 11, a branch to OVFL is taken. INC.B CMP.B JEQ STATUS #11,STATUS OVFL
B-30
Instruction Set Overview
* INCD[.W] * INCD.B Syntax
Double-increment destination Double-increment destination INCD INCD.B dst dst or INCD.W dst
Operation Emulation Emulation Example Status Bits
dst + 2 -> dst ADD ADD.B #2,dst #2,dst
The destination operand is incremented by two. The original contents are lost. N: Set if result is negative, reset if positive Z: Set if dst contained 0FFFEh, reset otherwise Set if dst contained 0FEh, reset otherwise C: Set if dst contained 0FFFEh or 0FFFFh, reset otherwise Set if dst contained 0FEh or 0FFh, reset otherwise V: Set if dst contained 07FFEh or 07FFFh, reset otherwise Set if dst contained 07Eh or 07Fh, reset otherwise OscOff, CPUOff, and GIE are not affected. The item on the top of the stack (TOS) is removed without using a register. ....... PUSH INCD
Mode Bits Example
R5 SP
; R5 is the result of a calculation, which is stored ; in the system stack ; Remove TOS by double-increment from stack ; Do not use INCD.B, SP is a word-aligned ; register
RET Example The byte on the top of the stack is incremented by two. INCD.B 0(SP) ; Byte on TOS is increment by two
Instruction Set Description
B-31
Instruction Set Overview
* INV[.W] * INV.B Syntax
Invert destination Invert destination INV INV.B dst dst
Operation Emulation Emulation Description Status Bits
.NOT.dst -> dst XOR XOR.B #0FFFFh,dst #0FFh,dst
The destination operand is inverted. The original contents are lost. N: Set if result is negative, reset if positive Z: Set if dst contained 0FFFFh, reset otherwise Set if dst contained 0FFh, reset otherwise C: Set if result is not zero, reset otherwise ( = .NOT. Zero) Set if result is not zero, reset otherwise ( = .NOT. Zero) V: Set if initial destination operand was negative, otherwise reset OscOff, CPUOff, and GIE are not affected. Content of R5 is negated (twos complement). MOV #00Aeh,R5 ; INV R5 ; Invert R5, INC R5 ; R5 is now negated, Content of memory byte LEO is negated. MOV.B INV.B INC.B #0AEh,LEO ; MEM(LEO) = 0AEh LEO ; Invert LEO, MEM(LEO) = 051h LEO ; MEM(LEO) is negated,MEM(LEO) = 052h
Mode Bits Example
R5 = 000AEh R5 = 0FF51h R5 = 0FF52h
Example
B-32
Instruction Set Overview
JC JHS Syntax
Jump if carry set Jump if higher or same JC JHS label label
Operation
If C = 1: PC + 2 x offset -> PC If C = 0: execute following instruction The status register carry bit (C) is tested. If it is set, the 10-bit signed offset contained in the instruction LSBs is added to the program counter. If C is reset, the next instruction following the jump is executed. JC (jump if carry/higher or same) is used for the comparison of unsigned numbers (0 to 65536). Status bits are not affected. The P0IN.1 signal is used to define or control the program flow. BIT JC ...... #10h,&P0IN PROGA ; State of signal -> Carry ; If carry=1 then execute program routine A ; Carry=0, execute program here
Description
Status Bits Example
Example
R5 is compared to 15. If the content is higher or the same, branch to LABEL. CMP JHS ...... #15,R5 LABEL ; Jump is taken if R5 15 ; Continue here if R5 < 15
Instruction Set Description
B-33
Instruction Set Overview
JEQ, JZ Syntax Operation
Jump if equal, jump if zero JEQ label, JZ label
If Z = 1: PC + 2 x offset -> PC If Z = 0: execute following instruction The status register zero bit (Z) is tested. If it is set, the 10-bit signed offset contained in the instruction LSBs is added to the program counter. If Z is not set, the instruction following the jump is executed. Status bits are not affected. Jump to address TONI if R7 contains zero. TST JZ R7 TONI ; Test R7 ; if zero: JUMP
Description
Status Bits Example
Example
Jump to address LEO if R6 is equal to the table contents. CMP JEQ ...... R6,Table(R5) LEO ; Compare content of R6 with content of ; MEM (table address + content of R5) ; Jump if both data are equal ; No, data are not equal, continue here
Example
Branch to LABEL if R5 is 0. TST JZ ...... R5 LABEL
B-34
Instruction Set Overview
JGE Syntax Operation
Jump if greater or equal JGE label
If (N .XOR. V) = 0 then jump to label: PC + 2 x offset -> PC If (N .XOR. V) = 1 then execute the following instruction The status register negative bit (N) and overflow bit (V) are tested. If both N and V are set or reset, the 10-bit signed offset contained in the instruction LSBs is added to the program counter. If only one is set, the instruction following the jump is executed. This allows comparison of signed integers.
Description
Status Bits Example
Status bits are not affected. When the content of R6 is greater or equal to the memory pointed to by R7, the program continues at label EDE. CMP JGE ...... ...... ...... @R7,R6 EDE ; R6 (R7)?, compare on signed numbers ; Yes, R6 (R7) ; No, proceed
Instruction Set Description
B-35
Instruction Set Overview
JL Syntax Operation
Jump if less JL label
If (N .XOR. V) = 1 then jump to label: PC + 2 x offset -> PC If (N .XOR. V) = 0 then execute following instruction The status register negative bit (N) and overflow bit (V) are tested. If only one is set, the 10-bit signed offset contained in the instruction LSBs is added to the program counter. If both N and V are set or reset, the instruction following the jump is executed. This allows comparison of signed integers.
Description
Status Bits Example
Status bits are not affected. When the content of R6 is less than the memory pointed to by R7, the program continues at label EDE. CMP JL ...... ...... ...... @R7,R6 EDE ; R6 < (R7)?, compare on signed numbers ; Yes, R6 < (R7) ; No, proceed
B-36
Instruction Set Overview
JMP Syntax Operation Description
Jump unconditionally MP label
PC + 2 x offset -> PC The 10-bit signed offset contained in the instruction LSBs is added to the program counter. Status bits are not affected. This one-word instruction replaces the BRANCH instruction in the range of - 511 to +512 words relative to the current program counter.
Status Bits Hint:
Instruction Set Description
B-37
Instruction Set Overview
JN Syntax Operation
Jump if negative JN label
if N = 1: PC + 2 x offset -> PC if N = 0: execute following instruction The negative bit (N) of the status register is tested. If it is set, the 10-bit signed offset contained in the instruction LSBs is added to the program counter. If N is reset, the next instruction following the jump is executed. Status bits are not affected. The result of a computation in R5 is to be subtracted from COUNT. If the result is negative, COUNT is to be cleared and the program continues execution in another path. SUB JN ...... ...... ...... ...... CLR ...... ...... ...... R5,COUNT L$1 ; COUNT - R5 -> COUNT ; If negative continue with COUNT=0 at PC=L$1 ; Continue with COUNT0
Description
Status Bits Example
L$1
COUNT
B-38
Instruction Set Overview
JNC JLO Syntax
Jump if carry not set Jump if lower JNC JNC label label
Operation
if C = 0: PC + 2 x offset -> PC if C = 1: execute following instruction The status register carry bit (C) is tested. If it is reset, the 10-bit signed offset contained in the instruction LSBs is added to the program counter. If C is set, the next instruction following the jump is executed. JNC (jump if no carry/lower) is used for the comparison of unsigned numbers (0 to 65536). Status bits are not affected. The result in R6 is added in BUFFER. If an overflow occurs, an error handling routine at address ERROR is used. ADD JNC ...... ...... ...... ...... ...... ...... ...... R6,BUFFER CONT ; BUFFER + R6 -> BUFFER ; No carry, jump to CONT ; Error handler start
Description
Status Bits Example
ERROR
CONT
; Continue with normal program flow
Example
Branch to STL 2 if byte STATUS contains 1 or 0. CMP.B JLO ...... #2,STATUS STL2
; STATUS < 2 ; STATUS 2, continue here
Instruction Set Description
B-39
Instruction Set Overview
JNE, JNZ Syntax Operation
Jump if not equal, jump if not zero JNE label, JNZ label
If Z = 0: PC + 2 x offset -> PC If Z = 1: execute following instruction The status register zero bit (Z) is tested. If it is reset, the 10-bit signed offset contained in the instruction LSBs is added to the program counter. If Z is set, the next instruction following the jump is executed. Status bits are not affected. Jump to address TONI if R7 and R8 have different contents. CMP JNE ...... R7,R8 TONI ; COMPARE R7 WITH R8 ; if different: jump ; if equal, continue
Description
Status Bits Example
B-40
Instruction Set Overview
MOV[.W] MOV.B Syntax
Move source to destination Move source to destination MOV MOV.B src -> dst The source operand is moved to the destination. The source operand is not affected. The previous contents of the destination are lost. Status bits are not affected. OscOff, CPUOff, and GIE are not affected. The contents of table EDE (word data) are copied to table TOM. The length of the tables must be 020h locations. MOV MOV MOV DEC JNZ ...... ...... ...... #EDE,R10 #020h,R9 @R10+,TOM-EDE-2(R10) R9 Loop ; Prepare pointer ; Prepare counter ; Use pointer in R10 for both tables ; Decrement counter ; Counter 0, continue copying ; Copying completed src,dst src,dst or MOV.W src,dst
Operation Description
Status Bits Mode Bits Example
Loop
Example
The contents of table EDE (byte data) are copied to table TOM. The length of the tables should be 020h locations MOV #EDE,R10 MOV #020h,R9 MOV.B @R10+,TOM-EDE-1(R10) DEC JNZ ...... ...... ...... R9 Loop ; Prepare pointer ; Prepare counter ; Use pointer in R10 for ; both tables ; Decrement counter ; Counter 0, continue ; copying ; Copying completed
Loop
Instruction Set Description
B-41
Instruction Set Overview
* NOP Syntax Operation Emulation Description
No operation NOP None MOV #0,#0
No operation is performed. The instruction may be used for the elimination of instructions during the software check or for defined waiting times. Status bits are not affected. The NOP instruction is mainly used for two purposes:
Status Bits
-
To hold one, two or three memory words To adjust software timing
Note: Emulating No-Operation Instruction Other instructions can emulate no-operation instruction using different numbers of cycles and code words. Examples: MOV MOV BIC JMP BIC 0(R4),0(R4) @R4,0(R4) #0,EDE(R4) $+2 #0,R5 ; 6 cycles, 3 words ; 5 cycles, 2 words ; 4 cycles, 2 words ; 2 cycles, 1 word ; 1 cycle, 1 word
B-42
Instruction Set Overview
* POP[.W] * POP.B Syntax
Pop word from stack to destination Pop byte from stack to destination POP POP.B dst dst
Operation
@SP -> dst SP + 2 -> SP MOV MOV.B @SP+,dst @SP+,dst or MOV.W @SP+,dst
Emulation Emulation Description
The stack location pointed to by the stack pointer (TOS) is moved to the destination. The stack pointer is incremented by two afterwards. Status bits are not affected. The contents of R7 and the status register are restored from the stack. POP POP R7 SR ; Restore R7 ; Restore status register
Status Bits Example
Example
The contents of RAM byte LEO is restored from the stack. POP.B LEO ; The low byte of the stack is moved to LEO.
Example
The contents of R7 is restored from the stack. POP.B R7 ; The low byte of the stack is moved to R7, ; the high byte of R7 is 00h
Example
The contents of the memory pointed to by R7 and the status register are restored from the stack. POP.B 0(R7) ; The low byte of the stack is moved to the ; the byte which is pointed to by R7 : Example: R7 = 203h ; Mem(R7) = low byte of system stack : Example: R7 = 20Ah ; Mem(R7) = low byte of system stack
POP
(
SR
Note: The System Stack Pointer The system stack pointer (SP) is always incremented by two, independent of the byte suffix.
Instruction Set Description
B-43
Instruction Set Overview
PUSH[.W] PUSH.B Syntax
Push word onto stack Push byte onto stack PUSH PUSH.B SP - 2 SP src @SP The stack pointer is decremented by two, then the source operand is moved to the RAM word addressed by the stack pointer (TOS). N: Z: C: V: Not affected Not affected Not affected Not affected src src or PUSH.W src
Operation
Description
Status Bits
Mode Bits Example
OscOff, CPUOff, and GIE are not affected. The contents of the status register and R8 are saved on the stack. PUSH PUSH SR R8 ; save status register ; save R8
Example
The contents of the peripheral TCDAT is saved on the stack. PUSH.B &TCDAT ; save data from 8-bit peripheral module, ; address TCDAT, onto stack
Note: The System Stack Pointer The system stack pointer (SP) is always decremented by two, independent of the byte suffix.
B-44
Instruction Set Overview
* RET Syntax Operation
Return from subroutine RET @SP PC SP + 2 SP MOV @SP+,PC
Emulation Description
The return address pushed onto the stack by a CALL instruction is moved to the program counter. The program continues at the code address following the subroutine call. Status bits are not affected.
Status Bits
Instruction Set Description
B-45
Instruction Set Overview
RETI Syntax Operation
Return from interrupt RETI TOS SP + 2 TOS SP + 2 SR SP PC SP
Description
The status register is restored to the value at the beginning of the interrupt service routine by replacing the present SR contents with the TOS contents. The stack pointer (SP) is incremented by two. The program counter is restored to the value at the beginning of interrupt service. This is the consecutive step after the interrupted program flow. Restoration is performed by replacing the present PC contents with the TOS memory contents. The stack pointer (SP) is incremented.
Status Bits
N: Z: C: V:
restored from system stack restored from system stack restored from system stack restored from system stack
Mode Bits Example
OscOff, CPUOff, and GIE are restored from system stack. Figure B-5 illustrates the main program interrupt.
Figure B-5.Main Program Interrupt
PC -6 PC -4 PC -2 PC PC +2 PC +4 PC +6 PC +8 Interrupt Accepted PC+2 is Stored Onto Stack PC = PCi PCi +2 PCi +4 Interrupt Request
PCi +n-4 PCi +n-2 PCi +n RETI
B-46
Instruction Set Overview
* RLA[.W] * RLA.B Syntax Operation Emulation Description
Rotate left arithmetically Rotate left arithmetically RLA RLA.B dst dst or RLA.W dst
C <- MSB <- MSB-1 .... LSB+1 <- LSB <- 0 ADD ADD.B dst,dst dst,dst
The destination operand is shifted left one position as shown in Figure B-6. The MSB is shifted into the carry bit (C) and the LSB is filled with 0. The RLA instruction acts as a signed multiplication by 2. An overflow occurs if dst 04000h and dst < 0C000h before operation is performed: the result has changed sign.
Figure B-6.Destination Operand--Arithmetic Shift Left
Word C Byte 7 0 15 0 0
An overflow occurs if dst 040h and dst < 0C0h before the operation is performed: the result has changed sign. Status Bits N: Z: C: V: Set if result is negative, reset if positive Set if result is zero, reset otherwise Loaded from the MSB Set if an arithmetic overflow occurs: the initial value is 04000h dst < 0C000h; otherwise it is reset Set if an arithmetic overflow occurs: the initial value is 040h dst < 0C0h; otherwise it is reset
Mode Bits Example
OscOff, CPUOff, and GIE are not affected. R7 is multiplied by 4. RLA RLA R7 R7 ; Shift left R7 (x 2) - emulated by ADD R7,R7 ; Shift left R7 (x 4) - emulated by ADD R7,R7
Example
The low byte of R7 is multiplied by 4. RLA.B RLA.B R7 R7 ; Shift left low byte of R7 (x 2) - emulated by ; ADD.B R7,R7 ; Shift left low byte of R7 (x 4) - emulated by ; ADD.B R7,R7
Note: RLA Substitution The assembler does not recognize the instruction: RLA @R5+ nor RLA.B @R5+.
It must be substituted by: ADD @R5+,-2(R5) or ADD.B @R5+,-1(R5).
Instruction Set Description
B-47
Instruction Set Overview
* RLC[.W] * RLC.B Syntax Operation Emulation Description
Rotate left through carry Rotate left through carry RLC RLC.B dst dst or RLC.W dst
C <- MSB <- MSB-1 .... LSB+1 <- LSB <- C ADDC dst,dst
The destination operand is shifted left one position as shown in Figure B-7. The carry bit (C) is shifted into the LSB and the MSB is shifted into the carry bit (C).
Figure B-7.Destination Operand--Carry Left Shift
Word C Byte 7 0 15 0
Status Bits
N: Z: C: V:
Set if result is negative, reset if positive Set if result is zero, reset otherwise Loaded from the MSB Set if arithmetic overflow occurs, reset otherwise Set if 03FFFh < dstinitial < 0C000h, reset otherwise Set if 03Fh < dstinitial < 0C0h, reset otherwise
Mode Bits Example
OscOff, CPUOff, and GIE are not affected. R5 is shifted left one position. RLC R5 ; (R5 x 2) + C -> R5
Example
The input P0IN.1 information is shifted into the LSB of R5. BIT.B RLC #2,&P0IN R5 ; Information -> Carry ; Carry=P0in.1 -> LSB of R5
Example
The MEM(LEO) content is shifted left one position. RLC.B LEO ; Mem(LEO) x 2 + C -> Mem(LEO)
Example
The input P0IN.1 information is to be shifted into the LSB of R5. BIT.B RLC.B #2,&P0IN R5 ; Information -> Carry ; Carry = P0in.1 -> LSB of R5 ; High byte of R5 is reset
Note: RLC and RLC.B Emulation The assembler does not recognize the instruction: RLC @R5+.
It must be substituted by: ADDC @R5+,-2(R5).
B-48
Instruction Set Overview
RRA[.W] RRA.B Syntax
Rotate right arithmetically Rotate right arithmetically RRA RRA.B dst dst or RRA.W dst
Operation Description
MSB -> MSB, MSB -> MSB-1, ... LSB+1 -> LSB,
LSB -> C
The destination operand is shifted right one position as shown in Figure B-8. The MSB is shifted into the MSB, the MSB is shifted into the MSB-1, and the LSB+1 is shifted into the LSB.
Figure B-8.Destination Operand--Arithmetic Right Shift
Word C Byte 15 0 15 0
Status Bits
N: Z: C: V:
Set if result is negative, reset if positive Set if result is zero, reset otherwise Loaded from the LSB Reset
Mode Bits
OscOff, CPUOff, and GIE are not affected.
Instruction Set Description
B-49
Running Title--Attribute Reference
Example
R5 is shifted right one position. The MSB retains the old value. It operates equal to an arithmetic division by 2. RRA R5 ; R5/2 -> R5
; ;
The value in R5 is multiplied by 0.75 (0.5 + 0.25). PUSH RRA ADD RRA ...... ...... R5 R5 @SP+,R5 R5 ; hold R5 temporarily using stack ; R5 x 0.5 -> R5 ; R5 x 0.5 + R5 = 1.5 x R5 -> R5 ; (1.5 x R5) x 0.5 = 0.75 x R5 -> R5
; OR ; RRA PUSH RRA ADD ...... Example R5 R5 @SP @SP+,R5 ; R5 x 0.5 -> R5 ; R5 x 0.5 -> TOS ; TOS x 0.5 = 0.5 x R5 x 0.5 = 0.25 x R5 -> TOS ; R5 x 0.5 + R5 x 0.25 = 0.75 x R5 -> R5
The low byte of R5 is shifted right one position. The MSB retains the old value. It operates equal to an arithmetic division by 2. RRA.B R5 ; R5/2 -> R5: operation is on low byte only ; High byte of R5 is reset
; ;
The value in R5 (low byte only) is multiplied by 0.75 (0.5 + 0.25). PUSH.B RRA.B ADD.B RRA.B ...... R5 R5 @SP+,R5 R5 ; hold low byte of R5 temporarily using stack ; R5 x 0.5 -> R5 ; R5 x 0.5 + R5 = 1.5 x R5 -> R5 ; (1.5 x R5) x 0.5 = 0.75 x R5 -> R5
; OR ; RRA.B PUSH.B RRA.B ADD.B ...... R5 R5 @SP @SP+,R5 ; R5 x 0.5 -> R5 ; R5 x 0.5 -> TOS ;TOS x 0.5 = 0.5 x R5 x 0.5 = 0.25 x R5 -> TOS ; R5 x 0.5 + R5 x 0.25 = 0.75 x R5 -> R5
B-50
Instruction Set Overview
RRC[.W] RRC.B Syntax
Rotate right through carry Rotate right through carry RRC RRC dst dst or RRC.W dst
Operation Description
C -> MSB -> MSB-1 .... LSB+1 -> LSB -> C The destination operand is shifted right one position as shown in Figure B-6. The carry bit (C) is shifted into the MSB, the LSB is shifted into the carry bit (C).
Figure B-9.Destination Operand--Carry Right Shift
Word C Byte 7 0 15 0
Status Bits
N: Z: C: V:
Set if result is negative, reset if positive Set if result is zero, reset otherwise Loaded from the LSB Set if initial destination is positive and initial carry is set, otherwise reset
Mode Bits Example
OscOff, CPUOff, and GIE are not affected. R5 is shifted right one position. The MSB is loaded with 1. SETC RRC ; Prepare carry for MSB ; R5/2 + 8000h -> R5
R5
Example
R5 is shifted right one position. The MSB is loaded with 1. SETC RRC.B ; Prepare carry for MSB ; R5/2 + 80h -> R5; low byte of R5 is used
R5
Instruction Set Description
B-51
Instruction Set Overview
* SBC[.W] * SBC.B Syntax
Subtract (borrow*) from destination Subtract (borrow*) from destination SBC SBC.B dst dst or SBC.W dst
Operation
dst + 0FFFFh + C -> dst dst + 0FFh + C -> dst SUBC SUBC.B #0,dst #0,dst
Emulation
Description
The carry bit (C) is added to the destination operand minus one. The previous contents of the destination are lost. N: Set if result is negative, reset if positive Z: Set if result is zero, reset otherwise C: Reset if dst was decremented from 0000 to 0FFFFh, set otherwise Reset if dst was decremented from 00 to 0FFh, set otherwise V: Set if initially C = 0 and dst = 08000h Set if initially C = 0 and dst = 080h OscOff, CPUOff, and GIE are not affected. The 16-bit counter pointed to by R13 is subtracted from a 32-bit counter pointed to by R12. SUB SBC @R13,0(R12) 2(R12) ; Subtract LSDs ; Subtract carry from MSD
Status Bits
Mode Bits Example
Example
The 8-bit counter pointed to by R13 is subtracted from a 16-bit counter pointed to by R12. SUB.B SBC.B @R13,0(R12) 1(R12) ; Subtract LSDs ; Subtract carry from MSD
Note: Borrow Is Treated as a .NOT. The borrow is treated as a .NOT. carry : Borrow Yes No Carry bit 0 1
B-52
Instruction Set Overview
* SETC Syntax Operation Emulation Description Status Bits
Set carry bit SETC 1 -> C BIS #1,SR
The carry bit (C) is set. N: Z: C: V: Not affected Not affected Set Not affected
Mode Bits Example
OscOff, CPUOff, and GIE are not affected. Emulation of the decimal subtraction: Subtract R5 from R6 decimally Assume that R5 = 3987 and R6 = 4137 ADD INV SETC DADD #6666h,R5 R5 ; Move content R5 from 0-9 to 6-0Fh ; R5 = 03987 + 6666 = 09FEDh ; Invert this (result back to 0-9) ; R5 = .NOT. R5 = 06012h ; Prepare carry = 1 ; Emulate subtraction by addition of: ; (10000 - R5 - 1) ; R6 = R6 + R5 + 1 ; R6 = 4137 + 06012 + 1 = 1 0150 = 0150
DSUB
R5,R6
Instruction Set Description
B-53
Instruction Set Overview
* SETN Syntax Operation Emulation Description Status Bits
Set negative bit SETN 1 -> N BIS #4,SR
The negative bit (N) is set. N: Z: C: V: Set Not affected Not affected Not affected
Mode Bits
OscOff, CPUOff, and GIE are not affected.
B-54
Instruction Set Overview
* SETZ Syntax Operation Emulation Description Status Bits
Set zero bit SETZ 1 -> Z BIS #2,SR
The zero bit (Z) is set. N: Z: C: V: Not affected Set Not affected Not affected
Mode Bits
OscOff, CPUOff, and GIE are not affected.
Instruction Set Description
B-55
Instruction Set Overview
SUB[.W] SUB.B Syntax
Subtract source from destination Subtract source from destination SUB SUB.B src,dst src,dst or SUB.W src,dst
Operation
dst + .NOT.src + 1 -> dst or [(dst - src -> dst)] The source operand is subtracted from the destination operand by adding the source operand's 1s complement and the constant 1. The source operand is not affected. The previous contents of the destination are lost. N: Set if result is negative, reset if positive Z: Set if result is zero, reset otherwise C: Set if there is a carry from the MSB of the result, reset otherwise. Set to 1 if no borrow, reset if borrow. V: Set if an arithmetic overflow occurs, otherwise reset OscOff, CPUOff, and GIE are not affected. See example at the SBC instruction. See example at the SBC.B instruction. Note: Borrow Is Treated as a .NOT. The borrow is treated as a .NOT. carry : Borrow Yes No Carry bit 0 1
Description
Status Bits
Mode Bits Example Example
B-56
Instruction Set Overview
SUBC[.W]SBB[.W] SUBC.B,SBB.B Syntax
Subtract source and borrow/.NOT. carry from destination Subtract source and borrow/.NOT. carry from destination SUBC SBB SUBC.B src,dst src,dst src,dst or or or SUBC.W SBB.W SBB.B src,dst src,dst src,dst or
Operation
dst + .NOT.src + C -> dst or (dst - src - 1 + C -> dst) The source operand is subtracted from the destination operand by adding the source operand's 1s complement and the carry bit (C). The source operand is not affected. The previous contents of the destination are lost. N: Set if result is negative, reset if positive. Z: Set if result is zero, reset otherwise. C: Set if there is a carry from the MSB of the result, reset otherwise. Set to 1 if no borrow, reset if borrow. V: Set if an arithmetic overflow occurs, reset otherwise. OscOff, CPUOff, and GIE are not affected. Two floating point mantissas (24 bits) are subtracted. LSBs are in R13 and R10, MSBs are in R12 and R9. SUB.W SUBC.B R13,R10 ; 16-bit part, LSBs R12,R9 ; 8-bit part, MSBs
Description
Status Bits
Mode Bits Example
Example
The 16-bit counter pointed to by R13 is subtracted from a 16-bit counter in R10 and R11(MSD). SUB.B SUBC.B ... @R13+,R10 @R13,R11 ; Subtract LSDs without carry ; Subtract MSDs with carry ; resulting from the LSDs
Note: Borrow Is Treated as a .NOT. Carry The borrow is treated as a .NOT. carry : Borrow Yes No Carry bit 0 1
Instruction Set Description
B-57
Instruction Set Overview
SWPB Syntax Operation Description
Swap bytes SWPB dst
Bits 15 to 8 <-> bits 7 to 0 The destination operand high and low bytes are exchanged as shown in Figure B-10. N: Z: C: V: Not affected Not affected Not affected Not affected
Status Bits
Mode Bits
OscOff, CPUOff, and GIE are not affected.
Figure B-10. Destination Operand Byte Swap
15 8 7 0
Example MOV SWPB Example #040BFh,R7 R7 ; 0100000010111111 -> R7 ; 1011111101000000 in R7
The value in R5 is multiplied by 256. The result is stored in R5,R4. SWPB MOV BIC BIC R5 R5,R4 #0FF00h,R5 #00FFh,R4 ; ;Copy the swapped value to R4 ;Correct the result ;Correct the result
B-58
Instruction Set Overview
SXT Syntax Operation Description Status Bits
Extend Sign SXT dst
Bit 7 -> Bit 8 ......... Bit 15 The sign of the low byte is extended into the high byte as shown in Figure B-11. N: Z: C: V: Set if result is negative, reset if positive Set if result is zero, reset otherwise Set if result is not zero, reset otherwise (.NOT. Zero) Reset
Mode Bits
OscOff, CPUOff, and GIE are not affected.
Figure B-11. Destination Operand Sign Extension
15 8 7 0
Example
R7 is loaded with the Timer/Counter value. The operation of the sign-extend instruction expands bit 8 to bit 15 with the value of bit 7. R7 is then added to R6. MOV.B SXT ADD &TCDAT,R7 R7 R7,R6 ; TCDAT = 080h: . . . . . . . . 1000 0000 ; R7 = 0FF80h: 1111 1111 1000 0000 ; add value of EDE to 16-bit ACCU
Instruction Set Description
B-59
Instruction Set Overview
* TST[.W] * TST.B Syntax
Test destination Test destination TST TST.B dst dst or TST.W dst
Operation
dst + 0FFFFh + 1 dst + 0FFh + 1 CMP CMP.B #0,dst #0,dst
Emulation
Description
The destination operand is compared with zero. The status bits are set according to the result. The destination is not affected. N: Z: C: V: Set if destination is negative, reset if positive Set if destination contains zero, reset otherwise Set Reset
Status Bits
Mode Bits Example
OscOff, CPUOff, and GIE are not affected. R7 is tested. If it is negative, continue at R7NEG; if it is positive but not zero, continue at R7POS. TST JN JZ ...... ...... ...... R7 R7NEG R7ZERO ; Test R7 ; R7 is negative ; R7 is zero ; R7 is positive but not zero ; R7 is negative ; R7 is zero
R7POS R7NEG R7ZERO Example
The low byte of R7 is tested. If it is negative, continue at R7NEG; if it is positive but not zero, continue at R7POS. TST.B JN JZ ...... ..... ...... R7 R7NEG R7ZERO ; Test low byte of R7 ; Low byte of R7 is negative ; Low byte of R7 is zero ; Low byte of R7 is positive but not zero ; Low byte of R7 is negative ; Low byte of R7 is zero
R7POS R7NEG R7ZERO
B-60
Instruction Set Overview
XOR[.W] XOR.B Syntax
Exclusive OR of source with destination Exclusive OR of source with destination XOR XOR.B src,dst src,dst or XOR.W src,dst
Operation Description
src .XOR. dst -> dst The source and destination operands are exclusive ORed. The result is placed into the destination. The source operand is not affected. N: Z: C: V: Set if result MSB is set, reset if not set Set if result is zero, reset otherwise Set if result is not zero, reset otherwise ( = .NOT. Zero) Set if both operands are negative
Status Bits
Mode Bits Example
OscOff, CPUOff, and GIE are not affected. The bits set in R6 toggle the bits in the RAM word TONI. XOR R6,TONI ; Toggle bits of word TONI on the bits set in R6
Example
The bits set in R6 toggle the bits in the RAM byte TONI. XOR.B R6,TONI ; Toggle bits in word TONI on bits ; set in low byte of R6,
Example
Reset to 0 those bits in low byte of R7 that are different from bits in RAM byte EDE. XOR.B INV.B EDE,R7 R7 ; Set different bit to "1s" ; Invert Lowbyte, Highbyte is 0h
Instruction Set Description
B-61
B-62
Appendix C
EPROM Programming
This appendix describes the MSP430 EPROM module. The EPROM module is erasable with ultraviolet light and electrically programmable. Devices with an EPROM module are offered in a windowed package for multiple programming and in an OTP package for one-time programmable devices.
Topic
C.1 C.2 C.3 C.4 C.5
Page
EPROM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-2 FAST Programming Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-4 Programming an EPROM Module Through a Serial Data Link Using the JTAG Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-5 Programming an EPROM Module With Controller's Software . . . . . C-6 Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-8
EPROM Programming
C-1
EPROM Operation
C.1 EPROM Operation
The CPU acquires data and instructions from the EPROM. When the programming voltage is applied to the TDI/VPP terminal, the CPU can also write to the EPROM module. The process of reading the EPROM is identical to the process of reading from other internal peripheral modules. Both programming and reading can occur on byte or word boundaries.
C.1.1 Erasure
The entire EPROM may be erased before programming begins. Erase the EPROM module by exposing the transparent window to ultraviolet light. Note: EPROM Exposed to Ambient Light (1) Since normal ambient light contains the correct wavelength for erasure, cover the transparent window with an opaque label when programming a device. Do not remove the table until it has to be erased. Any useful data in the EPROM module must be reprogrammed after exposure to ultraviolet light. The data in the EPROM module can be programmed serially through the integrated JTAG feature, or through software included as a part of the application software. The JTAG implementation features an internal mechanism for security purposes provided by the implemented fuse. Once the security fuse is activated, the device cannot be accessed through the JTAG functions. The JTAG is permanently operating in the by-pass mode. Refer to the appropriate data sheet for more information on the fuse implementation.
C.1.2 Programming Methods
The application must provide an external voltage supply to the TDI/VPP terminal to provide the necessary voltage and current for programming. The minimum programming time is noted in the electrical characteristics of the device data sheets. The EPROM control register EPCTL controls the EPROM programming, once the external voltage is supplied. The erase state is a 1. When EPROM bits are programmed, they are read as 0. The programming of the EPROM module can be done for single bytes, words, blocks of individual length, or the entire module. All bits that have a final level of 0 must be erased before the EPROM module is programmed. The programming can be done on single devices or even in-system. The supply voltage should be in the range required by the device data sheet but at least the maximum supply voltage of the target application. The levels on the JTAG terminals are defined in the device data sheet, and are usually CMOS levels.
C-2
EPROM Operation
Example C-1. MSP430 On-Chip Program Memory Format
Word Format Byte Format
xxxAh xxx8h xxx6h xxx4h
DEF0 9ABC 5678 1234
xxxBh xxxAh xxx9h xxx8h xxx7h xxx6h xxx5h xxx4h
DE F0 9A BC 56 78 12 34
C.1.3 EPROM Control Register EPCTL
Figure C-1.EPROM Control Register EPCTL
7 EPCTL 054h r-0 r-0 r-0 r-0 r-0 r-0
VPPS
0
EXE
rw-0
rw-0
For bit 0, the executable bit EXE initiates and ends the programming to the EPROM module. The external voltage must be supplied to the TDI/VPP or Test/VPP before the EXE bit is set. The timing conditions are noted in the data sheets. For bit 1, when the VPPS bit is set, the external programming voltage is connected to the EPROM module. The VPPS bit must be set before the EXE bit is set. It can be reset together with the EXE bit. The VPPS bit must not be cleared between programming operations. Note: Ensure that no VPP is applied to the programming voltage pin (TDI/VPP or Test/VPP) when the software in the device is executed or when the JTAG is not fully controlled. Otherwise, an undesired write operation may occur.
EPROM Programming
C-3
EPROM Operation
C.1.4 EPROM Protect
The EPROM access through the serial test and programming interface JTAG can be inhibited when the security fuse is activated. The security fuse is activated by serial instructions shifted into the JTAG. Activating the fuse is not reversible and any access to the internal system is disrupted. The by-pass function described in the standard IEEE 1149.1 is active.
C.2 FAST Programming Algorithm
The FAST programming cycle is normally used to program the data into the EPROM. A programmed logical 0 can be erased only by ultraviolet light. Fast programming uses two types of pulses: prime and final. The length of the prime pulse is typically 100ms (see the latest datasheet). After each prime pulse, the programmed data are verified. If the verification fails 25 times, the programming operation was false. If correct data are read, the final programming pulse is applied. The final programming pulse is 3 times the number of prime pulses applied.
Example C-2. Fast Programming Subroutine
Start Of Subroutine
VPP at TDI/VPP is Switched to EPROM: Set VPPS Bit Load Loop Into R_Count, Loop = 25
Write Data From BurnByte To EPROM Program One Prime Pulse (typ. 100 s)
No Verify Byte
Yes
R_Count = R_Count -1 Yes R_Count >0 No Invert Data in BurnByte Use inv. BurnByte for Error Indication
Final Programming Pulse Applied: 3-Times N Prime Pulse
End Of Subroutine: RET
C-4
EPROM Operation
C.3 Programming an EPROM Module Through a Serial Data Link Using the JTAG Feature
The hardware interconnection of the JTAG terminals is established through four separate terminals, plus the ground or VSS reference level. The JTAG terminals are TMS, TCK, TDI(/VPP), and TDO(/TDI).
Figure C-2.EPROM Programming With Serial Data Link
VPP (12.5 V/70 mA) TMS TCK TDI TMS
TCK TDI/VPP
TDO SN74HCT125 68 k
TDO/TDI MSP430Xxxx Xout/TCLK
TCLK
VCC/DVCC AVCC VSS/DVSS AVSS VCC/ DVCC 1k 27 SN74HCT125
Level Shifter Switches shown for programming situation
TDI in standard mode, VPP input during programming TDO in standard mode, data input TDI during programming See electrical characteristics in the latest data sheet
EPROM Programming
C-5
EPROM Operation
C.4 Programming an EPROM Module With Controller's Software
The procedure for programming an EPROM module is as follows: 1) Connect the required supply to the TDI/VPP terminal. 2) Run the proper software algorithm. The software algorithm that controls the EPROM programming cycle cannot run in the same EPROM module to which the data are being written. It is impossible to read instructions from the EPROM and write data to it at the same time. The software needs to run from another memory such as a ROM module, a RAM module, or another EPROM module.
Figure C-3.EPROM Programming With Controller's Software
TMS TCK VPP (11.5 V/70 mA) TDI/VPP 68 k VSS TDO/TDI 68 k VSS MSP430Xxxx
VSS/DVSS AVSS
Internally a pullup resistor is connected to TMS and TCK ROM devices of MSP430 have an internal pullup resistor at pin TDI/VPP. MSP430Pxxx or MSP430Exxx have no internal pullup resistor. They should be terminated according to the device data sheet. The TDO/TDI pin should be terminated according to the device data sheet.
C.4.1
Example
The software example writes one byte into the EPROM with the fast programming algorithm. The code is written position-independent, and will have been loaded to the RAM before it is used. The programming algorithm runs during the programming sequence in the RAM, thus avoiding conflict when the EPROM is written. The data (byte) that should be written is located in the RAM address BurnByte. The target address of the EPROM module is held in the register pointer defined with the set directive. The timing is adjusted to a cycle time of 1ms. When another cycle time/processor frequency is selected, the software should be adjusted according to the operating conditions.
C-6
EPROM Operation
Example C-3. Programming EPROM Module With Controller's Software
DE F0 yyyy 9A BC 56 78 12 34 R9 xxxx DE F0 9A BC 56 78 12 34
Example: Write data in yyyy into location xxxx BumByte = (yyyy) = (9Ah) R9 = xxxx
The target EPROM module cannot execute the programming code sequence while the data are being written into it. In the example, a subroutine moves the programming code sequence into another memory, for example, into the RAM.
Example C-4. Subroutine
Start Of Subroutine: Load_Burn_Routine
Source Start Address Of The Code Sequence>>R7 Destination Start Address Of The Code Sequence>> R10
Move One Word: (R7) >> (R10) Increment Source and Dest. Pointer in R7 and R10
No
End Of Source Code? Yes End Of Subroutine: RET
EPROM Programming
C-7
Code
C.5 Code
;------------------------------------------------------------- ; Definitions used in Subroutine : ; Move programming code sequence into RAM (load_burn_routine) ; Burn a byte into the EPROM area (Burn_EPROM) ;------------------------------------------------------------- EPCTL .set VPPS .set EXE .set BurnByte .set Burn_orig .set loops r_timer pointer .set .set .set 054h 2 1 0220h 0222h 25 r8 r9 ; ; ; ; ; ; ; ; ; ; EPROM Control Register Program Voltage bit Execution bit address of data to be written Start address of burn program in the RAM 1us = 1 cycle pointer to the EPROM address r9 is saved in the main routine before subroutine call is executed
r_count lp ov
.set .set .set
r10 3 2
; dec r_timer : 1 cycle : loop_t100 ; jnz : 2 cycles : loop_t100 ; mov #(100-ov)/lp,r_timer : 2 cycles
; Load EPROM programming sequence to another location e.g. RAM, Subroutine ;--- ;--- ;--- ;--- The address of Burn_EPROM (start of burn EPROM code) and the address of Burn_end (end of burn EPROM code) and the start address of the location of the destination code area (RAM_Burn_EPROM) are known at assembly/linking time
RAM_Burn_EPROM .set Burn_orig load_burn_routine push r9 push r10 mov #Burn_EPROM,R9 mov #RAM_Burn_EPROM,R10 load_burn1 mov @R9,0(R10) incd R10 incd R9 cmp #Burn_end,R9 jne load_burn1 pop r9 pop r10 ret
; load pointer source ; load pointer dest. ; ; ; ; move a word dest. pointer + 2 source pointer + 2 compare to end_of_table
; Program one byte into EPROM, Subroutine ;--- ; ;-- ;--- Burn subroutine: position independent code is needed since in this examples it is shifted to RAM >> only relative addressing, relative jump instructions, is used! The timing is correct due to 1us per cycle
Burn_EPROM dint mov.b push push mov Repeat_Burn mov.b
#VPPS,&EPCTL r_timer r_count #loops,r_count &BurnByte,0(pointer)
; ; ; ; ;
ensure correct burn timing VPPS on save registers programming subroutine 2 cycles = 2 us
; write to data to EPROM
C-8
Code
bis.b #EXE,&EPCTL
mov wait_100 dec jnz bic.b mov wait_10 dec jnz
#(100-ov)/lp,r_timer r_timer wait_100 #EXE,&EPCTL #4,r_timer r_timer wait_10
; 6 cycles = 6 us ; EXE on ; 4 cycles = 4 us ; total cycles VPPon to EXE ; 12 cycles = 12 us (min.) ;:programming pulse of 100us ;:starts, actual time 102us ;: ;: ;:EXE / prog. pulse off ;:wait min. 10 us ;:before verifying ;:programmed EPROM ;:location, actual 13+ us ; verify data = burned data ; data burned data > jump
cmp.b &BurnByte,0(pointer) jne Burn_EPROM_bad
; Continue here when data correctly burned into EPROM location mov.b &BurnByte,0(pointer) ; write to EPROM again bis.b #EXE,&EPCTL ; EXE on add #(0ffffh-loops+1),r_count ; Number of loops for ; successful programming final_puls mov #(300-ov)/lp,r_timer ;:programming pulse of wait_300 ;:3*100us*N starts dec r_timer ;: jnz wait_300 ;: inc r_count ;: jn final_puls ;: clr.b &EPCTL ;:EXE off / VPPS off jmp Burn_EPROM_end Burn_EPROM_bad dec r_count ; not ok : decrement ; loop counter jnz Repeat_Burn ; loop not ended : do ; another trial inv.b &BurnByte ; return the inverted data ; to flag ; failing the programming ; attempt the EPROM address ; is unchanged ; Burn_EPROM_end pop r_count pop r_timer eint ret Burn_end
EPROM Programming
C-9
C-10

▲Up To Search▲

Price & Availability of SLAU012

	To Download SLAU012 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .