 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| TSB12LV23/TSB41LV02 Mobile Reference Design Application Report June 1999 Mixed-Signal Products SLLA047 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof. Copyright (c) 1999, Texas Instruments Incorporated Contents 1 The Cable Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 The Physical Layer - TSB41LV02 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3 The PHY-Link Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4 The Link Layer - TSB12LV23 OHCI-Lynx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 5 The Link Layer - Serial EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5.1 Serial Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5.2 Parts List for Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 List of Figures Figure 1. Fuse Placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 2. PHY Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Figure 3. Link On . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 4. Clamping Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 5. TSB12LV23 Reset Illustration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 6. Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 7. Serial EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 8. TSB12LV23 Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 9. TSB12LV02 Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 10. TSB12LV23/TSB41LV02 Interface Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 List of Tables Table 1. Table 2. Table 3. Table 4. Registers and Bits Loadable Through Serial EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Serial EEPROM Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Link Part List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 PHY Part List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 TSB12LV23/TSB41LV02 Mobile Reference Design iii iv SLLA045 TSB12LV23/TSB41LV02 Mobile Reference Design John Mayberry ABSTRACT This application report describes the electrical connections between the Texas Instruments TSB12LV23 ( 400-Mbps OHCI-Lynx) and TSB41LV02 (400-Mbps PHY) for non-isolated mobile applications. The TSB12LV23 (OHCI-Lynx) is both an open host controller interface 1.0 (OHCI) and IEEE 1394.a compliant Link-layer device that transports data between the PCI bus and PHY interface. For more information refer to the TI Data Manual (SLLS328). The TSB41LV02 is a two-port 400 Mbps physical layer device and is IEEE 1394.a compliant. The TSB41LV02 is backward-compatible with the IEEE 1394-1995 standard and can operate at 100 Mbps, 200 Mbps, and 400 Mbps. For more information on the TSB41LV02, refer to the TI data sheet, IEEE 1394A Two-Port Cable Transceiver/Arbiter (literature number SLLS355). NOTE: This reference schematic does not represent an actual test board constructed or tested by Texas Instruments. 1 The Cable Interface Figure 8 of the OHCI-LYNX/TSB41LV02 schematic shows the electrical connections for the cable interface, which includes one 1394 port connected to the PHY. The second 1394 port is not implemented to show how to correctly terminate an unused port. If two 1394 ports are implemented, a 750-mA current-limited fuse must be connected between the 12-V supply and bus power as shown in Figure 1. D1 12 V Bus Power F1 750 mA Port 1 (1394 Connector [1]) Port 0 (1394 Connector [1]) Figure 1. Fuse Placement The cable power from each cable (terminal 1, PWR, on the 6 terminal 1394 connector) is connected to the other ports and is available as the bus power. The PHY does not operate off of bus power on the schematic. If bus power is required, then a voltage regulator is needed to regulate the bus power to 3.3 V for the PHY and is illustrated in Figure 2. 1 The Cable Interface U4 Bus Power C39 3.3 F C40 0.01 F 10 5 4 6 VIN VOUT 12 3 L1 680 H C41 100 F C42 100 F C43 0.01 F PHY Power PHY 3.3 V Power ON SIG GND ADJUST PWR GND LM2574HVM-3.3 V D1 MBRS1100T3 Figure 2. PHY Voltage Regulator The cable shield from each cable (terminals 7 and 8 (SHLD) on the 6 terminal 1394 connector) is connected to chassis ground through an R-C network. This R-C network is designed to prevent current from flowing on the cable shield in case of potential differences between it and chassis ground. We suggest a combination of a 1-M resistor, two 0.001-F capacitors, and two 0.01-F capacitors be connected to all the shield GND terminals (7 and 8) on the 1394 connectors. In addition, individual R-C networks could be set up for each connector, which would help prevent the cable shield noise on one port from coupling onto the other ports. The cable ground (terminal 2 (GND) on the 6-terminal 1394 connector) is tied directly to PHY ground. According to the 1394 standard, all PHYs in a network must be at the same ground potential for common mode signaling. The drivers on each port (TPA and TPB) are designed to work with an external 112- termination resistor network. This is to match the 110- cable impedance. One network is provided at each end of the twisted pair cable. The midpoint of the TPA resistor network is directly connected to TPBIAS; and the midpoint of the TPB resistor network is coupled to ground through a paralleled RC network. These termination resistor networks should be placed as close to the PHY as possible. The TPBIAS lines indicate the presence of an active connection to other nodes on the bus. A 1-F capacitor external filter is used to stabilize the TPBIAS lines. When a 1394 port is not brought out to a connector, it must be terminated correctly. To terminate a non-implemented port, the TPB+ and TPB- terminals must be tied together and connected to ground. The TPBIAS should be tied to ground through a 1-F capacitor filter. The TPA+ and TPA- lines can be left unconnected. Port 1 in the schematic is not brought out to a connector to illustrate a properly terminated port. 2 SLLA047 The Physical Layer - TSB41LV02 2 The Physical Layer - TSB41LV02 Figure 9 of the OHCI-LYNX/TSB41LV02 schematic shows the electrical connections for the physical layer (TSB41LV02). All of the power terminals on the TSB41LV02 PHY should be coupled to the associated power terminals and ground through a series of high-frequency decoupling capacitors. The rules for the decoupling capacitors are: * Place one 0.001-F capacitor as closely as possible to each power terminal on the PHY. * Place one 0.1-F capacitor as closely as possible to each power terminal group (two or more adjacent power terminals) on the PHY. * Place one 0.1-F capacitor as closely as possible to each single power terminal (not adjacent to another) on the PHY. A power terminal group is two or more adjacent power terminals connected to the same power supply. For example, terminals 30 and 31 are both connected to the AVDD supply. These two terminals constitute a power terminal group; and a 0.1-F capacitor should be placed as closely as possible to these terminals on the PHY. Terminal 56 (PLLVDD) is a single power terminal, since it is not adjacent to any other power terminal; and a 0.1-F capacitor should be placed as closely as possible to this terminal as well. Detailed information on capacitor placement is available in the TI datasheet SLLS-TBD). The TSB41LV02 has 5-V tolerant inputs. Whenever connecting to a 5-V device, the VCC5V terminal should be tied to the 5-V supply. If the TSB41LV02 is only connected to 3.3-V devices, the VCC5V terminal should be tied to the 3.3-V supply. The 3.3-V implementation is shown in the schematic. The ISO terminal is used to control the output differentiation on the PHY/Link interface for the Annex J method of isolation. If the IEEE 1394-1995 Annex J method of isolation is used, the ISO terminal should be tied low. If the TI bus-holder method of isolation or no isolation is used, then this terminal should be tied high. No isolation is implemented in the schematic, so ISO is tied to PHY_VCC through a 10-k resistor. Normally, the CPS terminal is connected to the cable power through a 400-k resistor, which is used to detect whether or not cable power is present. A common resistor value of 390 k may be used; however, for mobile designs where bus power is not needed, the CPS terminal should be tied directly to PHY ground through a 1-k pull-down resistor, which is used to indicate that cable power is not available. In additions, the power class should be set to 000b. NOTE: The only instance where the CPS terminal may not be connected to cable power is in the case of a 4-terminal connector or 6-terminal connector with power class 000b. Here the CPS may be tied to PHY ground through a 1-k resistor indicating cable power is not available. TSB12LV23/TSB41LV02 Mobile Reference Design 3 The Physical Layer - TSB41LV02 The FILTER0 and FILTER1 terminals are used to provide a filter capacitor for the internal PLL. A 0.1 F (10% or better) capacitor is the only external requirement needed to complete this filter. The SE and SM terminals are test inputs used in the manufacturing of the TSB41LV02. For normal use, these terminals should be tied to ground separately through 1-k pull-down resistors. The R0 and R1 terminals set the internal operating currents and the cable-driver output current. A 6.3-k 0.5% resistance is required to meet the voltage limits for the IEEE 1394-1995 standard output. To achieve this, a 6.34-k 0.5% and 1-M 1% resistor are placed in parallel. The X0 and XI terminals are the crystal oscillator inputs and connect to a 24.576 MHz parallel resonant fundamental mode crystal. There is a strict tolerance of 100 ppm on the 24.576 MHz crystal; however, it is suggested that this parameter be kept well below 100 ppm. This tolerance must be met to comply with the overall requirement of 100 ppm per the IEEE 1394-1995 standard. Loading requirements for every crystal depend on the board technology and distance from the PHY. The crystal manufacturer should be able to provide the loading requirements. NOTE: A crystal load capacitance of 15 pF or less is recommended. The external crystal terminating capacitors can be calculated as follows: C Termination + (CL * 4) 2 The TESTM terminal is a test control input used during the manufacturing of the TSB41LV02 PHY. It should be tied directly to VCC. A node can be a power provider, power consumer, or neither. The power class terminals (PC0-PC2) are used to program the power class value into the PWR field of the transmitted self-id packet. This ensures that every node on the bus understands the power requirements of the node. These terminals are programmed according to the Power Class Descriptions in the IEEE 1394.a Standard. In Figure 9 of the schematic the PHY is programmed as power class of 000b or 0. This indicates that the node is not capable of repeating power and does not use bus power. The power class terminals are hard-wired to their values on the schematic. Reset is best accomplished by connecting the RESET terminal to ground through a 0.1-F capacitor. The PD terminal is a legacy terminal that is no longer needed to power down the PHY which is now handled via the 1394.a suspend/resume feature. The PD terminal should be tied to ground through a 1-k pull-down resistor. The CNA terminal is not recommended for this design. This terminal should be left unconnected. 4 SLLA047 The PHY-Link Interface 3 The PHY-Link Interface The PHY-Link interface electrical connection is shown on Figure 10 of the OHCI-LYNX/TSB41LV02 interface schematic. The PHY-Link interface follows the IEEE 1394-1995 and 1394.a standards. No isolation is implemented in this schematic. The PHY and Link operate with common power and ground planes. The schematic shows no adjustment for EMI considerations. To help minimize EMI, we suggest including a 0- resistor on the SCLK signal as close as possible to the PHY. If EMI issues are a concern, the value of this resistor can be adjusted to reduce emissions. This will also reduce reflections that may occur when the distance between the PHY and Link is large (greater than 4 inches.) The SCLK is a 49.152-MHz clock provided by the PHY to the Link. SCLK is essential for transactions on the PHY-Link interface as well as transactions within the Link. The LREQ, or Link Request, signal is an input to the PHY from the Link. The Link uses this to initiate a service request to the PHY. CTL0 and CTL1 are bidirectional signals used to control communication between the PHY and the Link. These terminals should be directly connected between the PHY and Link. Both the TSB12LV23 (Link layer) and the TSB41LV02 (Phy) are 400-Mbps devices, which use terminals D0-D7 to transport data bidirectionally, and should be connected directly to each other respectively (i.e., D0 D0 . . . D7 D7). The Link's PHY_LPS (Link Power Status) terminal is asserted to indicate that the Link is powered on. The LPS input on the PHY can be tied to either the Link layer's PHY_LPS terminal or the Link layer's VCC. In addition, the line connecting the Link's PHY_LPS terminal with the PHY's LPS terminal should be pulled down to ground through a 4.7-k resistor. As is shown in Figure 3, the BMC/PHY_LINKON terminal on the TSB12LV23 is connected the TSB41LV02 C/LKON terminal through a 1-k series resistor and 10-k pulldown resistor on the TSB41LV02 side. The PHY's LKON signal is used to activate (wake) the Link when the Link is not active. This signal is driven low as long as the Link is not active. R19 PHY Side C/LKON 1 k R22 10 k LINK Side BMC/PHY_LINKON Figure 3. Link On All of the above PHY-Link interface signals could also be connected to a test header that would provide test points for new prototype designs, as is shown on Figure 10 of the schematic. TSB12LV23/TSB41LV02 Mobile Reference Design 5 The Link Layer - TSB12LV23 OHCI-Lynx 4 The Link Layer - TSB12LV23 OHCI-Lynx The TSB12LV23 is a 400 Mbps Link-layer specifically designed with power management and CARDBUS features. All of the power 3.3-V VCC terminals on the TSB12LV23 should be coupled together and ground through a series of high-frequency decoupling capacitors as is shown on Figure 8 of the schematic. * Place one 0.01-F and one 0.1-F capacitor as closely as possible to each power terminal on the Link. This will help minimize switching noise. * Also use a single 47-F capacitor to reduce dc ripple. The VCCP power terminals provide a voltage clamping rail for 5-V tolerant inputs. The VCCP voltage is determine by the PCI bus voltage. Figure 4 illustrates the voltage clamping rail. 3.3 V VCCP D1 3.3 V D2 PAD Figure 4. Clamping Voltage When implementing the TSB12LV23 in a mobile design, the VCCP terminals should be connected the Link's 3.3-V supply. The ISOLATED terminal is used to enable the bus holders for isolated designs. However, for most designs this is not required. * To disable the bus-holders connect the ISOLATED terminal to 3.3 V through a 4.7-k pullup resistor. * To enable the bus-holders connect the ISOLATED terminal to GND through a 220- pulldown resistor. The CARDBUS/CYCLEOUT terminal is sampled when G_RST is asserted, and it selects between the PCI buffers and CardBus buffers. After reset, this terminal may also function as CYCLEOUT which provides an 8-kHz cycle timer synchronization signal. * To use the PCI bus buffers, this terminal should be left unconnected, and an internal pullup resistor will enable the PCI buffers. * To enable the CardBus buffers this terminal should be pulled down with 220- resistor. It is important that a weak pulldown resistor be used if the design is going to use the CYCLEOUT feature. 6 SLLA047 The Link Layer - TSB12LV23 OHCI-Lynx The CYCLEIN terminal can be used to receive an optional external 8-kHz clock used as a cycle timer, which provides synchronization with other system devices. If not implemented, a 4.7-k pullup resistor should be used to tie this terminal to 3.3 V. The TSB12LV23's G_RST terminal allows for retaining context from a D3 to D0 transition when the PCI interface may transition from B3 to B0 and issue a PCI reset. The TSB12LV23 resets are illustrated in Figure 5. RST 1 2 3 RESET Non-PME Context RESET G_RST PME Context Figure 5. TSB12LV23 Reset Illustration If the design supports D3 Wake, then the G_RST terminal provides the hardware reset at power on, while the RST terminal should be connected to the PCI Bus RST, which will provides resets that retain the PME context. For designs that will not support D3 Wake, the RST terminal can either be pulled up to 3.3 V through a 4.7-k resistor or tied together with the G_RST terminal. An example implementation is shown in Figure 6. RST (76) R2 0 R1 Power On Reset 0 NOTE: For normal operation populate R2 and do not populate R1 For Mobile or D3_Wake operation populate R1 and do not populate R2 RST G_RST (10) Figure 6. Reset The CLKRUN terminal is used to turn the clock on and off. This is useful in mobile design where conserving power is important. When implementing CLKRUN, this terminal is connected to external circuitry that provides a common CLKRUN control signal. If the clock is never turned off, then this terminal should be left unconnected and an internal pulldown resistor will keep the clock active. The GPIO2 and GPIO3 are general-purpose I/O terminals that should each be pulled down to GND through a 220- resistors. For more information on the TSB12LV23, consult the TI data manual, TSB12LV23 (OHCI-LYNX) IEEE 1394-1995 Link-Layer Controller (literature number SLLS328). TSB12LV23/TSB41LV02 Mobile Reference Design 7 The Link Layer - Serial EEPROM 5 The Link Layer - Serial EEPROM The Serial EEPROM provides a convenient mechanism to load system specific data and is detected at reset via SDA and SCL terminals. The following are the types of data stored in the EEPROM: * * PCI: Max latency, min grant, subsystem VID, subsystem ID, Link enhancements, miscellaneous control, and CIS offset OHCI: GUID, HCControl.programPhyEnable The serial EEPROM is required for adapter cards, but it is optional for implementations where the BIOS could load GUID and other system specific registers. NOTE: SDA and SCL should each be pulled up to 3.3 V through 2.7-k resistors, and then connected to the EPROM's SDA and SCL terminals respectively (as is illustrated in Figure 7). If no serial EEPROM is used, then both the SDA and SCL terminals should be connected to ground through 220- pulldown resistors. R7 SDA (5) 2.7 k R8 SCL (4) 2.7 k R9 4.7 k 5 JP1 3.3 V 6 7 8 U4 SDA SCL WC VCC EEPROM GND A2 A1 A0 4 3 2 1 LINK Power (3.3 V) Figure 7. Serial EEPROM If the EEPROM has a write enable terminal, it should be connected to 3.3 V with a pullup resistor. In addition, a jumper to GND should be connected in series with the pull up, as is illustrated in Figure 7. This allows the EEPROM to be write-enabled and write-disabled. 5.1 Serial Bus Interface The TSB12LV23 provides a serial bus interface to initialize the 1394 global unique ID register and a few PCI configuration registers through a serial EEPROM. The TSB12LV23 communicates with the serial EEPROM via the 2-wire serial interface. After power up the serial interface initializes the locations listed in Table 1. While the TSB12LV23 is accessing the serial ROM, all incoming PCI slave accesses are terminated with retry status. Table 2 shows the serial ROM memory map required for initializing the TSB12LV23 registers. 8 SLLA047 The Link Layer - Serial EEPROM Table 1. Registers and Bits Loadable Through Serial EEPROM OFFSET OHCI register (24h) OHCI register(28h) OHCI register (50h) PCI register (2Ch) PCI register (2Dh) PCI register (3Eh) PCI register (F4h) PCI register (F0h) PCI register (40h) REGISTER 1394 GlobalUniqueIDHi 1394 GlobalUniqueIDLo Host control register PCI subsytem ID PCI vendor ID PCI maximum latency, PCI minimum grant Link enhancements control register PCI miscellaneous register PCI OHCI register BITS LOADED FROM EEPROM 31-0 31-0 23 15-0 15-0 15-0 13, 12, 9, 8, 7, 2, 1 15, 13, 10, 5-0 0 Table 2. Serial EEPROM Map BYTE ADDRESS 00 01 02 03 04 05 [7] Link_enhancementControl.enab_unfair [6] HCControl. ProgramPhy Enable [5] RSVD PCI maximum latency (0h) PCI vendor ID PCI vendor ID (msbyte) PCI subsystem ID (lsbyte) PCI subsystem ID [4] RSVD [3] RSVD [2] Link_enhancementControl.enab_ insert_idle [1] Link_enhancementControl.enab_accel [0] RSVD BYTE DESCRIPTION PCI_minimum grant (0h) 06 07 08 09 0A 0B 0C 0D 0E 0F 10 [15] RSVD [7] RSVD [15] PME D3 Cold [7] RSVD [14] RSVD [6] RSVD [14] RSVD [6] RSVD [13-12] AT threshold [5] Select D3 STAT [13] PME Support D2 [5] RSVD Mini ROM address 1394 GlobalUniqueIDHi (lsbyte 0) 1394 GlobalUniqueIDHi (byte 1) 1394 GlobalUniqueIDHi (byte 2) 1394 GlobalUniqueIDHi (msbyte 3) 1394 GlobalUniqueIDLo (lsbyte 0) 1394 GlobalUniqueIDLo (byte 1) 1394 GlobalUniqueIDLo (byte 2) 1394 GlobalUniqueIDLo (msbyte 3) Checksum [11] RSVD [3] GP2IIC [11] RSVD [3] RSVD [10] RSVD [2] Disable SCLK gate [10] D2 support [2] RSVD [9] Enable audio timestamp [1] Disable PCI gate [9] RSVD [1] RSVD [8] Enable DV CIP timestamp [0] Keep PCI [8] RSVD [0] Global swap 11 [4] Disable Target Abort [12] RSVD [4] RSVD 12 13 14 15-1E 1F CIS offset address RSVD RSVD TSB12LV23/TSB41LV02 Mobile Reference Design 9 The Link Layer - Serial EEPROM PCI BUS 18 19 21 22 23 25 26 27 31 32 33 34 36 37 38 40 54 56 57 58 59 61 62 64 66 67 68 69 71 72 73 74 28 41 53 65 14 15 29 43 44 45 47 48 49 8 17 51 52 12 TSB12LV23 U1 VCCP VCCP VCCP VCCP VCCP 3.3 VCC 3.3 VCC 3.3 VCC 3.3 VCC 3.3 VCC 3.3 VCC 3.3 VCC 3.3 VCC 3.3 VCC 3.3 VCC CYCLEIN 87 6 63 16 39 96 91 80 70 55 46 35 20 13 9 78 79 77 76 10 5 4 99 98 97 95 93 92 90 89 88 86 85 84 82 81 3 2 7 1 11 24 30 50 42 60 75 83 94 100 R9 220 PHY_LSP BMC/PHY_LINKON PHY_LREQ PHY_SCLK PHY_CTL0 PHY_CTL1 SDA SCL R2 4.7 k [1] R3 0 RST R4 0 Power On Reset R5 2.7 k R6 2.7 k R7 4.7 k U2 5 6 7 8 SDA SCL WC VCC 24C02 GND A2 A1 A0 4 3 2 1 C1 47 F PCI_AD31 PCI_AD30 PCI_AD29 PCI_AD28 PCI_AD27 PCI_AD26 PCI_AD25 PCI_AD24 PCI_AD23 PCI_AD22 PCI_AD21 PCI_AD20 PCI_AD19 PCI_AD18 PCI_AD17 PCI_AD16 PCI_AD15 PCI_AD14 PCI_AD13 PCI_AD12 PCI_AD11 PCI_AD10 PCI_AD9 PCI_AD8 PCI_AD7 PCI_AD6 PCI_AD5 PCI_AD4 PCI_AD3 PCI_AD2 PCI_AD1 PCI_AD0 PCI_C/BE3 PCI_C/BE2 PCI_C/BE1 PCI_C/BE0 3.3 V PHY-LINK Power 3.3 V C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 0.01 F 0.01 F 0.01 F 0.01 F 0.01 F 0.01 F 0.01 F 0.01 F 0.01 F 0.01 F C12 C13 0.1 F 0.1 F C14 C15 0.1 F 0.1 F C16 C17 0.1 F 0.1 F C18 C19 0.1 F 0.1 F C20 C21 0.1 F 0.1 F R1 4.7 k LINK Power (3.3 V) ISOLATED CARDBUS/CYCLEOUT RST G_RST SDA SCL PHY_LPS BMC/PHY_LINKON PHY_LREQ PHY_SCLK PHY_CTL0 PHY_CTL1 PHY_DATA0 PHY_DATA1 PHY_DATA2 PHY_DATA3 PHY_DATA4 PHY_DATA5 PHY_DATA6 PHY_DATA7 GPIO3 GPIO2 CLKRUN GND GND GND GND GND GND GND GND GND GND GND LINK Power (3.3 V) LINK Power (3.3 V) JP1 3.3 V PCI_GNT PCI_REQ PCI_IDSEL PCI_FRAME PCI_IRDY PCI_TRDY PCI_DEVSEL PCI_STOP PCI_PERR PCI_INTA/CINT PCI_PME/CSTSCHG PCI_SERR PCI_PAR PCI_CLK PHY_D0-7 CLK Run Circuitry R8 220 [1] NO D3_WAKE Requirements: Populate R3, Do Not Fill R4 D3_WAKE Required:,Populate R4, Do Not Fill R3 Figure 8. TSB12LV23 Schematic 10 SLLA047 C22 C23 0.001 F 0.001 F C24 0.001 F C25 0.001 F C26 C27 0.001 F 0.001 F C28 0.001 F C29 0.001 F PHY-LINK Power 3.3 V 16 VDD-5 V PLLVDD DVDD1 DVDD2 DVDD3 DVDD4 TESTM R12 ISO CPS R13 1 k 24 10 k 23 40 R0 R1 41 60 X0 59 X1 27 R10 6.34 k 0.5% R11 1M 1% Y1 C39 56 25 26 61 62 AVDD1 AVDD2 AVDD3 AVDD4 AVDD5 30 31 42 51 52 U3 C30 0.1 F C31 0.1 F C32 0.1 F C33 0.1 F C34 0.1 F C35 0.1 F C36 0.1 F C37 0.1 F C38 0.1 F 22 pF 24.576 MHz 100 ppm C40 22 pF PHY_LPS 0 R15 BMC/PHY_LINKON R16 4.7 k PHY_D0 PHY_D1 PHY_D2 PHY_D3 PHY_D4 PHY_D5 PHY_D6 PHY_D7 1 k R17 10 k PHY_LREQ PHY_SYSCLK PHY_CTL0 PHY_CTL1 C41 1 F 10% R21 56.2 R22 56.2 38 37 36 35 34 R24 C45 220 pF C42 5.11 k 0.1 F 54 55 28 29 57 58 R18 1 k R19 1 k 3 17 18 63 64 47 46 45 44 43 TBPIAS1 TPA1+ TPA1- TPB2+ TPB1- J1 C44 1F Figure 9. TSB12LV02 Schematic TBPIAS0 TPA0+ TPA0- TPB0+ TPB0- FILTER2 FILTER1 SE SM PLLGND1 PLLGND2 SHLD PWR TPA+ TPA- TPB+ TPB- GND SHLD R23 R25 56.2 56.2 1394 Con 7 1 6 5 4 3 2 8 19 C/LKON 15 LSP 1 LREQ 2 R14 SYSCLK 4 CTL0 5 CTL1 6 D0 7 D1 8 D2 9 D3 10 D4 11 D5 12 D6 13 D7 20 PC0 21 PC1 22 PC2 53 RESET 18 PD C46 0.001 F 0.01 F 0.001 F 0.01 F C47 C48 C49 C43 0.1 F CNA DGND1 DGND2 DGND3 DGND4 AGND1 AGND2 AGND3 AGND4 AGND5 AGND6 TSB41LV02 32 33 39 48 49 50 R20 1 k TSB12LV23/TSB41LV02 Mobile Reference Design R26 1 M The Link Layer - Serial EEPROM 11 The Link Layer - Serial EEPROM PHY_D0-7 PHY_D0 PHY_D1 PHY_D2 PHY_D3 PHY_D4 PHY_D5 PHY_D6 PHY_D7 PHY_CTL0 PHY_CTL1 PHY_LREQ PHY_SCLK BMC/PHY_LINKON PHY_LPS PHY_CTL0 PHY_CTL1 PHY_LREQ PHY_SCLK BMC/PHY_LINKON PHY_LPS TH1 SYSCLK D7 D6 D5 D4 D3 D2 D1 D0 1 3 5 7 9 11 13 15 17 19 NC CLK1 D14 D12 D10 D8 D6 D4 D2 D0 Test Header Recommended For Prototyping CLK2 D15 D13 D11 D09 D07 D05 D03 D01 GND 2 4 6 8 10 12 14 16 18 20 SEEPROM_CLK SEEPROM_DATA LREQ CTL1 CTL0 BMC/LKON LPS SCL SDA Figure 10. TSB12LV23/TSB41LV02 Interface Schematic 5.2 Parts List for Schematics The following parts are represented on the schematic pages. Other parts may be used as long as their function meets the IEEE 1394-1995 and IEEE 1394.a requirements. Table 3. Link Part List DESCRIPTION SUPPLIER KEMET KEMET KEMET KOA KOA KOA KOA TI SGS Thomson PART NUMBER C0805C103K5RAC C0805C104K5RAC T491A476K050AS RM73B2AT000J RM73B2AT221J RM73B2AT272J RM73B2AT472J TSB12LV23 M24C02R PACKAGE 0805 0805 2816 0805 0805 0805 0805 100 TERMINAL TQFP S08 QUANTITY 10 10 1 2 2 2 3 1 1 REFERENCE DESIGNATOR C2-C11 C12-C21 C1 R3-R4 R8-R9 R5-R6 R1-R2,R7 U1 U2 Capacitors 0.01 F 10% 0.1 F 10% 47 F 50 V Resistors 0 220 2.7 k 4.7 k Chips 1394 400-Mbps Link 3.3-V EEPROM 12 SLLA047 The Link Layer - Serial EEPROM Table 4. PHY Part List DESCRIPTION Capacitors 0.001 F 0.01 F 10% 0.1 F 10% 1 F 50 V 22 pF 220 pF Headers Resistors 1394 R/A Flat Header 0 56.2 1% 1 k 5% 5.11 k 6.34 k 0.5% 10 k 1 M 1% Chips Crystal 1394 3-Port 400-Mbps PHY XTAL, 24.576 MHz SUPPLIER KEMET KEMET KEMET KEMET KEMET KEMET MOLEX KOA KOA KOA KOA KOA KOA KOA TI FOX PART NUMBER C0805C102K5RAC C0805C103K5RAC C0805C104K5RAC T491A105M016AS C0805C220K5RAC C0805C221K5RAC 53462-0611 RM73B2AT000J RK73H2AT56R2F RM73B2AT102J RM73H2AT5111F RM73H2AT6341D RM73B2AT103J RK73H2AT105F TSB41LV02 FE 24.576 20PF PACKAGE 0805 0805 0805 0805 0805 0805 Socket_6 0805 0805 0805 0805 0805 0805 0805 80 TERMINAL TQFP XTAL_ FE QUANTITY 10 2 10 2 2 1 1 1 4 6 1 1 2 2 1 1 REFERENCE DESIGNATOR C22-C29, C46, C48 C47, C49 C30-C38, C42-C43 C41, C44 C39-C40 C45 J1 R14 R21-23, R25 R13, R15, R18-R20 R24 R10 R12, R17 R11, R26 U3 Y1 TSB12LV23/TSB41LV02 Mobile Reference Design 13 14 SLLA047 |
Price & Availability of SLLA047
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |