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| SN65LBC173, SN75LBC173 QUADRUPLE LOW-POWER DIFFERENTIAL LINE RECEIVERS SLLS170D - OCTOBER 1993 - REVISED JUNE 2000 D D D D D D D Meets or Exceeds the Requirements of ANSI Standards EIA/TIA-422-B, EIA/TIA-423-B, RS-485, and ITU Recommendations V.10 and V.11. Designed to Operate With Pulse Durations as Short as 20 ns Designed for Multipoint Bus Transmission on Long Bus Lines in Noisy Environments Input Sensitivity . . . 200 mV Low-Power Consumption . . . 20 mA Max Open-Circuit Fail-Safe Design Pin Compatible With SN75173 and AM26LS32 D OR N PACKAGE (TOP VIEW) 1B 1A 1Y G 2Y 2A 2B GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC 4B 4A 4Y G 3Y 3A 3B description The SN65LBC173 and SN75LBC173 are monolithic quadruple differential line receivers with 3-state outputs. Both are designed to meet the requirements of the ANSI standards EIA/TIA-422-B, EIA/TIA-423-B, RS-485, and ITU Recommendations V.10 and V.11. The devices are optimized for balanced multipoint bus transmission at data rates up to and exceeding 10 million bits per second. The four receivers share two ORed enable inputs, one active when high, the other active when low. Each receiver features high input impedance, input hysteresis for increased noise immunity, and input sensitivity of 200 mV over a common-mode input voltage range of 12 V to -7 V. Fail-safe design ensures that if the inputs are open circuited, the output is always high. Both devices are designed using the Texas Instruments proprietary LinBiCMOSTM technology that provides low power consumption, high switching speeds, and robustness. These devices offer optimum performance when used with the SN75LBC172 or SN75LBC174 quadruple line drivers. The SN65LBC173 and SN75LBC173 are available in the 16-pin DIP (N) and SOIC (D) packages. The SN65LBC173 is characterized over the industrial temperature range of - 40C to 85C. The SN75LBC173 is characterized for operation over the commercial temperature range of 0C to 70C. FUNCTION TABLE (each receiver) DIFFERENTIAL INPUTS A-B VID 0.2 V - 0.2 V < VID < 0.2 V VID - 0.2 V X Open Circuit ENABLES G H X H X H X L H X G X L X L X L H X L OUTPUT Y H H ? ? L L Z H H H = high level, L = low level, X = irrelevant, Z = high impedance (off), ? = indeterminate Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. LinBiCMOS is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2000, Texas Instruments Incorporated POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 SN65LBC173, SN75LBC173 QUADRUPLE LOW-POWER DIFFERENTIAL LINE RECEIVERS SLLS170D - OCTOBER 1993 - REVISED JUNE 2000 logic symbol G G 4 12 1 logic diagram (positive logic) G G 4 12 1A 1B 2A 2B 3A 3B 4A 4B 2 1 6 7 10 9 14 15 3 1Y 1A 1B 2 1 3 1Y 5 2Y 2A 2B 6 7 5 11 2Y 3Y 13 4Y 3A 3B 10 9 11 3Y This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. 4A 4B 14 15 13 4Y schematics of inputs and outputs EQUIVALENT OF A AND B INPUTS VCC 100 k A Only Input 18 k 100 k B Only 12 k 1 k 3 k Receiver Y Output Input TYPICAL OF ALL OUTPUTS VCC TYPICAL OF G AND G INPUTS VCC 2 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SN65LBC173, SN75LBC173 QUADRUPLE LOW-POWER DIFFERENTIAL LINE RECEIVERS SLLS170D - OCTOBER 1993 - REVISED JUNE 2000 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to 7 V Input voltage, VI (A or B inputs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 V Differential input voltage, VID (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 V Voltage range at Y, G, G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to VCC + 0.5 V Continuous total dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Operating free-air temperature range, TA: SN65LBC173 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 40C to 85C SN75LBC173 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 70C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65C to 150C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values are with respect to GND. 2. Differential input voltage is measured at the noninverting input with respect to the corresponding inverting input. DISSIPATION RATING TABLE PACKAGE D N TA 25C POWER RATING 1100 mW 1150 mW DERATING FACTOR ABOVE TA = 25C 8.7 mW/C 9.2 mW/C TA = 70C POWER RATING 708 mW 736 mW TA = 85C POWER RATING 578 mW 598 mW recommended operating conditions MIN Supply voltage, VCC Common-mode input voltage, VIC Differential input voltage, VID High-level input voltage, VIH Low-level input voltage, VIL High-level output current, IOH Low-level output current, IOL Operating free-air temperature, TA free air temperature SN65LBC173 SN75LBC173 - 40 0 G inputs 2 0.8 -8 16 85 70 4.75 -7 NOM 5 MAX 5.25 12 6 UNIT V V V V V mA mA C POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 3 SN65LBC173, SN75LBC173 QUADRUPLE LOW-POWER DIFFERENTIAL LINE RECEIVERS SLLS170D - OCTOBER 1993 - REVISED JUNE 2000 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER VIT + VIT - Vhys VIK VOH VOL IOZ Positive-going input threshold voltage Negative-going input threshold voltage Hysteresis voltage ( VIT + - VIT - ) Enable input clamp voltage High-level output voltage Low-level output voltage High-impedance-state output current II = - 18 mA VID = 200 mV, VID = - 200 mV, VO = 0 V to VCC VIH = 12 V, VIH = 12 V, VIH = - 7 V, VIH = - 7 V, VIH = 5 V VIL = 0 V VO = 0 Outputs enabled, Outputs disabled - 80 IO = 0, VID = 5 V 11 0.9 IOH = - 8 mA IOL = 8 mA VCC = 5 V, VCC = 0 V, VCC = 5 V, VCC = 0 V, Other inputs at 0 V Other inputs at 0 V Other inputs at 0 V Other inputs at 0 V 3.5 IO = - 8 mA IO = 8 mA TEST CONDITIONS MIN - 0.2 45 - 0.9 4.5 0.3 0.7 0.8 - 0.5 - 0.4 0.5 20 1 1 - 0.8 - 0.8 20 - 20 - 120 20 1.4 - 1.5 TYP MAX 0.2 UNIT V V mV V V V A mA mA mA mA A A mA mA II Bus input current A or B inputs IIH IIL IOS ICC High-level input current Low-level input current Short-circuit output current Supply current All typical values are at VCC = 5 V and TA = 25C. switching characteristics, VCC = 5 V, CL = 15 pF, TA = 25C PARAMETER tPHL tPLH tPZH tPZL tPHZ tPLZ tsk(p) tt Propagation delay time, high- to low-level output Propagation delay time, low- to high-level output Output enable time to high level Output enable time to low level Output disable time from high level Output disable time from low level Pulse skew (|tPHL - tPLH|) Transition time TEST CONDITIONS VID = - 1 5 V to 1 5 V, 1.5 1.5 V See Figure 2 See Figure 3 See Figure 2 See Figure 3 See Figure 2 See Figure 1 See Figure 1 MIN 11 11 TYP 22 22 17 18 35 25 0.5 5 MAX 30 30 30 30 45 40 6 10 UNIT ns ns ns ns ns ns ns ns 4 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SN65LBC173, SN75LBC173 QUADRUPLE LOW-POWER DIFFERENTIAL LINE RECEIVERS SLLS170D - OCTOBER 1993 - REVISED JUNE 2000 PARAMETER MEASUREMENT INFORMATION Generator (see Note A) 1.5 V 50 Output CL = 15 pF (see Note B) Input tPLH 90% Output 10% tt TEST CIRCUIT VOLTAGE WAVEFORMS 1.3 V 1.3 V VOL tt 0V 0V - 1.5 V tPHL VOH 2V Figure 1. tpd and tt Test Circuit and Voltage Waveforms VCC Output 1.5 V CL = 15 pF (see Note B) 5 k See Note C Output S1 Open S1 Input tPZH 1.3 V 1.3 V 0V tPHZ 0.5 V VOH S1 Closed 1.4 V 2 k 3V 1.3 V 0V VOLTAGE WAVEFORMS Generator (see Note A) 2V 50 (see Note D) TEST CIRCUIT NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR = 1 MHz, duty cycle = 50%, tr 6 ns, tf 6 ns, ZO = 50 . B. CL includes probe and jig capacitance. C. All diodes are 1N916 or equivalent. D. To test the active-low enable G, ground G and apply an inverted input waveform to G. Figure 2. tPHZ and tPZH Test Circuit and Voltage Waveforms POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 5 SN65LBC173, SN75LBC173 QUADRUPLE LOW-POWER DIFFERENTIAL LINE RECEIVERS SLLS170D - OCTOBER 1993 - REVISED JUNE 2000 PARAMETER MEASUREMENT INFORMATION VCC Output 1.5 V CL = 15 pF (see Note B) 5 k See Note C Input 3V 1.3 V 1.3 V 0V tPZL S2 Open 2V Generator (see Note A) 50 (see Note D) TEST CIRCUIT NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR = 1 MHz, duty cycle = 50%, tr 6 ns, tf 6 ns, ZO = 50 . B. CL includes probe and jig capacitance. C. All diodes are 1N916 or equivalent. D. To test the active-low enable G, ground G and apply an inverted input waveform to G. S2 0.5 V VOLTAGE WAVEFORMS Output 1.3 V tPLZ S2 Closed 1.4 V VOL 2 k Figure 3. tPZL and tPLZ Test Circuit and Voltage Waveforms TYPICAL CHARACTERISTICS OUTPUT VOLTAGE vs DIFFERENTIAL INPUT VOLTAGE 4.5 4 3.5 3 VIC = - 7 V VIC = 12 V VIC = 0 V VIC = 0 V 2.5 2 1.5 1 0.5 0 0 10 20 30 40 50 60 70 80 90 100 VID - Differential Input Voltage - mV VIC = - 7 V VIC = 12 V VCC = 5 V TA = 25C 5.5 5 VOH - High-Level Output Voltage - V 4.5 4 3.5 3 2.5 2 1.5 1 0.5 VID = 0.2 V TA = 25C 0 0 - 4 - 8 - 12 - 16 - 20 - 24 - 28 - 32 - 36 - 40 IOH - High-Level Output Current - mA VCC = 4.75 V VCC = 5 V VCC = 5.25 V HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT VO - Output Voltage - V Figure 4 Figure 5 6 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SN65LBC173, SN75LBC173 QUADRUPLE LOW-POWER DIFFERENTIAL LINE RECEIVERS SLLS170D - OCTOBER 1993 - REVISED JUNE 2000 TYPICAL CHARACTERISTICS LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT 660 600 VOL - Low-Level Output Voltage - mV 540 480 420 360 300 240 180 120 60 0 0 3 6 9 12 15 18 21 24 27 30 IOL - Low-Level Output Current - mA 0 10 K 100 K 2M 10 M 100 M I CC - Average Supply Current - mA TA = 25C VCC = 5 V VID = 200 mV 14 12 10 8 6 4 2 AVERAGE SUPPLY CURRENT vs FREQUENCY TA = 25C VCC = 5 V f - Frequency - Hz Figure 6 BUS Figure 7 INPUT CURRENT vs INPUT VOLTAGE (COMPLEMENTARY INPUT AT 0 V) 1 0.8 0.6 I I - Input Current - mA 0.4 0.2 0 - 0.2 - 0.4 - 0.6 - 0.8 PROPAGATION DELAY TIME vs FREE-AIR TEMPERATURE 24.5 VCC = 5 V CL = 15 pF VIO = 1.5 V -1 -8 IIIIIIIIIIIII IIIIIIIIIIIII IIIIIIIIIIIII IIIIIIIIIIIII IIIIIIIIIIIII IIIIIIIIIIIII IIIIIIIIIIIII IIIIIIIIIIIII IIIIIIIIIIIII IIIIIIIIIIIII IIIIIIIIIIIII IIIIIIIIIIIII IIIIIIIIIIIII IIIIIIIIIIIII TA = 25C VCC = 5 V The shaded region of this graph represents more than 1 unit load per RS-485. -2 0 2 4 6 8 10 -6 -4 12 VI - Input Voltage - V Propagation Delay Time - ns 24 tPHL 23.5 23 tPLH 22.5 22 - 40 - 20 0 20 40 60 80 100 TA - Free-Air Temperature - C Figure 8 Figure 9 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 7 SN65LBC173, SN75LBC173 QUADRUPLE LOW-POWER DIFFERENTIAL LINE RECEIVERS SLLS170D - OCTOBER 1993 - REVISED JUNE 2000 MECHANICAL DATA D (R-PDSO-G**) 14 PIN SHOWN PLASTIC SMALL-OUTLINE PACKAGE 0.050 (1,27) 0.020 (0,51) 0.014 (0,35) 14 8 0.008 (0,20) NOM 0.244 (6,20) 0.228 (5,80) 0.157 (4,00) 0.150 (3,81) 0.010 (0,25) M Gage Plane 0.010 (0,25) 1 A 7 0- 8 0.044 (1,12) 0.016 (0,40) Seating Plane 0.069 (1,75) MAX 0.010 (0,25) 0.004 (0,10) 0.004 (0,10) PINS ** DIM A MAX 8 0.197 (5,00) 0.189 (4,80) 14 0.344 (8,75) 0.337 (8,55) 16 0.394 (10,00) 0.386 (9,80) 4040047 / D 10/96 A MIN NOTES: A. B. C. D. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15). Falls within JEDEC MS-012 8 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SN65LBC173, SN75LBC173 QUADRUPLE LOW-POWER DIFFERENTIAL LINE RECEIVERS SLLS170D - OCTOBER 1993 - REVISED JUNE 2000 MECHANICAL DATA N (R-PDIP-T**) 16 PIN SHOWN PINS ** DIM A 16 9 A MAX PLASTIC DUAL-IN-LINE PACKAGE 14 0.775 (19,69) 0.745 (18,92) 16 0.775 (19,69) 0.745 (18,92) 18 0.920 (23.37) 0.850 (21.59) 20 0.975 (24,77) 0.940 (23,88) A MIN 0.260 (6,60) 0.240 (6,10) 1 8 0.070 (1,78) MAX 0.035 (0,89) MAX 0.020 (0,51) MIN 0.310 (7,87) 0.290 (7,37) 0.200 (5,08) MAX Seating Plane 0.125 (3,18) MIN 0.100 (2,54) 0.021 (0,53) 0.015 (0,38) 0- 15 0.010 (0,25) NOM 0.010 (0,25) M 14/18 PIN ONLY 4040049/C 08/95 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-001 (20 pin package is shorter then MS-001.) POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 9 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Customers are responsible for their applications using TI components. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof. Copyright (c) 2000, Texas Instruments Incorporated |
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