View SLLS317_1002817.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

TSB41LV03 IEEE 1394a THREE PORT CABLE TRANSCEIVER/ARBITER
SLLS317- SEPTEMBER 1998
D D
D D D D
D D D
Fully Supports Provisions of IEEE 1394-1995 Standard for High-Performance Serial Bus and the P1394a Supplement (Version 2.0) Full P1394a Support Includes: Connection Debounce, Arbitrated Short Reset, Multispeed Concatenation, Arbitration Acceleration, Fly-By Concatenation, Port Disable/Suspend/Resume Provides Three 1394a Fully-Compliant Cable Ports at 100/200/400 Megabits per Second (Mbits/s) Fully Compliant with Open HCI Requirements Cable Ports Monitor Line Conditions for Active Connection to Remote Node Power-Down Features to Conserve Energy in Battery-Powered Applications include: Automatic Device Power-Down during Suspend, Device Power-Down Terminal, Link Interface Disable via LPS, and Inactive Ports Powered-Down Logic Performs System Initialization and Arbitration Functions Encode and Decode Functions Included for Data-Strobe Bit Level Encoding Incoming Data Resynchronized to Local Clock
D D D D D D D D D D D D
Single 3.3-V Supply Operation Interface to Link Layer Controller Supports Low-Cost TITM Bus-Holder Isolation and Optional Annex J Electrical Isolation Data Interface to Link-Layer Controller Through 2/4/8 Parallel Lines at 49.152 MHz Low Cost 24.576-MHz Crystal Provides Transmit, Receive Data at 100/200/400 Mbits/s, and Link-Layer Controller Clock at 49.152 MHz Interoperable with Link-Layer Controllers Using 3.3-V and 5-V Supplies Interoperable with other Physical Layers (PHYs) Using 3.3 V and 5 V Supplies Node Power Class Information Signaling for System Power Management Cable Power Presence Monitoring Separate Cable Bias (TPBIAS) for Each Port Register Bits give Software Control of Contender Bit, Power Class Bits, Link Active Bit, and 1394a Features Fully Interoperable with FireWireTM Implementation of IEEE Std 1394 Low-Cost High-Performance 80-Pin TQFP (PFP) Thermally Enhanced Package
description
The TSB41LV03 provides the digital and analog transceiver functions needed to implement a three-port node in a cable-based IEEE-1394 network. Each cable port incorporates two differential line transceivers. The transceivers include circuitry to monitor the line conditions as needed for determining connection status, for initialization and arbitration, and for packet reception and transmission. The TSB41LV03 is designed to interface with a link layer controller (LLC), such as the TSB12LV22, TSB12LV21, TSB12LV31, TSB12LV41, or TSB12LV01. The TSB41LV03 requires only an external 24.576-MHz crystal as a reference. An external clock can be provided instead of a crystal. An internal oscillator drives an internal phase-locked loop (PLL), which generates the required 393.216-MHz reference signal. This reference signal is internally divided to provide the clock signals used to control transmission of the outbound encoded strobe and data information. A 49.152-MHz clock signal, supplied to the associated LLC for synchronization of the two chips, is used for resynchronization of the received data. The power-down (PD) function, when enabled by asserting the PD terminal high, stops operation of the PLL.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. TI is a trademark of Texas Instruments Incorporated. FireWire is a trademark of Apple Computer, Incorporated.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright (c) 1998, Texas Instruments Incorporated
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
1
TSB41LV03 IEEE 1394a THREE PORT CABLE TRANSCEIVER/ARBITER
SLLS317- SEPTEMBER 1998
description (continued)
The TSB41LV03 supports an optional isolation barrier between itself and its LLC. When the ISO input terminal is tied high, the LLC interface outputs behave normally. When the ISO terminal is tied low, internal differentiating logic is enabled, and the outputs are driven such that they can be coupled through a capacitive or transformer galvanic isolation barrier as described in IEEE P1394a section 5.9.4. To operate with TI Bus Holder isolation the ISO on the PHY terminal must be tied HIGH. Data bits to be transmitted through the cable ports are received from the LLC on two, four, or eight parallel paths (depending on the requested transmission speed). They are latched internally in the TSB41LV03 in synchronization with the 49.152-MHz system clock. These bits are combined serially, encoded, and transmitted at 98.304, 196.608, or 392.216 Mbits/s (referred to as S100, S200, and S400 speed respectively) as the outbound data-strobe information stream. During transmission, the encoded data information is transmitted differentially on the TPB cable pair(s), and the encoded strobe information is transmitted differentially on the TPA cable pair(s). During packet reception the TPA and TPB transmitters of the receiving cable port are disabled, and the receivers for that port are enabled. The encoded data information is received on the TPA cable pair, and the encoded strobe information is received on the TPB cable pair. The received data-strobe information is decoded to recover the receive clock signal and the serial data bits. The serial data bits are split into two-, four-, or eight-bit parallel streams (depending upon the indicated receive speed), resynchronized to the local 49.152-MHz system clock and sent to the associated LLC. The received data is also transmitted (repeated) on the other active (connected) cable ports. Both the TPA and TPB cable interfaces incorporate differential comparators to monitor the line states during initialization and arbitration. The outputs of these comparators are used by the internal logic to determine the arbitration status. The TPA channel monitors the incoming cable common-mode voltage. The value of this common-mode voltage is used during arbitration to set the speed of the next packet transmission. In addition, the TPB channel monitors the incoming cable common-mode voltage on the TPB pair for the presence of the remotely supplied twisted-pair bias voltage. The TSB41LV03 provides a 1.86-V nominal bias voltage at the TPBIAS terminal for port termination. The PHY contains three independent TPBIAS circuits. This bias voltage, when seen through a cable by a remote receiver, indicates the presence of an active connection. This bias voltage source must be stabilized by an external filter capacitor of 1 F. The line drivers in the TSB41LV03, operating in a high-impedance current mode, are designed to work with external 112- line-termination resistor networks in order to match the 110- cable impedance. One network is provided at each end of a twisted-pair cable. Each network is composed of a pair of series-connected 56- resistors. The midpoint of the pair of resistors that is directly connected to the twisted-pair A terminals is connected to its corresponding TPBIAS voltage terminal. The midpoint of the pair of resistors that is directly connected to the twisted-pair B terminals is coupled to ground through a parallel R-C network with recommended values of 5 k and 220 pF. The values of the external line-termination resistors are designed to meet the standard specifications when connected in parallel with the internal receiver circuits. An external resistor connected between the R0 and R1 terminals sets the driver output current, along with other internal operating currents. This current setting resistor has a value of 6.3 k 0.5%. This may be accomplished by placing a 6.34-k 0.5% resistor in parallel with a 1-M resistor. When the power supply of the TSB41LV03 is 0 V while the twisted-pair cables are connected, the TSB41LV03 transmitter and receiver circuitry presents a high-impedance signal to the cable and does not load the TPBIAS voltage at the other end of the cable.
2
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
TSB41LV03 IEEE 1394a THREE PORT CABLE TRANSCEIVER/ARBITER
SLLS317- SEPTEMBER 1998
description (continued)
When the TSB41LV03 is used with one or more of the ports not brought out to a connector, the twisted-pair terminals of the unused ports must be terminated for reliable operation. For each unused port, the TPB+ and TPB- terminals can be tied together and then pulled to ground, or the TPB+ and TPB- terminals can be connected to the suggested termination network. The TPA+ and TPA- and TPBIAS terminals of an unused port can be left unconnected. The TPBias terminal can be connected to a 1-F capacitor to ground or left floating. The TESTM, SE, and SM terminals are used to set up various manufacturing test conditions. For normal operation, the TESTM terminal should be connected to VDD, and the SE and SM terminals should be connected to ground. Four package terminals, used as inputs to set the default value for four configuration status bits in the self-ID packet, are hard-wired high or low as a function of the equipment design. The PC0-PC2 terminals are used to indicate the default power-class status for the node (the need for power from the cable or the ability to supply power to the cable). See Table 9 for power-class encoding. The C/LKON terminal is used as an input to indicate the that the node is a contender for bus manager. The PHY supports suspend/resume as defined in the IEEE P1394a specification. The suspend mechanism allows pairs of directly-connected ports to be placed into a low-power state while maintaining a port-to-port connection between 1394 bus segments. While in a low-power state, a port is unable to transmit or receive data-transaction packets. However, a port in a low-power state is capable of detecting connection status changes and detecting incoming TPBias. When all three ports of the TSB41LV03 are suspended, all circuits except the bandgap reference generator and bias-detection circuits are powered down, resulting in significant power savings. For additional details of suspend/resume operation refer to the P1394a specification. The use of suspend/resume is recommended for new designs. The port transmitter and receiver circuitry is disabled during power down (when the PD input terminal is asserted high), during reset (when the RESET input terminal is asserted low), when no active cable is connected to the port, or when controlled by the internal arbitration logic. The port twisted-pair bias-voltage circuitry is disabled during power down, during reset, or when the port is disabled as commanded by the LLC. The CNA (cable-not-active) terminal provides a high output when all twisted-pair cable ports are disconnected, and can be used along with LPS to determine when to power-down the TSB41LV03. The CNA output is not debounced. In power-down mode, the CNA detection circuitry remains enabled. The LPS (link power status) terminal works with the C/LKON terminal to manage the power usage in the node. The LPS signal from the LLC indicates to the PHY that the LLC is powered up and active. During LLC power-down mode, as indicated by the LPS input being low for more than 2.6 s, the TSB41LV03 deactivates the PHY-LLC interface to save power. The TSB41LV03 continues the necessary repeater function required for network operation during this low-power state. If the PHY receives a link-on packet from another node, the C/LKON terminal is activated to output a square-wave signal. The LLC recognizes this signal, reactivates any powered-down portions of the LLC, and notifies the PHY of its power-on status via the LPS terminal. The PHY confirms notification by deactivating the square-wave signal on the C/LKON terminal, and then enables the PHY-link interface.
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
3
TSB41LV03 IEEE 1394a THREE PORT CABLE TRANSCEIVER/ARBITER
SLLS317- SEPTEMBER 1998
PFP PACKAGE (TOP VIEW)
AGND TPBIAS2 TPA2+ TPA2- TPB2+ TPB2- AVDD TPBIAS1 TPA1+ TPA1- TPB1+ TPB1- AVDD AVDD TPBIAS0 TPA0+ TPA0- AGND AVDD AVDD AGND AGND R0 R1 DVDD DVDD DGND FILTER0 FILTER1 PLLVDD PLLGND PLLGND XI XO RESET DVDD DGND
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 123 45 6 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 7 8 9 10 11 12 13 14 15 16 17 18 19 20
TPB0+ TPB0- AGND AGND AGND AGND AGND AGND AVDD AVDD SM SE TESTM DVDD DVDD DGND CPS ISO PC2 PC1 PC0 C/LKON DGND
4
LREQ SYSCLK DGND CTL0 CTL1 DV DD D0 D1 VDD-5V D2 D3 D4 D5 D6 D7 DGND CNA PD LPS DGND
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
TSB41LV03 IEEE 1394a THREE PORT CABLE TRANSCEIVER/ARBITER
SLLS317- SEPTEMBER 1998
functional block diagram
CPS LPS ISO CNA SYSCLK LREQ CTL0 CTL1 D0 D1 D2 D3 D4 D5 D6 D7 PC0 PC1 PC2 C/LK0N Cable Port 1 TPB1+ TPB1- TPA2+ TPA2- Cable Port 2 Bias Voltage and Current Generator TPB2+ TPB2- Arbitration and Control State Machine Logic Cable Port 0 TPB0+ TPB0- Link Interface I/O TPA0+ TPA0-
Received Data Decoder/Retimer
TPA1+ TPA1-
R0 R1 TPBIAS0 TPBIAS1 TPBIAS2
PD RESET
Transmit Data Encoder
Crystal Oscillator, PLL System, and Clock Generator
XI XO FILTER0 FILTER1
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
5
TSB41LV03 IEEE 1394a THREE PORT CABLE TRANSCEIVER/ARBITER
SLLS317- SEPTEMBER 1998
Terminal Functions
TERMINAL NAME AGND TYPE Supply NO. 36, 37, 38, 39, 40, 41, 60, 61, 64, 65 34, 35, 47, 48, 54, 62, 63 I/O - DESCRIPTION Analog circuit ground terminals. These terminals should be tied together to the low-impedance circuit board ground plane.
AVDD
Supply
-
Analog circuit power terminals. A combination of high-frequency decoupling capacitors near each terminal are suggested, such as paralleled 0.1 F and 0.001 F. Lower frequency 10-F filtering capacitors are also recommended. These supply terminals are separated from PLLVDD and DVDD internal to the device to provide noise isolation. They should be tied at a low-impedance point on the circuit board. Cable not active output. This terminal is asserted high when there are no ports receiving incoming bias voltage. Cable power status input. This terminal is normally connected to cable power through a 400-k resistor. This circuit drives an internal comparator that is used to detect the presence of cable power. Control I/Os. These bidirectional signals control communication between the TSB41LV03 and the LLC. Bus Holders are built into these terminals. Bus manager contender programming input and link-on output. On hardware reset, this terminal is used to set the default value of the contender status indicated during self-ID. Programming is done by tying the terminal through a 10-k resistor to a high (contender) or low (not contender). The resistor allows the link-on output to override the input. Following hardware reset, this terminal is the link-on output, which is used to notify the LLC to power-up and become active. The link-on output is a square-wave signal with a period of approximately 163 ns (8 SYSCLK cycles) when active. The link-on output is deasserted low when the LPS input terminal is active.
CNA CPS
CMOS CMOS
17 27
O I
CTL0 CTL1 C/LKON
CMOS 5 V tol CMOS
4 5 22
I/O I/O
DGND
Supply
3, 16, 20, 21, 28, 70, 80 7, 8, 10, 11, 12, 13, 14, 15 6, 29, 30, 68, 69, 79
-
Digital circuit ground terminals. These terminals should be tied together to the low-impedance circuit board ground plane. Data I/Os. These are bidirectional data signals between the TSB41LV03 and the LLC. Bus holders are built into these terminals. Digital circuit power terminals. A combination of high-frequency decoupling capacitors near each terminal are suggested, such as paralleled 0.1 F and 0.001 F. Lower frequency 10-F filtering capacitors are also recommended. These supply terminals are separated from PLLVDD and AVDD internal to the device to provide noise isolation. They should be tied at a low-impedance point on the circuit board. PLL filter terminals. These terminals are connected to an external capacitor to form a lag-lead filter required for stable operation of the internal frequency-multiplier PLL running off of the crystal oscillator. A 0.1-F 10% capacitor is the only external component required to complete this filter. Link interface isolation control input. This terminal controls the operation of output differentiation logic on the CTL and D terminals. If an optional isolation barrier of the type described in Annex J of IEEE Std 1394-1995 is implemented between the TSB41LV03 and LLC, the ISO terminal should be tied low to enable the differentiation logic. If no isolation barrier is implemented (direct connection), or TI Bus Holder Isolation is implemented, the ISO terminal should be tied high to disable the differentiation logic. For additional information refer to TI application note Serial Bus Galvanic Isolation, SLLA011. Link Power Status input. This terminal is used to monitor the power status of the LLC, and is connected to either the VDD supplying the link layer controller through a 1-k resistor, or to a pulsed output, which is active when the LLC is powered. The pulsed output is useful when using an isolation barrier. If this input is low for more than 2.6 s, the LLC is considered powered-down. If this input is high for more than 20 ns, the LLC is considered powered-up. If the LLC is powered-down, the PHY-LLC interface is disabled, and the TSB41LV03 performs only the basic repeater functions required for network initialization and operation. Bus holder is built into this terminal.
D0-D7
CMOS 5 V tol Supply
I/O
DVDD
-
FILTER0 FILTER1 ISO
CMOS
71 72 26
I/O
CMOS
I
LPS
CMOS 5 V tol
19
I
6
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
TSB41LV03 IEEE 1394a THREE PORT CABLE TRANSCEIVER/ARBITER
SLLS317- SEPTEMBER 1998
Terminal Functions (Continued)
TERMINAL NAME LREQ PC0 PC1 PC2 PD PLLGND PLLVDD TYPE CMOS 5 V tol CMOS NO. 1 23 24 25 18 74, 75 73 I/O I I DESCRIPTION LLC Request input. The LLC uses this input to initiate a service request to the TSB41LV03. Bus holder is built into this terminal. Power class programming inputs. On hardware reset, these inputs set the default value of the power class indicated during self-ID. Programming is done by tying the terminals high or low. Refer to Table 9 for encoding. Power-down input. A logic high on this terminal turns off all internal circuitry except the cable-active monitor circuits, which control the CNA output. Bus holder is built into this terminal. PLL circuit ground terminals. These terminals should be tied together to the low impedance circuit board ground plane. PLL circuit power terminals. A combination of high-frequency decoupling capacitors near each terminal are suggested, such as paralleled 0.1 F and 0.001 F. Lower frequency 10-F filtering capacitors are also recommended. These supply terminals are separated from DVDD and AVDD internal to the device to provide noise isolation. They should be tied at a low-impedance point on the circuit board. Logic reset input. Asserting this terminal low resets the internal logic. An internal pull-up resistor to VDD is provided so only an external delay capacitor in parallel with a resistor are required for proper power-up operation (see power-up reset in the APPLICATIONS INFORMATION section). This input is otherwise a standard logic input, and can also be driven by an open-drain type driver. Current setting resistor terminals. These terminals are connected to an external resistance to set the internal operating currents and cable driver output currents. A resistance of 6.3 k 0.5% is required to meet the IEEE Std 1394-1995 output voltage limits. Test control input. This input is used in the manufacturing test of the TSB41LV03. For normal use this terminal should be tied to GND. Test control input. This input is used in the manufacturing test of the TSB41LV03. For normal use this terminal should be tied to GND. System clock output. Provides a 49.152-MHz clock signal, synchronized with data transfers, to the LLC. Test control input. This input is used in the manufacturing test of the TSB41LV03. For normal use this terminal should be tied to VDD.
CMOS 5 V tol Supply Supply
I - -
RESET
CMOS
78
I
R0 R1 SE SM SYSCLK TESTM TPA0+ TPA1+ TPA2+ TPA0- TPA1- TPA2- TPB0+ TPB1+ TPB2+ TPB0- TPB1- TPB2- TPBIAS0 TPBIAS1 TPBIAS2
Bias
66 67 32 33 2 31 45 52 58 44 51 57 43 50 56 42 49 55 46 53 59
-
CMOS CMOS CMOS CMOS Cable
I I O I I/O
Cable
I/O
Twisted-pair cable A differential-signal terminals. Board traces from each pair of positive and negative differential signal terminals should be kept matched and as short as possible to the external load resistors and to the cable connector.
Cable
I/O Twisted-pair cable B differential-signal terminals. Board traces from each pair of positive and negative differential signal terminals should be kept matched and as short as possible to the external load resistors and to the cable connector.
Cable
I/O
Cable
I/O
Twisted-pair bias output. This provides the 1.86-V nominal bias voltage needed for proper operation of the twisted-pair cable drivers and receivers, and for signaling to the remote nodes that there is an active cable connection. Each of these terminals must be decoupled with a 1-F capacitor to ground.
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
7
TSB41LV03 IEEE 1394a THREE PORT CABLE TRANSCEIVER/ARBITER
SLLS317- SEPTEMBER 1998
Terminal Functions (Continued)
TERMINAL NAME VDD-5V TYPE Supply NO. 9 I/O - DESCRIPTION 5-V VDD terminal. This terminal should be connected to the LLC VDD supply when a 5-V LLC is used, and should be connected to the PHY DVDD when a 3-V LLC is used. A combination of high-frequency decoupling capacitors near this terminal is suggested, such as paralleled 0.1 F and 0.001 F. When this terminal is tied to a 5-V supply, all terminal bus holders are disabled, regardless of the state of the ISO terminal. When this terminal is tied to a 3-V supply, Bus Holders are enabled when the ISO terminal is high. Crystal oscillator inputs. These terminals connect to a 24.576-MHz parallel resonant fundamental mode crystal. The optimum values for the external shunt capacitors are dependent on the specifications of the crystal used.
XI XO
Crystal
76 77
-
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage range, VDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 4 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to VDD+0.5 V 5-V tolerant I/O supply voltage range, VDD-5V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 5.5 V 5-V tolerant input voltage range, VI-5V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to VDD-5V+0.5 V Output voltage range at any output, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to VDD+0.5 V Electrostatic discharge (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HBM:2 kV, MM:200 V Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Operating free air temperature, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 70C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values, except differential I/O bus voltages, are with respect to network ground. 2. HBM is Human Body Model, MM is Machine Model. DISSIPATION RATING TABLE PACKAGE PFP PFP PFP# TA 25C POWER RATING 5.05 W 3.05 W DERATING FACTOR ABOVE TA = 25C 50.5 mW/C 30.5 mW/C TA = 70C POWER RATING 2.79 W 1.68 W
2.01 W 20.1 mW/C 1.11 W This is the inverse of the traditional junction-to-ambient thermal resistance (RJA). 1 oz. trace and copper pad with solder. 1 oz. trace and copper pad without solder. # Standard JEDEC High-K board. For more information, refer to TI application note PowerPAD Thermally Enhanced Package, TI literature number SLMA002.
8
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
TSB41LV03 IEEE 1394a THREE PORT CABLE TRANSCEIVER/ARBITER
SLLS317- SEPTEMBER 1998
recommended operating conditions
MIN Supply voltage VDD voltage, Source power node Non-source power node Case1 (Bus Holder): ISO = VDD, VDD 5V = VDD DD-5V Case 2 (5 V Tol): ISO = VDD, VDD-5V = 5 V Case1 (Bus Holder): ISO = VDD, VDD-5V = VDD Case 2 (5 V Tol): ISO = VDD, VDD-5V = 5 V CTL0, CTL1, D0-D7, CNA, C/LKON, and SYSCLK TPBIAS outputs RJA = 19.8C/W RJA = 32.8C/W RJA = 49.8C/W TA = 70C TA = 70C 118 168 0.4706 0.4706 2 1.08 0.5 0.315 0.8 0.55 0.5 ns ns -12 -5.6 VDD = 2.7 V VDD = 3 V to 3.6 V 3 2.7 2.3 2.6 1.2 12 1.3 92 106 125 260 265 2.515 2.015 mV V ms C V TYP 3.3 3 MAX 3.6 3.6 UNIT V
High-level input voltage, VIH
Low-level input voltage, VIL Output current, IOL/OH Output current, IO Maximum junction tem erature, TJ temperature, (see RJA values listed in thermal characteristics table) Differential input voltage, VID voltage Common mode input voltage, VIC voltage Common-mode Power-up reset time, tpu Receive input jitter
V mA mA
TA = 70C Cable inputs, during data reception Cable inputs, during arbitration TPB cable inputs, Source power node TPB cable inputs, Non-source power node RESET input TPA, TPB cable inputs, S100 operation TPA, TPB cable inputs, S200 operation TPA, TPB cable inputs, S400 operation Between TPA and TPB cable inputs, S100 operation
Receive input skew
Between TPA and TPB cable inputs, S200 operation Between TPA and TPB cable inputs, S400 operation
All typical values are at VDD = 3.3 V and TA = 25C. For a node that does not source power; see Section 4.2.2.2 in IEEE P1394a.
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
9
TSB41LV03 IEEE 1394a THREE PORT CABLE TRANSCEIVER/ARBITER
SLLS317- SEPTEMBER 1998
electrical characteristics over recommended ranges of operating conditions (unless otherwise noted) driver
PARAMETER VOD Differential output voltage Driver Difference current, TPA+, TPA-, TPB+, TPB- Common-mode speed signaling current, TPB+, TPB- Common-mode speed signaling current, TPB+, TPB- Off state differential voltage 56 , TEST CONDITION See Figure 1 Drivers enabled, speed signaling off. S200 speed signaling enabled S400 speed signaling enabled Drivers disabled, See Figure 1 MIN 172 -1.05 -4.84 -12.4 MAX 265 1.05 -2.53 -8.10 20 UNIT mV mA mA mA
mV Limits defined as algebraic sum of TPA+ and TPA- driver currents. Limits also apply to TPB+ and TPB- algebraic sum of driver currents. Limits defined as absolute limit of each of TPB+ and TPB- driver currents.
receiver
PARAMETER ZID ZIC VTH-R VTH-CB VTH+ VTH- VTH-SP200 Differential impedance Common-mode Common mode impedance Receiver input threshold voltage Cable bias detect threshold, TPBx cable inputs Positive arbitration comparator threshold voltage Negative arbitration comparator threshold voltage Speed signal threshold TEST CONDITION Drivers disabled Drivers disabled Drivers disabled Drivers disabled Drivers disabled Drivers disabled TPBIAS-TPA common mode voltage, drivers disabled TPBIAS-TPA common mode voltage, drivers disabled MIN 10 20 24 -30 0.6 89 -168 49 30 1.0 168 -89 131 TYP 14 4 MAX UNIT k pF k pF mV V mV mV mV
VTH-SP 400
Speed signal threshold
314
396
mV
10
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
TSB41LV03 IEEE 1394a THREE PORT CABLE TRANSCEIVER/ARBITER
SLLS317- SEPTEMBER 1998
device
PARAMETER IDD IDD-PD VTH Supply current Supply Current - Power-down or suspend mode Power status threshold, CPS input TEST CONDITION See Note 3 See Note 4 VDD = 3.3 V, 400-k resistor IOH = 12 mA VDD = 2.7 V, VOH High-level output voltage IOH = 4 mA VDD = 3 V to 3.6 V, IOH = 4 mA Annex J: IO = -9 mA, ISO = 0 V, VDD-5V = VDD IOL = 12 mA IOL = 4 mA Annex J: IOL = 9 mA, ISO = 0 V, VDD-5V = VDD Positive peak bus holder current Negative peak bus holder current Input current, LREQ, LPS, PD, TESTM, SE, SM, PC0-PC2 inputs Off-state output current, CTL0, CTL1. D0-D7, C/LKON I/Os Pullup current RESET input current, Positive input threshold voltage, LREQ, CTL0, CTL1, D1-D7 inputs Positive input threshold voltage, PD, LPS inputs Negative input threshold voltage, LREQ, CTL0, CTL1, D1-D7 inputs Negative input threshold voltage, PD, LPS inputs ISO = 3.6 V, VI = 0 V to VDD, ISO = 3.6 V, VI = 0 V to VDD, VDD = 3.6 V, VDD-5 = VDD VDD = 3.6 V, VDD-5 = VDD 0.05 -1 TA = 25C 4.7 VDD-0.5 V 2.2 2.8 VDD-0.4 0.5 0.4 0.4 1 -0.05 5 5 -80 -90 ISO = 0 V VDD/2+0.3 V -40 -45 -20 -22 VDD/2+0.9 V VDD-5V = VDD, ISO = 0 V, Vref = VDD x 0.42 VDD-5V = VDD, ISO = 0 V VDD/2-0.9 V Vref+0.2 V V Vref+1 VDD/2-0.3 V VDD-5V = VDD, ISO = 0 V, Vref = VDD x 0.42 At rated IO current mA mA A A A V V MIN TYP 160 114 4 7.5 MAX UNIT mA mA V
VOL
Low-level out ut voltage output
IBH+ IBH- II IOZ IIRST
ISO = 0 V, VDD = 3.6 V VO= VDD or 0 V VI=1.5 V VI=0 V VDD-5V = VDD,
VIT+
VIT-
VO TPBIAS output voltage 1.665 2.015 Measured at cable power side of resistor. This parameter applicable only when ISO low. NOTES: 3. Repeat (receive on port0, transmit on port1 and port2, full ISO payload of 84 s, S400, data value of CCCCCCCCh), VDD = 3.3 V, TA = 25C 4. Idle (receive cycle start on port0, transmit cycle start on port1 and port2), VDD = 3.3 V, TA = 25C
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
11
TSB41LV03 IEEE 1394a THREE PORT CABLE TRANSCEIVER/ARBITER
SLLS317- SEPTEMBER 1998
thermal characteristics
PARAMETER RJA RJC RJA RJC RJA RJC Junction-to-free-air thermal resistance Junction-to-case-thermal resistance Junction-to-free-air thermal resistance Junction-to-case-thermal resistance Junction-to-free-air thermal resistance Junction-to-case-thermal resistance TEST CONDITION Board mounted, No air flow, High conductivity TI recommended test board, chi soldered or greased to board chip thermal land with 1 oz. copper Board mounted, No air flow, High conductivity TI recommended test board with thermal land but no solder or grease thermal connection to thermal land with 1 oz. copper Board mounted, No air flow, JEDEC test board mounted flow MIN TYP 19.8 0.17 32.8 0.17 49.8 3.6 MAX UNIT C/W C/W C/W C/W C/W C/W
switching characteristics
PARAMETER Jitter, transmit Skew, transmit tr tf tsu th td TP differential rise time, transmit TP differential fall time, transmit Setup time, CTL0, CTL1, D1-D7, LREQ to SYSCLK Hold time, CTL0, CTL1, D1-D7, LREQ after SYSCLK Delay time, SYSCLK to CTL0, CTL1, D1-D7 TEST CONDITION Between TPA and TPB Between TPA and TPB 10% to 90%, 90% to 10%, 50% to 50%, 50% to 50%, 50% to 50%, At 1394 connector At 1394 connector See Figure 2 See Figure 2 See Figure 3 0.5 0.5 5 2 2 11 MIN TYP MAX 0.15 0.10 1.2 1.2 UNIT ns ns ns ns ns ns ns
PARAMETER MEASUREMENT INFORMATION
TPAx+ TPBx+
56
TPAx- TPBx-
Figure 1. Test Load Diagram
SYSCLK
tsu D, CTL, LREQ
th
Figure 2. D, CTL, LREQ Input Setup and Hold Time Waveforms
12
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
TSB41LV03 IEEE 1394a THREE PORT CABLE TRANSCEIVER/ARBITER
SLLS317- SEPTEMBER 1998
PARAMETER MEASUREMENT INFORMATION
SYSCLK
td D, CTL, LREQ
Figure 3. D and CTL Output Delay Relative to SYSCLK Waveforms
APPLICATION INFORMATION internal register configuration
There are 16 accessible internal registers in the TSB41LV03. The configuration of the registers at addresses 0 through 7 (the base registers) is fixed, while the configuration of the registers at addresses 8h through Fh (the paged registers) is dependent upon which one of eight pages, numbered 0h through 7h, is currently selected. The selected page is set in base register 7h. The configuration of the base registers is shown in Table 1, and corresponding field descriptions given in Table 2 The base register field definitions are unaffected by the selected page number. A reserved register or register field (marked as Reserved or Rsvd in the following register configuration tables) is read as 0, but is subject to future usage. All registers in address pages 2 through 6 are reserved. Table 1. Base Register Configuration
Address 0000 0001 0010 0011 0100 0101 0110 0111 Page_Select L RPIE RHB IBR Extended (111b) PHY_Speed (010b) C ISBR CTOI Rsvd Rsvd Jitter (000) CPSI Rsvd STOI PEI Reserved Port_Select BIT POSITION 0 1 2 Physical ID Gap_Count Num_Ports (0011b) Delay (0000b) Pwr_Class EAA EMC 3 4 5 6 R 7 CPS
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
13
TSB41LV03 IEEE 1394a THREE PORT CABLE TRANSCEIVER/ARBITER
SLLS317- SEPTEMBER 1998
APPLICATION INFORMATION
Table 2. Base Register Field Descriptions
FIELD Physical ID R CPS SIZE 6 1 1 TYPE Rd Rd Rd DESCRIPTION This field contains the physical address ID of this node determined during self-ID. The physical-ID is invalid after a bus reset until self-ID has completed as indicated by an unsolicited register-0 status transfer. Root. This bit indicates that this node is the root node. The R bit is reset to 0 by bus reset, and is set to 1 during tree-ID if this node becomes root. Cable-power-status. This bit indicates the state of the CPS input terminal. The CPS terminal is normally tied to serial bus cable power through a 400-k resistor. A 0 in this bit indicates that the cable power voltage has dropped below its threshold for ensured reliable operation. Root-holdoff bit. This bit instructs the PHY to attempt to become root after the next bus reset. The RHB bit is reset to 0 by a hardware reset, and is unaffected by a bus reset. Initiate bus reset. This bit instructs the PHY to initiate a long (166 s) bus reset at the next opportunity. Any receive or transmit operation in progress when this bit is set will complete before the bus reset is initiated. The IBR bit is reset to 0 after a hardware reset or a bus reset. Arbitration gap count. This value is used to set the subaction (fair) gap, arb-reset gap, and arb-delay times. The gap count can be set either by a write to the register, or by reception or transmission of a PHY_CONFIG packet. The gap count is reset to 3Fh by hardware reset or after two consecutive bus resets without an intervening write to the gap count register (either by a write to the PHY register or by a PHY_CONFIG packet). Extended register definition. For the TSB41LV03, this field is 111b, indicating that the extended register set is implemented. Number of ports. This field indicates the number of ports implemented in the PHY. For the TSB41LV03 this field is 3. PHY speed capability. For the TSB41LV03 PHY this field is 010b, indicating S400 speed capability. PHY repeater data delay. This field indicates the worst case repeater data delay of the PHY, expressed as 144+(delay x 20) ns. For the TSB41LV03 this field is 0. Link-active status. This bit indicates that this node's link is active. The logical AND of this bit and the LPS active status is replicated in the L field (bit 9) of the self-ID packet. This bit is set to 1 by a hardware reset and is unaffected by a bus reset. Contender status. This bit indicates that this node is a contender for the bus or isochronous resource manager. This bit is replicated in the c field (bit 20) of the self-ID packet. This bit is set to the state specified by the C/LKON input terminal by a hardware reset and is unaffected by a bus reset. PHY repeater jitter. This field indicates the worst case difference between the fastest and slowest repeater data delay, expressed as (Jitter+1) x 20 ns. For the TSB41LV03, this field is 0. Node power class. This field indicates this node power consumption and source characteristics and is replicated in the pwr field (bits 21-23) of the self-ID packet. This field is reset to the state specified by the PC0-PC2 input terminals upon a hardware reset, and is unaffected by a bus reset. See Table 9. Resuming port interrupt enable. This bit, if set to 1, enables the port event interrupt (PIE) bit to be set whenever resume operations begin on any port. This bit is reset to 0 by hardware reset and is unaffected by bus reset. Initiate short arbitrated bus reset. This bit, if set to 1, instructs the PHY to initiate a short (1.3 s) arbitrated bus reset at the next opportunity. This bit is reset to 0 by a bus reset. NOTE: Legacy IEEE Std 1394-1995 compliant PHYs can not be capable of performing short bus resets. Therefore, initiation of a short bus reset in a network that contains such a legacy device results in a long bus reset being performed. CTOI 1 Rd/Wr Configuration time-out interrupt. This bit is set to 1 when the arbitration controller times-out during tree-ID start, and may indicate that the bus is configured in a loop. This bit is reset to 0 by hardware reset, or by writing a 1 to this register bit. NOTE: If the network is configured in a loop, only those nodes which are part of the loop should generate a configuration-timeout interrupt. All other nodes should instead time out waiting for the tree-ID and/or self-ID process to complete and then generate a state time-out interrupt and bus-reset.
RHB IBR
1 1
Rd/Wr Rd/Wr
Gap_Count
6
Rd/Wr
Extended Num_Ports PHY_Speed Delay L
3 4 3 4 1
Rd Rd Rd Rd Rd/Wr
C
1
Rd/Wr
Jitter Pwr_Class
3 3
Rd Rd/Wr
RPIE
1
Rd/Wr
ISBR
1
Rd/Wr
14
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
TSB41LV03 IEEE 1394a THREE PORT CABLE TRANSCEIVER/ARBITER
SLLS317- SEPTEMBER 1998
APPLICATION INFORMATION
Table 2. Base Register Field Descriptions (Continued)
FIELD CPSI SIZE 1 TYPE Rd/Wr DESCRIPTION Cable power status interrupt. This bit is set to 1 whenever the CPS input transitions from high to low indicating that cable power may be too low for reliable operation. This bit is reset to 0 by hardware reset, or by writing a 1 to this register bit. State-timeout interrupt. This bit indicates that a state time-out has occurred. This bit is reset to 0 by hardware reset, or by writing a 1 to this register bit. Port event interrupt. This bit is set to 1 on any change in the connected, bias, disabled, or fault bits for any port for which the port interrupt enable (PIE) bit is set. Additionally, if the resuming port interrupt enable (RPIE) bit is set, the PEI bit is set to 1 at the start of resume operations on any port. This bit is reset to 0 by hardware reset, or by writing a 1 to this register bit. Enable accelerated arbitration. This bit enables the PHY to perform the various arbitration acceleration enhancements defined in P1394a (ACK-accelerated arbitration, asynchronous fly-by concatenation, and isochronous fly-by concatenation). This bit is reset to 0 by hardware reset and is unaffected by bus reset. NOTE: The EAA bit should be set only if the attached LLC is P1394a compliant. If the LLC is not P1394a compliant, use of the arbitration acceleration enhancements can interfere with isochronous traffic by excessively delaying the transmission of cycle-start packets. EMC 1 Rd/Wr Enable multispeed concatenated packets. This bit enables the PHY to transmit concatenated packets of differing speeds in accordance with the protocols defined in P1394a. This bit is reset to 0 by hardware reset and is unaffected by bus reset. NOTE: The use of multispeed concatenation is completely compatible with networks containing legacy IEEE Std 1394-1995 PHYs. However, use of multispeed concatenation requires that the attached LLC be P1394a compliant. Page_Select Port_Select 3 4 Rd/Wr Rd/Wr Page_Select. This field selects the register page to use when accessing register addresses 8 through 15. This field is reset to 0 by a hardware reset and is unaffected by bus-reset. Port_Select. This field selects the port when accessing per-port status or control (e.g., when one of the port status/control registers is accessed in page 0). Ports are numbered starting at 0. This field is reset to 0 by hardware-reset and is unaffected by bus-reset.
STOI PEI
1 1
Rd/Wr Rd/Wr
EAA
1
Rd/Wr
The port status page provides access to configuration and status information for each of the ports. The port is selected by writing 0 to the Page_Select field and the desired port number to the Port_Select field in base register 7. The configuration of the port status page registers is shown in Table 3 and corresponding field descriptions given in Table 4. If the selected port is unimplemented, all registers in the port status page are read as 0. Table 3. Page 0 (Port Status) Register Configuration
BIT POSITION Address 1000 1001 1010 1011 1100 1101 1110 1111 0 AStat Peer_Speed 1 2 BStat PIE Reserved Reserved Reserved Reserved Reserved Reserved 3 4 Ch Fault 5 Con 6 Bias Reserved 7 Dis
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
15
TSB41LV03 IEEE 1394a THREE PORT CABLE TRANSCEIVER/ARBITER
SLLS317- SEPTEMBER 1998
APPLICATION INFORMATION
Table 4. Page 0 (Port Status) Register Field Descriptions
FIELD AStat SIZE 2 TYPE Rd DESCRIPTION TPA line state. This field indicates the TPA line state of the selected port, encoded as follows: Arb Value Code 11 Z 01 1 10 0 00 invalid TPB line state. This field indicates the TPB line state of the selected port. This field has the same encoding as the ASTAT field. Child/parent status. A 1 indicates that the selected port is a child port. A 0 indicates that the selected port is the parent port. A disconnected, disabled, or suspended port is reported as a child port. The Ch bit is invalid after a bus-reset until tree-ID has completed. Debounced port connection status. This bit indicates that the selected port is connected. The connection must be stable for the debounce time of approximately 341 ms for the Con bit to be set to 1. The Con bit is reset to 0 by hardware reset and is unaffected by bus reset. NOTE: The Con bit indicates that the port is physically connected to a peer PHY, but the port is not necessarily active. Bias Dis Peer_Speed 1 1 3 Rd Rd/Wr Rd Debounced incoming cable bias status. A 1 indicates that the selected port is detecting incoming cable bias. The incoming cable bias must be stable for the debounce time of 52 s for the Bias bit to be set to 1. Port disabled control. If 1, the selected port is disabled. The Dis bit is reset to 0 by hardware reset (all ports are enabled for normal operation following hardware reset). The Dis bit is not affected by bus reset. Port peer speed. This field indicates the highest speed capability of the peer PHY connected to the selected port, encoded as follows: Peer Speed Code 000 S100 001 S200 010 S400 011-111 invalid The Peer_Speed field is invalid after a bus reset until self-ID has completed. NOTE: Peer speed codes higher than 010b (S400) are defined in P1394a. However, the TSB41LV03 is only capable of detecting peer speeds up to S400. PIE Fault 1 1 Rd/Wr Rd/Wr Port event interrupt enable. When set to 1, a port event on the selected port will set the port event interrupt (PEI) bit and notify the link. This bit is reset to 0 by a hardware reset, and is unaffected by bus-reset. Fault. This bit indicates that a resume-fault or suspend-fault has occurred on the selected port, and that the port is in the suspended state. A resume-fault occurs when a resuming port fails to detect incoming cable bias from its attached peer. A suspend-fault occurs when a suspending port continues to detect incoming cable bias from its attached peer. Writing 1 to this bit clears the fault bit to 0. This bit is reset to 0 by hardware reset and is unaffected by bus reset.
BStat Ch
2 1
Rd Rd
Con
1
Rd
16
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
TSB41LV03 IEEE 1394a THREE PORT CABLE TRANSCEIVER/ARBITER
SLLS317- SEPTEMBER 1998
APPLICATION INFORMATION
The Vendor Identification page is used to identify the vendor/manufacturer and compliance level. The page is selected by writing 1 to the Page_Select field in base register 7. The configuration of the Vendor Identification page is shown in Table 5, and corresponding field descriptions given in Table 6. Table 5. Page 1 (Vendor ID) Register Configuration
BIT POSITION Address 1000 1001 1010 1011 1100 1101 1110 1111 0 1 2 3 Compliance Reserved Vendor_ID[0] Vendor_ID[1] Vendor_ID[2] Product_ID[0] Product_ID[1] Product_ID[2] 4 5 6 7
Table 6. Page 1 (Vendor ID) Register Field Descriptions
FIELD Compliance Vendor_ID Product_ID SIZE 8 24 24 TYPE Rd Rd Rd DESCRIPTION Compliance level. For the TSB41LV03 this field is 01h, indicating compliance with the P1394a specification. Manufacturer's organizationally unique identifier (OUI). For the TSB41LV03 this field is 08_00_28h (Texas Instruments) (the MSB is at register address 1010b). Product identifier. For the TSB41LV03 this field is 46_xx_xxh (the MSB is at register address 1101b).
The Vendor-Dependent page provides access to the special control features of the TSB41LV03, as well as configuration and status information used in manufacturing test and debug. This page is selected by writing 7 to the Page_Select field in base register 7. The configuration of the Vendor-Dependent page is shown in Table 7 and corresponding field descriptions given in Table 8. Table 7. Page 7 (Vendor-Dependent) Register Configuration
BIT POSITION Address 1000 1001 1010 1011 1100 1101 1110 1111 0 NPA 1 2 3 Reserved Reserved for test Reserved for test Reserved for test Reserved for test Reserved for test Reserved for test Reserved for test 4 5 6 Link_Speed 7
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
17
TSB41LV03 IEEE 1394a THREE PORT CABLE TRANSCEIVER/ARBITER
SLLS317- SEPTEMBER 1998
APPLICATION INFORMATION
Table 8. Page 7 (Vendor-Dependent) Register Field Descriptions
FIELD NPA SIZE 1 TYPE Rd/Wr DESCRIPTION Null-packet actions flag. This bit instructs the PHY to not clear fair and priority requests when a null packet is received with arbitration acceleration enabled. If 1, then fair and priority requests are cleared only when a packet of more than 8 bits is received; ACK packets (exactly 8 data bits), null packets (no data bits), and mal-formed packets (less than 8 data bits) will not clear fair and priority requests. If 0, then fair and priority requests are cleared when any non-ACK packet is received, including null-packets or mal-formed packets of less than 8 bits. This bit is cleared to 0 by hardware reset and is unaffected by bus-reset. Link speed. This field indicates the top speed capability of the attached LLC. Encoding is as follows: Code Speed 00 S100 01 S200 10 S400 11 illegal This field is replicated in the "sp" field of the self-ID packet to indicate the speed capability of the node (PHY and LLC in combination). However, this field does not affect the PHY speed capability indicated to peer PHYs during self-ID; the TSB41LV03 PHY identifies itself as S400 capable to its peers regardless of the value in this field. This field is set to 10b (S400) by hardware reset and is unaffected by bus-reset.
Link_Speed
2
Rd/Wr
power-class programming
The PC0-PC2 terminals are programmed to set the default value of the power-class indicated in the pwr field (bits 21-23) of the transmitted self-ID packet. Descriptions of the various power-classes are given in Table 9 The default power-class value is loaded following a hardware reset, but is overriden by any value subsequently loaded into the Pwr_Class field in register 4. Table 9. Power Class Descriptions
PC0-PC2 000 001 010 011 100 101 110 111 DESCRIPTION Node does not need power and does not repeat power. Node is self-powered and provides a minimum of 15 W to the bus. Node is self-powered and provides a minimum of 30 W to the bus. Node is self-powered and provides a minimum of 45 W to the bus. Node may be powered from the bus and is using up to 3 W. Node is powered from the bus and uses up to 3 W. No additional power is needed to enable the link. Node is powered from the bus and uses up to 3 W. An additional 3 W is needed to enable the link. Node is powered from the bus and uses up to 3 W. An additional 7 W is needed to enable the link.
18
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
TSB41LV03 IEEE 1394a THREE PORT CABLE TRANSCEIVER/ARBITER
SLLS317- SEPTEMBER 1998
APPLICATION INFORMATION
TSB41LV03 CPS
400 k Cable Power Pair
1 F TPBIAS 56 TPA+ TPA- 56
Cable Pair A
Cable Port TPB+ TPB- 56 56 Cable Pair B
220 pF
5 k
Outer Shield Termination
NOTE A: The IEEE Std 1394-1995 calls for a 250-pF capacitor, which is a non-standard component value. A 220-pF capacitor is recommended.
Figure 4. TP Cable Connections
Outer Cable Shield
1 M
0.01 F
0.001 F
Chassis Ground
Figure 5. Typical Compliant DC Isolated Outer Shield Termination
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
19
TSB41LV03 IEEE 1394a THREE PORT CABLE TRANSCEIVER/ARBITER
SLLS317- SEPTEMBER 1998
APPLICATION INFORMATION
Outer Cable Shield
Chassis Ground
Figure 6. Non-DC Isolated Outer Shield Termination
1 k Link Power LPS
Square Wave Input 1 k
LPS
Figure 7. Non-Isolated Connection Variations for LPS
20
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
TSB41LV03 IEEE 1394a THREE PORT CABLE TRANSCEIVER/ARBITER
SLLS317- SEPTEMBER 1998
APPLICATION INFORMATION
V DD 0.1 F V DD 0.1 F V DD 0.001 F 6.34 k 0.5% 0.001 F 0.001 F 0.1 F 0.001 F 1 M 5%
12 pF
12 pF 0.1 F
VDD 0.1 F 0.001 F 0.1 F
24.576 MHz
0.001 F
0.001 F
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 RESET XO DGND FILTER0 DGND PLLGND PLLGND PLLV DD DVDD DVDD R1 DVDD R0 AGND AVDD AVDD FILTER1 AGND AGND XI
0.1 F
1 2 3
0.001 F
LREQ SYSCLK DGND CTL0 CTL1
AGND TPBIAS2 TPA2+ TPA2- TPB2+
60 59 58 57 56
1 F TPBIAS TP Cables Interface Connection
4 5 6
0.1 F
VDD Link VDD
CNA Out Power Down Link Pulse or VDD
C/LKON
TESTM
DGND
DGND
AGND
AGND
AGND
AGND
DVDD 7 D0 8 D1 9 V DD-5V 10 D2 11 D3 12 D4 13 D5 14 D6 15 D7 16 DGND 17 CNA 18 PD 19 LPS 20 DGND
TSB41LV03
55 TPB2- 54 AV DD 53 TPBIAS1 52 TPA1+ 51 TPA1- 50 TPB1+ 49 TPB1- 48 AV DD 47 AV DD 46 TPBIAS0 45 TPA0+ 44 TPA0- 43 TPB0+ 42 TPB0- 41 AGND AGND AVDD AVDD SM SE
V DD TPBIAS 1 F TP Cables Interface Connection V DD TPBIAS 1 F TP Cables Interface Connection
0.1 F
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
ISO 400 k 0.001 F
CPS
DVDD DVDD
0.001 F
PC0
PC1
PC2
ISO
0.001 F
Power-Class Programming
0.001 F
10 k Bus Manager
Cable Power
0.001 F
0.001 F
LKON
V DD
0.01 F
0.1 F
Figure 8. External Component Connections
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
V DD
0.1 F
21
TSB41LV03 IEEE 1394a THREE PORT CABLE TRANSCEIVER/ARBITER
SLLS317- SEPTEMBER 1998
APPLICATION INFORMATION designing with PowerPADTM
The TSB41LV03 is housed in a high performance, thermally enhanced, 80-pin PFP PowerPAD package. Use of the PowerPAD package does not require any special considerations except to note that the PowerPAD, which is an exposed die pad on the bottom of the device, is a metallic thermal and electrical conductor. Therefore, if not implementing PowerPAD PCB features, the use of solder masks (or other assembly techniques) may be required to prevent any inadvertent shorting by the exposed PowerPAD of connection etches or vias under the package. The recommended option, however, is to not run any etches or signal vias under the device, but to have only a grounded thermal land as explained below. Although the actual size of the exposed die pad may vary, the minimum size required for the keepout area for the 80-pin PFP PowerPAD package is 10 mm x 10 mm. It is recommended that there be a thermal land, which is an area of solder-tinned-copper, underneath the PowerPAD package. The thermal land will vary in size, depending on the PowerPAD package being used, the PCB construction, and the amount of heat that needs to be removed. In addition, the thermal land may or may not contain numerous thermal vias depending on PCB construction. Other requirements for thermal lands and thermal vias are detailed in the TI application note PowerPAD Thermally Enhanced Package Application Report, TI literature number SLMA002, available via the TI Web pages beginning at URL: http://www.ti.com.
Figure 9. Example of a Thermal Land for the TSB41LV03 PHY For the TSB41LV03, this thermal land should be grounded to the low impedance ground plane of the device. This improves not only thermal performance but also the electrical grounding of the device. It is also recommended that the device ground terminal landing pads be connected directly to the grounded thermal land. The land size should be as large as possible without shorting device signal terminals. The thermal land may be soldered to the exposed PowerPAD using standard reflow soldering techniques. While the thermal land may be electrically floated and configured to remove heat to an external heat sink, it is recommended that the thermal land be connected to the low impedance ground plane for the device. More information may be obtained from the TI application note PHY Layout, TI literature number SLLA020.
using the TSB41LV03 with a non-P1394a link layer
The TSB41LV03 implements the PHY-LLC interface specified in the P1394a Supplement. This interface is based upon the interface described in informative Annex J of IEEE Std 1394-1995, which is the interface used in older TI PHY devices. The PHY-LLC interface specified in P1394a is completely compatible with the older Annex J interface.
PowerPAD is a trademark of Texas Instruments Incorporated.
22
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
TSB41LV03 IEEE 1394a THREE PORT CABLE TRANSCEIVER/ARBITER
SLLS317- SEPTEMBER 1998
using the TSB41LV03 with a non-P1394a link layer (continued)
The P1394a Supplement includes enhancements to the Annex J interface that must be comprehended when using the TSB41LV03 with a non-P1394a LLC device.
D D D
A new LLC service request was added which allows the LLC to temporarily enable and disable asynchronous arbitration accelerations. If the LLC does not implement this new service request, the arbitration enhancements should not be enabled (see the EAA bit in PHY register 5). The capability to perform multispeed concatenation (the concatenation of packets of differing speeds) was added in order to improve bus efficiency (primarily during isochronous transmission). If the LLC does not support multispeed concatenation, multispeed concatenation should not be enabled in the PHY (see the EMC bit in PHY register 5). In order to accommodate the higher transmission speeds expected in future revisions of the standard, P1394A extended the speed code in bus requests from 2 bits to 3 bits, increasing the length of the bus request from 7 bits to 8 bits. The new speed codes were carefully selected so that new P1394a PHY and LLC devices would be compatible, for speeds from S100 to S400, with legacy PHY and LLC devices that use the 2-bit speed codes. The TSB41LV03 correctly interprets both 7-bit bus requests (with 2-bit speed code) and 8-bit bus requests (with 3-bit speed codes). Moreover, if a 7-bit bus request is immediately followed by another request (e.g., a register read or write request), the TSB41LV03 correctly interprets both requests. Although the TSB41LV03 correctly interprets 8-bit bus requests, a request with a speed code exceeding S400 results in the TSB41LV03 transmitting a null packet (data-prefix followed by data-end, with no data in the packet).
More explanation is included in the TI application note IEEE 1394a Features Supported by TI TSB41LV0X Physical Layer Devices, TI literature number SLL019.
using the TSB41LV03 with a lower-speed link layer
Although the TSB41LV03 is an S400 capable PHY, it may be used with lower speed LLCs, such as the S200 capable TSB12LV31. In such a case, the LLC has fewer data terminals than the PHY, and some Dn terminals on the TSB41LV03 will be unused. Unused Dn terminals should be pulled to ground through 10-k resistors. The TSB41LV03 transfers all received packet data to the LLC, even if the speed of the packet exceeds the capability of the LLC to accept it. Some lower speed LLC designs do not properly ignore packet data in such cases. On the rare occasions that the first 16 bits of partial data accepted by such a LLC match a node's bus and node ID, spurious header CRC or tcode errors may result. During bus initialization following a bus-reset, each PHY transmits a self-ID packet that indicates, among other information, the speed capability of the PHY. The bus manager (if one exists) builds a speed-map from the collected self-ID packets. This speed-map gives the highest possible speed that can be used on the node-to-node communication path between every pair of nodes in the network. In the case of a node consisting of a higher-speed PHY and a lower-speed LLC, the speed capability of the node (PHY and LLC in combination) is that of the lower-speed LLC. A sophisticated bus manager may be able to determine the LLC speed capability by reading the configuration ROM Bus_Info_Block, or by sending asynchronous request packets at different speeds to the node and checking for an acknowledge; the speed-map may then be adjusted accordingly. The speed-map should reflect that communication to such a node must be done at the lower speed of the LLC, instead of the higher speed of the PHY. However, speed-map entries for paths that merely pass through the node's PHY, but do not terminate at that node, should not be restricted by the lower speed of the LLC.
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
23
TSB41LV03 IEEE 1394a THREE PORT CABLE TRANSCEIVER/ARBITER
SLLS317- SEPTEMBER 1998
APPLICATION INFORMATION using the TSB41LV03 with a lower-speed link layer (continued)
To assist in building an accurate speed-map, the TSB41LV03 has the capability of indicating a speed other than S400 in its transmitted self-ID packet. This is controlled by the Link_Speed field in register 8 of the Vendor-Dependent page (page 7). Setting the Link_Speed field affects only the speed indicated in the self-ID packet; it has no effect on the speed signaled to peer PHYs during self-ID. The TSB41LV03 identifies itself as S400 capable to its peers regardless of the value in the Link_Speed field. Generally, the Link_Speed field should not be changed from its power-on default value of S400 unless it is determined that the speed-map (if one exists) is incorrect for path entries terminating in the local node. If the speed-map is incorrect, it can be assumed that the bus manager has used only the self-ID packet information to build the speed-map. In this case, the node may update the Link_Speed field to reflect the lower speed capability of the LLC and then initiate another bus-reset to cause the speed-map to be rebuilt. Note that in this scenario any speed-map entries for node-to-node communication paths that pass through the local node's PHY will be restricted by the lower speed. In the case of a leaf node (which has only one active port) the Link_Speed field may be set to indicate the speed of the LLC without first checking the speed-map. Changing the Link_Speed field in a leaf node can only affect those paths that terminate at that node, since no other paths can pass through a leaf node. It can have no effect on other paths in the speed-map. For hardware configurations which can only be a leaf node (all ports but one are unimplemented), it is recommended that the Link_Speed field be updated immediately after power-on or hardware reset. power-up reset To ensure proper operation of the TSB41LV03 the RESET terminal must be asserted low for a minimum of 2 ms from the time that PHY power reaches the minimum required supply voltage. When using a passive capacitor on the RESET terminal to generate a power-on reset signal, the minimum reset time will be assured if the value of the capacitor has a minimum value of 0.1 F and also satisfies the following equation: Cmin = 0.0077 x T + 0.085 where Cmin is the minimum capacitance on the RESET terminal in F, and T is the VDD ramp time, 10%-90%, in ms. Additionally, an approximately 120 k resistor should be connected in parallel with the reset capacitor from the RESET terminal to GND to ensure that the capacitor is discharged when PHY power is removed. An alternative to the passive reset is to actively drive RESET low for the minimum reset time following power on.
24
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
TSB41LV03 IEEE 1394a THREE PORT CABLE TRANSCEIVER/ARBITER
SLLS317- SEPTEMBER 1998
PRINCIPLES OF OPERATION
The TSB41LV03 is designed to operate with an LLC such as the Texas Instruments TSB12LV21, TSB12LV31, TSB12LV41, TSB12LV01, or TSB12LV22. Details of operation for the Texas Instruments LLC devices are found in the respective LLC data sheets. The following paragraphs describe the operation of the PHY-LLC interface. The interface to the LLC consists of the SYSCLK, CTL0-CTL1, D0-D7, LREQ, LPS, C/LKON, and ISO terminals on the TSB41LV03, as shown in Figure 10.
TSB41LV03
SYSCLK CTL0-CTL1 LINK LAYER CONTROLLER D0-D7 LREQ LPS C/LKON ISO ISO ISO
Figure 10. PHY-LLC Interface The SYSCLK terminal provides a 49.152-MHz interface clock. All control and data signals are synchronized to, and sampled on, the rising edge of SYSCLK. The CTL0 and CTL1 terminals form a bidirectional control bus, which controls the flow of information and data between the TSB41LV03 and LLC. The D0-D7 terminals form a bidirectional data bus, which is used to transfer status information, control information, or packet data between the devices. The TSB41LV03 supports S100, S200, and S400 data transfers over the D0-D7 data bus. In S100 operation only the D0 and D1 terminals are used; in S200 operation only the D0-D3 terminals are used; and in S400 operation all D0-D7 terminals are used for data transfer. When the TSB41LV03 is in control of the D0-D7 bus, unused Dn terminals are driven low during S100 and S200 operations. When the LLC is in control of the D0-D7 bus, unused Dn terminals are ignored by the TSB41LV03. The LREQ terminal is controlled by the LLC to send serial service requests to the PHY in order to request access to the serial-bus for packet transmission, read or write PHY registers, or control arbitration acceleration. The LPS and C/LKON terminals are used for power management of the PHY and LLC. The LPS terminal indicates the power status of the LLC, and may be used to reset the PHY-LLC interface or to disable SYSCLK. The C/LKON terminal is used to send a wake-up notification to the LLC and to indicate an interrupt to the LLC when either LPS is inactive or the PHY register L bit is zero. The ISO terminal is used to enable the output differentiation logic on the CTL0-CTL1 and D0-D7 terminals. Output differentiation is required when an isolation barrier of the type described in Annex J of IEEE Std 1394-1995 is implemented between the PHY and LLC. The TSB41LV03 normally controls the CTL0-CTL1 and D0-D7 bidirectional buses. The LLC is allowed to drive these buses only after the LLC has been granted permission to do so by the PHY.
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
25
TSB41LV03 IEEE 1394a THREE PORT CABLE TRANSCEIVER/ARBITER
SLLS317- SEPTEMBER 1998
PRINCIPLES OF OPERATION
There are four operations that may occur on the PHY-LLC interface: link service request, status transfer, data transmit, and data receive. The LLC issues a service request to read or write a PHY register, to request the PHY to gain control of the serial-bus in order to transmit a packet, or to control arbitration acceleration. The PHY may initiate a status transfer either autonomously or in response to a register read request from the LLC. The PHY initiates a receive operation whenever a packet is received from the serial-bus. The PHY initiates a transmit operation after winning control of the serial-bus following a bus-request by the LLC. The transmit operation is initiated when the PHY grants control of the interface to the LLC. The encoding of the CTL0-CTL1 bus is shown in Table 10 and Table 11. Table 10. CTL Encoding When PHY Has Control of the Bus
CTL0 0 0 1 1 CTL1 0 1 0 1 NAME Idle Status Receive Grant DESCRIPTION No activity (this is the default mode) Status information is being sent from the PHY to the LLC An incoming packet is being sent from the PHY to the LLC The LLC has been given control of the bus to send an outgoing packet
Table 11. CTL Encoding When LLC Has Control of the Bus
CTL0 0 0 CTL1 0 1 NAME Idle Hold DESCRIPTION The LLC releases the bus (transmission has been completed) The LLC is holding the bus while data is being prepared for transmission, or indicating that another packet is to be transmitted (concatenated) without arbitrating An outgoing packet is being sent from the LLC to the PHY None
1 1
0 1
Transmit Reserved
LLC service request
To request access to the bus, to read or write a PHY register, or to control arbitration acceleration, the LLC sends a serial bit stream on the LREQ terminal as shown in Figure 11.
LR0
LR1
LR2
LR3
LR (n-2)
LR (n-1)
Each cell represents one clock sample time, and n is the number of bits in the request stream.
Figure 11. LREQ Request Stream
26
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
TSB41LV03 IEEE 1394a THREE PORT CABLE TRANSCEIVER/ARBITER
SLLS317- SEPTEMBER 1998
PRINCIPLES OF OPERATION LLC service request (continued)
The length of the stream will vary depending on the type of request as shown in Table 12. Table 12. Request Stream BIt Length
REQUEST TYPE Bus Request Read Register Request Write Register Request Acceleration Control Request NUMBER OF BITS 7 or 8 9 17 6
Regardless of the type of request, a start-bit of 1 is required at the beginning of the stream, and a stop-bit of 0 is required at the end of the stream. The second through fourth bits of the request stream indicate the type of the request. In the descriptions below, bit 0 is the most significant and is transmitted first in the request bit stream. The LREQ terminal is normally low. Encoding for the request type is shown in Table 13. Table 13. Request Type Encoding
LR1-LR3 000 001 010 011 100 101 110 111 NAME ImmReq IsoReq PriReq FairReq RdReg WrReg AccelCtl Reserved DESCRIPTION Immediate bus request. Upon detection of idle, the PHY takes control of the bus immediately without arbitration. Isochronous bus request. Upon detection of idle, the PHY arbitrates for the bus without waiting for a subaction gap. Priority bus request. The PHY arbitrates for the bus after a subaction gap, ignores the fair protocol. Fair bus request. The PHY arbitrates for the bus after a subaction gap, follows the fair protocol. The PHY returns the specified register contents through a status transfer. Write to the specified register. Enable or disable asynchronous arbitration acceleration. Reserved.
For a bus request the length of the LREQ bit stream is 7 or 8 bits as shown in Table 14. Table 14. Bus Request
BIT(s) 0 1-3 4-6 7 NAME Start Bit Request Type Request Speed Stop Bit DESCRIPTION Indicates the beginning of the transfer (always 1). Indicates the type of bus request. See Table 13. Indicates the speed at which the PHY will send the data for this request. See Table 15 for the encoding of this field. Indicates the end of the transfer (always 0). If bit 6 is 0, this bit may be omitted.
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
27
TSB41LV03 IEEE 1394a THREE PORT CABLE TRANSCEIVER/ARBITER
SLLS317- SEPTEMBER 1998
PRINCIPLES OF OPERATION LLC service request (continued)
The 3-bit request speed field used in bus requests is shown in Table 15. Table 15. Bus Request Speed Encoding
LR4-LR5 000 010 100 All Others DATA RATE S100 S200 S400 Invalid
NOTE: The TSB41LV03 will accept a bus request with an invalid speed code and process the bus request normally. However, during packet transmission for such a request, the TSB41LV03 will ignore any data presented by the LLC and will transmit a null packet.
For a read register request the length of the LREQ bit stream is 9 bits as shown in Table 16. Table 16. Read Register Request
BIT(s) 0 1-3 4-7 8 NAME Start Bit Request Type Address Stop Bit A 100 indicating this is a read register request. Identifies the address of the PHY register to be read. Indicates the end of the transfer (always 0). DESCRIPTION Indicates the beginning of the transfer (always 1).
For a write register request the length of the LREQ bit stream is 17 bits as shown in Table 17. Table 17. Write Register Request
BIT(s) 0 1-3 4-7 8-15 16 NAME Start Bit Request Type Address Data Stop Bit A 100 indicating this is a write register request. Identifies the address of the PHY register to be written to. Gives the data that is to be written to the specified register address. Indicates the end of the transfer (always 0). DESCRIPTION Indicates the beginning of the transfer (always 1).
For an acceleration control request the Length of the LREQ data stream is 6 bits as shown in Table 18. Table 18. Acceleration Control Request
BIT(s) 0 1-3 4 5 NAME Start Bit Request Type Control Stop BIt DESCRIPTION Indicates the beginning of the transfer (always 1). A 110 indicating this is an acceleration control request. Asynchronous period arbitration acceleration is enabled if 1, and disabled if 0. Indicates the end of the transfer (always 0).
28
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
TSB41LV03 IEEE 1394a THREE PORT CABLE TRANSCEIVER/ARBITER
SLLS317- SEPTEMBER 1998
PRINCIPLES OF OPERATION LLC service request (continued)
For fair or priority access, the LLC sends the bus request (FairReq or PriReq) at least one clock after the PHY-LLC interface becomes idle. If the CTL terminals are asserted to the receive state (10b) by the PHY, then any pending fair or priority request is lost (cleared). Additionally, the PHY ignores any fair or priority requests if the Receive state is asserted while the LLC is sending the request. The LLC may then reissue the request one clock after the next interface idle. The cycle master node uses a priority bus request (PriReq) to send a cycle start message. After receiving or transmitting a cycle start message, the LLC can issue an isochronous bus request (IsoReq). The PHY will clear an isochronous request only when the serial bus has been won. To send an acknowledge packet, the LLC must issue an immediate bus request (ImmReq) during the reception of the packet addressed to it. This is required in order to minimize the idle gap between the end of the received packet and the start of the transmitted acknowledge packet. As soon as the receive packet ends, the PHY immediately grants control of the bus to the LLC. The LLC sends an acknowledgment to the sender unless the header CRC of the received packet is corrupted. In this case, the LLC does not transmit an acknowledge, but instead cancels the transmit operation and releases the interface immediately; the LLC must not use this grant to send another type of packet. After the interface is released the LLC may proceed with another request. The LLC may make only one bus request at a time. Once the LLC issues any request for bus access (ImmReq, IsoReq, FairReq, or PriReq), it cannot issue another bus request until the PHY indicates that the bus request was lost (bus arbitration lost and another packet received), or won (bus arbitration won and the LLC granted control). The PHY ignores new bus requests while a previous bus request is pending. All bus requests are cleared upon a bus reset. For write register requests, the PHY loads the specified data into the addressed register as soon as the request transfer is complete. For read register requests, the PHY returns the contents of the addressed register to the LLC at the next opportunity through a status transfer. If a received packet interrupts the status transfer, then the PHY continues to attempt the transfer of the requested register until it is successful. A write or read register request may be made at any time, including while a bus request is pending. Once a read register request is made, the PHY ignores further read register requests until the register contents are successfully transferred to the LLC. A bus reset does not clear a pending read register request. The TSB41LV03 includes several arbitration acceleration enhancements, which allow the PHY to improve bus performance and throughput by reducing the number and length of inter-packet gaps. These enhancements include autonomous (fly-by) isochronous packet concatenation, autonomous fair and priority packet concatenation onto acknowledge packets, and accelerated fair and priority request arbitration following acknowledge packets. The enhancements are enabled when the EAA bit in PHY register 5 is set. The arbitration acceleration enhancements may interfere with the ability of the cycle master node to transmit the cycle start message under certain circumstances. The acceleration control request is therefore provided to allow the LLC to temporarily enable or disable the arbitration acceleration enhancements of the TSB41LV03 during the asynchronous period. The LLC typically disables the enhancements when its internal cycle counter rolls over indicating that a cycle start message is imminent, and then re-enables the enhancements when it receives a cycle start message. The acceleration control request may be made at any time, however, and is immediately serviced by the PHY. Additionally, a bus reset or isochronous bus request will cause the enhancements to be re-enabled, if the EAA bit is set.
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
29
TSB41LV03 IEEE 1394a THREE PORT CABLE TRANSCEIVER/ARBITER
SLLS317- SEPTEMBER 1998
PRINCIPLES OF OPERATION status transfer
A status transfer is initiated by the PHY when there is status information to be transferred to the LLC. The PHY waits until the interface is idle before starting the transfer. The transfer is initiated by the PHY asserting Status (01b) on the CTL terminals, along with the first two bits of status information on the D[0:1] terminals. The PHY maintains CTL = Status for the duration of the status transfer. The PHY may prematurely end a status transfer by asserting something other than Status on the CTL terminals. This occurs if a packet is received before the status transfer completes. The PHY continues to attempt to complete the transfer until all status information has been successfully transmitted. There is at least one idle cycle between consecutive status transfers. The PHY normally sends just the first four bits of status to the LLC. These bits are status flags that are needed by the LLC state machines. The PHY sends an entire 16-bit status packet to the LLC after a read register request, or when the PHY has pertinent information to send to the LLC or transaction layers. The only defined condition where the PHY automatically sends a register to the LLC is after self-ID, where the PHY sends the physical-ID register that contains the new node address. All status transfers are either 4 or 16 bits unless interrupted by a received packet. The status flags are considered to have been successfully transmitted to the LLC immediately upon being sent, even if a received packet subsequently interrupts the status transfer. Register contents are considered to have been successfully transmitted only when all 8 bits of the register have been sent. A status transfer is retried after being interrupted only if any status flags remain to be sent, or if a register transfer has not yet completed. The definition of the bits in the status transfer is shown in Table 19 and the timing is shown in Figure 12. Table 19. Status Bits
BIT(s) 0 1 2 3 4-7 8-15 NAME Arbitration Reset Gap Subaction Gap Bus Reset Interrupt Address Data DESCRIPTION Indicates that the PHY has detected that the bus has been idle for an arbitration reset gap time (as defined in the IEEE 1394-1995 standard). This bit is used by the LLC in the busy/retry state machine. Indicates that the PHY has detected that the bus has been idle for a subaction gap time (as defined in the IEEE 1394-1995 standard). This bit is used by the LLC to detect the completion of an isochronous cycle. Indicates that the PHY has entered the bus reset state. Indicates that a PHY interrupt event has occurred. An interrupt event may be a configuration time-out, a cable-power voltage falling too low, a state time-out, or a port status change. This field holds the address of the PHY register whose contents are being transferred to the LLC. This field holds the register contents. SYSCLK (a) (b)
CTL0, CTL1
00
01
00 11
D0, D1
00
S[0:1]
S[14:15]
00
Figure 12. Status Transfer Timing
30
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
TSB41LV03 IEEE 1394a THREE PORT CABLE TRANSCEIVER/ARBITER
SLLS317- SEPTEMBER 1998
PRINCIPLES OF OPERATION status transfer (continued)
The sequence of events for a status transfer is as follows:
D
Status transfer initiated. The PHY indicates a status transfer by asserting status on the CTL lines along with the status data on the D0 and D1 lines (only 2 bits of status are transferred per cycle). Normally (unless interrupted by a receive operation), a status transfer will be either 2 or 8 cycles long. A 2-cycle (4 bit) transfer occurs when only status information is to be sent. An 8-cycle (16 bit) transfer occurs when register data is to be sent in addition to any status information. Status transfer terminated. The PHY normally terminates a status transfer by asserting Idle on the CTL lines. If a bus reset is pending, the PHY may also assert Grant on the CTL line immediately following a complete status transfer. The PHY may also interrupt a status transfer at any cycle by asserting Receive on the CTL lines to begin a receive operation. The PHY shall assert at least one cycle of Idle between consecutive status transfers. The PHY may also assert Grant on the CTL lines immediately following a complete status transfer.
D
receive Whenever the PHY detects the data-prefix state on the serial bus, it initiates a receive operation by asserting Receive on the CTL terminals and a logic 1 on each of the D terminals (data-on indication). The PHY indicates the start of a packet by placing the speed code (encoded as shown in Table 20) on the D terminals, followed by packet data. The PHY holds the CTL terminals in the receive state until the last symbol of the packet has been transferred. The PHY indicates the end of packet data by asserting Idle on the CTL terminals. All received packets are transferred to the LLC. Note that the speed code is part of the PHY-LLC protocol and is not included in the calculation of CRC or any other data protection mechanisms. It is possible for the PHY to receive a null packet, which consists of the data-prefix state on the serial bus followed by the data-end state, without any packet data. A null packet is transmitted whenever the packet speed exceeds the capability of the receiving PHY, or whenever the LLC immediately releases the bus without transmitting any data. In this case, the PHY will assert receive on the CTL terminals with the data-on indication (all 1s) on the D terminals, followed by Idle on the CTL terminals, without any speed code or data being transferred. In all cases, in normal operation, the TSB41LV03 sends at least one data-on indication before sending the speed code or terminating the receive operation. The TSB41LV03 also transfers its own self-ID packet, transmitted during the self-ID phase of bus initialization, to the LLC. This packet it transferred to the LLC just as any other received self-ID packet.
SYSCLK (a) CTL0, CTL1 00 01 (b) (c) D0-D7 XX FF ("data-on") SPD (d) d0 dn 00 10 00 (e)
NOTE B: SPD = Speed code, see Table 20 d0-dn = Packet data
Figure 13. Normal Packet Reception Timing
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
31
TSB41LV03 IEEE 1394a THREE PORT CABLE TRANSCEIVER/ARBITER
SLLS317- SEPTEMBER 1998
PRINCIPLES OF OPERATION
receive (continued) The sequence of events for a normal packet reception is as follows:
D D D D D
Receive operation initiated. The PHY indicates a receive operation by asserting Receive on the CTL lines. Normally, the interface is idle when receive is asserted. However, the receive operation may interrupt a status transfer operation that is in progress so that the CTL lines may change from status to receive without an intervening Idle. Data-on indication. The PHY may assert the data-on indication code on the D lines for one or more cycles preceding the speed-code. Speed-code. The PHY indicates the speed of the received packet by asserting a speed-code on the D lines for one cycle immediately preceding packet data. The link decodes the speed-code on the first Receive cycle for which the D lines are not the data-on code. If the speed-code is invalid, or indicates a speed higher that that which the link is capable of handling, the link should ignore the subsequent data. Receive data. Following the data-on indication (if any) and the speed-code, the PHY asserts packet data on the D lines with receive on the CTL lines for the remainder of the receive operation. Receive operation terminated. The PHY terminates the receive operation by asserting Idle on the CTL lines. The PHY asserts at least one cycle of Idle following a receive operation.
SYSCLK (a) CTL0, CTL1 00 01 10 (b) 00 (c)
D0-D7
XX
FF ("data-on")
00
Figure 14. Null Packet Reception Timing The sequence of events for a null packet reception is as follows:
D D D
Receive operation initiated. The PHY indicates a receive operation by asserting receive on the CTL lines. Normally, the interface is idle when receive is asserted. However, the receive operation may interrupt a status transfer operation that is in progress so that the CTL lines may change from status to receive without an intervening Idle. Data-on indication. The PHY asserts the data-on indication code on the D lines for one or more cycles. Receive operation terminated. The PHY terminates the receive operation by asserting Idle on the CTL lines. The PHY shall assert at least one cycle of Idle following a receive operation.
32
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
TSB41LV03 IEEE 1394a THREE PORT CABLE TRANSCEIVER/ARBITER
SLLS317- SEPTEMBER 1998
PRINCIPLES OF OPERATION
receive (continued) Table 20. Receive Speed Codes
D0-D7 00XX XXXX 0100 XXXX 0101 0000 1YYY YYYY DATA RATE S100 S200 S400 "data-on" indication
NOTE: X = Output as 0 by PHY, ignored by LLC. Y = Output as 1 by PHY, ignored by LLC.
transmit
When the LLC issues a bus request through the LREQ terminal, the PHY arbitrates to gain control of the bus. If the PHY wins arbitration for the serial bus, the PHY-LLC interface bus is granted to the LLC by asserting the grant state (11b) on the CTL terminals for one SYSCLK cycle, followed by Idle for one clock cycle. The LLC then takes control of the bus by asserting either idle (00b), hold (01b) or transmit (10b) on the CTL terminals. Unless the LLC is immediately releasing the interface, the LLC may assert the idle state for at most one clock before it must assert either hold or transmit on the CTL terminals. The hold state is used by the LLC to retain control of the bus while it prepares data for transmission. The LLC may assert hold for zero or more clock cycles (i.e., the LLC need not assert hold before transmit). The PHY asserts data-prefix on the serial bus during this time. When the LLC is ready to send data, the LLC asserts transmit on the CTL terminals as well as sending the first bits of packet data on the D lines. The transmit state is held on the CTL terminals until the last bits of data have been sent. The LLC then asserts either Hold or Idle on the CTL terminals for one clock cycle, and then asserts idle for one additional cycle before releasing the interface bus and putting the CTL and D terminals in a high-impedance state. The PHY then regains control of the interface bus. The Hold state asserted at the end of packet transmission indicates to the PHY that the LLC requests to send another packet (concatenated packet) without releasing the serial bus. The PHY responds to this concatenation request by waiting the required minimum packet separation time and then asserting Grant as before. This function may be used to send a unified response after sending an acknowledge, or to send consecutive isochronous packets during a single isochronous period. Unless multispeed concatenation is enabled, all packets transmitted during a single bus ownership must be of the same speed (since the speed of the packet is set before the first packet). If multispeed concatenation is enabled (when the EMSC bit of PHY register 5 is set), the LLC must specify the speed code of the next concatenated packet on the D terminals when it asserts hold on the CTL terminals at the end of a packet. The encoding for this speed code is the same as the speed code that precedes received packet data as given in Table 20. After sending the last packet for the current bus ownership, the LLC releases the bus by asserting Idle on the CTL terminals for two clock cycles. The PHY begins asserting Idle on the CTL terminals one clock after sampling Idle from the link. Note that whenever the D and CTL terminals change direction between the PHY and the LLC, there is an extra clock period allowed so that both sides of the interface can operate on registered versions of the interface signals.
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
33
TSB41LV03 IEEE 1394a THREE PORT CABLE TRANSCEIVER/ARBITER
SLLS317- SEPTEMBER 1998
PRINCIPLES OF OPERATION transmit (continued)
SYSCLK (a) (b) (c) (d) 00 01 (f) D0-D7 00 00 d0, d1, . . . dn 00 SPD 00 00 (e) (g)
CTL0, CTL1
00
11
00
00
01
10
00
00
Link controls CTL and D PHY High-Impedance CTL and D outputs
NOTE A: SPD = Speed code, see Table 20 d0-dn = Packet data
Figure 15. Normal Packet Transmission Timing The sequence of events for a normal packet transmission is as follows:
D D D D D
Transmit operation initiated. The PHY asserts grant on the CTL lines followed by idle to hand over control of the interface to the link so that the link may transmit a packet. The PHY releases control of the interface (i.e., it 3-states the CTL and D outputs) following the idle cycle. Optional idle cycle. The link may assert at most one idle cycle preceding assertion of either hold or transmit. This idle cycle is optional; the link is not required to assert Idle preceding either hold or transmit. Optional hold cycles. The link may assert hold for up to 47 cycles preceding assertion of transmit. These hold cycle(s) are optional; the link is not required to assert hold preceding transmit. Transmit data. When data is ready to be transmitted, the link asserts transmit on the CTL lines along with the data on the D lines. Transmit operation terminated. The transmit operation is terminated by the link asserting hold or idle on the CTL lines. The link asserts hold to indicate that the PHY is to retain control of the serial bus in order to transmit a concatenated packet. The link asserts idle to indicate that packet transmission is complete and the PHY may release the serial bus. The link then asserts Idle for one more cycle following this cycle of hold or idle before releasing the interface and returning control to the PHY. Concatenated packet speed-code. If multispeed concatenation is enabled in the PHY, the link shall assert a speed-code on the D lines when it asserts Hold to terminate packet transmission. This speed-code indicates the transmission speed for the concatenated packet that is to follow. The encoding for this concatenated packet speed-code is the same as the encoding for the received packet speed-code (see Table 20). The link may not concatenate an S100 packet onto any higher-speed packet. After regaining control of the interface, the PHY shall assert at least one cycle of idle before any subsequent status transfer, receive operation, or transmit operation.
D
D
34
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
TSB41LV03 IEEE 1394a THREE PORT CABLE TRANSCEIVER/ARBITER
SLLS317- SEPTEMBER 1998
PRINCIPLES OF OPERATION transmit (continued)
SYSCLK (a) (b) (c) (d) (e)
CTL0, CTL1
00
11
00
00
01
00
00
D0-D7
00
00
00
Link controls CTL and D PHY High-Impedance CTL and D outputs
Figure 16. Cancelled/Null Packet Transmission The sequence of events for a cancelled/null packet transmission is as follows:
D D D D
Transmit operation initiated. PHY asserts grant on the CTL lines followed by idle to hand over control of the interface to the link. Optional Idle cycle. The link may assert at most one idle cycle preceding assertion of hold. This idle cycle is optional; the link is not required to assert idle preceding Hold. Optional Hold cycles. The link may assert Hold for up to 47 cycles preceding assertion of idle. These hold cycle(s) are optional; the link is not required to assert hold preceding Idle. Null transmit termination. The null transmit operation is terminated by the link asserting two cycles of idle on the CTL lines and then releasing the interface and returning control to the PHY. Note that the link may assert idle for a total of 3 consecutive cycles if it asserts the optional first idle cycle but does not assert hold. It is recommended that the link assert 3 cycles of Idle to cancel a packet transmission if no hold cycles are asserted. This ensures that either the link or PHY controls the interface in all cycles. After regaining control of the interface, the PHY shall assert at least one cycle of Idle before any subsequent status transfer, receive operation, or transmit operation.
D
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
35
TSB41LV03 IEEE 1394a THREE PORT CABLE TRANSCEIVER/ARBITER
SLLS317- SEPTEMBER 1998
MECHANICAL DATA
PFP (S-PQFP-G80)
0,27 0,17 41
PowerPADTM PLASTIC QUAD FLATPACK
0,50 60
0,08 M
61
40
Thermal Pad (see Note D)
80
21
0,13 NOM
1 9,50 TYP 12,20 SQ 11,80 14,20 SQ 13,80 1,05 0,95
20 Gage Plane 0,25 0,15 0,05 0,75 0,45 Seating Plane 0- 7
1,20 MAX
0,08 4146925/A 01/98
NOTES: B. C. D. E.
All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions include mold flash or protrusions. The package thermal performance may be enhanced by bonding the thermal pad to an external thermal plane. This pad is electrically and thermally connected to the backside of the die and possibly selected leads. F. Falls within JEDEC MS-026
PowerPAD is a trademark of Texas Instruments Incorporated.
36
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof.
Copyright (c) 2000, Texas Instruments Incorporated

▲Up To Search▲

Price & Availability of SLLS317

	To Download SLLS317 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .