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W24L257 32K x 8 CMOS STATIC RAM
GENERAL DESCRIPTION
The W24L257 is a normal-speed, very low-power CMOS static RAM organized as 32768 x 8 bits that operates on a wide voltage range from 3V to 5.5V power supply. This device is manufactured using Winbond's high performance CMOS technology.
FEATURES
* *
Low power consumption: Access time: 70 nS * 3.3V/5V power supply * Fully static operation * All inputs and outputs directly TTL compatible
*
*
Three-state outputs Battery back-up operation capability * Data retention voltage: 2V (min.) * Packaged in 330 mil SOP, and standard type one TSOP (8 mm x 13.4 mm)
PIN CONFIGURATIONS
BLOCK DIAGRAM
CLK GEN. A12 PRECHARGE CKT.
A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O1 I/O2 I/O3 VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
VCC WE A13 A8 A9 A11 OE A10 CS I/O8
A14 A2 A3 A4 A5 A6 A7 A13 I/O1 : I/O8 DATA CNTRL . CLK GEN. I/O CKT. COLUMN DECODER R O W D E C O D E R CORE CELL ARRAY 512 ROWS 32 X 8 COLUMNS
WE
I/O7
A11 A10 A1 A0 A8 A9
CS
I/O6
OE
I/O5 I/O4
PIN DESCRIPTION
OE A11 A9 A8 A13 WE VDD A14 A12 A7 A6 A5 A4 A3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 A10 CS I/O8 I/O7 I/O6 I/O5 I/O4 VSS I/O3 I/O2 I/O1 A0 A1 A2
SYMBOL A0-A14 I/O1-I/O8 CS WE OE VDD VSS NC
DESCRIPTION Address Inputs Data Inputs/Outputs Chip Select Input Write Enable Input Output Enable Input Power Supply Ground No Connection
28-pin TSOP
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Publication Release Date: December 2000 Revision A3
W24L257
TRUTH TABLE
CS H L L L OE X H L X WE X H H L MODE Not Selected Output Disable Read Write I/O1-I/O8 High Z High Z Data Out Data In VDD CURRENT ISB, ISB1 IDD IDD IDD
DC CHARACTERISTICS
Absolute Maximum Ratings
PARAMETER Supply Voltage to VSS Potential Input/Output to VSS Potential Allowable Power Dissipation Storage Temperature Operating Temperature L/LL LE LI RATING 3.3V 5V -0.5 to +4.6 -0.5 to +7.0 -0.5 to VDD +0.5 1.0 -65 to +150 0 to 70 -20 to 85 -40 to 85 UNIT V V W C C
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device.
Operating Characteristics
(VDD = 5V 10%; VDD = 3.3V 5%; VSS = 0V; TA (C) = 0 to 70 for L/LL, -20 to 85 for LE, -40 to 85 for LI)
PARAMETER Input Low Voltage Input High Voltage Input Leakage Current Output Leakage Current
SYM. VIL VIH ILI ILO
TEST CONDITIONS VIN = VSS to VDD VI/O = VSS to VDD, CS = VIH (min.) or OE = VIH (min.) or WE = VIL (max.) IOL = +2.1 mA IOH = -1.0 mA CS = VIL (max.) and I/O = 0 mA, Cycle = min. Duty = 100%
3.3V MIN. MAX. -0.5 +2.0 -1 -1 +0.6 VDD +0.5 +1 +1
5V MIN. MAX. -0.5 -2 -2 +0.8 +2 +2 +2.2 VDD +0.5
UNIT V V A A
Output Low Voltage Output High Voltage Operating Power Supply Current
VOL VOH IDD
2.2 -
0.4 35
2.4 -
0.4 70
V V mA
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W24L257
Operating Characteristics, continued
PARAMETER Standby Power Supply Current
SYM. ISB ISB1
TEST CONDITIONS -
3.3V MIN. MAX. 1 15 30 MIN. -
5V MAX. 3 15 30
UNIT mA A
CS = VIH (min.) or Cycle = min. Duty = 100% CS VDD -0.2V LL/LE/LI L
Note: Typical parameter is measured under ambient temperature TA = 25 C and VDD = 3.3V/5V
CAPACITANCE
(VDD = 5V 10%; VDD = 3V 5%, TA = 25 C, f = 1 MHz)
PARAMETER Input Capacitance Input/Output Capacitance
SYM. CIN CI/O
CONDITIONS VIN = 0V VOUT = 0V
MAX. 6 8
UNIT pF pF
Note: These parameters are sampled but not 100% tested.
AC Characteristics
AC Test Conditions PARAMETER Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Level Output Load AC Test Loads and Waveform
1 TTL OUTPUT 100 pF Including Jig and Scope OUTPUT 5 pF Including Jig and Scope (For TCLZ, TOLZ, TCHZ, TOHZ, TWHZ, TOW ) 3.0 V 0V 5 nS
90% 10% 90% 10%
CONDITIONS 0V to 3.0V 5 nS 1.5V See the drawing below
1 TTL
5 nS
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Publication Release Date: December 2000 Revision A3
W24L257
AC Characteristics, continued
Read Cycle
(VDD = 5V 10%; VDD = 3V 5%; VSS = 0V; TA (C) = 0 to 70 for L/LL, -20 to 85 for LE, -40 to 85 for LI)
PARAMETER
SYMBOL MIN.
3.3V/5V MAX. 70 70 35 30 30 -
UNIT
Read Cycle Time Address Access Time Chip Select Access Time Output Enable to Output Valid Chip Selection to Output in Low Z Output Enable to Output in Low Z Chip Deselection to Output in High Z Output Disable to Output in High Z Output Hold from Address Change
These parameters are sampled but not 100% tested
TRC TAA TACS TAOE TCLZ* TOLZ* TCHZ* TOHZ* TOH
70 10 5 10
nS nS nS nS nS nS nS nS nS
Write Cycle
PARAMETER SYMBOL MIN. Write Cycle Time Chip Selection to End of Write Address Valid to End of Write Address Setup Time Write Pulse Width Write Recovery Time Data Valid to End of Write Data Hold from End of Write Write to Output in High Z Output Disable to Output in High Z Output Active from End of Write These parameters are sampled but not 100% tested TWC TCW TAW TAS TWP TWR TDW TDH TWHZ* TOHZ* TOW 70 55 55 0 40 35 0 5 25 25 3.3V/5V MAX. nS nS nS nS nS nS nS nS nS nS nS UNIT
CS , WE
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W24L257
TIMING WAVEFORMS
Read Cycle 1
(Address Controlled)
TRC Address TOH DOUT T AA TOH
Read Cycle 2
(Chip Select Controlled)
CS1
TACS TCLZ DOUT TCHZ
Read Cycle 3
(Output Enable Controlled)
TRC Address TAA OE TAOE TOLZ CS TOH
TACS DOUT TCLZ
T CHZ
TOHZ
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Publication Release Date: December 2000 Revision A3
W24L257
Timing Waveforms, continued
Write Cycle 1
TWC Address TWR OE
TCW CS
TAW WE TAS TOHZ DOUT TDW DIN TDH (1, 4) TWP
Write Cycle 2
(OE = VIL Fixed)
TWC Address TCW CS TWR
TAW WE TAS TWP TWHZ (1, 4) TOH (2) TOW (3)
D OUT
TDW DIN
TDH
Notes: 1. During this period, I/O pins are in the output state, so input signals of opposite phase to the outputs should not be applied. 2. The data output from DOUT are the same as the data written to DIN during the write cycle. 3. DOUT provides the read data for the next address. 4. Transition is measured 500 mV from steady state with CL = 5 pF. This parameter is guaranteed but not 100% tested.
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W24L257
DATA RETENTION CHARACTERISTICS
(TA (C) = 0 to 70 for L/LL, -20 to 85 for LE, -40 to 85 for LI)
PARAMETER VDD for Data Retention Data Retention Current
SYM. VDR IDDDR
TEST CONDITIONS CS VDD -0.2V CS VDD -0.2V, VDD = 3V LL/LE/LI L
MIN. 2.0 0 TRC*
TYP. -
MAX. 15 30 -
UNIT V A A nS nS
Chip Deselect to Data Retention Time Operation Recovery Time * Read Cycle Time
TCDR TR
See data retention waveform
DATA RETENTION WAVEFORM
VDD
0.9 VDD TCDR
> V DR = 2V
0.9 VDD TR
CS
CS > VDD - 0.2V =
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Publication Release Date: December 2000 Revision A3
W24L257
ORDERING INFORMATION
PART NO. ACCESS TIME (nS) 70 70 70 70 70 70 70 70 OPERATING VOLTAGE OPERATING TEMPERATURE STANDBY CURRENT MAX. (A) 15 15 15 15 15 15 15 15 PACKAGE
(V)
3.3V/5V 3.3V/5V 3.3V/5V 3.3V/5V 3.3V/5V 3.3V/5V 3.3V/5V 3.3V/5V
(C)
0 to 70 0 to 70 -20 to 85 -40 to 85 0 to 70 0 to 70 -20 to 85 -40 to 85
W24L257S70L W24L257S70LL W24L257S70LE W24L257S70LI W24L257Q70L W24L257Q70LL W24L257Q70LE W24L257Q70LI
Notes:
450 mil SOP 450 mil SOP 450 mil SOP 450 mil SOP Small TSOP Small TSOP Small TSOP Small TSOP
1. Winbond reserves the right to make changes to its products without prior notice. 2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications where personal injury might occur as a consequence of product failure.
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W24L257
BONDING PAD DIAGRAM
6 A4 7 A3 5 A5 4 A6 3 2 1 30 29 28 27 26 25 24
A7 A12 A14 VDD VDD WEB A13
A8 A9 A11
AC5394 23
OEB
Y
X
8 A2 9 A1 10 11 12 13 14 15 16 17 18 19 20 21
22 A10
A0 I/O0 I/O1 I/O2 VSS
VSS I/O3 I/O4 I/O5 I/O6 I/O7 CSB
PAD NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
X -232.25 -351.70 -471.15 -590.60 -710.05 -829.50 -992.79 -992.79 -857.86 -738.41 -594.84 -451.06 -310.67 -171.78 24.45 151.80 298.07 443.28 588.20 732.84 871.11 992.75 992.75 810.09 690.64 571.19 451.74 332.29 120.25 -93.23
Y 1445.22 1445.22 1445.22 1445.22 1445.22 1445.22 1362.24 -1306.11 -1452.79 -1452.79 -1414.13 -1414.13 -1414.13 -1405.28 -1405.28 -1414.13 -1414.13 -1414.13 -1414.13 -1414.13 -1452.79 -1312.15 1373.67 1445.22 1445.22 1445.22 1445.22 1445.22 1444.65 1444.65
Note: For bare chip form (C.O.B.) applications, the substrate must be connected to VDD or left floating in the PCB layout.
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Publication Release Date: December 2000 Revision A3
W24L257
PACKAGE DIMENSIONS 28-pin SO Wide Body
Symbol
Dimension in Inches
Dimension in mm
Min. Nom. Max.
0.112 0.004 0.093 0.014 0.008 0.098 0.016 0.010 0.713 0.326 0.044 0.453 0.028 0.059 0.331 0.050 0.465 0.036 0.067 0.103 0.020 0.014 0.733 0.336 0.056 0.477 0.044 0.075 0.047 0.004 0 10
Min. Nom. Max.
2.85 0.10 2.36 0.36 0.20 2.49 0.41 0.25 18.11 8.28 1.12 11.51 0.71 1.50 8.41 1.27 11.81 0.91 1.70 2.62 0.51 0.36 18.62 8.53 1.42 12.12 1.12 1.91 1.19 0.10 0 10
28
15
e1
E
HE
L
Detail F
1 b 14
A A1 A2 b c D E e HE L LE S y Notes:
D
e1 c
A2 A
S
e
y
A1
LE
See Detail F Seating Plane
1. Dimension D Max. & S include mold flash or tie bar burrs. 2. Dimension b does not include dambar protrusion/intrusion. 3. Dimension D & E include mold mismatch . and determined at the mold parting line. 4. Controlling dimension: Inches. 5. General appearance spec should be based on final visual inspection spec.
28-pin Standard Type One TSOP
HD
Symbol
Dimension In Inches Min. Nom. Max.
0.047 0.002 0.035 0.007 0.004 0.461 0.311 0.520 0.040 0.008 0.006 0.465 0.315 0.528 0.022 0.020 0.024 0.010 0.000 0 3 0.004 5 0.028 0.006 0.041 0.011 0.008 0.469 0.319 0.536
Dimension In mm Min. Nom. Max.
1.20 0.05 0.95 0.17 0.10 11.70 7.90 13.20 1.00 0.20 0.15 11.80 8.00 13.40 0.55 0.50 0.60 0.25 0.00 0 3 0.10 5 0.70 0.15 1.05 0.27 0.21 11.90 8.10 13.60
D c
1
e
E
b
A2 A
A A1 A2 b c D E HD e L L1 Y
L L1
A1
Controlling dimension: Millimeters
Y
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W24L257
VERSION HISTORY
VERSION A1 A2 DATE May 2000 Nov. 2000 PAGE 1, 2, 3, 4, 7 1, 9 2, 3, 7, 8 A3 Dec. 2000 2, 4, 5 Initial Issued Add in 5V specification Modify package as 330 mil SOP and standard type one TSOP (8 mm x 13.4 mm) Add in LE, LI specification Modify the 3.3V 10%, to 3.3V 5%, DESCRIPTION
Headquarters
Winbond Electronics (H.K.) Ltd.
Unit 9-15, 22F, Millennium City, No. 4, Creation Rd. III, No. 378 Kwun Tong Rd; Science-Based Industrial Park, Kowloon, Hong Kong Hsinchu, Taiwan TEL: 852-27513100 TEL: 886-3-5770066 FAX: 852-27552064 FAX: 886-3-5796096 http://www.winbond.com.tw/ Voice & Fax-on-demand: 886-2-27197006
Winbond Electronics North America Corp. Winbond Memory Lab. Winbond Microelectronics Corp. Winbond Systems Lab.
2727 N. First Street, San Jose, CA 95134, U.S.A. TEL: 408-9436666 FAX: 408-5441798
Taipei Office
11F, No. 115, Sec. 3, Min-Sheng East Rd., Taipei, Taiwan TEL: 886-2-27190505 FAX: 886-2-27197502
Note: All data and specifications are subject to change withou t notice.
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Publication Release Date: December 2000 Revision A3

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