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W83697HF WINBOND I/O
W83697HF Data Sheet Revision History
Version Pages 1 n.a. Dates 08/23/99 Version 0.40 on Web Main Contents First published. For Beta Site customers only H/W monitor register correction
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98, 107, 116
11/15/99
0.41
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Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales.
W83697HF PRELIMINARY
1 PIN DESCRIPTION.............................................................................................................7
1.1 LPC INTERFACE .................................................................................................................................................. 7 1.2 FDC INTERFACE.................................................................................................................................................. 8 1.3 MULTI-MODE PARALLEL PORT ..................................................................................................................... 9 1.4 SERIAL PORT INTERFACE.............................................................................................................................. 14 1.5 INFRARED PORT ............................................................................................................................................... 15 1.6 FRESH ROM INTERFACE ................................................................................................................................ 15 1.7 HARDWARE MONITOR INTERFACE........................................................................................................... 15 1.8 GAME PORT & MIDI PORT ............................................................................................................................. 17 1.9 POWER PINS ....................................................................................................................................................... 18
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LPC (LOW PIN COUNT) INTERFACE.........................................................................19 FDC FUNCTIONAL DESCRIPTION .............................................................................20
3.1.1 AT interface.................................................................................................................................................... 20 3.1.2 FIFO (Data) ................................................................................................................................................... 20 3.1.3 Data Separator .............................................................................................................................................. 21 3.1.4 Write Precompensation ................................................................................................................................. 21 3.1.5 FDC Core....................................................................................................................................................... 22 3.1.6 FDC Commands ............................................................................................................................................ 22
3.1 W83697HF FDC................................................................................................................................................... 20
3.2 REGISTER DESCRIPTIONS ............................................................................................................................. 34 3.2.1 Status Register A (SA Register) (Read base address + 0) .......................................................................... 34 3.2.2 Status Register B (SB Register) (Read base address + 1) .......................................................................... 36 3.2.3 Digital Output Register (DO Register) (Write base address + 2).............................................................. 38 3.2.4 Tape Drive Register (TD Register) (Read base address + 3)..................................................................... 38 3.2.5 Main Status Register (MS Register) (Read base address + 4)................................................................... 39 3.2.6 Data Rate Register (DR Register) (Write base address + 4)...................................................................... 39 3.2.7 FIFO Register (R/W base address + 5)........................................................................................................ 41 3.2.8 Digital Input Register (DI Register) (Read base address + 7)................................................................... 43 3.2.9 Configuration Control Register (CC Register) (Write base address + 7)................................................. 44
4
UART PORT.........................................................................................................................45
Publication Release Date: Aug 1999 Revision 0.40
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W83697HF
PRELIMINARY
4.1 UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER (UART A, UART B) ........................... 45 4.2 REGISTER ADDRESS........................................................................................................................................ 45 4.2.1 UART Control Register (UCR) (Read/Write) .............................................................................................. 45 4.2.2 UART Status Register (USR) (Read/Write).................................................................................................. 48 4.2.3 Handshake Control Register (HCR) (Read/Write)...................................................................................... 50 4.2.4 Handshake Status Register (HSR) (Read/Write) ......................................................................................... 51 4.2.5 UART FIFO Control Register (UFR) (Write only)...................................................................................... 52 4.2.6 Interrupt Status Register (ISR) (Read only)................................................................................................. 53 4.2.7 Interrupt Control Register (ICR) (Read/Write)............................................................................................ 54 4.2.8 Programmable Baud Generator (BLL/BHL) (Read/Write) ....................................................................... 54 4.2.9 User-defined Register (UDR) (Read/Write) ................................................................................................. 55
5
CIR RECEIVER PORT......................................................................................................56
5.1.1 Bank0.Reg0 - Receiver Buffer Registers (RBR) (Read) .............................................................................. 56 5.1.2 Bank0.Reg1 - Interrupt Control Register (ICR).......................................................................................... 56 5.1.3 Bank0.Reg2 - Interrupt Status Register (ISR) ............................................................................................. 56 5.1.4 Bank0~3.Reg3 - CIR Control Register 0/Bank Select Register (CTR0/BSR) (BANK0~3) ...................... 57 5.1.5 Bank0.Reg4 - CIR Control Register (CTR) ................................................................................................. 57 5.1.6 Bank0.Reg5 - UART Line Status Register (USR)....................................................................................... 58 5.1.7 Bank0.Reg6 - Remote Infrared Config Register (RIR_CFG) .................................................................... 59 5.1.8 Bank0.Reg7 - User Defined Register (UDR/AUDR) .................................................................................. 61 5.1.9 Bank1.Reg0~1 - Baud Rate Divisor Latch (BLL/BHL).............................................................................. 62 5.1.10 Bank1.Reg2 - Version ID Regiister I (VID)............................................................................................... 63 5.1.11 Bank0~3.Reg3 - CIR Control Register 0/Bank Select Register (CTR0/BSR) (BANK0~3) .................... 63 5.1.12 Bank1.Reg4 - Timer Low Byte Register (TMRL) ...................................................................................... 63 5.1.13 Bank1.Reg5 - Timer High Byte Register (TMRH) .................................................................................... 63
5.1 CIR REGISTERS.................................................................................................................................................. 56
6
PARALLEL PORT.............................................................................................................64
6.1 PRINTER INTERFACE LOGIC......................................................................................................................... 64 6.2 ENHANCED PARALLEL PORT (EPP)............................................................................................................ 65 6.2.1 Data Swapper ................................................................................................................................................ 65 6.2.2 Printer Status Buffer...................................................................................................................................... 66 6.2.3 Printer Control Latch and Printer Control Swapper ................................................................................. 67 6.2.4 EPP Address Port .......................................................................................................................................... 67 6.2.5 EPP Data Port 0-3 ........................................................................................................................................ 68
Publication Release Date: Aug 1999 Revision 0.40
W83697HF
PRELIMINARY
6.2.6 Bit Map of Parallel Port and EPP Registers............................................................................................... 68 6.2.7 EPP Pin Descriptions.................................................................................................................................... 69 6.2.8 EPP Operation............................................................................................................................................... 69 6.3 EXTENDED CAPABILITIES PARALLEL (ECP) PORT............................................................................... 70 6.3.1 ECP Register and Mode Definitions ............................................................................................................ 70 6.3.2 Data and ecpAFifo Port................................................................................................................................ 71 6.3.3 Device Status Register (DSR)........................................................................................................................ 71 6.3.4 Device Control Register (DCR) .................................................................................................................... 72 6.3.5 cFifo (Parallel Port Data FIFO) Mode = 010............................................................................................ 73 6.3.6 ecpDFifo (ECP Data FIFO) Mode = 011 ................................................................................................... 73 6.3.7 tFifo (Test FIFO Mode) Mode = 110........................................................................................................... 73 6.3.8 cnfgA (Configuration Register A) Mode = 111 .......................................................................................... 73 6.3.9 cnfgB (Configuration Register B) Mode = 111 .......................................................................................... 73 6.3.10 ecr (Extended Control Register) Mode = all ............................................................................................. 74 6.3.11 Bit Map of ECP Port Registers................................................................................................................... 75 6.3.12 ECP Pin Descriptions ................................................................................................................................. 76 6.3.13 ECP Operation ............................................................................................................................................ 77 6.3.14 FIFO Operation........................................................................................................................................... 77 6.3.15 DMA Transfers ............................................................................................................................................ 78 6.3.16 Programmed I/O (NON-DMA) Mode........................................................................................................ 78 6.4 EXTENSION FDD MODE (EXTFDD)............................................................................................................. 78 6.5 EXTENSION 2FDD MODE (EXT2FDD) ........................................................................................................ 78
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GENERAL PURPOSE I/O.................................................................................................79 ACPI REGISTERS FEATURES ......................................................................................82 HARDWARE MONITOR..................................................................................................83
9.1 GENERAL DESCRIPTION ................................................................................................................................ 83 9.2 ACCESS INTERFACE........................................................................................................................................ 83 9.2.1 LPC interface ................................................................................................................................................. 83 9.3 ANALOG INPUTS............................................................................................................................................... 85 9.3.1 Monitor over 4.096V voltage: ...................................................................................................................... 85 9.3.2 Monitor negative voltage:............................................................................................................................. 85 9.3.3 Temperature Measurement Machine ........................................................................................................... 86 9.4 FAN SPEED COUNT AND FAN SPEED CONTROL ................................................................................... 87
Publication Release Date: Aug 1999 Revision 0.40
W83697HF
PRELIMINARY
9.4.1 Fan speed count............................................................................................................................................. 87 9.4.2 Fan speed control .......................................................................................................................................... 89 9.5 SMI# INTERRUPT MODE................................................................................................................................. 90 9.5.1 Voltage SMI# mode :..................................................................................................................................... 90 9.5.2 Fan SMI# mode :........................................................................................................................................... 90 9.5.3 Temperature SMI# mode .............................................................................................................................. 90 9.6 OVT# INTERRUPT MODE ............................................................................................................................... 93 9.7 REGISTERS AND RAM..................................................................................................................................... 94 9.7.1 Address Register (Port x5h) .......................................................................................................................... 94 9.7.2 Data Register (Port x6h) ............................................................................................................................... 97 9.7.3 Configuration Register 3/4 Index 40h ............................................................................................................. 97 9.7.4 Interrupt Status Register 13/4 Index 41h......................................................................................................... 98 9.7.5 Interrupt Status Register 2 3/4 Index 42h........................................................................................................ 99 9.7.6 SMI# Mask Register 1 3/4 Index 43h............................................................................................................... 99 9.7.7 SMI# Mask Register 2 3/4 Index 44h.............................................................................................................100 9.7.8 Reserved Register 3/4 Index 45h ....................................................................................................................100 9.7.9 Chassis Clear Register -- Index 46h...........................................................................................................100 9.7.10 VID/Fan Divisor Register 3/4 Index 47h.....................................................................................................101 9.7.11 Value RAM 3/4 Index 20h- 3Fh or 60h - 7Fh (auto-increment) ...............................................................101 9.7.12 Device ID Register - Index 49h ................................................................................................................102 9.7.13 Pin Control Register - Index 4Bh .............................................................................................................103 9.7.14 SMI#/OVT# Property Select Register- Index 4Ch ..................................................................................104 9.7.15 FAN IN/OUT and BEEP Control Register- Index 4Dh..........................................................................104 9.7.16 Register 50h ~ 5Fh Bank Select Register - Index 4Eh (No Auto Increase)...........................................105 9.7.17 Winbond Vendor ID Register - Index 4Fh (No Auto Increase) .............................................................106 9.7.18 Winbond Test Register -- Index 50h - 55h (Bank 0) ..............................................................................106 9.7.19 BEEP Control Register 1-- Index 56h (Bank 0)......................................................................................106 9.7.20 BEEP Control Register 2-- Index 57h (Bank 0)......................................................................................107 9.7.21 Chip ID -- Index 58h (Bank 0) .................................................................................................................108 9.7.22 Reserved Register -- Index 59h (Bank 0) ................................................................................................108 9.7.23 PWMOUT1 Control -- Index 5Ah (Bank 0) ............................................................................................109 9.7.24 PWMOUT2 Control -- Index 5Bh (Bank 0) ............................................................................................109 9.7.25 PWMOUT1/2 Clock Select -- Index 5Ch (Bank 0)..................................................................................109 9.7.26 VBAT Monitor Control Register -- Index 5Dh (Bank 0) ........................................................................110 9.7.27 Reserved Register -- 5Eh (Bank 0) .........................................................................................................111 9.7.28 Reserved Register -- Index 5Fh (Bank 0)................................................................................................111 Publication Release Date: Aug 1999 Revision 0.40
W83697HF
PRELIMINARY
9.7.29 Temperature Sensor 2 Temperature (High Byte) Register - Index 50h (Bank 1).................................111 9.7.30 Temperature Sensor 2 Temperature (Low Byte) Register - Index 51h (Bank 1) ..................................111 9.7.31 Temperature Sensor 2 Configuration Register - Index 52h (Bank 1)...................................................112 9.7.32 Temperature Sensor 2 Hysteresis (High Byte) Register - Index 53h (Bank 1)......................................112 9.7.33 Temperature Sensor 2 Hysteresis (Low Byte) Register - Index 54h (Bank 1).......................................113 9.7.34 Temperature Sensor 2 Over-temperature (High Byte) Register - Index 55h (Bank 1) ........................113 9.7.35 Temperature Sensor 2 Over-temperature (Low Byte) Register - Index 56h (Bank 1)..........................114 9.7.36 Interrupt Status Register 3 -- Index 50h (BANK4)..................................................................................114 9.7.37 SMI# Mask Register 3 -- Index 51h (BANK 4) .....................................................................................115 9.7.38 Reserved Register -- Index 52h (Bank 4) .................................................................................................115 9.7.39 BEEP Control Register 3-- Index 53h (Bank 4)......................................................................................115 9.7.40 Temperature Sensor 1 Offset Register -- Index 54h (Bank 4)................................................................116 9.7.41 Temperature Sensor 2 Offset Register -- Index 55h (Bank 4)................................................................116 9.7.42 Reserved Register -- Index 57h--58h .......................................................................................................117 9.7.43 Real Time Hardware Status Register I -- Index 59h (Bank 4) ...............................................................117 9.7.44 Real Time Hardware Status Register II -- Index 5Ah (Bank 4) .............................................................118 9.7.45 Real Time Hardware Status Register III -- Index 5Bh (Bank 4)............................................................118 9.7.46 Reserved Register -- Index 5Ch (Bank 4).................................................................................................119 9.7.47 VID Output Register -- Index 5Dh (Bank 4) ...........................................................................................119 9.7.48 Value RAM 23/4 Index 50h - 5Ah (auto-increment) (BANK 5)................................................................119 9.7.49 Winbond Test Register -- Index 50h (Bank 6) .........................................................................................120 9.7.50 FAN 1 Pre-Scale Register ndex00h ......................................................................................................121 9.7.51 FAN 1 Duty Cycle Select Register-- 01h (Bank 0) ..................................................................................122 9.7.52 FAN 2 Pre-Scale Register-- Index 02h ....................................................................................................122 9.7.53 FAN2 Duty Cycle Select Register-- Index 03h.........................................................................................123 9.7.54 FAN Configuration Register-- Index 04h................................................................................................123 9.7.55 CPUT1 Target Temperature Register/ Fan 1 Target Speed Register -- Index 05h .............................124 9.7.56 CPUT2 Target Temperature Register/ Fan 2 Target Speed Register -- Index 06h .............................124 9.7.57 Tolerance of Target Temperature or Target Speed Register -- Index 07h ..........................................124 9.7.58 Fan 1 PWM Stop Duty Cycle Register -- Index 08h ...............................................................................125 9.7.59 Fan 2 PWM Stop Duty Cycle Register -- 09h (Bank 0) ..........................................................................125 9.7.60 Fan 1 Start-up Duty Cycle Register -- Index 0Ah ...................................................................................125 9.7.61 Fan 2 Start-up Duty Cycle Register -- Index 0Bh ...................................................................................126 9.7.62 Fan 1 Stop Time Register -- Index 0Ch ...................................................................................................126 9.7.63 Fan 2 Stop Time Register -- Index 0Dh...................................................................................................126 9.7.64 Fan Step Down Time Register -- Index 0Eh............................................................................................126
Publication Release Date: Aug 1999 Revision 0.40
W83697HF
PRELIMINARY
9.7.65 Fan Step Up Time Register -- Index 0Fh.................................................................................................126
10 CONFIGURATION REGISTER................................................................................... 128
10.1 PLUG AND PLAY CONFIGURATION .......................................................................................................128 10.2 COMPATIBLE PNP ........................................................................................................................................128 10.2.1 Extended Function Registers ....................................................................................................................128 10.2.2 Extended Functions Enable Registers (EFERs)......................................................................................129 10.2.3 Extended Function Index Registers (EFIRs), Extended Function Data Registers(EFDRs) ................129 10.3 CONFIGURATION SEQUENCE ..................................................................................................................129 10.3.1 Enter the extended function mode............................................................................................................129 10.3.2 Configurate the configuration registers ..................................................................................................129 10.3.3 Exit the extended function mode...............................................................................................................129 10.3.4 Software programming example..............................................................................................................130 10.4 CHIP (GLOBAL) CONTROL REGISTER....................................................................................................131 10.5 LOGICAL DEVICE 0 (FDC) ..........................................................................................................................136 10.6 LOGICAL DEVICE 1 (PARALLEL PORT) .................................................................................................139 10.7 LOGICAL DEVICE 2 (UART A)...................................................................................................................140 10.8 LOGICAL DEVICE 3 (UART B) ...................................................................................................................141 10.9 LOGICAL DEVICE 6 (CIR) ...........................................................................................................................142 10.10 LOGICAL DEVICE 7 (GAME PORT GPIO PORT 1) ..............................................................................143 10.11 LOGICAL DEVICE 8 (MIDI PORT AND GPIO PORT 5).......................................................................144 10.12 LOGICAL DEVICE 9 (GPIO PORT 2 ~ GPIO PORT 4 ) .........................................................................146 10.13 LOGICAL DEVICE A (ACPI)......................................................................................................................148 10.14 LOGICAL DEVICE B (HARDWARE MONITOR)...................................................................................153
11 ORDERING INSTRUCTION......................................................................................... 154 12 HOW TO READ THE TOP MARKING...................................................................... 154 13 PACKAGE DIMENSIONS ............................................................................................. 155
Publication Release Date: Aug 1999 Revision 0.40
W83697HF PRELIMINARY
GENERAL DESCRIPTION
The W83697HF is evolving product from Winbond's most popular I/O family. They feature a whole new interface, namely LPC (Low Pin Count) interface, which will be supported in the new generation chipset. This interface as its name suggests is to provide an economical implementation of I/O's interface with lower pin count and still maintains equivalent performance as its ISA interface counterpart. Approximately 40 pin counts are saved in LPC I/O comparing to ISA implementation. With this additional freedom, we can implement more devices on a single chip as demonstrated in W83697HF's integration of Game Port and MIDI Port. It is fully transparent in terms of software which means no BIOS or device driver update is needed except chip-specific configuration. The disk drive adapter functions of W83697HF include a floppy disk drive controller compatible with the industry standard 82077/ 765, data separator, write pre-compensation circuit, decode logic, data rate selection, clock generator, drive interface control logic, and interrupt and DMA logic. The wide range of functions integrated onto the W83697HF greatly reduces the number of components required for interfacing with floppy disk drives. The W83697HF supports four 360K, 720K, 1.2M, 1.44M, or 2.88M disk drives and data transfer rates of 250 Kb/s, 300 Kb/s, 500 Kb/s,1 Mb/s, and 2 Mb/s. The W83697HF provides two high-speed serial communication ports (UARTs), one of which supports serial Infrared communication. Each UART includes a 16-byte send/receive FIFO, a programmable baud rate generator, complete modem control capability, and a processor interrupt system. Both UARTs provide legacy speed with baud rate up to 115.2k bps and also advanced speed with baud rates of 230k, 460k, or 921k bps which support higher speed modems. In addition, the W83697HF provides IR functions: IrDA 1.0 (SIR for 1.152K bps) and TV remote IR (Consumer IR, supporting NEC, RC-5, extended RC-5, and RECS-80 protocols). The W83697HF supports one PC-compatible printer port (SPP), Bi-directional Printer port (BPP) and also Enhanced Parallel Port (EPP) and Extended Capabilities Port (ECP). Through the printer port interface pins, also available are: Extension FDD Mode and Extension 2FDD Mode allowing one or two external floppy disk drives to be connected. The configuration registers support mode selection, function enable/disable, and power down function selection. Furthermore, the configurable PnP features are compatible with the plug-and-play feature TM demand of Windows 95/98 , which makes system resource allocation more efficient than ever. The W83697HF provides a set of flexible I/O control functions to the system designer through a set of General Purpose I/O ports. These GPIO ports may serve as simple I/O or may be individually configured to provide a predefined alternate function. General Purpose Port 1 is designed to be functional even in power down mode (VCC is off). The W83697HF is made to fully comply with Microsoft(c) PC98 and PC99 Hardware Design Guide, and meet the requirements of ACPI. The W83697HF contains a game port and a MIDI port. The game port is designed to support 2 joysticks and can be applied to all standard PC game control devices, They are very important for a entertainment or consumer computer.
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Publication Release Date: Aug 1999 Revision 0.40
W83697HF
PRELIMINARY
The W83697HF provides Flash ROM interface. That can support up to 4M legacy flash ROM. The W83697HF support hardware status monitoring for personal computers. It can be used to monitor several critical hardware parameters of the system, including power supply voltages, fan speeds, and temperatures, which are very important for a high-end computer system to work stably and properly. TM Moreover, W83697HF support the Smart Fan control system, including the "Thermal Cruise " and TM "Speed Cruise " functions. Smart Fan can make system more stable and user friendly.
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Publication Release Date: Aug 1999 Revision 0.40
W83697HF
PRELIMINARY FEATURES
General
* * * * * * * * Meet LPC Spec. 1.01 Support LDRQ#(LPC DMA), SERIRQ (serial IRQ) Include all the features of Winbond I/O W83877TF Integrate Hardware Monitor functions Compliant with Microsoft PC98/PC99 Hardware Design Guide Support DPM (Device Power Management), ACPI Programmable configuration settings Single 24 or 48 MHz clock input
FDC
* * * * * * * * * * * * * Compatible with IBM PC AT disk drive systems Variable write pre-compensation with track selectable capability Support vertical recording format DMA enable logic 16-byte data FIFOs Support floppy disk drives and tape drives Detects all overrun and underrun conditions Built-in address mark detection circuit to simplify the read electronics FDD anti-virus functions with software write protect and FDD write enable signal (write data signal was forced to be inactive) Support up to four 3.5-inch or 5.25-inch floppy disk drives Completely compatible with industry standard 82077 360K/720K/1.2M/1.44M/2.88M format; 250K, 300K, 500K, 1M, 2M bps data transfer rate Support 3-mode FDD, and its Win95/98 driver
UART
* * * Two high-speed 16550 compatible UARTs with 16-byte send/receive FIFOs MIDI compatible Fully programmable serial-interface characteristics: --- 5, 6, 7 or 8-bit characters --- Even, odd or no parity bit generation/detection --- 1, 1.5 or 2 stop bits generation Internal diagnostic capabilities: --- Loop-back controls for communications link fault isolation --- Break, parity, overrun, framing error simulation Programmable baud generator allows division of 1.8461 MHz and 24 MHz by 1 to (216-1) Maximum baud rate up to 921k bps for 14.769 MHz and 1.5M bps for 24 MHz Publication Release Date: Aug 1999 Revision 0.40
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* *
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W83697HF
PRELIMINARY
Infrared
* * * Support IrDA version 1.0 SIR protocol with maximum baud rate up to 115.2K bps Support SHARP ASK-IR protocol with maximum baud rate up to 57,600 bps Support Consumer IR with Wake-Up function.
Parallel Port
* * * * * * Compatible with IBM parallel port Support PS/2 compatible bi-directional parallel port Support Enhanced Parallel Port (EPP) - Compatible with IEEE 1284 specification Support Extended Capabilities Port (ECP) - Compatible with IEEE 1284 specification Extension FDD mode supports disk drive B; and Extension 2FDD mode supports disk drives A and B through parallel port Enhanced printer port back-drive current protection
Game Port
* * Support two separate Joysticks Support every Joystick two axes (X,Y) and two buttons (S1,S2) controllers
MIDI Port
* * * The baud rate is 31.25 Kbaud 16-byte input FIFO 16-byte output FIFO
Flash ROM Interface
* Support up to 4M flash ROM
General Purpose I/O Ports
* * * 48 programmable general purpose I/O ports General purpose I/O ports can serve as simple I/O ports, watch dog timer output, power LED output, infrared I/O pins, suspend LED output, Beep output Functional in power down mode
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Publication Release Date: Aug 1999 Revision 0.40
W83697HF
PRELIMINARY
Hardware Monitor Functions
* * * * * * * * * * * * * * Smart fan control system, support "Thermal Cruise " and "Speed Cruise " TM 2 thermal inputs from optionally remote thermistors or 2N3904 transistors or Pentium II/III thermal diode output 6 positive voltage inputs (typical for +12V, -12V, +5V, -5V, +3.3V, Vcore) 2 intrinsic voltage monitoring (typical for Vbat, +5VSB) 2 fan speed monitoring inputs 2 fan speed control Build in Case open detection circuit WATCHDOG comparison of all monitored values Programmable hysteresis and setting points for all monitored items Over temperature indicate output Automatic Power On voltage detection Beep Issue SMI#, IRQ, OVT# to activate system protection TM Winbond Hardware Doctor Support TM TM Intel LDCM / Acer ADM compatible
TM TM
Package
* 128-pin PQFP
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Publication Release Date: Aug 1999 Revision 0.40
W83697HF
PRELIMINARY PIN CONFIGURATION FOR 697HF
VTIN2 VTIN1 AVCC VREF VCORE +3.3VIN +12VIN -12VIN -5VIN AGND FANIO2 FANIO1 FANPWM2 FANPWM1 OVT#/SMI# BEEP MSI/GP51/WDTO MSO/GP50/PLED GPAS2/GP17 GPBS2/GP16 GPAY/GP15 GPBY/GP14 GPBX/GP13 GPAX/GP12 GPBS1/GP11 GPAS1/GP10
103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128
VBAT CASEOPEN# CIRRX VSB PME# MEMW#/GP52 MEMR#/GP53 ROMCS#/GP54 XD0/GP20 XD1/GP21 XD2/GP22 XD3/GP23 GND XD4/GP24 XD5/GP25 XD6/GP26 XD7/GP27 XA0/GP30 XA1/GP31 XA2/GP32 XA3/GP33 XA4/GP34 XA5/GP35 XA6/GP36 XA7/GP37 XA8/GP40 XA9/GP41 VCC XA10/GP42 XA11/GP43 XA12/GP44 XA13/GP45 XA14/GP46 XA15/GP47 XA16/GP55 XA17/GP56 XA18/GP57 IRTX 11 199 9 9 999 99 9 88 8 88888 8 877 7 7 777 7 7 76 666 6 00 0 9 8 7 6 5 4 3 21 0 98 7 65432 1 098 7 6 5 4 3 2 1 0 9 8 76 5 21 0 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39
W83697HF
IRRX RIB# DCDB# SOUTB GND SINB DTRB# RTSB# DSRB# CTSB# RIA# DCDA# SOUTA SINA DTRA# RTSA# DSRA# CTSA# STB# VCC AFD# INIT# PD0 PD1 PD2 PD3
1 1 1 1 1 1 1 1 1 1 2 2 2 2 22 2 2 2 2 3 3 3 3 3 3 33 3 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 45 6 7 8 9 0 1 2 3 4 5 67 8
DRVDEN0 INDEX# MOA# DSB# VCC DSA# MOB# DIR# STEP# WD# WE# TRAK0# WP# RDATA# HEAD# DSKCHG# CLKIN# GND PCICLK LDRQ# SERIRQ VCC3 LAD3 LAD2 LAD1 LAD0 LFRAME# LRESET# SLCT PE BUSY ACK# ERR# SLIN# PD7 PD6 PD5 PD4
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Publication Release Date: Aug 1999 Revision 0.40
W83697HF
PRELIMINARY 1. PIN DESCRIPTION
Note: Please refer to Section 13.2 DC CHARACTERISTICS for details. I/O8t I/O12t I/O12tp3 I/OD12t I/O24t OUT12t OUT12tp3 OD12 OD24 INcs INt INtd INts INtsp3 - TTL level bi-directional pin with 8 mA source-sink capability - TTL level bi-directional pin with 12 mA source-sink capability - 3.3V TTL level bi-directional pin with 12 mA source-sink capability - TTL level bi-directional pin open drain output with 12 mA sink capability - TTL level bi-directional pin with 24 mA source-sink capability - TTL level output pin with 12 mA source-sink capability - 3.3V TTL level output pin with 12 mA source-sink capability - Open-drain output pin with 12 mA sink capability - Open-drain output pin with 24 mA sink capability - CMOS level Schmitt-trigger input pin - TTL level input pin - TTL level input pin with internal pull down resistor - TTL level Schmitt-trigger input pin - 3.3V TTL level Schmitt-trigger input pin
1.1 LPC Interface
SYMBOL CLKIN PME# PCICLK LDRQ# SERIRQ LAD[3:0] LFRAME# LRESET# PIN 17 98 19 20 21 23-26 27 28 I/O INt OD12 INtsp3 O12tp3 I/OD12t I/O12tp3 INtsp3 INtsp3 FUNCTION System clock input. According to the input frequency 24MHz or 48MHz, it is selectable through register. Default is 24MHz input. Generated PME event. PCI clock input. Encoded DMA Request signal. Serial IRQ input/Output. These signal lines communicate address, control, and data information over the LPC bus between a host and a peripheral. Indicates start of a new cycle or termination of a broken cycle. Reset signal. It can connect to PCIRST# signal on the host.
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Publication Release Date: Aug 1999 Revision 0.40
W83697HF
PRELIMINARY
1.2 FDC Interface
SYMBOL DRVDEN0 INDEX# PIN 1 2 I/O OD24 INcs Drive Density Select bit 0. This Schmitt-triggered input from the disk drive is active low when the head is positioned over the beginning of a track marked by an index hole. This input pin is pulled up internally by a 1 K resistor. The resistor can be disabled by bit 7 of L0-CRF0 (FIPURDWN). Motor A On. When set to 0, this pin enables disk drive 0. This is an open drain output. Drive Select B. When set to 0, this pin enables disk drive B. This is an open drain output. Drive Select A. When set to 0, this pin enables disk drive A. This is an open drain output. Motor B On. When set to 0, this pin enables disk drive 1. This is an open drain output. Direction of the head step motor. An open drain output. Logic 1 = outward motion Logic 0 = inward motion STEP# WD# WE# TRAK0# 9 10 11 12 OD24 OD24 OD24 INcs Step output pulses. This active low open drain output produces a pulse to move the head to another track. Write data. This logic low open drain writes pre-compensation serial data to the selected FDD. An open drain output. Write enable. An open drain output. Track 0. This Schmitt-triggered input from the disk drive is active low when the head is positioned over the outermost track. This input pin is pulled up internally by a 1 K resistor. The resistor can be disabled by bit 7 of L0-CRF0 (FIPURDWN). Write protected. This active low Schmitt input from the disk drive indicates that the diskette is write-protected. This input pin is pulled up internally by a 1 K resistor. The resistor can be disabled by bit 7 of L0-CRF0 (FIPURDWN). The read data input signal from the FDD. This input pin is pulled up internally by a 1 K resistor. The resistor can be disabled by bit 7 of L0-CRF0 (FIPURDWN). FUNCTION
MOA# DSB# DSA# MOB# DIR#
3 4 6 7 8
OD24 OD24 OD24 OD24 OD24
WP#
13
INcs
RDATA#
14
INcs
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Publication Release Date: Aug 1999 Revision 0.40
W83697HF
PRELIMINARY
1.2 FDC Interface, continued
SYMBOL HEAD#
PIN 15
I/O OD24
DSKCHG#
16
INcs
FUNCTION Head select. This open drain output determines which disk drive head is active. Logic 1 = side 0 Logic 0 = side 1 Diskette change. This signal is active low at power on and whenever the diskette is removed. This input pin is pulled up internally by a 1 K resistor. The resistor can be disabled by bit 7 of L0-CRF0 (FIPURDWN).
1.3 Multi-Mode Parallel Port
The following pins have alternate functions, which are controlled by CR28 and L3-CRF0. SYMBOL SLCT PIN 29 I/O INt FUNCTION PRINTER MODE: An active high input on this pin indicates that the printer is selected. This pin is pulled high internally. Refer to the description of the parallel port for definition of this pin in ECP and EPP mode. EXTENSION FDD MODE: WE2# This pin is for Extension FDD B; its function is the same as the WE# pin of FDC. EXTENSION 2FDD MODE: WE2# This pin is for Extension FDD A and B; its function is the same as the WE# pin of FDC. PRINTER MODE: An active high input on this pin indicates that the printer has detected the end of the paper. This pin is pulled high internally. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. EXTENSION FDD MODE: WD2# This pin is for Extension FDD B; its function is the same as the WD# pin of FDC. EXTENSION 2FDD MODE: WD2# This pin is for Extension FDD A and B; its function is the same as the WD# pin of FDC.
OD12
OD12
PE
30
INt
OD12
OD12
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W83697HF
PRELIMINARY
1.3 Multi-Mode Parallel Port, continued
SYMBOL BUSY
PIN 31
I/O INt
OD12
OD12
ACK#
32
INt
OD12
OD12
ERR#
33
INt
OD12 OD12
FUNCTION PRINTER MODE: An active high input indicates that the printer is not ready to receive data. This pin is pulled high internally. Refer to the description of the parallel port for definition of this pin in ECP and EPP mode. EXTENSION FDD MODE: MOB2# This pin is for Extension FDD B; its function is the same as the MOB# pin of FDC. EXTENSION 2FDD MODE: MOB2# This pin is for Extension FDD A and B; its function is the same as the MOB# pin of FDC. PRINTER MODE: ACK# An active low input on this pin indicates that the printer has received data and is ready to accept more data. This pin is pulled high internally. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. EXTENSION FDD MODE: DSB2# This pin is for the Extension FDD B; its functions is the same as the DSB# pin of FDC. EXTENSION 2FDD MODE: DSB2# This pin is for Extension FDD A and B; its function is the same as the DSB# pin of FDC. PRINTER MODE: ERR# An active low input on this pin indicates that the printer has encountered an error condition. This pin is pulled high internally. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. EXTENSION FDD MODE: HEAD2# This pin is for Extension FDD B; its function is the same as the HEAD#pin of FDC. EXTENSION 2FDD MODE: HEAD2# This pin is for Extension FDD A and B; its function is the same as the HEAD# pin of FDC.
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W83697HF
PRELIMINARY
1.3 Multi-Mode Parallel Port, continued
SYMBOL SLIN#
PIN 34
I/O OD12
OD12
OD12
INIT#
43
OD12
OD12
OD12
AFD#
44
OD12
OD12
OD12
FUNCTION PRINTER MODE: SLIN# Output line for detection of printer selection. This pin is pulled high internally. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. EXTENSION FDD MODE: STEP2# This pin is for Extension FDD B; its function is the same as the STEP# pin of FDC. EXTENSION 2FDD MODE: STEP2# This pin is for Extension FDD A and B; its function is the same as the STEP# pin of FDC. PRINTER MODE: INIT# Output line for the printer initialization. This pin is pulled high internally. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. EXTENSION FDD MODE: DIR2# This pin is for Extension FDD B; its function is the same as the DIR# pin of FDC. EXTENSION 2FDD MODE: DIR2# This pin is for Extension FDD A and B; its function is the same as the DIR# pin of FDC. PRINTER MODE: AFD# An active low output from this pin causes the printer to auto feed a line after a line is printed. This pin is pulled high internally. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. EXTENSION FDD MODE: DRVDEN0 This pin is for Extension FDD B; its function is the same as the DRVDEN0 pin of FDC. EXTENSION 2FDD MODE: DRVDEN0 This pin is for Extension FDD A and B; its function is the same as the DRVDEN0 pin of FDC.
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W83697HF
PRELIMINARY
1.3 Multi-Mode Parallel Port, continued
SYMBOL STB#
PIN 46
I/O OD12
PD0
42
I/O12t
INt
INt
PD1
41
I/O12t
INt
INt
PD2
40
I/O12t
INt
INt
FUNCTION PRINTER MODE: STB# An active low output is used to latch the parallel data into the printer. This pin is pulled high internally. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. EXTENSION FDD MODE: This pin is a tri-state output. EXTENSION 2FDD MODE: This pin is a tri-state output. PRINTER MODE: PD0 Parallel port data bus bit 0. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. EXTENSION FDD MODE: INDEX2# This pin is for Extension FDD B; its function is the same as the INDEX# pin of FDC. It is pulled high internally. EXTENSION 2FDD MODE: INDEX2# This pin is for Extension FDD A and B; its function is the same as the INDEX# pin of FDC. It is pulled high internally. PRINTER MODE: PD1 Parallel port data bus bit 1. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. EXTENSION FDD MODE: TRAK02# This pin is for Extension FDD B; its function is the same as the TRAK0# pin of FDC. It is pulled high internally. EXTENSION. 2FDD MODE: TRAK02# This pin is for Extension FDD A and B; its function is the same as the TRAK0# pin of FDC. It is pulled high internally. PRINTER MODE: PD2 Parallel port data bus bit 2. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. EXTENSION FDD MODE: WP2# This pin is for Extension FDD B; its function is the same as the WP# pin of FDC. It is pulled high internally. EXTENSION. 2FDD MODE: WP2# This pin is for Extension FDD A and B; its function is the same as the WP# pin of FDC. It is pulled high internally.
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W83697HF
PRELIMINARY
1.3 Multi-Mode Parallel Port, continued
SYMBOL PD3
PIN 39
I/O I/O12t
INt
INt
PD4
38
I/O12t
INt
INt
PD5
37
I/O12t
PD6 36 I/OD12t OD12
PD7
35
I/OD12t
OD12
FUNCTION PRINTER MODE: PD3 Parallel port data bus bit 3. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. EXTENSION FDD MODE: RDATA2# This pin is for Extension FDD B; its function is the same as the RDATA# pin of FDC. It is pulled high internally. EXTENSION 2FDD MODE: RDATA2# This pin is for Extension FDD A and B; its function is the same as the RDATA# pin of FDC. It is pulled high internally. PRINTER MODE: PD4 Parallel port data bus bit 4. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. EXTENSION FDD MODE: DSKCHG2# This pin is for Extension FDD B; the function of this pin is the same as the DSKCHG# pin of FDC. It is pulled high internally. EXTENSION 2FDD MODE: DSKCHG2# This pin is for Extension FDD A and B; this function of this pin is the same as the DSKCHG# pin of FDC. It is pulled high internally. PRINTER MODE: PD5 Parallel port data bus bit 5. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. EXTENSION FDD MODE: This pin is a tri-state output. EXTENSION 2FDD MODE: This pin is a tri-state output. PRINTER MODE: PD6 Parallel port data bus bit 6. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. EXTENSION FDD MODE: This pin is a tri-state output. EXTENSION. 2FDD MODE: MOA2# This pin is for Extension FDD A; its function is the same as the MOA# pin of FDC. PRINTER MODE: PD7 Parallel port data bus bit 7. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. EXTENSION FDD MODE: This pin is a tri-state output. EXTENSION 2FDD MODE: DSA2# This pin is for Extension FDD A; its function is the same as the DSA# pin of FDC.
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W83697HF
PRELIMINARY
1.4 Serial Port Interface
SYMBOL CTSA# CTSB# DSRA# DSRB# RTSA# HEFRAS PIN 47 55 48 56 49 I/O INt FUNCTION Clear To Send. It is the modem control input. The function of these pins can be tested by reading bit 4 of the handshake status register. Data Set Ready. An active low signal indicates the modem or data set is ready to establish a communication link and transfer data to the UART. UART A Request To Send. An active low signal informs the modem or data set that the controller is ready to send data. During power-on reset, this pin is pulled down internally and is defined as HEFRAS, which provides the power-on value for CR26 bit 6 (HEFRAS). A 4.7 k is recommended if intends to pull up. (select 4EH as configuration I/O ports address) UART B Request To Send. An active low signal informs the modem or data set that the controller is ready to send data. UART A Data Terminal Ready. An active low signal informs the modem or data set that the controller is ready to communicate. During power-on reset, this pin is pulled down internally and is defined as PNPCSV#, which provides the power-on value for CR24 bit 0 (PNPCSV#). A 4.7 k is recommended if intends to pull up. (clear the default value of FDC, UARTs, and PRT) UART B Data Terminal Ready. An active low signal informs the modem or data set that controller is ready to communicate. Serial Input. It is used to receive serial data through the communication link. UART A Serial Output. It is used to transmit serial data out to the communication link. During power on reset , this pin is pulled down internally and is defined as PENROM#, which provides the power on value for CR24 bit 1. A 4.7k is recommended if intends to pull up . UART B Serial Output. During power-on reset, this pin is pulled down internally and is defined as PEN48, which provides the power-on value for CR24 bit 6 (EN48). A 4.7 k resistor is recommended if intends to pull up. Data Carrier Detect. An active low signal indicates the modem or data set has detected a data carrier. Ring Indicator. An active low signal indicates that a ring signal is being received from the modem or data set.
INt
I/O8t
RTSB# DTRA# PNPCSV#
57 50
I/O8t I/O8t
DTRB# SINA SINB SOUTA PENROM# SOUTB PEN48
58 51 59 52
I/O8t INt I/O8t
61
I/O8t
DCDA# DCDB# RIA# RIB#
53 62 54 63
INt INt
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W83697HF
PRELIMINARY
1.5 Infrared Port
SYMBOL IRRX IRTX CIRRX# PIN 64 65 100 I/O Ints OUT12t INt FUNCTION Alternate Function Input: Infrared Receiver input. General purpose I/O port 3 bit 6. Alternate Function Output: Infrared Transmitter Output. General purpose I/O port 3 bit 7. Consumer IR receiving input. This pin can Wake-Up system from S5cold.
1.6 Fresh ROM Interface
SYMBOL XA18-XA16 GP57-GP55 XA15-XA10 GP47-GP42 XA9-XA8 GP41-GP40 XA7-XA0 GP37-GP30 XD7-XD4 GP27-GP24 XD3-XD0 GP23-GP20 ROMCS# GP54 MEMR# GP53 MEMW# GP52 PIN 66-68 69-74 76-77 78-85 86-89 91-94 95 96 97 I/O O I/OD12t O I/OD12t O I/OD12t O I/OD12t O I/OD12t O I/OD12t O I/OD12t O I/OD12t O I/OD12t FUNCTION Flash ROM interface Address[18:16] General purpose I/O port 5 bit7-5 Flash ROM interface Address[15:10] General purpose I/O port 4 bit7-2 Flash ROM interface Address[9:8] General purpose I/O port 4 bit1-0 Flash ROM interface Address[7:0] General purpose I/O port 3 bit7-0 Flash ROM interface Data Bus[7:4] General purpose I/O port 2 bit7-4 Flash ROM interface Data Bus [3:0] General purpose I/O port 2 bit3-0 Flash ROM interface Chip Select General purpose I/O port 5 bit4 Flash ROM interface Memory Read Enable General purpose I/O port 5 bit3 Flash ROM interface Memory Write Enable General purpose I/O port 5 bit2
1.7 Hardware Monitor Interface
SYMBOL
CASEOPEN#
PIN 101 102 103
I/O INt Power AIN
FUNCTION CASE OPEN. An active low signal from an external device when case is opened. Battery Voltage Input Temperature sensor 2 input. It is used for CPU temperature measuration.
VBAT VTIN2
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W83697HF
PRELIMINARY
1.7 Hardware Monitor Interface
SYMBOL VTIN1 VREF VCORE +3.3VIN +12VIN -12VIN -5VIN FANIO[2:1]
PIN 104 106 107 108 109 110 111 113114
I/O AIN AOUT AIN AIN AIN AIN AIN I/O12ts
FUNCTION Temperature sensor 1 input. It is used for system temperature measuration. Reference Voltage for temperature measuration. 0V to 4.096V FSR Analog Inputs. 0V to 4.096V FSR Analog Inputs. 0V to 4.096V FSR Analog Inputs. 0V to 4.096V FSR Analog Inputs. 0V to 4.096V FSR Analog Inputs. 0V to +5V amplitude fan tachometer input. Alternate Function: Fan on-off control output. These multifunctional pins can be programmable input or output.
FANPWM[2: 1] OVT# / SMI#
BEEP
115116 117
O12 OD12
Fan speed control. Use the Pulse Width Modulatuion (PWM) technic knowledge to control the Fan's RPM. Over temperature Shutdown Output. It indicated the VTIN1 or VTIN2 is over temperature limit. System Management Interrupt.
118
OD12
Beep function for hardware monitor. This pin is low after system reset.
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W83697HF
PRELIMINARY
1.8 Game Port & MIDI Port
SYMBOL MSI GP51 PLED MSO GP50 WDTO GPAS2 GP17 GPBS2 GP16 GPAY GP15 GPBY GP14 GPBX GP13 GPAX GP12 GPBS1 GP11 GPAS1 GP10 128 127 126 125 124 123 122 120 PIN 119 I/O INt I/OD12 OD24t OUT12t I/OD12 OD24t INcs I/OD12 INcs I/OD12 I/OD12 I/OD12 I/OD12 I/OD12 I/OD12 I/OD12 I/OD12 I/OD12 INcs I/OD12 INcs I/OD12 MIDI serial data input . General purpose I/O port 5 bit 1. Alternate Function Output(Default) Power LED output, this signal is low after system reset. MIDI serial data output. General purpose I/O port 5 bit 0. Alternate Function : Watch dog timer output. Active-low, Joystick I switch input 2. This pin has an internal pullup resistor. (Default) General purpose I/O port 1 bit 7. Active-low, Joystick II switch input 2. This pin has an internal pull-up resistor. (Default) General purpose I/O port 1 bit 6. Joystick I timer pin. this pin connect to Y positioning variable resistors for the Josystick. (Default) General purpose I/O port 1 bit 5. Joystick II timer pin. this pin connect to Y positioning variable resistors for the Josystick. (Default) General purpose I/O port 1 bit 4. Joystick II timer pin. this pin connect to X positioning variable resistors for the Josystick. (Default) General purpose I/O port 1 bit 3. Joystick I timer pin. this pin connect to X positioning variable resistors for the Josystick. (Default) General purpose I/O port 1 bit 2. Active-low, Joystick II switch input 1. This pin has an internal pull-up resistor. (Default) General purpose I/O port 1 bit 1. Active-low, Joystick I switch input 1. This pin has an internal pullup resistor. (Default) General purpose I/O port 1 bit 0. Publication Release Date: Aug 1999 Revision 0.40 FUNCTION
121
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W83697HF
PRELIMINARY
1.9 POWER PINS
PIN 5, 45, 75, 99 22 105 112 18, 60, 90, FUNCTION +5V power supply for the digital circuitry. +5V stand-by power supply for the digital circuitry. +3.3V power supply for driving 3V on host interface. Analog VCC input. Internally supplier to all analog circuitry. Internally connected to all analog circuitry. The ground reference for all analog inputs.. Ground.
SYMBOL VCC VSB VCC3V AVCC AGND GND
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Publication Release Date: Aug 1999 Revision 0.40
W83697HF
PRELIMINARY
2. LPC (LOW PIN COUNT) INTERFACE
LPC interface is to replace ISA interface serving as a bus interface between host (chip-set) and peripheral (Winbond I/O). Data transfer on the LPC bus are serialized over a 4 bit bus. The general characteristics of the interface implemented in Winbond LPC I/O are: * One control line, namely LFRAME#, which is used by the host to start or stop transfers. peripherals drive this signal. No
* The LAD[3:0] bus, which communicates information serially. The information conveyed are cycle type, cycle direction, chip selection, address, data, and wait states. * MR (master reset) of Winbond ISA I/O is replaced with a active low reset signal, namely LRESET#, in Winbond LPC I/O. * An additional 33 MHz PCI clock is needed in Winbond LPC I/O for synchronization. * DMA requests are issued through LDRQ#. * Interrupt requests are issued through SERIRQ. * Power management events are issued through PME#. Comparing to its ISA counterpart, LPC implementation saves up to 40 pin counts free for integrating more devices on a single chip. The transition from ISA to LPC is transparent in terms of software which means no BIOS or device driver update is needed except chip-specific configuration.
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Publication Release Date: Aug 1999 Revision 0.40
W83697HF/F
PRELIMINARY 3. FDC FUNCTIONAL DESCRIPTION
3.1 W83697HF FDC
The floppy disk controller of the W83697HF integrates all of the logic required for floppy disk control. The FDC implements a PC/AT or PS/2 solution. All programmable options default to compatible values. The FIFO provides better system performance in multi-master systems. The digital data separator supports up to 2 M bits/sec data rate. The FDC includes the following blocks: AT interface, Precompensation, Data Rate Selection, Digital Data Separator, FIFO, and FDC Core. 3.1.1 AT interface The interface consists of the standard asynchronous signals: RD#, WR#, A0-A3, IRQ, DMA control, and a data bus. The address lines select between the configuration registers, the FIFO and control/status registers. This interface can be switched between PC/AT, Model 30, or PS/2 normal modes. The PS/2 register sets are a superset of the registers found in a PC/AT. 3.1.2 FIFO (Data) The FIFO is 16 bytes in size and has programmable threshold values. All command parameter information and disk data transfers go through the FIFO. Data transfers are governed by the RQM and DIO bits in the Main Status Register. The FIFO defaults to disabled mode after any form of reset. This maintains PC/AT hardware compatibility. The default values can be changed through the CONFIGURE command. The advantage of the FIFO is that it allows the system a larger DMA latency without causing disk errors. The following tables give several examples of the delays with a FIFO. The data are based upon the following formula: THRESHOLD # x (1/DATA/RATE) *8 - 1.5 S = DELAY FIFO THRESHOLD 1 Byte 2 Byte 8 Byte 15 Byte FIFO THRESHOLD 1 Byte 2 Byte 8 Byte 15 Byte MAXIMUM DELAY TO SERVICING AT 500K BPS Data Rate 1 x 16 S - 1.5 S = 14.5 S 2 x 16 S - 1.5 S = 30.5 S 8 x 16 S - 1.5 S = 6.5 S 15 x 16 S - 1.5 S = 238.5 S MAXIMUM DELAY TO SERVICING AT 1M BPS Data Rate 1 x 8 S - 1.5 S = 6.5 S 2 x 8 S - 1.5 S = 14.5 S 8 x 8 S - 1.5 S = 62.5 S 15 x 8 S - 1.5 S = 118.5 S
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Publication Release Date: Aug 1999 Revision 0.40
W83697HF/F
PRELIMINARY
At the start of a command the FIFO is always disabled and command parameters must be sent based upon the RQM and DIO bit settings in the main status register. When the FDC enters the command execution phase, it clears the FIFO of any data to ensure that invalid data are not transferred. An overrun and underrun will terminate the current command and the data transfer. Disk writes will complete the current sector by generating a 00 pattern and valid CRC. Reads require the host to remove the remaining data so that the result phase may be entered. DMA transfers are enabled with the SPECIFY command and are initiated by the FDC by activating the DRQ pin during a data transfer command. The FIFO is enabled directly by asserting DACK# and addresses need not be valid. Note that if the DMA controller is programmed to function in verify mode a pseudo read is performed by the FDC based only on DACK#. This mode is only available when the FDC has been configured into byte mode (FIFO disabled) and is programmed to do a read. With the FIFO enabled the above operation is performed by using the new VERIFY command. No DMA operation is needed.@
3.1.3
Data Separator
The function of the data separator is to lock onto the incoming serial read data. When a lock is achieved the serial front end logic of the chip is provided with a clock which is synchronized to the read data. The synchronized clock, called the Data Window, is used to internally sample the serial data portion of the bit cell, and the alternate state samples the clock portion. Serial to parallel conversion logic separates the read data into clock and data bytes. The Digital Data Separator (DDS) has three parts: control logic, error adjustment, and speed tracking. The DDS circuit cycles once every 12 clock cycles ideally. Any data pulse input will be synchronized and then adjusted by immediate error adjustment. The control logic will generate RDD and RWD for every pulse input. During any cycle where no data pulse is present, the DDS cycles are based on speed. A digital integrator is used to keep track of the speed changes in the input data stream.
3.1.4
Write Precompensation
The write precompensation logic is used to minimize bit shifts in the RDDATA stream from the disk drive. Shifting of bits is a known phenomenon in magnetic media and is dependent on the disk media and the floppy drive. The FDC monitors the bit stream that is being sent to the drive. The data patterns that require precompensation are well known. Depending upon the pattern, the bit is shifted either early or late relative to the surrounding bits.
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W83697HF/F
PRELIMINARY
3.1.5 Perpendicular Recording Mode The FDC is also capable of interfacing directly to perpendicular recording floppy drives. Perpendicular recording differs from the traditional longitudinal method in that the magnetic bits are oriented vertically. This scheme packs more data bits into the same area. FDCs with perpendicular recording drives can read standard 3.5" floppy disks and can read and write perpendicular media. Some manufacturers offer drives that can read and write standard and perpendicular media in a perpendicular media drive. A single command puts the FDC into perpendicular mode. All other commands operate as they normally do. The perpendicular mode requires a 1 Mbps data rate for the FDC. At this data rate the FIFO eases the host interface bottleneck due to the speed of data transfer to or from the disk.
3.1.6
FDC Core
The W83697HF FDC is capable of performing twenty commands. Each command is initiated by a multi-byte transfer from the microprocessor. The result can also be a multi-byte transfer back to the microprocessor. Each command consists of three phases: command, execution, and result. Command The microprocessor issues all required information to the controller to perform a specific operation. Execution The controller performs the specified operation. Result After the operation is completed, status information and other housekeeping information is provided to the microprocessor.
3.1.7
FDC Commands
Command Symbol Descriptions: C: Cylinder number 0 - 256 D: Data Pattern DIR: Step Direction DIR = 0, step out DIR = 1, step in DS0: Disk Drive Select 0 DS1: Disk Drive Select 1 DTL: Data Length EC: Enable Count EOT: End of Track EFIFO: Enable FIFO EIS: Enable Implied Seek EOT: End of track
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W83697HF/F
PRELIMINARY
FIFOTHR: GAP: GPL: H: HDS: HLT: HUT: LOCK: MFM: MT: N: NCN: ND: OW: PCN: POLL: PRETRK: R: RCN: R/W: SC: SK: SRT: ST0: ST1: ST2: ST3: WG: FIFO Threshold Gap length selection Gap Length Head number Head number select Head Load Time Head Unload Time Lock EFIFO, FIFOTHR, PTRTRK bits prevent affected by software reset MFM or FM Mode Multitrack The number of data bytes written in a sector New Cylinder Number Non-DMA Mode Overwritten Present Cylinder Number Polling Disable Precompensation Start Track Number Record Relative Cylinder Number Read/Write Sector/per cylinder Skip deleted data address mark Step Rate Time Status Register 0 Status Register 1 Status Register 2 Status Register 3 Write gate alters timing of WE
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W83697HF/F
PRELIMINARY
(1) Read Data PHASE Command R/W W W W W W W W W W Execution Result R R R R R R R -------------------- ST0 ------------------------------------------ ST1 ------------------------------------------ ST2 -------------------------------------------- C --------------------------------------------- H --------------------------------------------- R --------------------------------------------- N -----------------------Sector ID information after command execution D7 0 D6 0 D5 SK 0 D4 0 0 D3 0 0 D2 1 D1 1 D0 0 REMARKS Command codes Sector ID information prior to command execution
MT MFM
HDS DS1 DS0
---------------------- C --------------------------------------------- H --------------------------------------------- R --------------------------------------------- N ------------------------------------------- EOT ------------------------------------------ GPL ------------------------------------------ DTL -----------------------
Data transfer between the FDD and system Status information after command execution
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W83697HF/F
PRELIMINARY
(2) Read Deleted Data PHASE Command R/W W W W W W W W W W Execution Result R R R R R R R -------------------- ST0 ------------------------------------------ ST1 ------------------------------------------ ST2 -------------------------------------------- C --------------------------------------------- H --------------------------------------------- R --------------------------------------------- N -----------------------Sector ID information after command execution D7 D6 D5 SK 0 D4 0 0 D3 1 0 D2 1 D1 0 D0 0 REMARKS Command codes
MT MFM 0 0
HDS DS1 DS0 Sector ID information prior to command execution
---------------------- C --------------------------------------------- H --------------------------------------------- R --------------------------------------------- N ------------------------------------------- EOT ------------------------------------------ GPL ------------------------------------------ DTL -----------------------
Data transfer between the FDD and system Status information after command execution
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W83697HF/F
PRELIMINARY
(3) Read A Track PHASE Command R/W W W W W W W W W W Execution D7 0 0 D6 MFM 0 D5 0 0 D4 0 0 D3 0 0 D2 0 D1 1 D0 0 REMARKS Command codes
HDS DS1 DS0 Sector ID information prior to command execution
---------------------- C --------------------------------------------- H --------------------------------------------- R --------------------------------------------- N ------------------------------------------- EOT ------------------------------------------ GPL ------------------------------------------ DTL -----------------------
Data transfer between the FDD and system; FDD reads contents of all cylinders from index hole to EOT R R R R R R R -------------------- ST0 ------------------------------------------ ST1 ------------------------------------------ ST2 -------------------------------------------- C --------------------------------------------- H --------------------------------------------- R --------------------------------------------- N -----------------------Sector ID information after command execution Status information after command execution
Result
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PRELIMINARY
(4) Read ID PHASE Command Execution R/W W W D7 0 0 D6 MFM 0 D5 0 0 D4 0 0 D3 1 0 D2 0 D1 1 D0 0 REMARKS Command codes The first correct ID information on the cylinder is stored in Data Register R R R R R R R -------------------- ST0 ------------------------------------------ ST1 ------------------------------------------ ST2 -------------------------------------------- C --------------------------------------------- H --------------------------------------------- R --------------------------------------------- N -----------------------Disk status after the command has been completed Status information after command execution
HDS DS1 DS0
Result
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PRELIMINARY
(5) Verify PHASE Command R/W W W W W W W W W Execution Result R R R R R R R -------------------- ST0 ------------------------------------------ ST1 ------------------------------------------ ST2 -------------------------------------------- C --------------------------------------------- H --------------------------------------------- R --------------------------------------------- N -----------------------Sector ID information after command execution D7 EC D6 0 D5 0 D4 1 0 D3 0 0 D2 1 D1 1 D0 0 REMARKS Command codes Sector ID information prior to command execution
MT MFM SK
HDS DS1 DS0
---------------------- C --------------------------------------------- H --------------------------------------------- R --------------------------------------------- N ------------------------------------------- EOT ------------------------------------------ GPL ------------------------------------------ DTL/SC -------------------
No data transfer takes place Status information after command execution
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PRELIMINARY
(6) Version PHASE Command Result (7) Write Data PHASE Command R/W W W W W W W W W W Execution Result R R R R R R R -------------------- ST0 ------------------------------------------ ST1 ------------------------------------------ ST2 -------------------------------------------- C --------------------------------------------- H --------------------------------------------- R --------------------------------------------- N -----------------------Sector ID information after Command execution D7 0 D6 0 D5 0 0 D4 0 0 D3 0 0 D2 1 D1 0 D0 1 REMARKS Command codes Sector ID information prior to Command execution R/W W R D7 0 1 D6 0 0 D5 0 0 D4 1 1 D3 0 0 D2 0 0 D1 0 0 D0 0 0 REMARKS Command code Enhanced controller
MT MFM
HDS DS1 DS0
---------------------- C --------------------------------------------- H --------------------------------------------- R --------------------------------------------- N ------------------------------------------- EOT ------------------------------------------ GPL ------------------------------------------ DTL -----------------------
Data transfer between the FDD and system Status information after Command execution
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PRELIMINARY
(8) Write Deleted Data PHASE Command R/W W W W W W W W W W Execution Result R R R R R R R -------------------- ST0 ------------------------------------------ ST1 ------------------------------------------ ST2 -------------------------------------------- C --------------------------------------------- H --------------------------------------------- R --------------------------------------------- N -----------------------Sector ID information after command execution D7 0 D6 0 D5 0 0 D4 0 0 D3 1 0 D2 0 D1 0 D0 1 REMARKS Command codes Sector ID information prior to command execution
MT MFM
HDS DS1 DS0
---------------------- C --------------------------------------------- H --------------------------------------------- R --------------------------------------------- N ------------------------------------------- EOT ------------------------------------------ GPL ------------------------------------------ DTL -----------------------
Data transfer between the FDD and system Status information after command execution
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PRELIMINARY
(9) Format A Track PHASE Command R/W W W W W W W Execution for Each Sector Repeat: Result W W W W R R R R R R R D7 0 0 D6 MFM 0 D5 0 0 D4 0 0 D3 1 0 D2 1 D1 0 D0 1 REMARKS Command codes Bytes/Sector Sectors/Cylinder Gap 3 Filler Byte Input Sector Parameters
HDS DS1 DS0
---------------------- N -------------------------------------------- SC ------------------------------------------- GPL ------------------------------------------ D --------------------------------------------- C --------------------------------------------- H --------------------------------------------- R --------------------------------------------- N ------------------------------------------- ST0 ------------------------------------------ ST1 ------------------------------------------ ST2 -------------------------------------- Undefined ---------------------------------- Undefined ---------------------------------- Undefined ---------------------------------- Undefined -------------------
Status information after command execution
(10) Recalibrate PHASE Command Execution R/W W W D7 0 0 D6 0 0 D5 0 0 D4 0 0 D3 0 0 D2 1 0 D1 1 D0 1 REMARKS Command codes Head retracted to Track 0 Interrupt
DS1 DS0
(11) Sense Interrupt Status PHASE Command Result R/W W R R D7 0 D6 0 D5 0 D4 0 D3 1 D2 0 D1 0 D0 0 REMARKS Command code Status information at the end of each seek operation
---------------- ST0 ---------------------------------------- PCN -------------------------
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(12) Specify PHASE Command R/W W W W (13) Seek PHASE Command R/W W W W Execution R D7 0 0 D6 0 0 D5 0 0 D4 0 0 D3 1 0 D2 1 D1 1 D0 1 REMARKS Command codes D7 0 D6 0 D5 0 D4 0 D3 0 D2 0 D1 1 D0 1 REMARKS Command codes
| ---------SRT ----------- | --------- HUT ---------- | |------------ HLT ----------------------------------| ND
HDS DS1 DS0 Head positioned over proper cylinder on diskette
-------------------- NCN -----------------------
(14) Configure PHASE Command R/W W W W W Execution D7 0 0 0 D6 0 0 D5 0 0 D4 1 0 D3 0 0 D2 0 0 D1 1 0 D0 1 0 REMARKS Configure information
EIS EFIFO POLL | ------ FIFOTHR ----| Internal registers written
| --------------------PRETRK ----------------------- |
(15) Relative Seek PHASE Command R/W W W W D7 1 0 D6 DIR 0 D5 0 0 D4 0 0 D3 1 0 D2 1 D1 1 D0 1 REMARKS Command codes
HDS DS1 DS0
| -------------------- RCN ---------------------------- |
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PRELIMINARY
(16) Dumpreg PHASE Command Result R/W W R R R R R R R R R R D7 0 D6 0 D5 0 D4 0 D3 1 D2 1 D1 1 D0 0 REMARKS Registers placed in FIFO
----------------------- PCN-Drive 0------------------------------------------ PCN-Drive 1 ----------------------------------------- PCN-Drive 2------------------------------------------ PCN-Drive 3 --------------------------SRT ------------------ | --------- HUT ------------------ HLT -----------------------------------| ND ------------------------ SC/EOT ---------------------LOCK 0 D3 D2 D1 D0 GAP WG 0 EIS EFIFO POLL | ------ FIFOTHR ------------------------------PRETRK -------------------------
(17) Perpendicular Mode PHASE Command (18) Lock PHASE Command Result R/W W R D7 0 D6 0 D5 0 0 D4 1 LOCK D3 0 0 D2 1 0 D1 0 0 D0 0 0 REMARKS Command Code LOCK 0 R/W W W D7 0 OW D6 0 0 D5 0 D3 D4 1 D2 D3 0 D1 D2 D1 D0 REMARKS Command Code 0 1 0 D0 GAP WG
(19) Sense Drive Status PHASE Command Result (20) Invalid PHASE Command R/W W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS Invalid codes (no operation- FDC goes to standby state) ST0 = 80H ------------- Invalid Codes ----------------R/W W W R D7 0 0 D6 0 0 D5 0 0 D4 0 0 D3 D2 D1 D0 REMARKS Command Code Status information about disk drive 0 1 0 0 0 HDS DS1 DS0
---------------- ST3 -------------------------
Result
R
-------------------- ST0 ----------------------
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PRELIMINARY
3.2 Register Descriptions
There are several status, data, and control registers in W83697HF. These registers are defined below: ADDRESS OFFSET base address + 0 base address + 1 base address + 2 base address + 3 base address + 4 base address + 5 base address + 7 READ SA REGISTER SB REGISTER TD REGISTER MS REGISTER DT (FIFO) REGISTER DI REGISTER REGISTER WRITE
DO REGISTER TD REGISTER DR REGISTER DT (FIFO) REGISTER CC REGISTER
3.2.1
Status Register A (SA Register) (Read base address + 0)
This register is used to monitor several disk interface pins in PS/2 and Model 30 modes. In PS/2 mode, the bit definitions for this register are as follows:
7 6 5 4 3 2 1 0
DIR WP INDEX HEAD TRAK0 STEP DRV2 INIT PENDING
INIT PENDING (Bit 7): This bit indicates the value of the floppy disk interrupt output. DRV2# (Bit 6): 0 A second drive has been installed 1 A second drive has not been installed STEP (Bit 5): This bit indicates the complement of STEP# output. TRAK0# (Bit 4): This bit indicates the value of TRAK0# input.
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PRELIMINARY
HEAD (Bit 3): This bit indicates the complement of HEAD# output. 0 side 0 1 side 1 INDEX# (Bit 2): This bit indicates the value of INDEX# output. WP# (Bit 1): 0 1 disk is write-protected disk is not write-protected
DIR (Bit 0) This bit indicates the direction of head movement. 0 1 outward direction inward direction
In PS/2 Model 30 mode, the bit definitions for this register are as follows:
7 6 5 4 3 2 1 0
DIR WP INDEX HEAD TRAK0 STEP F/F DRQ INIT PENDING
INIT PENDING (Bit 7): This bit indicates the value of the floppy disk interrupt output. DRQ (Bit 6): This bit indicates the value of DRQ output pin. STEP F/F (Bit 5): This bit indicates the complement of latched STEP# output. TRAK0 (Bit 4): This bit indicates the complement of TRAK0# input.
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PRELIMINARY
HEAD# (Bit 3): This bit indicates the value of HEAD# output. 0 1 side 1 side 0
INDEX (Bit 2): This bit indicates the complement of INDEX# output. WP (Bit 1): 0 1 disk is not write-protected disk is write-protected
DIR# (Bit 0) This bit indicates the direction of head movement. 0 1 inward direction outward direction
3.2.2
Status Register B (SB Register) (Read base address + 1)
This register is used to monitor several disk interface pins in PS/2 and Model 30 modes. In PS/2 mode, the bit definitions for this register are as follows:
7 1 6 1 MOT EN A MOT EN B WE RDATA Toggle WDATA Toggle Drive SEL0 5 4 3 2 1 0
Drive SEL0 (Bit 5): This bit indicates the status of DO REGISTER bit 0 (drive select bit 0). WDATA Toggle (Bit 4): This bit changes state at every rising edge of the WD# output pin. RDATA Toggle (Bit 3): This bit changes state at every rising edge of the RDATA# output pin. WE (Bit 2): This bit indicates the complement of the WE# output pin. MOT EN B (Bit 1) Publication Release Date: Aug 1999 Revision 0.40
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PRELIMINARY
This bit indicates the complement of the MOB# output pin. MOT EN A (Bit 0) This bit indicates the complement of the MOA# output pin. In PS/2 Model 30 mode, the bit definitions for this register are as follows:
7 6 5 4 3 2 1 0
DSC DSD WE F/F RDATA F/F WD F/F DSA DSB DRV2
DRV2# (Bit 7): 0 1 A second drive has been installed A second drive has not been installed
DSB# (Bit 6): This bit indicates the status of DSB# output pin. DSA# (Bit 5): This bit indicates the status of DSA# output pin. WD F/F(Bit 4): This bit indicates the complement of the latched WD# output pin at every rising edge of the WD# output pin. RDATA F/F(Bit 3): This bit indicates the complement of the latched RDATA# output pin . WE F/F (Bit 2): This bit indicates the complement of latched WE# output pin. DSD# (Bit 1): 0 Drive D has been selected 1 Drive D has not been selected DSC# (Bit 0): 0 Drive C has been selected 1 Drive C has not been selected
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3.2.3 Digital Output Register (DO Register) (Write base address + 2) The Digital Output Register is a write-only register controlling drive motors, drive selection, DRQ/IRQ enable, and FDC resetting. All the bits in this register are cleared by the MR pin. The bit definitions are as follows:
7 6 5 4 3 2 1-0 Drive Select: 00 select drive A 01 select drive B 10 select drive C 11 select drive D Floppy Disk Controller Reset Active low resets FDC DMA and INT Enable Active high enable DRQ/IRQ Motor Enable A. Motor A on when active high Motor Enable B. Motor B on when active high Motor Enable C. Motor C on when active high Motor Enable D. Motor D on when active high
3.2.4
Tape Drive Register (TD Register) (Read base address + 3)
This register is used to assign a particular drive number to the tape drive support mode of the data separator. This register also holds the media ID, drive type, and floppy boot drive information of the floppy disk drive. In normal floppy mode, this register includes only bit 0 and 1. The bit definitions are as follows:
7 X 6 X 5 X 4 X 3 X 2 X Tape sel 0 Tape sel 1 1 0
If three mode FDD function is enabled (EN3MODE = 1 in CR9), the bit definitions are as follows:
7 6 5 4 3 2 1 0
Tape Sel 0 Tape Sel 1 Floppy boot drive 0 Floppy boot drive 1 Drive type ID0 Drive type ID1 Media ID0 Media ID1
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Media ID1 Media ID0 (Bit 7, 6): These two bits are read only. These two bits reflect the value of CR8 bit 3, 2. Drive type ID1 Drive type ID0 (Bit 5, 4): These two bits reflect two of the bits of CR7. Which two bits are reflected depends on the last drive selected in the DO REGISTER. Floppy Boot drive 1, 0 (Bit 3, 2): These two bits reflect the value of CR8 bit 1, 0. Tape Sel 1, Tape Sel 0 (Bit 1, 0): These two bits assign a logical drive number to the tape drive. Drive 0 is not available as a tape drive and is reserved as the floppy disk boot drive. TAPE SEL 1 0 0 1 1 3.2.5 TAPE SEL 0 0 1 0 1 DRIVE SELECTED None 1 2 3
Main Status Register (MS Register) (Read base address + 4)
The Main Status Register is used to control the flow of data between the microprocessor and the controller. The bit definitions for this register are as follows:
7 6 5 4 3 2 1 0
FDD 0 Busy, (D0B = 1), FDD number 0 is in the SEEK mode. FDD 1 Busy, (D1B = 1), FDD number 1 is in the SEEK mode. FDD 2 Busy, (D2B = 1), FDD number 2 is in the SEEK mode. FDD 3 Busy, (D3B = 1), FDD number 3 is in the SEEK mode. FDC Busy, (CB). A read or write command is in the process when CB = HIGH. Non-DMA mode, the FDC is in the non-DMA mode, this bit is set only during the execution phase in non-DMA mode. Transition to LOW state indicates execution phase has ended. DATA INPUT/OUTPUT, (DIO). If DIO= HIGH then transfer is from Data Register to the processor. If DIO = LOW then transfer is from processor to Data Register. Request for Master (RQM). A high on this bit indicates Data Register is ready to send or receive data to or from the processor.
3.2.6
Data Rate Register (DR Register) (Write base address + 4)
The Data Rate Register is used to set the transfer rate and write precompensation. The data rate of the FDC is programmed by the CC REGISTER for PC-AT and PS/2 Model 30 and PS/2 mode, and not by the DR REGISTER. The real data rate is determined by the most recent write to either of the DR REGISTER or CC REGISTER.
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PRELIMINARY
7 6 5 0 DRATE0 DRATE1 PRECOMP0 PRECOMP1 PRECOMP2 POWER DOWN S/W RESET 4 3 2 1 0
S/W RESET (Bit 7): This bit is the software reset bit. POWER-DOWN (Bit 6): 0 FDC in normal mode 1 FDC in power-down mode PRECOMP2 PRECOMP1 PRECOMP0 (Bit 4, 3, 2): These three bits select the value of write precompensation. The following tables show the precompensation values for the combination of these bits. PRECOMP 2 0 0 0 0 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 PRECOMPENSATION DELAY 250K - 1 Mbps Default Delays 41.67 nS 83.34 nS 125.00 nS 166.67 nS 208.33 nS 250.00 nS 0.00 nS (disabled) 2 Mbps Tape drive Default Delays 20.8 nS 41.17 nS 62.5nS 83.3 nS 104.2 nS 125.00 nS 0.00 nS (disabled)
DATA RATE 250 KB/S 300 KB/S 500 KB/S 1 MB/S 2 MB/S
DEFAULT PRECOMPENSATION DELAYS 125 nS 125 nS 125 nS 41.67nS 20.8 nS
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PRELIMINARY
DRATE1 DRATE0 (Bit 1, 0): These two bits select the data rate of the FDC and reduced write current control. 00 500 KB/S (MFM), 250 KB/S (FM), RWC = 1 01 300 KB/S (MFM), 150 KB/S (FM), RWC = 0 10 250 KB/S (MFM), 125 KB/S (FM), RWC = 0 11 1 MB/S (MFM), Illegal (FM), RWC = 1 The 2 MB/S data rate for Tape drive is only supported by setting 01 to DRATE1 and DRATE0 bits, as well as setting 10 to DRT1 and DRT0 bits which are two of the Configure Register CRF4 or CRF5 bits in logic device 0. Please refer to the function description of CRF4 or CRF5 and data rate table for individual data rates setting. 3.2.7 FIFO Register (R/W base address + 5)
The Data Register consists of four status registers in a stack with only one register presented to the data bus at a time. This register stores data, commands, and parameters and provides diskette-drive status information. Data bytes are passed through the data register to program or obtain results after a command. In the W83697HF, this register defaults to FIFO disabled mode after reset. The FIFO can change its value and enable its operation through the CONFIGURE command. Status Register 0 (ST0)
7-6 5 4 3 2 1-0
US1, US0 Drive Select: 00 Drive A selected 01 Drive B selected 10 Drive C selected 11 Drive D selected HD Head address: 1 Head selected 0 Head selected NR Not Ready: 1 Drive is not ready 0 Drive is ready EC Equipment Check: 1 When a fault signal is received from the FDD or the track 0 signal fails to occur after 77 step pulses 0 No error SE Seek end: 1 seek end 0 seek error IC Interrupt Code: 00 Normal termination of command 01 Abnormal termination of command 10 Invalid command issue 11 Abnormal termination because the ready signal from FDD changed state during command execution
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PRELIMINARY
Status Register 1 (ST1)
7 6 5 4 3 2 1 0
Missing Address Mark. 1 When the FDC cannot detect the data address mark or the data address mark has been deleted. NW (Not Writable). 1 If a write Protect signal is detected from the diskette drive during execution of write data. ND (No DATA). 1 If specified sector cannot be found during execution of a read, write or verifly data. Not used. This bit is always 0. OR (Over Rum). 1 If the FDC is not serviced by the host system within a certain time interval during data transfer. DE (data Error).1 When the FDC detects a CRC error in either the ID field or the data field. Not used. This bit is always 0. EN (End of track). 1 When the FDC tries to access a sector beyond the final sector of a cylinder.
Status Register 2 (ST2)
7 6 5 4 3 2 1 0
MD (Missing Address Mark in Data Field). 1 If the FDC cannot find a data address mark (or the address mark has been deleted) when reading data from the media 0 No error BC (Bad Cylinder) 1 Bad Cylinder 0 No error SN (Scan Not satisfied) 1 During execution of the Scan command 0 No error SH (Scan Equal Hit) 1 During execution of the Scan command, if the equal condition is satisfied 0 No error WC (Wrong Cylinder) 1 Indicates wrong Cylinder DD (Data error in the Data field) 1 If the FDC detects a CRC error in the data field 0 No error CM (Control Mark) 1 During execution of the read data or scan command 0 No error Not used. This bit is always 0
Status Register 3 (ST3)
7 6 5 4 3 2 1 0
US0 Unit Select 0 US1 Unit Select 1 HD Head Address TS Two-Side TO Track 0 RY Ready WP Write Protected FT Fault
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3.2.8 Digital Input Register (DI Register) (Read base address + 7) The Digital Input Register is an 8-bit read-only register used for diagnostic purposes. In a PC/XT or AT only Bit 7 is checked by the BIOS. When the register is read, Bit 7 shows the complement of DSKCHG#, while other bits of the data bus remain in tri-state. Bit definitions are as follows:
7 6 5 4 3 2 1 0
x
x
x
x
xxx for hard disk controller x Reservedreadthe this register, these bits are in tri-state During a of
DSKCHG
In the PS/2 mode, the bit definitions are as follows:
7 6 1 5 1 4 1 3 1 HIGH DENS DRATE0 DRATE1 2 1 0
DSKCHG
DSKCHG (Bit 7): This bit indicates the complement of the DSKCHG# input. Bit 6-3: These bits are always a logic 1 during a read. DRATE1 DRATE0 (Bit 2, 1): These two bits select the data rate of the FDC. Refer to the DR register bits 1 and 0 for the settings corresponding to the individual data rates. HIGH DENS# (Bit 0): 0 500 KB/S or 1 MB/S data rate (high density FDD) 1 250 KB/S or 300 KB/S data rate In the PS/2 Model 30 mode, the bit definitions are as follows:
7 6 0 5 0 4 0 DRATE0 DRATE1 NOPREC DMAEN 3 2 1 0
DSKCHG
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DSKCHG (Bit 7): This bit indicates the status of DSKCHG# input. Bit 6-4: These bits are always a logic 1 during a read. DMAEN (Bit 3): This bit indicates the value of DO REGISTER bit 3. NOPREC (Bit 2): This bit indicates the value of CC REGISTER NOPREC bit. DRATE1 DRATE0 (Bit 1, 0): These two bits select the data rate of the FDC. 3.2.9 Configuration Control Register (CC Register) (Write base address + 7)
This register is used to control the data rate. In the PC/AT and PS/2 mode, the bit definitions are as follows:
7 6 5 4 3 2 1 0
x
x
x
x
x
x
DRATE0 DRATE1
X: Reserved Bit 7-2: Reserved. These bits should be set to 0. DRATE1 DRATE0 (Bit 1, 0): These two bits select the data rate of the FDC. In the PS/2 Model 30 mode, the bit definitions are as follows:
7 X 6 X 5 X 4 X 3 X DRATE0 DRATE1 NOPREC 2 1 0
X: Reserved Bit 7-3: Reserved. These bits should be set to 0. NOPREC (Bit 2): This bit indicates no precompensation. It has no function and can be set by software. DRATE1 DRATE0 (Bit 1, 0): These two bits select the data rate of the FDC.
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PRELIMINARY 4.
4.1
UART PORT
Universal Asynchronous Receiver/Transmitter (UART A, UART B)
The UARTs are used to convert parallel data into serial format on the transmit side and convert serial data to parallel format on the receiver side. The serial format, in order of transmission and reception, is a start bit, followed by five to eight data bits, a parity bit (if programmed) and one, one and half (five-bit format only) or two stop bits. The UARTs are capable of handling divisors of 1 to 65535 and producing a 16x clock for driving the internal transmitter logic. Provisions are also included to use this 16x clock to drive the receiver logic. The UARTs also support the MIDI data rate. Furthermore, the UARTs also include complete modem control capability and a processor interrupt system that may be software trailed to the computing time required to handle the communication link. The UARTs have a FIFO mode to reduce the number of interrupts presented to the CPU. In each UART, there are 16-byte FIFOs for both receive and transmit mode.
4.2
Register Address
4.2.1 UART Control Register (UCR) (Read/Write) The UART Control Register controls and defines the protocol for asynchronous data communications, including data length, stop bit, parity, and baud rate selection.
7 6 5 4 3 2 1 0
Data length select bit 0 (DLS0) Data length select bit 1(DLS1) Multiple stop bits enable (MSBE) Parity bit enable (PBE) Even parity enable (EPE) Parity bit fixed enable (PBFE) Set silence enable (SSE) Baudrate divisor latch access bit (BDLAB)
Bit 7: BDLAB. When this bit is set to a logical 1, designers can access the divisor (in 16-bit binary format) from the divisor latches of the baudrate generator during a read or write operation. When this bit is reset, the Receiver Buffer Register, the Transmitter Buffer Register, or the Interrupt Control Register can be accessed. Bit 6: SSE. A logical 1 forces the Serial Output (SOUT) to a silent state (a logical 0). Only IRTX is affected by this bit; the transmitter is not affected. Bit 5: PBFE. When PBE and PBFE of UCR are both set to a logical 1, (1) if EPE is logical 1, the parity bit is fixed as logical 0 to transmit and check. (2) if EPE is logical 0, the parity bit is fixed as logical 1 to transmit and check.
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TABLE 4-1 UART Register Bit Map Bit Number
Register Address Base +0 BDLAB = 0 Receiver Buffer Register (Read Only) Transmitter Buffer Register (Write Only) Interrupt Control Register RBR 0 RX Data Bit 0 1 RX Data Bit 1 2 RX Data Bit 2 3 RX Data Bit 3 4 RX Data Bit 4 5 RX Data Bit 5 6 RX Data Bit 6 7 RX Data Bit 7
+0 BDLAB = 0 +1 BDLAB = 0
TBR
TX Data Bit 0
TX Data Bit 1 TBR Empty Interrupt Enable (ETBREI) Interrupt Status Bit (0) RCVR FIFO Reset Data Length Select Bit 1 (DLS1) Request to Send (RTS) Overrun Error (OER) DSR Toggling (TDSR) Bit 1 Bit 1 Bit 9
TX Data Bit 2 USR Interrupt Enable (EUSRI) Interrupt Status Bit (1) XMIT FIFO Reset Multiple Stop Bits Enable (MSBE) Loopback RI Input Parity Bit Error (PBER) RI Falling Edge (FERI) Bit 2 Bit 2 Bit 10
TX Data Bit 3 HSR Interrupt Enable (EHSRI) Interrupt Status Bit (2)** DMA Mode Select Parity Bit Enable (PBE) IRQ Enable
TX Data Bit 4 0
TX Data Bit 5 0
TX Data Bit 6 0
TX Data Bit 7 0
ICR
RBR Data Ready Interrupt Enable (ERDRI) "0" if Interrupt Pending FIFO Enable
+2
Interrupt Status Register (Read Only) UART FIFO Control Register (Write Only) UART Control Register
ISR
0
0
FIFOs Enabled **
FIFOs Enabled ** RX Interrupt Active Level (MSB) Baudrate Divisor Latch Access Bit (BDLAB) 0
+2
UFR
Reserved
Reversed
RX Interrupt Active Level (LSB) Set Silence Enable (SSE) 0
+3
UCR
Data Length Select Bit 0 (DLS0) Data Terminal Ready (DTR) RBR Data Ready (RDR)
Even Parity Enable (EPE) Internal Loopback Enable Silent Byte Detected (SBD) Clear to Send (CTS) Bit 4 Bit 4 Bit 12
Parity Bit Fixed Enable PBFE) 0
+4
Handshake Control Register UART Status Register
HCR
+5
USR
No Stop Bit Error (NSER) DCD Toggling (TDCD) Bit 3 Bit 3 Bit 11
TBR Empty (TBRE) Data Set Ready (DSR) Bit 5 Bit 5 Bit 13
TSR Empty (TSRE) Ring Indicator (RI) Bit 6 Bit 6 Bit 14
RX FIFO Error Indication (RFEI) ** Data Carrier Detect (DCD) Bit 7 Bit 7 Bit 15
+6
Handshake Status Register User Defined Register Baudrate Divisor Latch Low Baudrate Divisor Latch High
HSR
CTS Toggling (TCTS) Bit 0 Bit 0 Bit 8
+7 +0 BDLAB = 1 +1 BDLAB = 1
UDR BLL BHL
*: Bit 0 is the least significant bit. The least significant bit is the first bit serially transmitted or received. **: These bits are always 0 in 16450 Mode.
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Bit 4: EPE. This bit describes the number of logic 1's in the data word bits and parity bit only when bit 3 is programmed. When this bit is set, an even number of logic 1's are sent or checked. When the bit is reset, an odd number of logic 1's are sent or checked. Bit 3: PBE. When this bit is set, the position between the last data bit and the stop bit of the SOUT will be stuffed with the parity bit at the transmitter. For the receiver, the parity bit in the same position as the transmitter will be detected. Bit 2: MSBE. This bit defines the number of stop bits in each serial character that is transmitted or received. (1) If MSBE is set to a logical 0, one stop bit is sent and checked. (2) If MSBE is set to a logical 1, and data length is 5 bits, one and a half stop bits are sent and checked. (3) If MSBE is set to a logical 1, and data length is 6, 7, or 8 bits, two stop bits are sent and checked. Bits 0 and 1: DLS0, DLS1. These two bits define the number of data bits that are sent or checked in each serial character.
TABLE 4-2 WORD LENGTH DEFINITION
DLS1 0 0 1 1
DLS0 0 1 0 1
DATA LENGTH 5 bits 6 bits 7 bits 8 bits
4.2.2 UART Status Register (USR) (Read/Write) This 8-bit register provides information about the status of the data transfer during communication.
7 6 5 4 3 2 1 0
RBR Data ready (RDR) Overrun error (OER) Parity bit error (PBER) No stop bit error (NSER) Silent byte detected (SBD) Transmitter Buffer Register empty (TBRE) Transmitter Shift Register empty (TSRE) RX FIFO Error Indication (RFEI)
Bit 7: RFEI. In 16450 mode, this bit is always set to a logic 0. In 16550 mode, this bit is set to a logic 1 when there is at least one parity bit error, no stop bit error or silent byte detected in the FIFO. In 16550 mode, this bit is cleared by reading from the USR if there are no remaining errors left in the FIFO.
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W83697HF/F
PRELIMINARY
Bit 6: TSRE. In 16450 mode, when TBR and TSR are both empty, this bit will be set to a logical 1. In 16550 mode, if the transmit FIFO and TSR are both empty, it will be set to a logical 1. Other thanthese two cases, this bit will be reset to a logical 0. Bit 5: TBRE. In 16450 mode, when a data character is transferred from TBR to TSR, this bit will be set to a logical 1. If ETREI of ICR is a logical 1, an interrupt will be generated to notify the CPU to write the next data. In 16550 mode, this bit will be set to a logical 1 when the transmit FIFO is empty. It will be reset to a logical 0 when the CPU writes data into TBR or FIFO. Bit 4: SBD. This bit is set to a logical 1 to indicate that received data are kept in silent state for a full word time, including start bit, data bits, parity bit, and stop bits. In 16550 mode, it indicates the same condition for the data on top of the FIFO. When the CPU reads USR, it will clear this bit to a logical 0. Bit 3: NSER. This bit is set to a logical 1 to indicate that the received data have no stop bit. In 16550 mode, it indicates the same condition for the data on top of the FIFO. When the CPU reads USR, it will clear this bit to a logical 0. Bit 2: PBER. This bit is set to a logical 1 to indicate that the parity bit of received data is wrong. In 16550 mode, it indicates the same condition for the data on top of the FIFO. When the CPU reads USR, it will clear this bit to a logical 0. Bit 1: OER. This bit is set to a logical 1 to indicate received data have been overwritten by the next received data before they were read by the CPU. In 16550 mode, it indicates the same condition instead of FIFO full. When the CPU reads USR, it will clear this bit to a logical 0. Bit 0: RDR. This bit is set to a logical 1 to indicate received data are ready to be read by the CPU in the RBR or FIFO. After no data are left in the RBR or FIFO, the bit will be reset to a logical 0.
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Publication Release Date: Aug 1999 Revision 0.40
W83697HF/F
PRELIMINARY
4.2.3
Handshake Control Register (HCR) (Read/Write)
This register controls the pins of the UART used for handshaking peripherals such as modem, and controls the diagnostic mode of the UART.
7 0 6 0 5 0 Data terminal ready (DTR) Request to send (RTS) Loopback RI input IRQ enable Internal loopback enable 4 3 2 1 0
Bit 4: When this bit is set to a logical 1, the UART enters diagnostic mode by an internal loopback, as follows: (1) SOUT is forced to logical 1, and SIN is isolated from the communication link instead of the TSR. (2) Modem output pins are set to their inactive state. (3) Modem input pins are isolated from the communication link and connect internally as DTR (bit 0 of HCR) DSR, RTS ( bit 1 of HCR) CTS, Loopback RI input ( bit 2 of HCR) RI and IRQ enable ( bit 3 of HCR) DCD. Aside from the above connections, the UART operates normally. This method allows the CPU to test the UART in a convenient way. Bit 3: The UART interrupt output is enabled by setting this bit to a logic 1. In the diagnostic mode this bit is internally connected to the modem control input DCD . Bit 2: This bit is used only in the diagnostic mode. In the diagnostic mode this bit is internally connected to the modem control input RI . Bit 1: This bit controls the RTS output. The value of this bit is inverted and output to RTS . Bit 0: This bit controls the DTR output. The value of this bit is inverted and output to DTR .
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Publication Release Date: Aug 1999 Revision 0.40
W83697HF/F
PRELIMINARY
4.2.4
Handshake Status Register (HSR) (Read/Write)
This register reflects the current state of four input pins for handshake peripherals such as a modem and records changes on these pins.
7 6 5 4 3 2 1 0
CTS toggling (TCTS) DSR toggling (TDSR) RI falling edge (FERI) DCD toggling (TDCD) Clear to send (CTS) Data set ready (DSR) Ring indicator (RI) Data carrier detect (DCD)
Bit 7: This bit is the opposite of the DCD input. This bit is equivalent to bit 3 of HCR in loopback mode. Bit 6: This bit is the opposite of the RI input. This bit is equivalent to bit 2 of HCR in loopback mode. Bit 5: This bit is the opposite of the DSR input. This bit is equivalent to bit 0 of HCR in loopback mode. Bit 4: This bit is the opposite of the CTS input. This bit is equivalent to bit 1 of HCR in loopback mode. Bit 3: TDCD. This bit indicates that the DCD pin has changed state after HSR was read by the CPU.
Bit 2: FERI. This bit indicates that the RI pin has changed from low to high state after HSR was read by the CPU. Bit 1: TDSR. This bit indicates that the DSR pin has changed state after HSR was read by the CPU. Bit 0: TCTS. This bit indicates that the CTS pin has changed state after HSR was read.
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Publication Release Date: Aug 1999 Revision 0.40
W83697HF/F
PRELIMINARY
4.2.5
UART FIFO Control Register (UFR) (Write only)
This register is used to control the FIFO functions of the UART.
7 6 5 4 3 2 1 0
FIFO enable Receiver FIFO reset Transmitter FIFO reset DMA mode select Reserved Reserved RX interrupt active level (LSB) RX interrupt active level (MSB)
Bit 6, 7: These two bits are used to set the active level for the receiver FIFO interrupt. For example, if the interrupt active level is set as 4 bytes, once there are more than 4 data characters in the receiver FIFO, the interrupt will be activated to notify the CPU to read the data from the FIFO. TABLE 4-3 FIFO TRIGGER LEVEL BIT 7 0 0 1 1 Bit 4, 5: Reserved Bit 3: When this bit is programmed to logic 1, the DMA mode will change from mode 0 to mode 1 if UFR bit 0 = 1. Bit 2: Setting this bit to a logical 1 resets the TX FIFO counter logic to initial state. This bit will clear to a logical 0 by itself after being set to a logical 1. Bit 1: Setting this bit to a logical 1 resets the RX FIFO counter logic to initial state. This bit will clear to a logical 0 by itself after being set to a logical 1. Bit 0: This bit enables the 16550 (FIFO) mode of the UART. This bit should be set to a logical 1 before other bits of UFR are programmed. BIT 6 0 1 0 1 RX FIFO INTERRUPT ACTIVE LEVEL (BYTES) 01 04 08 14
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Publication Release Date: Aug 1999 Revision 0.40
W83697HF/F
PRELIMINARY
4.2.6
Interrupt Status Register (ISR) (Read only)
This register reflects the UART interrupt status, which is encoded by different interrupt sources into 3 bits.
7 6 5 0 4 0 0 if interrupt pending Interrupt Status bit 0 Interrupt Status bit 1 Interrupt Status bit 2 FIFOs enabled FIFOs enabled 3 2 1 0
Bit 7, 6: These two bits are set to a logical 1 when UFR bit 0 = 1. Bit 5, 4: These two bits are always logic 0. Bit 3: In 16450 mode, this bit is 0. In 16550 mode, both bit 3 and 2 are set to a logical 1 when a timeout interrupt is pending. Bit 2, 1: These two bits identify the priority level of the pending interrupt, as shown in the table below. Bit 0: This bit is a logical 1 if there is no interrupt pending. If one of the interrupt sources has occurred, this bit will be set to a logical 0. TABLE 4-4 INTERRUPT CONTROL FUNCTION ISR
Bit 3 0 0 0 Bit 2 0 1 1 Bit 1 0 1 0 Bit 0 1 0 0 Interrupt priority First Second Interrupt Type UART Receive Status RBR Data Ready
INTERRUPT SET AND FUNCTION
Interrupt Source No Interrupt pending 1. OER = 1 2. PBER =1 Read USR 1. Read RBR 2. Read RBR until FIFO data under active level Read RBR 3. NSER = 1 4. SBD = 1 1. RBR data ready 2. FIFO interrupt active level reached Clear Interrupt -
1
1
0
0
Second
FIFO Data Timeout
Data present in RX FIFO for 4 characters period of time since last access of RX FIFO. TBR empty
0
0
1
0
Third
TBR Empty
1. Write data into TBR 2. Read ISR (if priority is third)
0
0
0
0
Fourth
Handshake status
1. TCTS = 1 3. FERI = 1
2. TDSR = 1 4. TDCD = 1
Read HSR
** Bit 3 of ISR is enabled when bit 0 of UFR is logical 1.
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W83697HF/F
PRELIMINARY
4.2.7 Interrupt Control Register (ICR) (Read/Write) This 8-bit register allows the five types of controller interrupts to activate the interrupt output signal separately. The interrupt system can be totally disabled by resetting bits 0 through 3 of the Interrupt Control Register (ICR). A selected interrupt can be enabled by setting the appropriate bits of this register to a logical 1.
7 0 6 0 5 0 4 0 RBR data ready interrupt enable (ERDRI) TBR empty interrupt enable (ETBREI) UART receive status interrupt enable (EUSRI) Handshake status interrupt enable (EHSRI) 3 2 1 0
Bit 7-4: These four bits are always logic 0. Bit 3: EHSRI. Setting this bit to a logical 1 enables the handshake status register interrupt. Bit 2: EUSRI. Setting this bit to a logical 1 enables the UART status register interrupt. Bit 1: ETBREI. Setting this bit to a logical 1 enables the TBR empty interrupt. Bit 0: ERDRI. Setting this bit to a logical 1 enables the RBR data ready interrupt.
4.2.8
Programmable Baud Generator (BLL/BHL) (Read/Write)
Two 8-bit registers, BLL and BHL, compose a programmable baud generator that uses 24 MHz to 16 generate a 1.8461 MHz frequency and divides it by a divisor from 1 to 2 -1. The output frequency of the baud generator is the baud rate multiplied by 16, and this is the base frequency for the transmitter and receiver. The table in the next page illustrates the use of the baud generator with a frequency of 1.8461 MHz. In high-speed UART mode (refer to CR0C bit7 and CR0C bit6), the programmable baud generator directly uses 24 MHz and the same divisor as the normal speed divisor. In highspeed mode, the data transmission rate can be as high as 1.5M bps.
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Publication Release Date: Aug 1999 Revision 0.40
W83697HF/F
PRELIMINARY
4.2.9
User-defined Register (UDR) (Read/Write)
This is a temporary register that can be accessed and defined by the user. TABLE 4-5 BAUD RATE TABLE BAUD RATE FROM DIFFERENT PRE-DIVIDER Pre-Div: 13 1.8461M Hz 50 75 110 134.5 150 300 600 1200 1800 2000 2400 3600 4800 7200 9600 19200 38400 57600 115200 Pre-Div:1.625 14.769M Hz 400 600 880 1076 1200 2400 4800 9600 14400 16000 19200 28800 38400 57600 76800 153600 307200 460800 921600 Pre-Div: 1.0 24M Hz 650 975 1430 1478.5 1950 3900 7800 15600 23400 26000 31200 46800 62400 93600 124800 249600 499200 748800 1497600 Decimal divisor used to generate 16X clock 2304 1536 1047 857 768 384 192 96 64 58 48 32 24 16 12 6 3 2 1 Error Percentage between desired and actual ** ** 0.18% 0.099% ** ** ** ** ** 0.53% ** ** ** ** ** ** ** ** **
** The percentage error for all baud rates, except where indicated otherwise, is 0.16%. Note. Pre-Divisor is determined by CRF0 of UART A and B.
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Publication Release Date: Aug 1999 Revision 0.40
W83697HF/F
PRELIMINARY 5. CIR RECEIVER PORT
5.1 CIR Registers
5.1.1 Bank0.Reg0 - Receiver Buffer Registers (RBR) (Read) Receiver Buffer Register is read only. When the CIR pulse train has been detected and passed by the internal signal filter, the data samped and shifted into shifter register will write into Receiver Buffer Register. In the CIR, this port is only supports PIO mode and the address port is defined in the PnP. 5.1.2 Bank0.Reg1 - Interrupt Control Register (ICR) Power on default <7:0> = 00000000 binary Bit 7 6-3 2 1 0 Name EN_GLBI Reserved EN_TMR_I En_LSR_I EN_RX_I Read/Write Read/Write Read/Write Read/Write Read/Write Description Enable Global Interrupt. Write 1, enable interrupt. Write 0, disable global interrupt. Reserved Enable Timer Interrupt. Enable Line-Status-Register interrupt. Receiver Thershold-Level Interrupt Enable.
5.1.3 Bank0.Reg2 - Interrupt Status Register (ISR) Power on default <7:0> = 00000000 binary Bit 7-3 2 Name Reserved TMR_I Read/Write Read Only Description Reserved Timer Interrupt. Set to 1 when timer count to 0. This bit will be affected by (1) the timer registers are defined in Bank4.Reg0 and Bank1.Reg0~1, (2) EN_TMR(Enable Timer, in Bank0.Reg3.Bit2) should be set to 1, (3) ENTMR_I (Enable Timer Interrupt, in Bank0.Reg1.Bit2) should be set to 1. Line-Status-Register interrupt. Set to 1 when overrun, or parity bit, or stop bit, or silent byte detected error in the Line Status Register (LSR) sets to 1. Clear to 0 when LSR is read. Receiver Thershold-Level Interrupt. Set to 1 when (1) the Receiver Buffer Register (RBR) is equal or larger than the threshold level, (2) RBR occurs time-out if the receiver buffer register has valid data and below the threshold level. Clear to 0 when RBR is less than threshold level from reading RBR.
1
LSR_I
Read Only
0
RXTH_I
Read Only
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Publication Release Date: Aug 1999 Revision 0.40
W83697HF/F
PRELIMINARY
5.1.4 Bank0~3.Reg3 - CIR Control Register 0/Bank Select Register (CTR0/BSR) (BANK0~3) Power on default <7:0> = 00000000 binary Bit 7-6 Name BNK_SEL<1:0> Read/Write Read/Write Description Bank Select Register. These two bits are shared same address so that Bank Select Register (BSR) can be programmed to desired Bank in any Bank. BNK_SEL<1:0> = 00 Select Bank 0. BNK_SEL<1:0> = 01 Select Bank 1. BNK_SEL<1:0> = Reserved. BNK_SEL<1:0> = Reserved. Receiver FIFO Threshold Level. It is to determine the RXTH_I to become 1 when the Receiver FIFO Threshold Level is equal or larger than the defined value shown as follow. RXFTL<1:0> = 00 -- 1 byte RXFTL<1:0> = 01 -- 4 bytes RXFTL<1:0> = 10 -- 8 bytes RXFTL<1:0> = 11 -- 14 bytes Timer Test. Write to 1, then reading the TMRL/TMRH will return the programmed values of TMRL/TMRH, that is, does not return down count counter value. This bit is for test timer register. Enable timer. Write to 1, enable the timer Setting this bit to a logical 1 resets the RX FIFO counter logic to initial state. This bit will clear to a logical 0 by itself after being set to a logical 1. Timer input clock. Winbond test register
5-4
RXFTL1/0
Read/Write
3
TMR_TST
Read/Write
2 1
EN_TMR RXF_RST
Read/Write Read/Write
0
TMR_CLK
Read/Write
5.1.5 Bank0.Reg4 - CIR Control Register (CTR) Power on default <7:0> = 0010,1001 binary Bit 7-5 Name RX_FR<2:0> Read/Write Read/Write Description Receiver Frequency Range 2~0. These bits select the input frequency of the receiver ranges. For the input signal, that is through a band pass filter, i.e., the frequency of the input signal is located at this defined range then the signal will be received. Receiver Frequency Select 4~0. Select the receiver operation frequency.
4-0
RX_FSL<4:0>
Read/Write
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PRELIMINARY
Table: Low Frequency range select of receiver.
RX_FR2~0 (Low Frequency) 001 RX_FSL4~0 00010 00011 00100 00101 00110 00111 01000 01001 01011 01100 01101 01111 10000 10010 10011 10101 10111 11010 11011 11101 Min. 26.1 28.2 29.4 30.0 31.4 32.1 32.8 33.6* 34.4 36.2 37.2 38.2 40.3 41.5 42.8 44.1 45.5 48.7 50.4 54.3 Max. 29.6 32.0 33.3 34.0 35.6 36.4 37.2 38.1* 39.0 41.0 42.1 43.2 45.7 47.1 48.5 50.0 51.6 55.2 57.1 61.5 Min. 24.7 26.7 27.8 28.4 29.6 30.3 31.0 31.7 32.5 34.2 35.1 36.0 38.1 39.2 40.4 41.7 43.0 46.0 47.6 51.3 010 Max. 31.7 34.3 35.7 36.5 38.1 39.0 39.8 40.8 41.8 44.0 45.1 46.3 49.0 50.4 51.9 53.6 55.3 59.1 61.2 65.9 Min. 23.4 25.3 26.3 26.9 28.1 28.7 29.4 30.1 30.8 32.4 33.2 34.1 36.1 37.2 38.3 39.5 40.7 43.6 45.1 48.6 011 Max. 34.2 36.9 38.4 39.3 41.0 42.0 42.9 44.0 45.0 47.3 48.6 49.9 52.7 54.3 56.0 57.7 59.6 63.7 65.9 71.0
Note that the other non-defined values are reserved.
5.1.6 Bank0.Reg5 - UART Line Status Register (USR) Power on default <7:0> = 0000,0000 binary Bit 7-3 2 1 0 Name Reserved RX_TO OV_ERR RDR Read/Write Read/Write Read/Write Read/Write Set to 1 when receiver FIFO or frame status FIFO occurs time-out. Read this bit will be cleared. Received FIFO overrun. Read to clear. This bit is set to a logical 1 to indicate received data are ready to be read by the CPU in the RBR or FIFO. After no data are left in the RBR or FIFO, the bit will be reset to a logical 0. Description
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Publication Release Date: Aug 1999 Revision 0.40
W83697HF/F
PRELIMINARY
5.1.7 Bank0.Reg6 - Remote Infrared Config Register (RIR_CFG) Power on default <7:0> = 0000,0000 binary Bit 7-6 Name SMPSEL<1:0> Read/Write Read/Write Description Sampling Mode Select. Select internal decoder methodology from the internal filter. Selected decoder mode will determine the receive data format. The sampling mode is shown as bellow: SMPSEL<1:0> = 00 T-Period Sample Mode. SMPSEL<1:0> = 01 Over-Sampling Mode. SMPSEL<1:0> = 10 Over-Sampling with re-sync. SMPSEL<1:0> = 11 FIFO Test Mode. The T-period code format is defined as follows. (Number of bits) - 1
B7 B6 B5 B4 B3 B2 B1 B0
Bit value
5-4
LP_SL<1:0>
Read/Write
3-2
RXDMSL<1:0>
Read/Write
1
PRE_DIV
Read/Write
0
RXINV
Read/Write
The Bit value is set to 0, then the high pulse will be received. The Bit value is set to 1, then no energy will be received. The opposite results will be generated when the bit RXINV (Bank0.Reg6.Bit0) is set to 1. Low pass filter source selcetion. LP_SL<1:0> = 00 Select raw IRRX signal. LP_SL<1:0> = 01 Select R.B.P. signal LP_SL<1:0> = 10 Select D.B.P. signal. LP_SL<1:0> = 11 Reserved. Receiver Demodulation Source Selection. RXDMSL<1:0> = 00 select B.P. and L.P. filter. RXDMSL<1:0> = 01 select B.P. but not L.P. RXDMSL<1:0> = 10 Reserved. RXDMSL<1:0> = 11 do not pass demodulation. Baud Rate Pre-divisor. Set to 1, the baud rate generator input clock is set to 1.8432M Hz which is set to predivisor into 13. When set to 0, the pre-divisor is set to 1, that is, the input clock of baud rate generator is set to 24M Hz. Receiving Signal Invert. Write to 1, Invert the receiving signal.
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Publication Release Date: Aug 1999 Revision 0.40
W83697HF/F
PRELIMINARY
5.1.8 Bank0.Reg7 - User Defined Register (UDR/AUDR) Power on default <7:0> = 0000,0000 binary Bit 7 Name RXACT Read/Write Read/Write Description Receive Active. Set to 1 whenever a pulse or pulse-train is detected by the receiver. If a 1 is written into the bit position, the bit is cleared and the receiver is de-actived. When this bit is set, the receiver samples the IR input continuously at the programmed baud rate and transfers the data to the receiver FIFO. Set to 1 whenever a pulse or pulse-train (modulated pulse) is detected by the receiver. Can be used by the sofware to detect idle condition Cleared Upon Read. FIFO Level Value. Indicate that how many bytes are there in the current received FIFO. Can read these bits then get the FIFO level value and successively read RBR by the prior value.
6
RX_PD
Read Only
5 4-0
Reserved FOLVAL
Read Only
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Publication Release Date: Aug 1999 Revision 0.40
W83697HF/F
PRELIMINARY
5.1.9 Bank1.Reg0~1 - Baud Rate Divisor Latch (BLL/BHL) The two registers of BLL and BHL are baud rate divisor latch in the legacy UART/SIR/ASK-IR mode. Read/Write these registers, if set in Advanced UART mode, will occur backward operation, that is, will go to legacy UART mode and clear some register values shown table as follows. TABLE :BAUD RATE TABLE BAUD RATE USING 24 MHZ TO GENERATE 1.8461 MHZ Desired Baud Rate 50 75 110 134.5 150 300 600 1200 1800 2000 2400 3600 4800 7200 9600 19200 38400 57600 115200 1.5M 1 Decimal divisor used to generate 16X clock 2304 1536 1047 857 768 384 192 96 64 58 48 32 24 16 12 6 3 2 1
Note 1
Percent error difference between desired and actual ** ** 0.18% 0.099% ** ** ** ** ** 0.53% ** ** ** ** ** ** ** ** ** 0%
Note 1: Only use in high speed mode, when Bank0.Reg6.Bit7 is set. ** The percentage error for all baud rates, except where indicated otherwise, is 0.16%
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Publication Release Date: Aug 1999 Revision 0.40
W83697HF/F
PRELIMINARY
5.1.10 Bank1.Reg2 - Version ID Regiister I (VID) Power on default <7:0> = 0001,0000 binary Bit 7-0 VID Name Read/Write Read Only Description Version ID, default is set to 0x10.
5.1.11 Bank0~3.Reg3 - CIR Control Register 0/Bank Select Register (CTR0/BSR) (BANK0~3) This register is defined same as in Bank0.Reg3.
5.1.12 Bank1.Reg4 - Timer Low Byte Register (TMRL) Power on default <7:0> = 0000,0000 binary Bit 7-0 TMRL Name Read/Write Read/Write Description Timer Low Byte Register. This is a 12-bit timer (another 4-bit is defined in Bank1.Reg5) which resolution is 1 ms, 12 that is, the programmed maximum time is 2 -1 ms. The timer is a down-counter. The timer start down count when the bit EN_TMR (Enable Timer) of Bank0.Reg2. is set to 1. When the timer down count to zero and EN_TMR=1, the TMR_I is set to 1. When the counter down count to zero, a new initial value will be re-loaded into timer counter.
5.1.13 Bank1.Reg5 - Timer High Byte Register (TMRH) Power on default <7:0> = 0000,0000 binary Bit 7-4 3-0 Name Reserved TMRH Read/Write Read/Write Description Reserved. Timer High Byte Register. See Bank1.Reg4.
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Publication Release Date: Aug 1999 Revision 0.40
W83697HF/F
PRELIMINARY 6. PARALLEL PORT
6.1 Printer Interface Logic
The parallel port of the W83627HF makes possible the attachment of various devices that accept eight bits of parallel data at standard TTL level. The W83627HF supports an IBM XT/AT compatible parallel port (SPP), bi-directional parallel port (BPP), Enhanced Parallel Port (EPP), Extended Capabilities Parallel Port (ECP), Extension FDD mode (EXTFDD), Extension 2FDD mode (EXT2FDD) on the parallel port. Refer to the configuration registers for more information on disabling, power-down, and on selecting the mode of operation. Table 6-1 shows the pin definitions for different modes of the parallel port.
TABLE 6-1-1 PARALLEL PORT CONNECTOR AND PIN DEFINITIONS HOST CONNECTOR 1 2-9 10 11 12 13 14 15 16 17 Notes: n : Active Low 1. Compatible Mode 2. High Speed Mode 3. For more information, refer to the IEEE 1284 standard. PIN NUMBER OF W83627HF 36 31-26, 24-23 22 21 19 18 35 34 33 32 PIN ATTRIBUTE O I/O I I I I O I O O SPP nSTB PD<0:7> nACK BUSY PE SLCT nAFD nERR nINIT nSLIN EPP nWrite PD<0:7> Intr nWait PE Select nDStrb nError nInit nAStrb ECP nSTB, HostClk 2 PD<0:7> nACK, PeriphClk2 BUSY, PeriphAck2 PEerror, nAckReverse2 SLCT, Xflag2 nAFD, HostAck2 nFault1, nPeriphRequest2 nINIT1, nReverseRqst2 nSLIN1 , ECPMode2
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PRELIMINARY
TABLE 6-1-2 PARALLEL PORT CONNECTOR AND PIN DEFINITIONS HOST CONNECTOR 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 PIN NUMBER OF W83627HF 36 31 30 29 28 27 26 24 23 22 21 19 18 35 34 33 32 PIN ATTRIBUTE O I/O I/O I/O I/O I/O I/O I/O I/O I I I I O I O O SPP nSTB PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 nACK BUSY PE SLCT nAFD nERR nINIT nSLIN PIN ATTRIBUTE --I I I I I --OD OD OD OD OD OD OD OD OD OD EXT2FDD --INDEX2# TRAK02# WP2# RDATA2# DSKCHG2# --MOA2# DSA2# DSB2# MOB2# WD2# WE2# RWC2# HEAD2# DIR2# STEP2# PIN ATTRIBUTE --I I I I I ------OD OD OD OD OD OD OD OD EXTFDD --INDEX2# TRAK02# WP2# RDATA2# DSKCHG2# ------DSB2# MOB2# WD2# WE2# RWC2# HEAD2# DIR2# STEP2#
6.2 Enhanced Parallel Port (EPP)
TABLE 6-2 PRINTER MODE AND EPP REGISTER ADDRESS A2 0 0 0 0 0 1 1 1 1 A1 0 0 1 1 1 0 0 1 1 A0 0 1 0 0 1 0 1 0 1 REGISTER Data port (R/W) Printer status buffer (Read) Printer control latch (Write) Printer control swapper (Read) EPP address port (R/W) EPP data port 0 (R/W) EPP data port 1 (R/W) EPP data port 2 (R/W) EPP data port 2 (R/W) NOTE 1 1 1 1 2 2 2 2 2
Notes: 1. These registers are available in all modes. 2. These registers are available only in EPP mode.
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PRELIMINARY
6.2.1 Data Swapper The system microprocessor can read the contents of the printer's data latch by reading the data swapper.
6.2.2 Printer Status Buffer The system microprocessor can read the printer status by reading the address of the printer status buffer. The bit definitions are as follows:
7 6 5 4 3 2 1 1 1 TMOUT ERROR SLCT PE ACK BUSY 0
Bit 7: This signal is active during data entry, when the printer is off-line during printing, when the print head is changing position, or during an error state. When this signal is active, the printer is busy and cannot accept data. Bit 6: This bit represents the current state of the printer's ACK# signal. A 0 means the printer has received a character and is ready to accept another. Normally, this signal will be active for approximately 5 microseconds before BUSY# stops. Bit 5: Logical 1 means the printer has detected the end of paper. Bit 4: Logical 1 means the printer is selected. Bit 3: Logical 0 means the printer has encountered an error condition. Bit 1, 2: These two bits are not implemented and are logic one during a read of the status register. Bit 0: This bit is valid in EPP mode only. It indicates that a 10 S time-out has occurred on the EPP bus. A logic 0 means that no time-out error has occurred; a logic 1 means that a time-out error has been detected. Writing a logic 1 to this bit will clear the time-out status bit; writing a logic 0 has no effect.
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Publication Release Date: Aug 1999 Revision 0.40
W83697HF/F
PRELIMINARY
6.2.3 Printer Control Latch and Printer Control Swapper The system microprocessor can read the contents of the printer control latch by reading the printer control swapper. Bit definitions are as follows:
7 1 6 1 STROBE AUTO FD INIT SLCT IN IRQ ENABLE DIR 5 4 3 2 1 0
Bit 7, 6: These two bits are a logic one during a read. They can be written. Bit 5: Direction control bit When this bit is a logic 1, the parallel port is in input mode (read); when it is a logic 0, the parallel port is in output mode (write). This bit can be read and written. In SPP mode, this bit is invalid and fixed at zero. Bit 4: A 1 in this position allows an interrupt to occur when ACK# changes from low to high. Bit 3: A 1 in this bit position selects the printer. Bit 2: A 0 starts the printer (50 microsecond pulse, minimum). Bit 1: A 1 causes the printer to line-feed after a line is printed. Bit 0: A 0.5 microsecond minimum high active pulse clocks data into the printer. Valid data must be present for a minimum of 0.5 microseconds before and after the strobe pulse.
6.2.4 EPP Address Port The address port is available only in EPP mode. Bit definitions are as follows:
7 6 5 4 3 2 1 0
PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7
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PRELIMINARY
The contents of DB0-DB7 are buffered (non-inverting) and output to ports PD0-PD7 during a write operation. The leading edge of IOW# causes an EPP address write cycle to be performed, and the trailing edge of IOW# latches the data for the duration of the EPP write cycle. PD0-PD7 ports are read during a read operation. The leading edge of IOR# causes an EPP address read cycle to be performed and the data to be output to the host CPU.
6.2.5 EPP Data Port 0-3 These four registers are available only in EPP mode. Bit definitions of each data port are as follows:
7 6 5 4 3 2 1 0
PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7
When accesses are made to any EPP data port, the contents of DB0-DB7 are buffered (noninverting) and output to the ports PD0-PD7 during a write operation. The leading edge of IOW# causes an EPP data write cycle to be performed, and the trailing edge of IOW# latches the data for the duration of the EPP write cycle. During a read operation, ports PD0-PD7 are read, and the leading edge of IOR# causes an EPP read cycle to be performed and the data to be output to the host CPU. 6.2.6 Bit Map of Parallel Port and EPP Registers
REGISTER Data Port (R/W) Status Buffer (Read) Control Swapper (Read) Control Latch (Write) EPP Address Port R/W) EPP Data Port 0 (R/W) EPP Data Port 1 (R/W) EPP Data Port 2 (R/W) EPP Data Port 3 (R/W)
7 PD7 BUSY# 1 1 PD7 PD7 PD7 PD7 PD7
6 PD6 ACK# 1 1 PD6 PD6 PD6 PD6 PD6
5 PD5 PE 1 DIR PD5 PD5 PD5 PD5 PD5
4 PD4 SLCT IRQEN IRQ PD4 PD4 PD4 PD4 PD4
3 PD3
ERROF#
2 PD2 1 INIT# INIT# PD2 PD2 PD2 PD2 PD2
1 PD1 1 AUTOFD# AUTOFD# PD1 PD1 PD1 PD1 PD1
0 PD0 TMOUT STROBE# STROBE# PD0 PD0 PD0 PD0 PD0
SLIN SLIN PD3 PD3 PD3 PD3 PD3
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PRELIMINARY
6.2.7 EPP Pin Descriptions EPP NAME nWrite PD<0:7> Intr nWait PE Select nDStrb nError nInits nAStrb TYPE O I/O I I I I O I O O EPP DESCRIPTION Denotes an address or data read or write operation. Bi-directional EPP address and data bus. Used by peripheral device to interrupt the host. Inactive to acknowledge that data transfer is completed. Active to indicate that the device is ready for the next transfer. Paper end; same as SPP mode. Printer selected status; same as SPP mode. This signal is active low. It denotes a data read or write operation. Error; same as SPP mode. This signal is active low. When it is active, the EPP device is reset to its initial operating mode. This signal is active low. It denotes an address read or write operation.
6.2.8 EPP Operation When the EPP mode is selected in the configuration register, the standard and bi-directional modes are also available. The PDx bus is in the standard or bi-directional mode when no EPP read, write, or address cycle is currently being executed. In this condition all output signals are set by the SPP Control Port and the direction is controlled by DIR of the Control Port. A watchdog timer is required to prevent system lockup. The timer indicates that more than 10 S have elapsed from the start of the EPP cycle to the time WAIT# is deasserted. The current EPP cycle is aborted when a time-out occurs. The time-out condition is indicated in Status bit 0. 6.2.8.1 EPP Operation The EPP operates on a two-phase cycle. First, the host selects the register within the device for subsequent operations. Second, the host performs a series of read and/or write byte operations to the selected register. Four operations are supported on the EPP: Address Write, Data Write, Address Read, and Data Read. All operations on the EPP device are performed asynchronously. 6.2.8.2 EPP Version 1.9 Operation The EPP read/write operation can be completed under the following conditions: a. If the nWait is active low, when the read cycle (nWrite inactive high, nDStrb/nAStrb active low) or write cycle (nWrite active low, nDStrb/nAStrb active low) starts, the read/write cycle proceeds normally and will be completed when nWait goes inactive high. b. If nWait is inactive high, the read/write cycle will not start. It must wait until nWait changes to active low, at which time it will start as described above. 6.2.8.3 EPP Version 1.7 Operation The EPP read/write cycle can start without checking whether nWait is active or inactive. Once the read/write cycle starts, however, it will not terminate until nWait changes from active low to inactive high.
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6.3 Extended Capabilities Parallel (ECP) Port This port is software and hardware compatible with existing parallel ports, so it may be used as a
standard printer mode if ECP is not required. It provides an automatic high burst-bandwidth channel that supports DMA for ECP in both the forward (host to peripheral) and reverse (peripheral to host) directions. Small FIFOs are used in both forward and reverse directions to improve the maximum bandwidth requirement. The size of the FIFO is 16 bytes. The ECP port supports an automatic handshake for the standard parallel port to improve compatibility mode transfer speed. The ECP port supports run-length-encoded (RLE) decompression (required) in hardware. Compression is accomplished by counting identical bytes and transmitting an RLE byte that indicates how many times the next byte is to be repeated. Hardware support for compression is optional. For more information about the ECP Protocol, refer to the Extended Capabilities Port Protocol and ISA Interface Standard. 6.3.1 ECP Register and Mode Definitions NAME data ecpAFifo dsr dcr cFifo ecpDFifo tFifo cnfgA cnfgB ecr ADDRESS Base+000h Base+000h Base+001h Base+002h Base+400h Base+400h Base+400h Base+400h Base+401h Base+402h I/O R/W R/W R R/W R/W R/W R/W R R/W R/W ECP MODES 000-001 011 All All 010 011 110 111 111 All FUNCTION Data Register ECP FIFO (Address) Status Register Control Register Parallel Port Data FIFO ECP FIFO (DATA) Test FIFO Configuration Register A Configuration Register B Extended Control Register
Note: The base addresses are specified by CR23, which are determined by configuration register or hardware setting.
MODE 000 001 010 011 100 101 110 111 SPP mode PS/2 Parallel Port mode Parallel Port Data FIFO mode
DESCRIPTION
ECP Parallel Port mode EPP mode (If this option is enabled in the CR9 and CR0 to select ECP/EPP mode) Reserved Test mode Configuration mode
Note: The mode selection bits are bit 7-5 of the Extended Control Register.
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6.3.2 Data and ecpAFifo Port Modes 000 (SPP) and 001 (PS/2) (Data Port) During a write operation, the Data Register latches the contents of the data bus on the rising edge of the input. The contents of this register are output to the PD0-PD7 ports. During a read operation, ports PD0-PD7 are read and output to the host. The bit definitions are as follows:
7 6 5 4 3 2 1 0
PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7
Mode 011 (ECP FIFO-Address/RLE) A data byte written to this address is placed in the FIFO and tagged as an ECP Address/RLE. The hardware at the ECP port transmits this byte to the peripheral automatically. The operation of this register is defined only for the forward direction. The bit definitions are as follows:
7 6 5 4 3 2 1 0
Address or RLE
Address/RLE
6.3.3 Device Status Register (DSR) These bits are at low level during a read of the Printer Status Register. The bits of this status register are defined as follows:
7 6 5 4 3 2 1 1 1 0 1
nFault Select PError nAck nBusy
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Bit 7: This bit reflects the complement of the Busy input. Bit 6: This bit reflects the nAck input. Bit 5: This bit reflects the PError input. Bit 4: This bit reflects the Select input. Bit 3: This bit reflects the nFault input. Bit 2-0: These three bits are not implemented and are always logic one during a read.
6.3.4 Device Control Register (DCR) The bit definitions are as follows:
7 1 6 1 strobe autofd nInit SelectIn ackIntEn Direction 5 4 3 2 1 0
Bit 6, 7: These two bits are logic one during a read and cannot be written. Bit 5: This bit has no effect and the direction is always out if mode = 000 or mode = 010. Direction is valid in all other modes. 0 the parallel port is in output mode. 1 the parallel port is in input mode. Bit 4: Interrupt request enable. When this bit is set to a high level, it may be used to enable interrupt requests from the parallel port to the CPU due to a low to high transition on the ACK# input. Bit 3: This bit is inverted and output to the SLIN# output. 0 The printer is not selected. 1 The printer is selected. Bit 2: This bit is output to the INIT# output. Bit 1: This bit is inverted and output to the AFD# output. Bit 0: This bit is inverted and output to the STB# output.
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6.3.5 cFifo (Parallel Port Data FIFO) Mode = 010 This mode is defined only for the forward direction. The standard parallel port protocol is used by a hardware handshake to the peripheral to transmit bytes written or DMAed from the system to this FIFO. Transfers to the FIFO are byte aligned. 6.3.6 ecpDFifo (ECP Data FIFO) Mode = 011 When the direction bit is 0, bytes written or DMAed from the system to this FIFO are transmitted by a hardware handshake to the peripheral using the ECP parallel port protocol. Transfers to the FIFO are byte aligned. When the direction bit is 1, data bytes from the peripheral are read under automatic hardware handshake from ECP into this FIFO. Reads or DMAs from the FIFO will return bytes of ECP data to the system. 6.3.7 tFifo (Test FIFO Mode) Mode = 110 Data bytes may be read, written, or DMAed to or from the system to this FIFO in any direction. Data in the tFIFO will not be transmitted to the parallel port lines. However, data in the tFIFO may be displayed on the parallel port data lines. 6.3.8 cnfgA (Configuration Register A) Mode = 111 This register is a read-only register. When it is read, 10H is returned. This indicates to the system that this is an 8-bit implementation. 6.3.9 cnfgB (Configuration Register B) Mode = 111
The bit definitions are as follows: 7 6 5 4 3 2 1 1 1 0 1
IRQx 0 IRQx 1 IRQx 2 intrValue compress Bit 7: This bit is read-only. It is at low level during a read. This means that this chip does not support hardware RLE compression. Bit 6: Returns the value on the ISA IRQ line to determine possible conflicts.
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Bit 5-3: Reflect the IRQ resource assigned for ECP port. cnfgB[5:3] IRQ resource 000 reflect other IRQ resources selected by PnP register (default) 001 IRQ7 010 IRQ9 011 IRQ10 100 IRQ11 101 IRQ14 110 IRQ15 111 IRQ5 Bit 2-0: These five bits are at high level during a read and can be written. 6.3.10 ecr (Extended Control Register) Mode = all This register controls the extended ECP parallel port functions. The bit definitions are follows:
7 6 5 4 3 2 1 0
empty full service Intr dmaEn nErrIntrEn MODE MODE MODE
Bit 7-5: These bits are read/write and select the mode. 000 001 Standard Parallel Port mode. The FIFO is reset in this mode. PS/2 Parallel Port mode. This is the same as 000 except that direction may be used to tri-state the data lines and reading the data register returns the value on the data lines and not the value in the data register. Parallel Port FIFO mode. This is the same as 000 except that bytes are written or DMAed to the FIFO. FIFO data are automatically transmitted using the standard parallel port protocol. This mode is useful only when direction is 0. ECP Parallel Port Mode. When the direction is 0 (forward direction), bytes placed into the ecpDFifo and bytes written to the ecpAFifo are placed in a single FIFO and auto transmitted to the peripheral using ECP Protocol. When the direction is 1 (reverse direction), bytes are moved from the ECP parallel port and packed into bytes in the ecpDFifo. Selects EPP Mode. In this mode, EPP is activated if the EPP mode is selected. Reserved. Test Mode. The FIFO may be written and read in this mode, but the data will not be transmitted on the parallel port. Configuration Mode. The confgA and confgB registers are accessible at 0x400 and 0x401 in this mode. Publication Release Date: Aug 1999 Revision 0.40
010
011
100 101 110 111
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Bit 4: Read/Write (Valid only in ECP Mode) 1 Disables the interrupt generated on the asserting edge of nFault. 0 Enables an interrupt pulse on the high to low edge of nFault. If nFault is asserted (interrupt) an interrupt will be generated and this bit is written from a 1 to 0. Bit 3: Read/Write 1 Enables DMA. 0 Disables DMA unconditionally. Bit 2: Read/Write 1 Disables DMA and all of the service interrupts. 0 Enables one of the following cases of interrupts. When one of the service interrupts has occurred, the serviceIntr bit is set to a 1 by hardware. This bit must be reset to 0 to re-enable the interrupts. Writing a 1 to this bit will not cause an interrupt. (a) dmaEn = 1: During DMA this bit is set to a 1 when terminal count is reached. (b) dmaEn = 0 direction = 0: This bit is set to 1 whenever there are writeIntr Threshold or more bytes free in the FIFO. (c) dmaEn = 0 direction = 1: This bit is set to 1 whenever there are readIntr Threshold or more valid bytes to be read from the FIFO. Bit 1: Read only 0 The FIFO has at least 1 free byte. 1 The FIFO cannot accept another byte or the FIFO is completely full. Bit 0: Read only 0 The FIFO contains at least 1 byte of data. 1 The FIFO is completely empty. 6.3.11 Bit Map of ECP Port Registers D7 data ecpAFifo dsr dcr cFifo ecpDFifo tFifo cnfgA cnfgB ecr
PD7 Addr/RLE nBusy 1
D6
PD6
D5
PD5
D4
PD4
D3
PD3
D2
PD2
D1
PD1
D0
PD0
NOTE
2
Address or RLE field nAck 1 PError Directio Select ackIntEn nFault SelectIn 1 nInit 1 autofd 1 strobe
1 1 2 2 2
Parallel Port Data FIFO ECP Data FIFO Test FIFO 0 compress 0 intrValue MODE 0 1 1 1 nErrIntrEn 0 1 dmaEn 0 1 serviceIntr 0 1 full 0 1 empty
Notes: 1. These registers are available in all modes. 2. All FIFOs use one common 16-byte FIFO.
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6.3.12 ECP Pin Descriptions NAME nStrobe (HostClk) TYPE O DESCRIPTION The nStrobe registers data or address into the slave on the asserting edge during write operations. This signal handshakes with Busy. These signals contains address or data or RLE data. This signal indicates valid data driven by the peripheral when asserted. This signal handshakes with nAutoFd in reverse. This signal deasserts to indicate that the peripheral can accept data. It indicates whether the data lines contain ECP command information or data in the reverse direction. When in reverse direction, normal data are transferred when Busy (PeriphAck) is high and an 8-bit command is transferred when it is low. This signal is used to acknowledge a change in the direction of the transfer (asserted = forward). The peripheral drives this signal low to acknowledge nReverseRequest. The host relies upon nAckReverse to determine when it is permitted to drive the data bus. Indicates printer on line. Requests a byte of data from the peripheral when it is asserted. This signal indicates whether the data lines contain ECP address or data in the forward direction. When in forward direction, normal data are transferred when nAutoFd (HostAck) is high and an 8-bit command is transferred when it is low. Generates an error interrupt when it is asserted. This signal is valid only in the forward direction. The peripheral is permitted (but not required) to drive this pin low to request a reverse transfer during ECP Mode. This signal sets the transfer direction (asserted = reverse, deasserted = forward). This pin is driven low to place the channel in the reverse direction. This signal is always deasserted in ECP mode.
PD<7:0> nAck (PeriphClk) Busy (PeriphAck)
I/O I I
PError (nAckReverse)
I
Select (Xflag) nAutoFd (HostAck)
I O
nFault (nPeriphRequest)
I
nInit (nReverseRequest)
O
nSelectIn (ECPMode)
O
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6.3.13 ECP Operation The host must negotiate on the parallel port to determine if the peripheral supports the ECP protocol before ECP operation. After negotiation, it is necessary to initialize some of the port bits. The following are required: (a) Set direction = 0, enabling the drivers. (b) Set strobe = 0, causing the nStrobe signal to default to the deasserted state. (c) Set autoFd = 0, causing the nAutoFd signal to default to the deasserted state. (d) Set mode = 011 (ECP Mode) ECP address/RLE bytes or data bytes may be sent automatically by writing the ecpAFifo or ecpDFifo, respectively. 6.3.13.1 Mode Switching Software will execute P1284 negotiation and all operation prior to a data transfer phase under programmed I/O control (mode 000 or 001). Hardware provides an automatic control line handshake, moving data between the FIFO and the ECP port only in the data transfer phase (mode 011 or 010). If the port is in mode 000 or 001 it may switch to any other mode. If the port is not in mode 000 or 001 it can only be switched into mode 000 or 001. The direction can be changed only in mode 001. When in extended forward mode, the software should wait for the FIFO to be empty before switching back to mode 000 or 001. In ECP reverse mode the software waits for all the data to be read from the FIFO before changing back to mode 000 or 001. 6.3.13.2 Command/Data ECP mode allows the transfer of normal 8-bit data or 8-bit commands. In the forward direction, normal data are transferred when HostAck is high and an 8-bit command is transferred when HostAck is low. The most significant bits of the command indicate whether it is a run-length count (for compression) or a channel address. In the reverse direction, normal data are transferred when PeriphAck is high and an 8-bit command is transferred when PeriphAck is low. The most significant bit of the command is always zero. 6.3.13.3 Data Compression The W83627HF supports run length encoded (RLE) decompression in hardware and can transfer compressed data to a peripheral. Note that the odd (RLE) compression in hardware is not supported. In order to transfer data in ECP mode, the compression count is written to the ecpAFifo and the data byte is written to the ecpDFifo. 6.3.14 FIFO Operation The FIFO threshold is set in configuration register 5. All data transfers to or from the parallel port can proceed in DMA or Programmed I/O (non-DMA) mode, as indicated by the selected mode. The FIFO is used by selecting the Parallel Port FIFO mode or ECP Parallel Port Mode. After a reset, the FIFO is disabled.
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6.3.15 DMA Transfers DMA transfers are always to or from the ecpDFifo, tFifo, or CFifo. The DMA uses the standard PC DMA services. The ECP requests DMA transfers from the host by activating the PDRQ pin. The DMA will empty or fill the FIFO using the appropriate direction and mode. When the terminal count in the DMA controller is reached, an interrupt is generated and serviceIntr is asserted, which will disable the DMA. 6.3.16 Programmed I/O (NON-DMA) Mode The ECP or parallel port FIFOs can also be operated using interrupt driven programmed I/O. Programmed I/O transfers are to the ecpDFifo at 400H and ecpAFifo at 000H or from the ecpDFifo located at 400H, or to/from the tFifo at 400H. The host must set the direction, state, dmaEn = 0 and serviceIntr = 0 in the programmed I/O transfers. The ECP requests programmed I/O transfers from the host by activating the IRQ pin. The programmed I/O will empty or fill the FIFO using the appropriate direction and mode.
6.4 Extension FDD Mode (EXTFDD)
In this mode, the W83627HF changes the printer interface pins to FDC input/output pins, allowing the user to install a second floppy disk drive (FDD B) through the DB-25 printer connector. The pin assignments for the FDC input/output pins are shown in Table 6-1. After the printer interface is set to EXTFDD mode, the following occur: (1) Pins MOB# and DSB# will be forced to inactive state. (2) Pins DSKCHG#, RDATA#, WP#, TRAK0#, INDEX# will be logically ORed with pins PD4-PD0 to serve as input signals to the FDC. (3) Pins PD4-PD0 each will have an internal resistor of about 1K ohm to serve as pull-up resistor for FDD open drain/collector output. (4) If the parallel port is set to EXTFDD mode after the system has booted DOS or another operating system, a warm reset is needed to enable the system to recognize the extension floppy drive.
6.5 Extension 2FDD Mode (EXT2FDD)
In this mode, the W83627HF changes the printer interface pins to FDC input/output pins, allowing the user to install two external floppy disk drives through the DB-25 printer connector to replace internal floppy disk drives A and B. The pin assignments for the FDC input/output pins are shown in Table6-1. After the printer interface is set to EXTFDD mode, the following occur: (1) Pins MOA#, DSA#, MOB#, and DSB# will be forced to inactive state. (2) Pins DSKCHG#, RDATA#, WP#, TRAK0#, and INDEX# will be logically ORed with pins PD4-PD0 to serve as input signals to the FDC. (3) Pins PD4-PD0 each will have an internal resistor of about 1K ohm to serve as pull-up resistor for FDD open drain/collector output. (4) If the parallel port is set to EXT2FDD mode after the system has booted DOS or another operating system, a warm reset is needed to enable the system to recognize the extension floppy drive.
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PRELIMINARY 7. GENERAL PURPOSE I/O
W83697HF provides 24 input/output ports that can be individually configured to perform a simple basic I/O function or a pre-defined alternate function. Those 24 GP I/O ports are divided into three groups, each group contains 8 ports. The first group is configured through control registers in logical device 7, the second group in logical device 8, and the third group in logical device 9. Users can configure each individual port to be an input or output port by programming respective bit in selection register (CRF0: 0 = output, 1 = input). Invert port value by setting inversion register (CRF2: 0 = noninverse, 1 = inverse). Port value is read/written through data register (CRF1). Table 7.1 and 7.2 gives more details on GPIO's assignment. In addition, GPIO1 is designed to be functional even in power loss condition (VCC or VSB is off). Figure 7.1 shows the GP I/O port's structure. Right after Power-on reset, those ports default to perform basic input function except ports in GPIO1 which maintains its previous settings until a battery loss condition. Table 7.1 SELECTION BIT 0 = OUTPUT 1 = INPUT 0 0 1 1 0 1 0 1 Basic non-inverting output Basic inverting output Basic non-inverting input Basic inverting input INVERSION BIT 0 = NON INVERSE 1 = INVERSE BASIC I/O OPERATIONS
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Table 7.2 GP I/O PORT DATA REGISTER REGISTER BIT ASSIGNMENT BIT 0 BIT 1 BIT 2 BIT 3 GP1 BIT 4 BIT 5 BIT 6 BIT 7 BIT 0 BIT 1 GP2 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT 0 BIT 1 BIT 2 BIT 3 GP3 BIT 4 BIT 5 BIT 6 BIT 7 GP I/O PORT GP10 GP11 GP12 GP13 GP14 GP15 GP16 GP17 GP20 GP21 GP22 GP23 GP24 GP25 GP26 GP27 GP30 GP31 GP32 GP33 GP34 GP35 GP36 GP37
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Figure 7.1
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PRELIMINARY 8. ACPI REGISTERS FEATURES
W83697HF supports both ACPI and legacy power managements. The switch logic of the power management block generates an SMI interrupt in the legacy mode and an PME interrupt in the ACPI mode. The new ACPI feature routes SMI / PME logic output either to SMI or to PME .The SMI / PME logic routes to SMI only when both PME_EN = 0 and SMIPME_OE = 1. Similarly, the SMI / PME logic routes to PME only when both PME_EN = 1 and SMIPME_OE = 1.
PME_EN IRQ events
SMIPME_OE
SMI / PME Logic
0 1
SMIPME_OE
SMI
PME
Device Idle Timers Device Trap Global STBY Timer
IRQs
Sleep/Wake State machine
WAK_STS Clock Control
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PRELIMINARY 9. HARDWARE MONITOR
9.1 General Description
The W83697HF can be used to monitor several critical hardware parameters of the system, including power supply voltages, fan speeds, and temperatures, which are very important for a high-end computer system to work stable and properly. W83697HF provides LPC interface to access hardware . An 8-bit analog-to-digital converter (ADC) was built inside W83697HF. The W83697HF can simultaneously monitor 7 analog voltage inputs, 2 fan tachometer inputs, 2 remote temperature, one case-open detection signal. The remote temperature sensing can be performed by thermistors, or TM 2N3904 NPN-type transistors, or directly from Intel Deschutes CPU thermal diode output. Also the W83697HF provides: 2 PWM (pulse width modulation) outputs for the fan speed control; beep tone output for warning; SMI#(through serial IRQ) , OVT#, GPO# signals for system protection events. Through the application software or BIOS, the users can read all the monitored parameters of system from time to time. And a pop-up warning can be also activated when the monitored item was out of TM TM the proper/preset range. The application software could be Winbond's Hardware Doctor , or Intel LDCM (LanDesk Client Management), or other management application software. Also the users can set up the upper and lower limits (alarm thresholds) of these monitored parameters and to activate one programmable and maskable interrupts. An optional beep tone could be used as warning signal when the monitored parameters is out of the preset range.
9.2
Access Interface
The W83697HF provides two interface for microprocessor to read/write hardware monitor internal registers. 9.2.1 LPC interface
The first interface uses LPC Bus to access which the ports of low byte (bit2~bit0) are defined in the port 5h and 6h. The other higher bits of these ports is set by W83697HF itself. The general decoded address is set to port 295h and port 296h. These two ports are described as following: Port 295h: Index port. Port 296h: Data port. The register structure is showed as the Figure 9.1
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Configuration Register 40h SMI# Status/Mask Registers 41h, 42h, 44h, 45h Fan Divisor Register 47h Device ID 48h Monitor Value Registers 20h~3Fh and 60h~7Fh (auto-increment) VID<4>/Device ID 49h Temperature 2, 3 Serial Bus Address 4Ah Control Register 4Bh~4Dh Select Bank for 50h~5Fh Reg. 4Eh Winbond Vendor ID 4Fh BANK 0 R-T Table Value BEEP Control Register Winbond Test Register 50h~58h BANK 1 Temperature 2 Control/Staus Registers 50h~56h BANK 2 Reserved 50h~56h BANK 4 Additional Control/Staus Registers 50h~5Ch BANK 5 Additional Limit Value & Value RAM 50h~57h
ISA Data Bus
ISA Address Bus
Port 5h
Index Register
Port 6h Data Register
Figure 9.1 : ISA interface access diagram
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9.3 Analog Inputs
The maximum input voltage of the analog pin is 4.096V because the 8-bit ADC has a 16mv LSB. Really, the application of the PC monitoring would most often be connected to power suppliers. The CPU V-core voltage ,+3.3V ,battery and 5VSB voltage can directly connected to these analog inputs. The +12V,-12V and -5V voltage inputs should be reduced a factor with external resistors so as to obtain the input range. As Figure 9.2 shows.
VCOREA Positive Inputs VCOREB +3.3VIN AVCC(+5V) VBAT R1 V1 Positive Input R2 5VSB +12VIN
Pin 100 Pin 99 Pin 98 Pin 97 Pin 74 Pin 61 Pin 96 8-bit ADC with 16mV LSB
Negative Input
V2 V3 R5
R3
N12VIN N5VIN
Pin 95 Pin 94
R6 R 10K, 1%
R4
VREF VTIN3 Pin 102 Pin 103 Pin 104
Pin 101
Typical Thermister Connection RTHM 10K, 25 C
VTIN2 VTIN1
**The Connections of VTIN1 and VTIN2 are same as VTIN3
Figure. 9.2
9.3.1
Monitor over 4.096V voltage:
The input voltage +12VIN can be expressed as following equation.
12 VIN = V1 x
R2 R1 + R 2
The value of R1 and R2 can be selected to 28K Ohms and 10K Ohms, respectively, when the input voltage V1 is 12V. The node voltage of +12VIN can be subject to less than 4.096V for the maximun input range of the 8-bit ADC. The Pin 97 is connected to the power supply VCC with +5V. There are two functions in this pin with 5V. The first function is to supply internal analog power in the W83697HF and the second function is that this voltage with 5V is connected to internal serial resistors to monitor the +5V voltage. The value of two serial resistors are 34K ohms and 50K ohms so Publication Release Date: Dec 1999 Revision 0.41
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that input voltage to ADC is 2.98V which is less than 4.096V of ADC maximum input voltage. The express equation can represent as follows.
Vin = VCC x
50 K 50 K + 34 K
2 .98 V
where VCC is set to 5V. The Pin 61 is connected to 5VSB voltage. W83697HF monitors this voltage and the internal two serial resistors are 17K and 33K so that input voltage to ADC is 3.3V which less than 4.096V of ADC maximum input voltage. 9.3.2 Monitor negative voltage:
The negative voltage should be connected two series resistors and a positive voltage VREF (is equal to 3.6V). In the Figure 9.2, the voltage V2 and V3 are two negative voltage which they are -12V and 5V respectively. The voltage V2 is connected to two serial resistors then is connected to another terminal VREF which is positive voltage. So as that the voltage node N12VIN can be obtain a posedge voltage if the scales of the two serial resirtors are carefully selected. It is recommanded from Winbond that the scale of two serial resistors are R3=232K ohms and R4=56K ohm. The input voltage of node N12VIN can be calculated by following equation.
N 12VIN = (VREF + V2 ) x (
232 K ) + V2 232 K + 56 K
where VREF is equal 3.6V. If the V2 is equal to -12V then the voltage is equal to 0.567V and the converted hexdecimal data is set to 35h by the 8-bit ADC with 16mV-LSB.This monitored value should be converted to the real negative votage and the express equation is shown as follows.
V2 =
N 12VIN - VREF x 1-
Where is 232K/(232K+56K). If the N2VIN is 0.567 then the V2 is approximately equal to -12V. The another negative voltage input V3 (approximate -5V) also can be evaluated by the similar method and the serial resistors can be selected with R5=120K ohms and R6=56K ohms by the Winbond recommended. The expression equation of V3 With -5V voltage is shown as follows.
V3 =
N 5VIN - VREF x 1-
Where the is set to 120K/(120K+56K). If the monitored ADC value in the N5VIN channel is 0.8635, VREF=3.6V and the parameter is 0.6818 then the negative voltage of V3 can be evalated to be -5V.
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PRELIMINARY
9.3.3 Temperature Measurement Machine The temperature data format is 8-bit two's-complement for sensor 2 and 9-bit two's-complement for sensor 1. The 8-bit temperature data can be obtained by reading the CR[27h]. The 9-bit temperature data can be obtained by reading the 8 MSBs from the Bank1 CR[50h] and the LSB from the Bank1 CR[51h] bit 7. The format of the temperature data is show in Table 1. Temperature 8-Bit Digital Output 8-Bit Binary +125C +25C +1C +0.5C +0C -0.5C -1C -25C -55C 0111,1101 0001,1001 0000,0001 0000,0000 1111,1111 1110,0111 1100,1001 8-Bit Hex 7Dh 19h 01h 00h FFh E7h C9h Table 2. 9-Bit Digital Output 9-Bit Binary 0,1111,1010 0,0011,0010 0,0000,0010 0,0000,0001 0,0000,0000 1,1111,1111 1,1111,1110 1,1100,1110 1,1001,0010 9-Bit Hex 0FAh 032h 002h 001h 000h 1FFh 1FFh 1CEh 192h
9.3.3.1 Monitor temperature from thermistor: The W83697HF can connect three thermistors to measure three different envirment temperature. The specification of thermistor should be considered to (1) value is 3435K, (2) resistor value is 10K ohms at 25C. In the Figure 9.2, the themistor is connected by a serial resistor with 10K Ohms, then connect to VREF (Pin 101). 9.3.3.2 Monitor temperature from Pentium II
TM
thermal diode or bipolar transistor 2N3904
TM
The W83697HF can alternate the thermistor to Pentium II (Deschutes) thermal diode interface or TM transistor 2N3904 and the circuit connection is shown as Figure 9.3. The pin of Pentium II D- is connected to power supply ground (GND) and the pin D+ is connected to pin VTINx in the W83697HF. The resistor R=30K ohms should be connected to VREF to supply the diode bias current and the bypass capacitor C=3300pF should be added to filter the high frequency noise. The transistor 2N3904 should be connected to a form with a diode, that is, the Base (B) and Collector (C) in the 2N3904 should be tied togeter to act as a thermal diode.
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W83697HF
PRELIMINARY
VREF R=30K, 1%
Bipolar Transistor Temperature Sensor
VTINx C=3300pF C B E R=30K, 1% 2N3904
W83627HF
OR
Pentium II CPU Therminal Diode D+ C=3300pF D-
VTINx
Figure 9.3
9.4
9.4.1
FAN Speed Count and FAN Speed Control
Fan speed count
Inputs are provides for signals from fans equipped with tachometer outputs. The level of these signals should be set to TTL level, and maximum input voltage can not be over +5.5V. If the input signals from the tachometer outputs are over the VCC, the external trimming circuit should be added to reduce the voltage to obtain the input specification. The normal circuit and trimming circuits are shown as Figure 9.4. Determine the fan counter according to:
Count = 135 x 10 6 . RPM x Divisor
In other words, the fan speed counter has been read from register CR28 or CR29 or CR2A, the fan speed can be evaluated by the following equation. RPM =
1.35 x 10
6
Count x Divisor
The default divisor is 2 and defined at CR47.bit7~4, CR4B.bit7~6, and Bank0 CR5D.bit5~7 which are three bits for divisor. That provides very low speed fan counter such as power supply fan. The followed table is an example for the relation of divisor, PRM, and count.
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PRELIMINARY
Divisor 1 2 (default) 4 8 16 32 64 128
+12V
Nominal PRM 8800 4400 2200 1100 550 275 137 68
+5V
Time per Revolution 6.82 ms 13.64 ms 27.27 ms 54.54 ms 109.08 ms 218.16 ms 436.32 ms 872.64 ms Table 1.
Counts 153 153 153 153 153 153 153 153
+12V
70% RPM 6160 3080 1540 770 385 192 96 48
Time for 70% 9.74 ms 19.48 ms 38.96 ms 77.92 ms 155.84 ms 311.68 ms 623.36 ms 1246.72 ms
diode +12V FAN Out GND
Pull-up resister 4.7K Ohms
diode +12V
Pull-up resister 4.7K Ohms
14K~39K Fan Input Pin 111-113
Fan Input
Pin 111-113
FAN Out GND
FAN Connector
W83627HF
FAN Connector
10K
W83627HF
Fan with Tach Pull-Up to +5V
Fan with Tach Pull-Up to +12V, or Totem-Pole Output and Register Attenuator
+12V
+12V
diode +12V FAN Out GND
Pull-up resister > 1K +12V Pin 111-113 FAN Out
diode
Pull-up resister < 1K or totem-pole output
Fan Input > 1K Pin 111-113
Fan Input 3.9V Zener
GND
FAN Connector
W83627HF
3.9V Zener
FAN Connector
W83627HF
Fan with Tach Pull-Up to +12V and Zener Clamp
Fan with Tach Pull-Up to +12V, or Totem-Pole Output and Zener Clamp
Figure 9.4
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PRELIMINARY
9.4.2
Fan speed control
The W83697HF provides 2 sets for fan PWM speed control. The duty cycle of PWM can be programmed by a 8-bit registers which are defined in the Bank0 CR5A and CR5B. The default duty cycle is set to 100%, that is, the default 8-bit registers is set to FFh. The expression of duty can be represented as follows.
Duty - cycle (%) =
Programmed 8 - bit Register Value 255
x 100%
The PWM clock frequency also can be program and defined in the Bank0.CR5C . The application circuit is shown as follows.
+12V
R1 R2 D PWM Clock Input G S NMOS + C FAN PNP Transistor
Figure 9.5
9.5
9.5.1
SMI# interrupt mode
Voltage SMI# mode :
SMI# interrupt for voltage is Two-Times Interrupt Mode. Voltage exceeding high limit or going below low limit will causes an interrupt if the previous interrupt has been reset by reading all the interrupt Status Register. (Figure 9.6 ) 9.5.2 Fan SMI# mode :
SMI# interrupt for fan is Two-Times Interrupt Mode. Fan count exceeding the limit, or exceeding and then going below the limit, will causes an interrupt if the previous interrupt has been reset by reading all the interrupt Status Register. (Figure 9.7 )
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PRELIMINARY
High limit
Low limit
Fan Count limit
SMI#
*
*
*
*
SMI#
*
*
*Interrupt Reset when Interrupt Status Registers are read
Figure 9.6 9.5.3
Figure 9.7
The W83697HF temperature sensor 1 SMI# interrupt has two modes:
(1) Comparator Interrupt Mode Setting the THYST (Temperature Hysteresis) limit to 127C will set temperature sensor 1 SMI# to the Comparator Interrupt Mode. Temperature exceeds TO (Over Temperature) Limit causes an interrupt and this interrupt will be reset by reading all the Interrupt Status Register. Once an interrupt event has occurred by exceeding TO, then reset, if the temperature remains above the TO , the interrupt will occur again when the next conversion has completed. If an interrupt event has occurred by exceeding TO and not reset, the interrupts will not occur again. The interrupts will continue to occur in this manner until the temperature goes below TO. (Figure 9.8 ) (2) Two-Times Interrupt Mode Setting the THYST lower than TO will set temperature sensor 1 SMI# to the Two-Times Interrupt Mode. Temperature exceeding TO causes an interrupt and then temperature going below THYST will also cause an interrupt if the previous interrupt has been reset by reading all the interrupt Status Register. Once an interrupt event has occurred by exceeding TO , then reset, if the temperature remains above the THYST , the interrupt will not occur. (Figure 9.9 )
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PRELIMINARY
THYST 127'C
TOI
TOI
THYST
SMI#
*
*
*
*
SMI#
*
*
*
*Interrupt Reset when Interrupt Status Registers are read
Figure 9.8
Figure 9.9
9.5.4 The W83697HF temperature sensor 2 and sensor 3 SMI# interrupt has two modes and it is programmed at CR[4Ch] bit 6. (1) Comparator Interrupt Mode Temperature exceeding TO causes an interrupt and this interrupt will be reset by reading all the Interrupt Status Register. Once an interrupt event has occurred by exceeding TO, then reset, if the temperature remains above the THYST, the interrupt will occur again when the next conversion has completed. If an interrupt event has occurred by exceeding TO and not reset, the interrupts will not occur again. The interrupts will continue to occur in this manner until the temperature goes below THYST. ( Figure 9.10 ) (2) Two-Times Interrupt Mode Temperature exceeding TO causes an interrupt and then temperature going below THYST will also cause an interrupt if the previous interrupt has been reset by reading all the interrupt Status Register. Once an interrupt event has occurred by exceeding TO , then reset, if the temperature remains above the THYST , the interrupt will not occur. (Figure 9.11 )
TOI TOI
THYST
THYST
SMI#
*
*
*
*
*
SMI#
*
*
*
*Interrupt Reset when Interrupt Status Registers are read
Figure 9.10
Figure 9.11
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PRELIMINARY
9.6 OVT# interrupt mode
The OVT# signal is only related with temperature sensor 2 and 3 (VTIN2 / VTIN3). 9.6.1 The W83697HF temperature sensor 2 and 3 Over-Temperature (OVT#) has the following modes (1) Comparator Mode : Setting Bank1/2 CR[52h] bit 2 to 0 will set OVT# signal to comparator mode. Temperature exceeding TO causes the OVT# output activated until the temperature is less than THYST. ( Figure 9.12) (2) Interrupt Mode: Setting Bank1/2 CR[52h] bit 2 to 1 will set OVT# signal to interrupt mode. Setting Temperature exceeding TO causes the OVT# output activated indefinitely until reset by reading temperature sensor 2 or sensor 3 registers. Temperature exceeding TO , then OVT# reset, and then temperature going below THYST will also cause the OVT# activated indefinitely until reset by reading temperature sensor2 or sensor 3 registers. Once the OVT# is activated by exceeding TO , then reset, if the temperature remains above THYST , the OVT# will not be activated again.( Figure 9.12)
To
THYST
OVT#
(Comparator Mode; default)
OVT#
(Interrupt Mode)
*
*
*
*
*Interrupt Reset when Temperature 2/3 is read
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PRELIMINARY
9.7 REGISTERS AND RAM
9.7.1 Address Register (Port x5h) Port x5h 00h Bit 6:0 Read/write , Bit 7: Read Only 8 bits
7 6 5 4 3 2 1 0
Data Port: Power on Default Value Attribute: Size:
Data
Bit7: Read Only The logical 1 indicates the device is busy because of a Serial Bus transaction or another LPC bus transaction. With checking this bit, multiple LPC drivers can use W83697HF hardware monitor without interfering with each other or a Serial Bus driver. It is the user's responsibility not to have a Serial Bus and LPC bus operations at the same time. This bit is: Set: with a write to Port x5h or when a Serial Bus transaction is in progress. Reset: with a write or read from Port x6h if it is set by a write to Port x5h. Bit 6-0: Read/Write
Bit 7 Busy (Power On default 0)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Address Pointer (Power On default 00h) A6 A5 A4 A3 A2 A1 A0
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Address Pointer Index (A6-A0) Registers and RAM A6-A0 in Hex 40h 41h Power On Value of Registers: in Binary 00001000 00000000 Auto-increment to the address of Interrupt Status Register 2 after a read or write to Port x6h. Notes
Configuration Register Interrupt Register 1 Interrupt Register 2 Status
Status
42h 43h
00000000 00000000 Auto-increment to the address of SMIY Mask Register 2 after a read or write to Port x6h. Auto-increment to the address of NMI Mask Register 2 after a read or write to Port x6h
SMI#Y Mask Register 1 SMIY Mask Register 2 NMI Mask Register 1
44h 45h
00000000 00000000
NMI Mask Register 2 Fan Divisor Register Reserved Device ID Register Reserved Reserved SMI#/OVT# Property Select Register FAN IN/OUT and BEEP Control Register Register 50h-5Fh Bank Select Register Winbond Vendor ID Register POST RAM
46h 47h 48h 49h 4Ah 4Bh 4Ch 4Dh
01000000 <7:4> = 0101;
<7:1> = 0000001
<7:0> = 00000000 <7:0> = 00010101
4Eh 4Fh
<7> = 1 ; <6:3> = Reserved ; <2:0> = 000 <7:0> = 01011100 (High Byte) <7:0> = 10100011 (Low Byte) Auto-increment to the next location after a read or write to Port x6h and stop at 1Fh. Auto-increment to the next location after a read or write to Port x6h and stop at 7Fh.
00-1Fh
Value RAM Value RAM
20-3Fh 60-7Fh
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PRELIMINARY
Temperature Registers Reserved Additional Configuration Registers 2 Bank1 50h-56h Bank2 50h-56h Bank4 50h-5Dh
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PRELIMINARY
9.7.2 Data Register (Port x6h) Data Port: Port x6h Power on Default Value 00h Attribute: Read/write Size: 8 bits
7 6 5 4 3 2 1 0
Data
Bit 7-0: Data to be read from or to be written to RAM and Register. 9.7.3 Configuration Register Index 40h Register Location: 40h Power on Default Value 01h Attribute: Read/write Size: 8 bits
7 6 5 4 3 2 1 0
START SMI#Enable RESERVED INT_Clear RESERVED RESERVED RESERVED INITIALIZATION
Bit 7: A one restores power on default value to all registers except the Serial Bus Address register. This bit clears itself since the power on default is zero. Bit 6: Reserced Bit 5: Reserved Bit 4: Reserved Bit 3: A one disables the SMI# output without affecting the contents of Interrupt Status Registers. The device will stop monitoring. It will resume upon clearing of this bit. Bit 2: Reserved Bit 1: A one enables the SMI# Interrupt output. Bit 0: A one enables startup of monitoring operations, a zero puts the part in standby mode. Note: The outputs of Interrupt pins will not be cleared if the user writes a zero to this location after an interrupt has occurred unlike "INT_Clear'' bit.
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9.7.4 Interrupt Status Register 1 Index 41h Register Location: 41h Power on Default Value 00h Attribute: Read Only Size: 8 bits
7 6 5 4 3 2 1 0
VCORE Reserved +3.3VIN AVCC TEMP1 TEMP2 FAN1 FAN2
Bit 7: A one indicates the fan count limit of FAN2 has been exceeded. Bit 6: A one indicates the fan count limit of FAN1 has been exceeded. Bit 5: A one indicates a High limit of VTIN2 has been exceeded from temperature sensor 2. Bit 4: A one indicates a High limit of VTIN1 has been exceeded from temperature sensor 1. Bit 3: A one indicates a High or Low limit of +5VIN has been exceeded. Bit 2: A one indicates a High or Low limit of +3.3VIN has been exceeded. Bit 1: Reserved Bit 0: A one indicates a High or Low limit of VCORE has been exceeded.
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PRELIMINARY
9.7.5 Interrupt Status Register 2 Index 42h Register Location: 42h Power on Default Value 00h Attribute: Read Only Size: 8 bits
7 6 5 4 3 2 1 0
+12VIN -12VIN -5VIN Reserved CaseOpen Reserved Reserved Reserved
Bit 7-6:Reserved.This bit should be set to 0. Bit 5: Reserved. Bit 4: A one indicates case has been opened. Bit 3: Reserved. Bit 2: A one indicates a High or Low limit of -5VIN has been exceeded. Bit1: A one indicates a High or Low limit of -12VIN has been exceeded. Bit0: A one indicates a High or Low limit of +12VIN has been exceeded. 9.7.6 SMI# Mask Register 1 Index 43h Register Location: 43h Power on Default Value 00h Attribute: Read/Write Size: 8 bits
7 6 5 4 3 2 1 0
VCORE Reserved +3.3VIN AVCC TEMP1 TEMP2 FAN1 FAN2
Bit 7-0: A one disables the corresponding interrupt status bit for SMI interrupt.
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9.7.7 SMI# Mask Register 2 Index 44h Register Location: 44h Power on Default Value 00h Attribute: Read/Write Size: 8 bits
7 6 5 4 3 2 1 0
+12VIN -12VIN -5VIN Reserved CaseOpen Reserved Reserved Reserved
Bit 7-6: Reserved. This bit should be set to 0. Bit 5-0: A one disables the corresponding interrupt status bit for SMI interrupt. 9.7.8 Reserved Register Index 45h
9.7.9 Chassis Clear Register -- Index 46h Register Location: 46h Power on Default Value 00h Attribute: Read/Write Size: 8 bits
7 6 5 4 3 2 1 0
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Chassis Clear
Bit 7: Set 1 , clear case open event. This bit self clears after clearing case open event. Bit 6-0:Reserved. This bit should be set to 0.
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PRELIMINARY
9.7.10 Fan Divisor Register Index 47h Register Location: 47h Power on Default Value <3:0> is mapped to VID<3:0> Attribute: Read/Write Size: 8 bits
7 6 5 4 3 2 1 0
Reserved Reserved Reserved Reserved FAN1DIV_B0 FAN1DIV_B1 FAN2DIV_B0 FAN2DIV_B1
Bit 7-6: FAN2 Speed Control. Bit 5-4: FAN1 Speed Control. Bit 3-0: Reserved Note : Please refer to Bank0 CR[5Dh] , Fan divisor table. 9.7.11 Value RAM Index 20h- 3Fh or 60h - 7Fh (auto-increment) Address A6-A0 20h 21h 22h 23h 24h 25h 26h 27h 28h Address A6-A0 with Auto-Increment 60h 61h 62h 63h 64h 65h 66h 67h 68h VCORE reading Reserved +3.3VIN reading AVCC(+5V) reading +12VIN reading -12VIN reading -5VIN reading Temperature sensor 1 reading FAN1 reading Note: This location stores the number of counts of the internal clock per revolution. FAN2 reading Note: This location stores the number of counts of the internal clock per revolution. FAN3 reading Note: This location stores the number of counts of the internal clock per revolution. VCORE High Limit Description
29h
69h
2Ah
6Ah
2Bh
6Bh
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PRELIMINARY
2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh 6Ch 6Dh 6Eh 6Fh 70h 71h 72h 73h 74h 75h 76h 77h 78h 79h 7Ah 7Bh VCORE Low Limit Reserved Reserved +3.3VIN High Limit +3.3VIN Low Limit AVCC(+5V) High Limit AVCC(+5V) Low Limit +12VIN High Limit +12VIN Low Limit -12VIN High Limit -12VIN Low Limit -5VIN High Limit -5VIN Low Limit Temperature sensor 1 (VTIN1) High Limit Temperature sensor 1 (VTIN1) Hysteresis Limit FAN1 Fan Count Limit Note: It is the number of counts of the internal clock for the Low Limit of the fan speed. FAN2 Fan Count Limit Note: It is the number of counts of the internal clock for the Low Limit of the fan speed. Reserved. Reserved
3Ch
7Ch
3Dh 3E- 3Fh
7Dh 7E- 7Fh
Setting all ones to the high limits for voltages and fans (0111 1111 binary for temperature) means interrupts will never be generated except the case when voltages go below the low limits.
9.7.12 Device ID Register - Index 49h Register Location: Power on Default Value Size: 49h <7:1> is 000,0002 binary 8 bits
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PRELIMINARY
7 6 5 4 3 2 1 0
Reserved
DID<6:0>
Bit 7-1: Read Only - Device ID<6:0> Bit 0 : Reserved 9.7.13 Reserved - Index 4Bh
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PRELIMINARY
9.7.14 SMI#/OVT# Property Select Register- Index 4Ch Register Location: Power on Default Value Attribute: Size:
7 6
4Ch 00h Read/Write 8 bits
5 4 3 2 1 0
Reserved Reserved OVTPOL DIS_OVT Reserved Reserved T2_INTMode Reserved
Bit 7: Reserved. User Defined. Bit6: Set to 1, the SMI# output type of Temperature 2(VTIN2) is set to Comparator Interrupt mode. Set to 0, the SMI# output type is set to Two-Times Interrupt mode. (default 0) Bit5: Reserved. User Defined. Bit 4: Reserved Bit 3: Disable temperature sensor 2 over-temperature (OVT) output if set to 1. Default 0, enable OVT1 output through pin OVT#. Bit 2: Over-temperature polarity. Write 1, OVT# active high. Write 0, OVT# active low. Default 0. Bit 1: Reserved. Bit 0: Reserved. 9.7.15 FAN IN/OUT and BEEP Control Register- Index 4Dh Register Location: Power on Default Value Attribute: Size: 4Dh 15h Read/Write 8 bits
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PRELIMINARY
7 6 5 4 3 2 1 0
FANINC1 FANOPV1 FANINC2 FANOPV2 Reserved Reserved Reserved Reserved
Bit 7~4: Reserved. Bit 3: FAN 2 output value if FANINC2 sets to 0. Write 1, then pin 113 always generate logic high signal. Write 0, pin 113 always generates logic low signal. This bit default 0. Bit 2: FAN 2 Input Control. Set to 1, pin 113 acts as FAN clock input, which is default value. Set to 0, this pin 113 acts as FAN control signal and the output value of FAN control is set by this register bit 3. Bit 1: FAN 1 output value if FANINC1 sets to 0. Write 1, then pin 114 always generate logic high signal. Write 0, pin 114 always generates logic low signal. This bit default 0. Bit 0: FAN 1 Input Control. Set to 1, pin 114 acts as FAN clock input, which is default value. Set to 0, this pin 114 acts as FAN control signal and the output value of FAN control is set by this register bit 1. 9.7.16 Register 50h ~ 5Fh Bank Select Register - Index 4Eh Register Location: Power on Default Value Attribute: Size:
7 6
4Eh 80h Read/Write 8 bits
5 4 3 2 1 0
BANKSEL0 BANKSEL1 BANKSEL2 Reserved Reserved Reserved Reserved HBACS
Bit 7: HBACS- High byte access. Set to 1, access Register 4Fh high byte register. Set to 0, access Register 4Fh low byte register. Default 1. Bit 6-3: Reserved. This bit should be set to 0. Bit 2-0: Index ports 0x50~0x5F Bank select. Publication Release Date: Dec 1999 Revision 0.41
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W83697HF
PRELIMINARY
9.7.17 Winbond Vendor ID Register - Index 4Fh (No Auto Increase) Register Location: Power on Default Value Attribute: Size:
15
4Fh <15:0> = 5CA3h Read Only 16 bits
8 7 0
VIDH
VIDL
Bit 15-8: Vendor ID High Byte if CR4E.bit7=1.Default 5Ch. Bit 7-0: Vendor ID Low Byte if CR4E.bit7=0. Default A3h. 9.7.18 Winbond Test Register -- Index 50h - 55h (Bank 0) 9.7.19 BEEP Control Register 1-- Index 56h (Bank 0) Register Location: Power on Default Value Attribute: Size:
7 6
56h 00h Read/Write 8 bits
5 4 3 2 1 0
EN_VC_BP Reserved EN_V33_BP EN_AVCC_BP EN_T1_BP EN_T2_BP EN_FAN1_BP EN_FAN2_BP
Bit 7: Enable BEEP Output from FAN 2 if the monitor value exceed the limit value. Write 1, enable BEEP output, which is default value. Bit 6: Enable BEEP Output from FAN 1 if the monitor value exceed the limit value. Write 1, enable BEEP output, which is default value.
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PRELIMINARY
Bit 5: Enable BEEP Output from Temperature Sensor 2 if the monitor value exceed the limit value. Write 1, enable BEEP output. Default 0 Bit 4: Enable BEEP output for Temperature Sensor 1 if the monitor value exceed the limit value. Write 1, enable BEEP output. Default 0 Bit 3: Enable BEEP output from AVCC (+5V), Write 1, enable BEEP output if the monitor value exceed the limits value. Default 0, that is disable BEEP output. Bit 2: Enable BEEP output from +3.3V. Write 1, enable BEEP output, which is default value. Bit 1: Reserved Bit 0: Enable BEEP Output from VCORE if the monitor value exceed the limits value. Write 1, enable BEEP output, which is default value 9.7.20 BEEP Control Register 2-- Index 57h (Bank 0) Register Location: Attribute: Size: 8 bits
7 6 5 4 3 2 1 0
57h Read/Write
Power on Default Value 80h
EN_V12_BP EN_NV12_BP EN_NV5_BP Reserved EN_CASO_BP Reserved Reserved EN_GBP
Bit 7: Enable Global BEEP. Write 1, enable global BEEP output. Default 1. Write 0, disable all BEEP output. Bit 6: Reserved. This bit should be set to 0. Bit5: Reserved Bit 4: Enable BEEP output for case open if case opend. Write 1, enable Default 0. Bit 3: Reserved Bit 2: Enable BEEP output from -5V, Write 1, enable BEEP output if the monitor value exceed the limits value. Default 0, that is disable BEEP output. Bit 1: Enable BEEP output from -12V, Write 1, enable BEEP output if the monitor value exceed the limits value. Default 0, that is disable BEEP output. Bit 0: Enable BEEP output from +12V, Write 1, enable BEEP output if the monitor value exceed the limits value. Default 0, that is disable BEEP output. BEEP output.
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PRELIMINARY
9.7.21 Chip ID -- Index 58h (Bank 0) Register Location: Power on Default Value Attribute: Size:
7 6
58h 60h Read Only 8 bits
5 4 3 2 1 0
CHIPID
Bit 7: Winbond Chip ID number. Read this register will return 60h. 9.7.22 Reserved Register -- Index 59h (Bank 0) Register Location: 59h Power on Default Value <7>=0 and <6:4> = 111 and <3:0> = 0000 Attribute: Read/Write Size: 8 bits
7 6 5 4 3 2 1 0
Reserved Reserved Reserved Reserved SELPIIV1 SELPIIV2 Reserved Reserved
Bit 7-6: Reserved Bit 5: Temperature sensor diode 2. Set to 1, select Pentium II compatible Diode. Set to 0 to select 2N3904
Bipolar mode.
Bit 4: Temperature sensor diode 1. Set to 1, select Pentium II compatible Diode. Set to 0 to select 2N3904
Bipolar mode.
Bit 3-0: Reserved
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PRELIMINARY
9.7.23 Reserved -- Index 5Ah (Bank 0) 9.7.24 Reserved -- Index 5Bh (Bank 0) 9.7.25 Reserved -- Index 5Ch (Bank 0)
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9.7.26 VBAT Monitor Control Register -- Index 5Dh (Bank 0) Register Location: 5Dh Power on Default Value 00h Attribute: Read/Write Size: 8 bits
7 6 5 4 3 2 1 0
EN_VBAT_MNT DIODES1 DIODES2 Reserved Reserved FANDIV1_B2 FANDIV2_B2 Reserved
Bit 7: Reserved. Bit 6: Fan2 divisor Bit 2. Bit 5: Fan1 divisor Bit 2. Bit 4 -3 : Reserved. Bit 2: Sensor 2 type selection. Set to 1, select bipolar sensor. Set to 0, select thermistor sensor. Bit 1: Sensor 1 type selection. Set to 1, select bipolar sensor. Set to 0, select thermistor sensor. Bit 0: Set to 1, enable battery voltage monitor. Set to 0, disable battery voltage monitor. If enable this bit, the monitor value is value after one monitor cycle. Note that the monitor cycle time is at least 300ms for W83697HF hardware monitor. Fan divisor table : Bit 2 Bit 1 Bit 0 0 0 0 0 0 0 1 1 0 1 0 1
Fan Divisor 1 2 4 8
Bit 2 1 1 1 1
Bit 1 0 0 1 1
Bit 0 0 1 0 1
Fan Divisor 16 32 64 128
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9.7.27 Reserved Register -- 5Eh (Bank 0) 9.7.28 Reserved Register -- 5Fh (Bank 0) 9.7.29 Temperature Sensor 2 Temperature (High Byte) Register - Index 50h (Bank 1) Register Location: Attribute: Size: 50h Read Only 8 bits
7 6 5 4 3 2 1 0
TEMP2<8:1>
Bit 7: Temperature <8:1> of sensor 2, which is high byte, means 1C. 9.7.30 Temperature Sensor 2 Temperature (Low Byte) Register - Index 51h (Bank 1) Register Location: 51h Attribute: Read Only Size: 8 bits
7 6 5 4 3 2 1 0
Reserved
TEMP2<0>
Bit 7: Temperature <0> of sensor2, which is low byte, means 0.5C. Bit 6-0: Reserved. 9.7.31 Temperature Sensor 2 Configuration Register - Index 52h (Bank 1) Register Location: 52h Power on Default Value 00h Size: 8 bits
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7 6 5 4 3 2 1 0
STOP2 INTMOD Reserved FAULT FAULT Reserved Reserved Reserved
Bit 7-5: Read - Reserved. This bit should be set to 0. Bit 4-3: Read/Write - Number of faults to detect before setting OVT# output to avoid false tripping due to noise. Bit 2: Read - Reserved. This bit should be set to 0. Bit 1: Read/Write - OVT# Interrupt mode select. This bit default is set to 0, which is compared mode. When set to 1, interrupt mode will be selected. Bit 0: Read/Write - When set to 1 the sensor will stop monitor. 9.7.32 Temperature Sensor 2 Hysteresis (High Byte) Register - Index 53h (Bank 1) Register Location: Power on Default Value Attribute: Size:
7 6
53h 4Bh Read/Write 8 bits
5 4 3 2 1 0
THYST2<8:1>
Bit 7-0: Temperature hysteresis bit 8-1, which is High Byte. The temperature default 75 degree C. 9.7.33 Temperature Sensor 2 Hysteresis (Low Byte) Register - Index 54h (Bank 1) Register Location: Power on Default Value Attribute: Size: 8 bits 54h 00h Read/Write
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7 6 5 4 3 2 1 0
Reserved
THYST2<0>
Bit 7: Hysteresis temperature bit 0, which is low Byte. Bit 6-0: Reserved. 9.7.34 Temperature Sensor 2 Over-temperature (High Byte) Register - Index 55h (Bank 1) Register Location: Power on Default Value Attribute: Size:
7 6
55h 50h Read/Write 8 bits
5 4 3 2 1 0
TOVF2<8:1>
Bit 7-0: Over-temperature bit 8-1, which is High Byte. The temperature default 80 degree C.
9.7.35 Temperature Sensor 2 Over-temperature (Low Byte) Register - Index 56h (Bank 1) Register Location: Power on Default Value Attribute: Size: 8 bits 56h 00h Read/Write
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7 6 5 4 3 2 1 0
Reserved
TOVF2<0>
Bit 7: Over-temperature bit 0, which is low Byte. Bit 6-0: Reserved. 9.7.36 Interrupt Status Register 3 -- Index 50h (BANK4) Register Location: Power on Default Value Attribute: Size:
7
50h 00h Read Only 8 bits
6 5 4 3 2 1 0
5VSB VBAT Reserved Reserved Reserved Reserved Reserved Reserved
Bit 7-2: Reserved. Bit 1: A one indicates a High or Low limit of VBAT has been exceeded. Bit 0: A one indicates a High or Low limit of 5VSB has been exceeded. 9.7.37 SMI# Mask Register 3 -- Index 51h (BANK 4) Register Location: Power on Default Value Attribute: Size: 8 bits 51h 00h Read/Write
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7 6 5 4 3 2 1 0
5VSB VBAT Reserved Reserved Reserved Reserved Reserved Reserved
Bit 7-2: Reserved. Bit 1: A one disables the corresponding interrupt status bit for SMI interrupt. Bit 0: A one disables the corresponding interrupt status bit for SMI interrupt. 9.7.38 Reserved Register -- Index 52h (Bank 4) 9.7.39 BEEP Control Register 3-- Index 53h (Bank 4) Register Location: Power on Default Value Attribute: Size:
7
53h 00h Read/Write 8 bits
6 5 4 3 2 1 0
EN_5VSB_BP EN_VBAT_BP Reserved Reserved Reserved EN_USER_BP Reserved Reserved
Bit 7-6: Reserved. Bit 5: User define BEEP output function. Write 1, the BEEP is always active. Write 0, this function is inactive. (Default 0) Bit 4-2: Reserved. Bit 1: Enable BEEP output from VBAT. Write 1, enable BEEP output, which is default value. Bit 0: Enable BEEP Output from 5VSB. Write 1, enable BEEP output, which is default value. 9.7.40 Temperature Sensor 1 Offset Register -- Index 54h (Bank 4) Register Location: Power on Default Value 54h 00h Publication Release Date: Dec 1999 Revision 0.41
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Attribute: Size:
7 6
Read/Write 8 bits
5 4 3 2 1 0
OFFSET1<7:0>
Bit 7-0: Temperature 1 base temperature. The temperature is added by both monitor value and offset value. 9.7.41 Temperature Sensor 2 Offset Register -- Index 55h (Bank 4) Register Location: Power on Default Value Attribute: Size:
7 6
55h 00h Read/Write 8 bits
5 4 3 2 1 0
OFFSET2<7:0>
Bit 7-0: Temperature 2 base temperature. The temperature is added by both monitor value and offset value. 9.7.42 Reserved Register -- Index 57h--58h 9.7.43 Real Time Hardware Status Register I -- Index 59h (Bank 4) Register Location: Power on Default Value Attribute: Size: 8 bits 59h 00h Read Only
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7 6 5 4 3 2 1 0
VCORE_STS Reserved +3.3VIN_STS AVCC_STS TEMP1_STS TEMP2_STS FAN1_STS FAN2_STS
Bit 7: FAN 2 Status. Set 1, the fan speed counter is over the limit value. Set 0, the fan speed counter is in the limit range. Bit 6: FAN 1 Status. Set 1, the fan speed counter is over the limit value. Set 0, the fan speed counter is in the limit range. Bit 5: Temperature sensor 2 Status. Set 1, the voltage of temperature sensor is over the limit value. Set 0, the voltage of temperature sensor is in the limit range. Bit 4: Temperature sensor 1 Status. Set 1, the voltage of temperature sensor is over the limit value. Set 0, the voltage of temperature sensor is in the limit range. Bit 3: AVCC Voltage Status. Set 1, the voltage of +5V is over the limit value. Set 0, the voltage of +5V is in the limit range. Bit 2: +3.3V Voltage Status. Set 1, the voltage of +3.3V is over the limit value. Set 0, the voltage of +3.3V is in the limit range. Bit 1: Reserved Bit 0: VCORE Voltage Status. Set 1, the voltage of VCORE A is over the limit value. Set 0, the voltage of VCORE A is in the limit range. 9.7.44 Real Time Hardware Status Register II -- Index 5Ah (Bank 4) Register Location: Power on Default Value Attribute: Size:
7 6
5Ah 00h Read Only 8 bits
5 4 3 2 1 0
+12VIN_STS -12VIN_STS -5VIN_STS Reserved CASE_STS Reserved Reserved Reserved
Bit 7-6: Reserved Publication Release Date: Dec 1999 Revision 0.41
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Bit 5: Reserved Bit 4: Case Open Status. Set 1, the case open sensor is sensed the high value. Set 0 Bit 3: Reserved Bit 2: -5V Voltage Status. Set 1, the voltage of -5V is over the limit value. Set 0, the voltage of -5V is during the limit range. Bit 1: -12V Voltage Status. Set 1, the voltage of -12V is over the limit value. Set 0, the voltage of 12V is during the limit range. Bit 0: +12V Voltage Status. Set 1, the voltage of +12V is over the limit value. Set 0, the voltage of +12V is in the limit range. 9.7.45 Real Time Hardware Status Register III -- Index 5Bh (Bank 4) Register Location: Power on Default Value Attribute: Size:
7
5Bh 00h Read Only 8 bits
6 5 4 3 2 1 0
5VSB_STS VBAT_STS Reserved Reserved Reserved Reserved Reserved Reserved
Bit 7-2: Reserved. Bit 1: VBAT Voltage Status. Set 1, the voltage of VBAT is over the limit value. Set 0, the voltage of VBAT is during the limit range. Bit 0: 5VSB Voltage Status. Set 1, the voltage of 5VSB is over the limit value. Set 0, the voltage of 5VSB is in the limit range. 9.7.46 Reserved Register -- Index 5Ch (Bank 4) 9.7.47 Reserved Register -- Index 5Dh (Bank 4)
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9.7.48 Value RAM 2 Index 50h - 5Ah (auto-increment) (BANK 5) Address A6-A0 Auto-Increment 50h 51h 52h 53h 54h 55h 56h 57h 5VSB reading VBAT reading Reserved Reserved 5VSB High Limit 5VSB Low Limit. VBAT High Limit VBAT Low Limit Description
9.7.49 Winbond Test Register -- Index 50h (Bank 6)
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9.7.50 FAN 1 Pre-Scale Register--Index00h
Power on default [7:0] = 0000-0001 b
Bit Name Read/Write Description
7
PWM_CLK_SEL1
Read/Write
PWM Input Clock Select. This bit select Fan 1 input clock to pre-scale divider. 0: 24 MHz 1: 180 KHz
6-0
PRE_SCALE1[6:0]
Read/Write
Fan 1 Input Clock Pre-Scale. The divider of input clock is the number defined by pre-scale. Thus, writing 1 transfers the input clock directly to counter. The maximum divider is 128 (7Fh). 01h : divider is 1 02h : divider is 2 03h : divider is 3 : :
PWM frequency = (Input Clock / Pre-scale) / 256
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9.7.51 FAN 1 Duty Cycle Select Register-- 01h (Bank 0) Power on default [7:0] 1111,1111 b
Bit Name Read/Write Description
7-0
F1_DC[7:0]
Read/Write
FanPWM1 Duty Cycle. This 8-bit register determines the number of input clock cycles, out of 256-cycle period, during which the PWM output is high. During smart fan 1 control mode, read this register will return smart fan duty cycle. 00h: PWM output is always logical Low. FFh: PWM output is always logical High. XXh: PWM output logical High (XX/256*100%) during one cycle. percentage is
9.7.52 FAN 2 Pre-Scale Register-- Index 02h
Power on default [7:0] = 0000,0001 b
Bit Name Read/Write Description
7
PWM_CLK_SEL2
Read/Write
PWM 2 Input Clock Select. This bit select Fan 2 input clock to pre-scale divider. 0: 1 MHz 1: 125 KHz
6-0
PRE_SCALE2[6:0]
Read/Write
Fan 2 Input Clock Pre-Scale. The divider of input clock is the number defined by pre-scale. Thus, writing 0 transfers the input clock directly to counter. The maximum divider is 128 (7Fh). 01h : divider is 1 02h : divider is 2 03h : divider is 3 : :
PWM frequency = (Input Clock / Pre-scale) / 256
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9.7.53 FAN2 Duty Cycle Select Register-- Index 03h
Power on default [7:0] = 1111,1111 b
Bit Name Read/Write Description
7-0
F2_DC[7:0]
Read/Write
FanPWM2 Duty Cycle. This 8-bit register determines the number of input clock cycles, out of 256-cycle period, during which the PWM output is high. During smart fan 2 control mode, read this register will return smart fan duty cycle. 00h: PWM output is always logical Low. FFh: PWM output is always logical High. XXh: PWM output logical High XX/256*100% during one cycle. percentage is
9.7.54 FAN Configuration Register-- Index 04h
Power on default [7:0] = 0000,0000 b
Bit Name Read/Write Description
7-2 5-4
Reserved FAN2_MODE
Read/Write Read/Write
Reserved FAN 2 PWM Control Mode. 00 - Manual PWM Control Mode. (Default) 01 - Thermal Cruise mode. 10 - Fan Speed Cruise Mode. 11 - Reserved.
3-2
FAN1_MODE
Read/Write
FAN 1 PWM Control Mode. 00 - Manual PWM Control Mode. (Default) 01 - Thermal Cruise mode. 10 - Fan Speed Cruise Mode. 11 - Reserved.
1
FAN2_OB
Read/Write
Enable Fan 2 as Output Buffer. Set to 0, FANPWM2 can drive logical high or logical low. Set to 1, FANPWM2 is open-drain Enable Fan 1 as Output Buffer. Set to 1, FANPWM1 can drive logical high or logical low. Set to 1, FANPWM1 is open-drain
0
FAN1_OB
Read/Write
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9.7.55 VTIN1 Target Temperature Register/ Fan 1 Target Speed Register -- Index 05h
Power on default [7:0] = 0000,0000 b CPUT1 target temperature register for Thermal Cruise mode.
Bit Name Read/Write Description
7 6-0
Reserved TEMP_TAR_T1[6:0 ]
Read/Write Read/Write
Reserved. VTIN1 Target Temperature. Only for Thermal Cruise Mode while CR84h bit3-2 is 01.
Fan 1 target speed register for Fan Speed Cruise mode.
Bit Name Read/Write Description
7-0
SPD_TAR_FAN1[7 :0]
Read/Write
Fan 1 Target Speed Control. Only for Fan Speed Cruise Mode while CR84h bit3-2 is 10.
9.7.56 VTIN2 Target Temperature Register/ Fan 2 Target Speed Register -- Index 06h
Power on - [7:0] = 0000,0000 b CPUT2 target temperature register for Thermal Cruise mode.
Bit Name Read/Write Description
7 6-0
Reserved TEMP_TAR_T2[6:0 ]
Read/Write Read/Write
Reserved. VTIN2 Target Temperature. Only for Thermal Cruise Mode while CR84h bit5-4 is 01.
Fan 2 target speed register for Fan Speed Cruise mode.
Bit Name Read/Write Description
7-0
SPD_TAR_FAN2[7: 0]
Read/Write
Fan 2 Target Speed Control. Only for Fan Speed Cruise Mode while CR84h bit5-4 is 10.
9.7.57 Tolerance of Target Temperature or Target Speed Register -- Index 07h
Power on default [7:0] = 0001,0001 b
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Tolerance of CPUT1/CPUT2 target temperature register.
Bit Name Read/Write Description
7-4 3-0
TOL_T2[3:0] TOL_T1[3:0]
Read/Write Read/Write
Tolerance of VTIN2 Target Temperature. Only for Thermal Cruise mode. Tolerance of VTIN1 Target Temperature. Only for Thermal Cruise mode.
Tolerance of Fan 1/2 target speed register.
Bit Name Read/Write Description
7-4 3-0
TOL_FS2[3:0] TOL_FS1[3:0]
Read/Write Read/Write
Tolerance of Fan 2 Target Speed Count. Only for Fan Speed Cruise mode. Tolerance of Fan 1 Target Speed Count. Only for Fan Speed Cruise mode.
9.7.58 Fan 1 PWM Stop Duty Cycle Register -- Index 08h
Power on default [7:0] = 0000,0001 b
Bit Name Read/Write Description
7-0
STOP_DC1[7:0]
Read/Write
In Thermal Cruise mode, PWM duty will be 0 if it decreases to under this value. This register should be written a non-zero minimum PWM stop duty cycle.
9.7.59 Fan 2 PWM Stop Duty Cycle Register -- 09h (Bank 0)
Power on default [7:0] = 0000,0001 b
Bit Name Read/Write Description
7-0
STOP_DC2[7:0]
Read/Write
In Thermal Cruise mode, PWM duty will be 0 if it decreases to under this register value. This register should be written a non-zero minimum PWM stop duty cycle.
9.7.60 Fan 1 Start-up Duty Cycle Register -- Index 0Ah
Power on default [7:0] = 0000,0001 b
Bit Name Read/Write Description
7-0
START_DC1[7:0]
Read/Write
In Thermal Cruise mode, PWM duty will increase from 0 to this register value to provide a minimum duty cycle Publication Release Date: Dec 1999 Revision 0.41
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to turn on the fan. This register should be written a fan start-up duty cycle.
9.7.61 Fan 2 Start-up Duty Cycle Register -- Index 0Bh
Power on default [7:0] = 0000,0001 b
Bit Name Read/Write Description
7-0
START_DC2[7:0]
Read/Write
In Thermal Cruise mode, PWM duty will increase from 0 to this register value to provide a minimum duty cycle to turn on the fan. This register should be written a fan start-up duty cycle.
9.7.62 Fan 1 Stop Time Register -- Index 0Ch
Power on default [7:0] = 0011,1100 b
Bit Name Read/Write Description
7-0
STOP_TIME1[7:0]
Read/Write
In Thermal Cruise mode, this register determines the time of which PWM duty is from stop duty cycle to 0 duty cycle. The unit of this register is 0.1 second. The default value is 6 seconds.
9.7.63 Fan 2 Stop Time Register -- Index 0Dh
Power on default [7:0] = 0011,1100 b
Bit Name Read/Write Description
7-0
STOP_TIME2[7:0]
Read/Write
In Thermal Cruise mode, this register determines the time of which PWM duty is from stop duty cycle to 0 duty cycle. The unit of this register is 0.1 second. The default value is 6 seconds.
9.7.64 Fan Step Down Time Register -- Index 0Eh
Power on defualt [7:0] = 0000,1010 b
Bit Name Read/Write Description
7-0
STEP_UP_T[7:0]
Read/Write
The time interval, which is 0.1 second unit, to decrease PWM duty in Smart Fan Control mode.
9.7.65 Fan Step Up Time Register -- Index 0Fh
Power on default [7:0] = 0000,1010 b
Bit Name Read/Write Description
7-0
STEP_DOWN_T[7:0 ]
Read/Write
The time interval, which is 0.1 second unit, to increase PWM duty in Smart Fan Control mode.
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PRELIMINARY 10 CONFIGURATION REGISTER
10.1 Plug and Play Configuration
The W83697HF uses Compatible PNP protocol to access configuration registers for setting up different types of configurations. In W83697HF, there are eleven Logical Devices (from Logical Device 0 to Logical Device B with the exception of logical device 4 for backward compatibility) which correspond to eleven individual functions: FDC (logical device 0), PRT (logical device 1), UART1 (logical device 2), UART2 (logical device 3), CIR (Consumer IR, logical device 6), GPIO1 (logical device 7), GPIO5(logical device 8),GPIO2 ~GPIO4(logical device 9), ACPI ((logical device A), and Hardware monitor (logical device B). Each Logical Device has its own configuration registers (above CR30). Host can access those registers by writing an appropriate logical device number into logical device select register at CR7.
10.2 Compatible PnP
10.2.1 Extended Function Registers In Compatible PnP, there are two ways to enter Extended Function and read or write the configuration registers. HEFRAS (CR26 bit 6) can be used to select one out of these two methods of entering the Extended Function mode as follows: HEFRAS 0 1 address and value write 87h to the location 2Eh twice write 87h to the location 4Eh twice
After Power-on reset, the value on RTSA# (pin 49) is latched by HEFRAS of CR26. In Compatible PnP, a specific value (87h) must be written twice to the Extended Functions Enable Register (I/O port address 2Eh or 4Eh). Secondly, an index value (02h, 07h-FFh) must be written to the Extended Functions Index Register (I/O port address 2Eh or 4Eh same as Extended Functions Enable Register) to identify which configuration register is to be accessed. The designer can then access the desired configuration register through the Extended Functions Data Register (I/O port address 2Fh or 4Fh).
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After programming of the configuration register is finished, an additional value (AAh) should be written to EFERs to exit the Extended Function mode to prevent unintentional access to those configuration registers. The designer can also set bit 5 of CR26 (LOCKREG) to high to protect the configuration registers against accidental accesses. The configuration registers can be reset to their default or hardware settings only by a cold reset (pin MR = 1). A warm reset will not affect the configuration registers. 10.2.2 Extended Functions Enable Registers (EFERs) After a power-on reset, the W83697HF enters the default operating mode. Before the W83697HF enters the extended function mode, a specific value must be programmed into the Extended Function Enable Register (EFER) so that the extended function register can be accessed. The Extended Function Enable Registers are write-only registers. On a PC/AT system, their port addresses are 2Eh or 4Eh (as described in previous section). 10.2.3 Extended Function Index Registers (EFIRs), Extended Function Data Registers(EFDRs) After the extended function mode is entered, the Extended Function Index Register (EFIR) must be loaded with an index value (02h, 07h-FEh) to access Configuration Register 0 (CR0), Configuration Register 7 (CR07) to Configuration Register FE (CRFE), and so forth through the Extended Function Data Register (EFDR). The EFIRs are write-only registers with port address 2Eh or 4Eh (as described in section 12.2.1) on PC/AT systems; the EFDRs are read/write registers with port address 2Fh or 4Fh (as described in section 9.2.1) on PC/AT systems.
10.3 Configuration Sequence
To program W83697HF configuration registers, the following configuration sequence must be followed: (1). Enter the extended function mode (2). Configure the configuration registers (3). Exit the extended function mode 10.3.1 Enter the extended function mode To place the chip into the extended function mode, two successive wrtites of 0x87 must be applied to Extended Function Enable Registers(EFERs, i.e. 2Eh or 4Eh). 10.3.2 Configurate the configuration registers The chip selects the logical device and activates the desired logical devices through Extended Function Index Register(EFIR) and Extended Function Data Register(EFDR). EFIR is located at the same address as EFER, and EFDR is located at address (EFIR+1). First, write the Logical Device Number (i.e.,0x07) to the EFIR and then write the number of the desired logical device to the EFDR. If accessing the Chip(Global) Control Registers, this step is not required. Secondly, write the address of the desired configuration register within the logical device to the EFIR and then write (or read) the desired configuration register through EFDR.
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10.3.3 Exit the extended function mode To exit the extended function mode, one write of 0xAA to EFER is required. Once the chip exits the extended function mode, it is in the normal running mode and is ready to enter the configuration mode. 10.3.4 Software programming example The following example is written in Intel 8086 assembly language. It assumes that the EFER is located at 2Eh, so EFIR is located at 2Eh and EFDR is located at 2Fh. If HEFRAS (CR26 bit 6) is set, 4Eh can be directly replaced by 4Eh and 2Fh replaced by 4Fh. ;----------------------------------------------------------------------------------; Enter the extended function mode ,interruptible double-write | ;----------------------------------------------------------------------------------MOV DX,2EH MOV AL,87H OUT DX,AL OUT DX,AL ;----------------------------------------------------------------------------; Configurate logical device 1, configuration register CRF0 | ;----------------------------------------------------------------------------MOV DX,2EH MOV AL,07H OUT DX,AL ; point to Logical Device Number Reg. MOV DX,2FH MOV AL,01H OUT DX,AL ; select logical device 1 ; MOV DX,2EH MOV AL,F0H OUT DX,AL ; select CRF0 MOV DX,2FH MOV AL,3CH OUT DX,AL ; update CRF0 with value 3CH ;-----------------------------------------; Exit extended function mode | ;-----------------------------------------MOV DX,2EH MOV AL,AAH OUT DX,AL
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10.4 Chip (Global) Control Register
CR02 (Default 0x00) Bit 7 - 1: Reserved. Bit 0: SWRST --> Soft Reset. CR07 Bit 7 - 0: LDNB7 - LDNB0 --> Logical Device Number Bit 7 - 0 CR20 Bit 7 - 0: DEVIDB7 - DEBIDB0 --> Device ID Bit 7 - Bit 0 = 0x 60 (read only). CR21 Bit 7 - 0: DEVREVB7 - DEBREVB0 --> Device Rev = 0x1X (read only). X : Version change number .(Bit 3~0). CR22 (Default 0xff) Bit 7~ 5: Reserved. Bit 4: HMPWD = 0 Power down = 1 No Power down Bit 3: URBPWD = 0 Power down = 1 No Power down Bit 2: URAPWD = 0 Power down = 1 No Power down Bit 1: PRTPWD = 0 Power down = 1 No Power down Bit 0: FDCPWD = 0 Power down = 1 No Power down
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CR23 (Default 0x00) Bit 7 ~ 1: Reserved. Bit 0: IPD (Immediate Power Down). When set to 1, it will put the whole chip into power down mode immediately. CR24 (Default 0x00) Bit 7 : Reserved. Bit 6: CLKSEL(Enable 48Mhz) = 0 The clock input on Pin 1 should be 24 Mhz. = 1 The clock input on Pin 1 should be 48 Mhz. The corresponding power-on setting pin is SOUTB (pin 61). Bit[5:4]: ROM size select 00 1M 01 2M 10 4M 11 Reserved Bit3:MEMW# Select (PIN97) = 0 MEMW# Disable = 1 MEMW# Enable Bit2:Reserved Bit1 : Enable Flash ROM Interface = 0 Flash ROM Interface is enabled after hardware reset = 1 Flash ROM Interface is disabled after hardware reset This bit is read only, and set/reset by power-on setting pin. The corresponding power-on setting pin is PENROM#(pin 52) Bit 0: PNPCSV = 0 The Compatible PnP address select registers have default values. = 1 The Compatible PnP address select registers have no default value. The corresponding power-on setting pin is DTRA# (pin 50). CR25 (Default 0x00) Bit 7 ~ 4: Reserved Bit 3: URBTRI Bit 2: URATRI Bit 1: PRTTRI Bit 0: FDCTRI.
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CR26 (Default 0x00) Bit 7: SEL4FDD =0 =1 Select two FDD mode. Select four FDD mode.
Bit 6: HEFRAS These two bits define how to enable Configuration mode. The corresponding power-on setting pin is RTSA #(pin 49). HEFRAS Address and Value = 0 Write 87h to the location 2E twice. = 1 Write 87h to the location 4Etwice. Bit 5: LOCKREG = 0 Enable R/W Configuration Registers. = 1 Disable R/W Configuration Registers. Bit4: Reserved Bit 3: DSFDLGRQ = 0 Enable FDC legacy mode on IRQ and DRQ selection, then DO register bit 3 is effective on selecting IRQ = 1 Disable FDC legacy mode on IRQ and DRQ selection, then DO register bit 3 is not effective on selecting IRQ Bit 2: DSPRLGRQ = 0 Enable PRT legacy mode on IRQ and DRQ selection, then DCR bit 4 is effective on selecting IRQ = 1 Disable PRT legacy mode on IRQ and DRQ selection, then DCR bit 4 is not effective on selecting IRQ Bit 1: DSUALGRQ = 0 Enable UART A legacy mode IRQ selecting, then MCR bit 3 is effective on selecting IRQ = 1 Disable UART A legacy mode IRQ selecting, then MCR bit 3 is not effective on selecting IRQ Bit 0: DSUBLGRQ = 0 Enable UART B legacy mode IRQ selecting, then MCR bit 3 is effective on selecting IRQ = 1 Disable UART B legacy mode IRQ selecting, then MCR bit 3 is not effective on selecting IRQ
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PRELIMINARY
CR28 (Default 0x00) Bit 7 - 3: Reserved. Bit 2 - 0: PRTMODS2 - PRTMODS0 = 0xx Parallel Port Mode = 100 Reserved = 101 External FDC Mode = 110 Reserved = 111 External two FDC Mode CR29 (GPIO1,5(50~51) & Game port & MIDI port Select default 0x00 ) Bit 7: Port Select (select Game Port or General Purpose I/O Port 1) =0 =1 Game Port General Purpose I/O Port 1 (pin121~128 select function GP10~GP17)
Bit [6:5] : (Pin119) 10 MSI 11 WDTO 12 Reserved 13 GP51 Bit[4:3] : (Pin 120) 10 MSO 11 PLED 12 Reserved 13 GP50 Bit2:(Pin117) OVT# & SMI Select(Pin117) = 0 OVT# = 1 SMI# Bit1~0: Reserved
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CR2A(GPIO2 ~ 5& Fresh ROM Interface Select Default 0xFF if PENROM# = 0 during POR, default 0x00 otherwise) Bit 7 : (PIN 86 ~89 & 91 ~94) = 0 GPIO 2 = 1 Fresh IF (xD7 ~ XD0) Bit 6 : (PIN 78 ~ 85) = 0 GPIO 3 = 1 Fresh IF (XA7 ~ XA0) Bit 5 : (PIN 69 ~ 74 & 76 ~77) = 0 GPIO 4 = 1 Fresh IF (XA!5 ~ XA10 & XA7 ~ A0) Bit 4: (PIN 66 ~ 68 & 95 ~ 97) = 0 GPIO 5(GP52 ~ 57) = 1 Fresh IF(XA18 ~ XA16 , ROMCS#, MEMR #, MEMW#) Bit 0~3 : Reserved
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10.5 Logical Device 0 (FDC)
CR30 (Default 0x01 if PNPCSV = 0 during POR, default 0x00 otherwise) Bit 7 - 1: Reserved. Bit 0: = 1 Activates the logical device. = 0 Logical device is inactive. CR60, CR 61 (Default 0x03, 0xf0 if PNPCSV = 0 during POR, default 0x00, 0x00 otherwise) These two registers select FDC I/O base address [0x100:0xFF8] on 8 byte boundary. CR70 (Default 0x06 if PNPCSV = 0 during POR, default 0x00 otherwise) Bit 7 - 4: Reserved. Bit 3 - 0: These bits select IRQ resource for FDC. CR74 (Default 0x02 if PNPCSV = 0 during POR, default 0x04 otherwise) Bit 7 - 3: Reserved. Bit 2 - 0: These bits select DRQ resource for FDC. = 0x00 DMA0 = 0x01 DMA1 = 0x02 DMA2 = 0x03 DMA3 = 0x04 - 0x07 No DMA active CRF0 (Default 0x0E) FDD Mode Register Bit 7: FIPURDWN This bit controls the internal pull-up resistors of the FDC input pins RDATA, INDEX, TRAK0, DSKCHG, and WP. =0 =1 The internal pull-up resistors of FDC are turned on.(Default) The internal pull-up resistors of FDC are turned off.
Bit 6: INTVERTZ This bit determines the polarity of all FDD interface signals. =0 =1 FDD interface signals are active low. FDD interface signals are active high.
Bit 5: DRV2EN (PS2 mode only) When this bit is a logic 0, indicates a second drive is installed and is reflected in status register A.
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Bit 4: Swap Drive 0, 1 Mode =0 =1 = 11 No Swap (Default) Drive and Motor select 0 and 1 are swapped. AT Mode (Default)
Bit 3 - 2 Interface Mode = 10 (Reserved) = 01 PS/2 = 00 Model 30 Bit 1: FDC DMA Mode = 0 Burst Mode is enabled = 1 Non-Burst Mode (Default) Bit 0: Floppy Mode = 0 Normal Floppy Mode (Default) = 1 Enhanced 3-mode FDD CRF1 (Default 0x00) Bit 7 - 6: Boot Floppy = 00 FDD A = 01 FDD B = 10 FDD C = 11 FDD D Bit 5, 4: Media ID1, Media ID0. These bits will be reflected on FDC's Tape Drive Register bit 7, 6. Bit 3 - 2: Density Select = 00 Normal (Default) = 01 Normal = 10 1 ( Forced to logic 1) = 11 0 ( Forced to logic 0) Bit 1: DISFDDWR = 0 Enable FDD write. = 1 Disable FDD write(forces pins WE, WD stay high). Bit 0: SWWP = 0 Normal, use WP to determine whether the FDD is write protected or not. = 1 FDD is always write-protected.
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CRF2 (Default 0xFF) Bit 7 - 6: FDD D Drive Type Bit 5 - 4: FDD C Drive Type Bit 3 - 2: FDD B Drive Type Bit 1 - 0: FDD A Drive Type CRF4 (Default 0x00) FDD0 Selection: Bit 7: Reserved. Bit 6: Precomp. Disable. = 1 Disable FDC Precompensation. = 0 Enable FDC Precompensation. Bit 5: Reserved. Bit 4 - 3: DRTS1, DRTS0: Data Rate Table select (Refer to TABLE A). = 00 Select Regular drives and 2.88 format = 01 3-mode drive = 10 2 Meg Tape = 11 Reserved Bit 2: Reserved. Bit 1:0: DTYPE0, DTYPE1: Drive Type select (Refer to TABLE B). CRF5 (Default 0x00) FDD1 Selection: Same as FDD0 of CRF4. TABLE A Drive Rate Table Select DRTS1 DRTS0 0 0 Data Rate DRATE1 1 0 0 1 1 0 0 1 1 0 0 1 DRATE0 1 0 1 0 1 0 1 0 1 0 1 0 Selected Data Rate MFM 1Meg 500K 300K 250K 1Meg 500K 500K 250K 1Meg 500K 2Meg 250K FM --250K 150K 125K --250K 250K 125K --250K --125K SELDEN
0
1
1
0
1 1 0 0 1 1 0 0 1 1 0 0
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TABLE B DTYPE0 0 DTYPE1 0 DRVDEN0(pin 2) SELDEN DRVDEN1(pin 3) DRATE0 DRIVE TYPE 4/2/1 MB 3.5"" 2/1 MB 5.25" 2/1.6/1 MB 3.5" (3-MODE)
0 1 1
1 0 1
DRATE1 SELDEN DRATE0
DRATE0 DRATE0 DRATE1
10.6 Logical Device 1 (Parallel Port)
CR30 (Default 0x01 if PNPCSV = 0 during POR, default 0x00 otherwise) Bit 7 - 1: Reserved. Bit 0: = 1 Activates the logical device. = 0 Logical device is inactive. CR60, CR 61 (Default 0x03, 0x78 if PNPCSV = 0 during POR, default 0x00, 0x00 otherwise) These two registers select Parallel Port I/O base address. [0x100:0xFFC] on 4 byte boundary (EPP not supported) or [0x100:0xFF8] on 8 byte boundary (all modes supported, EPP is only available when the base address is on 8 byte boundary). CR70 (Default 0x07 if PNPCSV = 0 during POR, default 0x00 otherwise) Bit 7 - 4: Reserved. Bit [3:0]: These bits select IRQ resource for Parallel Port. CR74 (Default 0x04) Bit 7 - 3: Reserved. Bit 2 - 0: These bits select DRQ resource for Parallel Port. 0x00=DMA0 0x01=DMA1 0x02=DMA2 0x03=DMA3 0x04 - 0x07= No DMA active
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CRF0 (Default 0x3F) Bit 7: Reserved. Bit 6 - 3: ECP FIFO Threshold. Bit 2 - 0: Parallel Port Mode (CR28 PRTMODS2 = 0) = 100 Printer Mode (Default) = 000 Standard and Bi-direction (SPP) mode = 001 EPP - 1.9 and SPP mode = 101 EPP - 1.7 and SPP mode = 010 ECP mode = 011 ECP and EPP - 1.9 mode = 111 ECP and EPP - 1.7 mode.
10.7 Logical Device 2 (UART A)
CR30 (Default 0x01 if PNPCSV = 0 during POR, default 0x00 otherwise) Bit 7 - 1: Reserved. Bit 0: = 1 Activates the logical device. = 0 Logical device is inactive. CR60, CR 61 (Default 0x03, 0xF8 if PNPCSV = 0 during POR, default 0x00, 0x00 otherwise) These two registers select Serial Port 1 I/O base address [0x100:0xFF8] on 8 byte boundary. CR70 (Default 0x04 if PNPCSV = 0 during POR, default 0x00 otherwise) Bit 7 - 4: Reserved. Bit 3 - 0: These bits select IRQ resource for Serial Port 1. CRF0 (Default 0x00) Bit 7 - 2: Reserved. Bit 1 - 0: SUACLKB1, SUACLKB0 = 00 = 01 = 10 = 11 UART A clock source is 1.8462 Mhz (24MHz/13) UART A clock source is 2 Mhz (24MHz/12) UART A clock source is 24 Mhz (24MHz/1) UART A clock source is 14.769 Mhz (24mhz/1.625)
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10.8 Logical Device 3 (UART B)
CR30 (Default 0x01 if PNPCSV = 0 during POR, default 0x00 otherwise) Bit 7 - 1: Reserved. Bit 0: = 1 Activates the logical device. = 0 Logical device is inactive. CR60, CR 61 (Default 0x02, 0xF8 if PNPCSV = 0 during POR, default 0x00, 0x00 otherwise) These two registers select Serial Port 2 I/O base address [0x100:0xFF8] on 8 byte boundary. CR70 (Default 0x03 if PNPCSV = 0 during POR, default 0x00 otherwise) Bit 7 - 4: Reserved. Bit [3:0]: These bits select IRQ resource for Serial Port 2. CRF0 (Default 0x00) Bit 7 - 4: Reserved. Bit 3: RXW4C =0 =1 No reception delay when SIR is changed from TX mode to RX mode. Reception delays 4 characters-time (40 bit-time) when SIR is changed from TX mode to RX mode. No transmission delay when SIR is changed from RX mode to TX mode. Transmission delays 4 characters-time (40 bit-time) when SIR is changed from RX mode to TX mode. UART B clock source is 1.8462 Mhz (24MHz/13) UART B clock source is 2 Mhz (24MHz/12) UART B clock source is 24 Mhz (24MHz/1) UART B clock source is 14.769 Mhz (24mhz/1.625)
Bit 2: TXW4C =0 =1
Bit 1 - 0: SUBCLKB1, SUBCLKB0 = 00 = 01 = 10 = 11
CRF1 (Default 0x00) Bit 7: Reserved. Bit 6: IRLOCSEL. IR I/O pins' location select. =0 =1 Through SINB/SOUTB. Through IRRX/IRTX.
Bit 5: IRMODE2. IR function mode selection bit 2. Bit 4: IRMODE1. IR function mode selection bit 1. Bit 3: IRMODE0. IR function mode selection bit 0.
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IR MODE 00X 010* 011* 100 101 110 111*
IR FUNCTION Disable IrDA IrDA ASK-IR ASK-IR ASK-IR ASK-IR tri-state
IRTX high Active pulse 1.6 S Active pulse 3/16 bit time Inverting IRTX/SOUTB pin Inverting IRTX/SOUTB & 500 KHZ clock Inverting IRTX/SOUTB Inverting IRTX/SOUTB & 500 KHZ clock
IRRX Demodulation into SINB/IRRX Demodulation into SINB/IRRX routed to SINB/IRRX routed to SINB/IRRX Demodulation into SINB/IRRX Demodulation into SINB/IRRX
Note: The notation is normal mode in the IR function.
Bit 2: HDUPLX. IR half/full duplex function select. =0 =1 =0 =1 =0 =1 The IR function is Full Duplex. The IR function is Half Duplex. the SOUTB pin of UART B function or IRTX pin of IR function in normal condition. inverse the SOUTB pin of UART B function or IRTX pin of IR function. the SINB pin of UART B function or IRRX pin of IR function in normal condition. inverse the SINB pin of UART B function or IRRX pin of IR function
Bit 1: TX2INV.
Bit 0: RX2INV.
10.9 Logical Device 6 (CIR)
CR30 (Default 0x00) Bit 7 - 1: Reserved. Bit 0: = 1 Activates the logical device. = 0 Logical device is inactive. CR60, CR 61 (Default 0x00, 0x00) These two registers select CIR I/O base address [0x100:0xFF8] on 8 byte boundary. CR70 (Default 0x00) Bit 7 - 4: Reserved. Bit [3:0]: These bits select IRQ resource for CIR.
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10.10 Logical Device 7 (Game Port GPIO Port 1)
CR30 (Default 0x00) Bit 7 - 1: Reserved. Bit 0: = 1 Activate Game Port./GP1 = 0 Game Port/GP1 is inactive. CR60, CR 61 (Default 0x02, 0x01 if PNPCSV = 0 during POR, default 0x00 otherwise) These two registers select the Game Port base address [0x100:0xFFF] on 8 byte boundary. CR62, CR 63 (Default 0x00, 0x00) These two registers select the GPIO1 base address [0x100:0xFFF] on 1 byte boundary IO address : CRF1 base address CRF0 (GP10-GP17 I/O selection register. Default 0xFF) When set to a '1', respective GPIO port is programmed as an input port. When set to a '0', respective GPIO port is programmed as an output port. CRF1 (GP10-GP17 data register. Default 0x00) If a port is programmed to be an output port, then its respective bit can be read/written If a port is programmed to be an input port, then its respective bit can only be read. CRF2 (GP10-GP17 inversion register. Default 0x00) When set to a '1', the incoming/outgoing port value is inverted. When set to a '0', the incoming/outgoing port value is the same as in data register.
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10.11
Logical Device 8 (MIDI Port and GPIO Port 5)
CR30 (MIDI Port Default 0x00) Bit 7 - 1: Reserved. Bit 0: = 1 MIDI/GP5 port is Activate = 0 MIDI/GP5 port is inactive. CR60, CR 61 (Default 0x03, 0x30 if PNPCSV = 0 during POR, default 0x00 otherwise) These two registers select the MIDI Port base address [0x100:0xFFF] on 2byte boundary. CR62, CR 63 (Default 0x00, 0x00 ) These two registers select the GPIO5 base address [0x100:0xFFF] on 4byte boundary. IO address : CRF1 base address IO address + 1 : CRF3 base address IO address + 2 : CRF4 base address IO address + 3 : CRF5 base address CR70 (Default 0x09 if PNPCSV = 0 during POR, default 0x00 otherwise) Bit 7 - 4: Reserved. Bit [3:0]: These bits select IRQ resource for MIDI Port . CRF0 (GP5 selection register. Default 0xFF) When set to a '1', respective GPIO port is programmed as an input port. When set to a '0', respective GPIO port is programmed as an output port. CRF1 (GP5 data register. Default 0x00) If a port is programmed to be an output port, then its respective bit can be read/written. If a port is programmed to be an input port, then its respective bit can only be read. CRF2 (GP5 inversion register. Default 0x00) When set to a '1', the incoming/outgoing port value is inverted. When set to a '0', the incoming/outgoing port value is the same as in data register.
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CRF3 (PLED mode register. Default 0x00) Bit 7 ~ 3 : Reserved . Bit 2: select WDTO count mode. =0 =1 = 00 = 01 = 10 = 11 second minute Power LED pin is tri-stated. Power LED pin is droved low. Power LED pin is a 1Hz toggle pulse with 50 duty cycle. Power LED pin is a 1/4Hz toggle pulse with 50 duty cycle.
Bit 1 ~ 0: select PLED mode
CRF4 (Default 0x00) Watch Dog Timer Time-out value. Writing a non-zero value to this register causes the counter to load the value to Watch Dog Counter and start counting down. Reading this register returns current value in Watch Dog Counter instead of Watch Dog Timer Time-out value. Bit 7 - 0: = 0x00 Time-out Disable = 0x01 Time-out occurs after 1 second/minute = 0x02 Time-out occurs after 2 second/minutes = 0x03 Time-out occurs after 3 second/minutes ................................................ = 0xFF Time-out occurs after 255 second/minutes CRF5 (Default 0x00) Bit 7 ~ 6 : Reserved . Bit 5: Force Watch Dog Timer Time-out, Write only* = 1 Force Watch Dog Timer time-out event; this bit is self-clearing. Bit 4: Watch Dog Timer Status, R/W = 1 Watch Dog Timer time-out occurred. = 0 Watch Dog Timer counting Bit 3 -0: These bits select IRQ resource for Watch Dog. Setting of 2 selects SMI.
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10.12 Logical Device 9 (GPIO Port 2 ~ GPIO Port 4 )
CR30 (Default 0x00) Bit 7 ~ 3: Reserved. Bit 2: = 1 Activate GPIO4. = 0 GPIO4 is inactive Bit 1: = 1 Activate GPIO3. = 0 GPIO3 is inactive Bit 0: = 1 Activate GPIO2. = 0 GPIO2 is inactive. CR60,61(Default 0x00,0x00). These two registers select the GP2,3,4 base address(0x100:FFE) ON 3 bytes boundary. IO address: : CRF1 base address IO address + 1 : CRF3 base address IO address + 2 : CRF7 base address
CRF0 (GP2 I/O selection register. Default 0xFF ) When set to a '1', respective GPIO port is programmed as an input port. When set to a '0', respective GPIO port is programmed as an output port. CRF1 (GP2 data register. Default 0x00 ) If a port is programmed to be an output port, then its respective bit can be read/written. If a port is programmed to be an input port, then its respective bit can only be read. CRF2 (GP2 inversion register. Default 0x00 ) When set to a '1', the incoming/outgoing port value is inverted. When set to a '0', the incoming/outgoing port value is the same as in data register. CRF3 (GP3 I/O selection register. Default 0xFF ) When set to a '1', respective GPIO port is programmed as an input port. When set to a '0', respective GPIO port is programmed as an output port. CRF4 (GP3 data register. Default 0x00 ) If a port is programmed to be an output port, then its respective bit can be read/written. If a port is programmed to be an input port, then its respective bit can only be read. CRF5 (GP3 inversion register. Default 0x00 ) When set to a '1', the incoming/outgoing port value is inverted. When set to a '0', the incoming/outgoing port value is the same as in data register. CRF6 (GP4 I/O selection register. Default 0xFF ) When set to a '1', respective GPIO port is programmed as an input port. When set to a '0', respective GPIO port is programmed as an output port.
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CRF7 (GP4 data register. Default 0x00 ) If a port is programmed to be an output port, then its respective bit can be read/written. If a port is programmed to be an input port, then its respective bit can only be read. CRF8 (GP5 inversion register. Default 0x00 ) When set to a '1', the incoming/outgoing port value is inverted. When set to a '0', the incoming/outgoing port value is the same as in data register.
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10.13 Logical Device A (ACPI)
CR30 (Default 0x00) Bit 7 - 1: Reserved. Bit 0: = 1 Activates the logical device. = 0 Logical device is inactive. CR70 (Default 0x00) Bit 7 - 4: Reserved. Bit 3 - 0: These bits select IRQ resources for S M I / PME CRE0 (Default 0x00) Bit7 : ENCIRWAKEUP. Enable CIR to wake-up system . = 0 Disable CIR wake up function = 1 Enable CIR wake up function Bit 5 : CIR_STS. This bit is cleared by reading 1 this register. = 0 Disable = 1 Enable Bit6, 4 ~ 0 : Reserved CRE 1 (Default 0x00) CIR wake up index register The range of CIR wake up index register is 0x20 ~ px2F . CRE 2 CIR wake up data register This register holds the value of wake up key register indicated by CRE1. This register can be read/written. CRE5 (Default 0x00) Bit 7 : Reserved Bit 6 ~ 0 :Compared Code Length . When the compared codes are storage in the data register, these data length should be written to this register. CRE6 (Default 0x00) Bit 7 - 6: Reserved. Bit 5 - 0: CIR Baud Rate Divisor. The clock base of CIR is 32khz, so that the baud rate is 32khz divided by ( CIR Baud Rate Divisor + 1).
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CRE7 (Default 0x00) Bit 7 - 3: Reserved. Bit 2:Reset CIR Power-On function. After using CIR power-on, the software should write logical 1 to restart CIR power-on function. Bit 1: Invert RX Data. = 1 Inverting RX Data. = 0 Not inverting RX Data. Bit 0: Enable Demodulation. = 1 Enable received signal to demodulate. = 0 Disable received signal to demodulate. CRF0 (Default 0x00) Bit 7: CHIPPME. Chip level auto power management enable. =0 =1 =0 =1 =0 =1 disable the auto power management functions enable the auto power management functions. disable the auto power management functions enable the auto power management functions. disable the auto power management functions enable the auto power management functions.
Bit 6: CIRPME. Consumer IR port auto power management enable.
Bit 5: MIDIPME. MIDI port auto power management enable.
Bit 4: Reserved. Return zero when read. Bit 3: PRTPME. Printer port auto power management enable. =0 =1 =0 =1 =0 =1 =0 =1 disable the auto power management functions. enable the auto power management functions. disable the auto power management functions. enable the auto power management functions. disable the auto power management functions. enable the auto power management functions. disable the auto power management functions. enable the auto power management functions.
Bit 2: FDCPME. FDC auto power management enable.
Bit 1: URAPME. UART A auto power management enable.
Bit 0: URBPME. UART B auto power management enable.
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CRF1 (Default 0x00) Bit 7: WAK_STS. This bit is set when the chip is in the sleeping state and an enabled resume event occurs. Upon setting this bit, the sleeping/working state machine will transition the system to the working state. This bit is only set by hardware and is cleared by writing a 1 to this bit position or by the sleeping/working state machine automatically when the global standby timer expires. =0 =1 the chip is in the sleeping state. the chip is in the working state.
Bit 6 - 5: Devices' trap status. Bit 4: Reserved. Return zero when read. Bit 3 - 0: Devices' trap status. CRF3 (Default 0x00) Bit 7 ~ 4: Reserved. Return zero when read. Bit 3 ~ 0: Device's IRQ status. These bits indicate the IRQ status of the individual device respectively. The device's IRQ status bit is set by their source device and is cleared by writing a 1. Writing a 0 has no effect. Bit 3: PRTIRQSTS. printer port IRQ status. Bit 2: FDCIRQSTS. FDC IRQ status. Bit 1: URAIRQSTS. UART A IRQ status. Bit 0: URBIRQSTS. UART B IRQ status. CRF4 (Default 0x00) Bit 7 ~ 4: Reserved. Return zero when read. Bit 3 ~ 0: These bits indicate the IRQ status of the individual GPIO function or logical device respectively. The status bit is set by their source function or device and is cleared by writing a1. Writing a 0 has no effect. Bit 3: HMIRQSTS. Hardware monitor IRQ status. Bit 2: WDTIRQSTS. Watch dog timer IRQ status. Bit 1: CIRIRQSTS. Consumer IR IRQ status. Bit 0: MIDIIRQSTS. MIDI IRQ status.
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CRF6 (Default 0x00) Bit 7 ~ 4: Reserved. Return zero when read. Bit 3 ~ 0: Enable bits of the PME/ SMI generation due to the device's IRQ. These bits enable the generation of an SMI / PME interrupt due to any IRQ of the devices. SMI / PME logic output = (PRTIRQEN and PRTIRQSTS) or (FDCIRQEN and FDCIRQSTS) or (URAIRQEN and URAIRQSTS) or (URBIRQEN and URBIRQSTS) or (HMIRQEN and HMIRQSTS) or (WDTIRQEN and WDTIRQSTS) or (IRQIN3EN and IRQIN3STS) or (IRQIN2EN and IRQIN2STS) or (IRQIN1EN and IRQIN1STS) or (IRQIN0EN and IRQIN0STS) Bit 3: PRTIRQEN. =0 =1 disable the generation of an SMI /PME interrupt due to printer port's IRQ. enable the generation of an SMI / PME interrupt due to printer port's IRQ.
Bit 2: FDCIRQEN. =0 =1 disable the generation of an SMI /PME interrupt due to FDC's IRQ. enable the generation of an SMI / PME interrupt due to FDC's IRQ.
Bit 1: URAIRQEN. =0 =1 disable the generation of an SMI /PME interrupt due to UART A's IRQ. enable the generation of an SMI / PME interrupt due to UART A's IRQ.
Bit 0: URBIRQEN. =0 =1 disable the generation of an SMI /PME interrupt due to UART B's IRQ. enable the generation of an SMI / PME interrupt due to UART B's IRQ.
CRF7 (Default 0x00) Bit 7 ~ 4: Reserved. Return zero when read. Bit 3 ~ 0: Enable bits of the SMI / PME generation due to the GPIO IRQ function or device's IRQ. Bit 3: HMIRQEN. =0 =1 disable the generation of an SMI /PME interrupt due to hardware monitor's IRQ. enable the generation of an SMI / PME interrupt due to hardware monitor's IRQ.
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Bit 2: WDTIRQEN. =0 =1 disable the generation of an SMI /PME interrupt due to watch dog timer's IRQ. enable the generation of an SMI / SMI interrupt due to watch dog timer's IRQ.
Bit 1: CIRIRQEN. =0 =1 disable the generation of an SMI /PME interrupt due to CIR's IRQ. enable the generation of an SMI / PME interrupt due to CIR's IRQ.
Bit 0: MIDIIRQEN. =0 =1 disable the generation of an SMI /PME interrupt due to MIDI's IRQ. enable the generation of an SMI / PME interrupt due to MIDI's IRQ.
CRF9 (Default 0x00) Bit 7 - 3: Reserved. Return zero when read. Bit 2: PME_EN: Select the power management events to be either an PME or SMI interrupt for the IRQ events. Note that: this bit is valid only when SMIPME_OE = 1. = 0 the power management events will generate an SMI event. = 1 the power management events will generate an PME event. Bit 1: FSLEEP: This bit selects the fast expiry time of individual devices. =0 1S = 1 8 mS. Bit 0: SMIPME_OE: This is the SMI and PME output enable bit. = 0 neither SMI nor PME will be generated. Only the IRQ status bit is set. = 1 an SMI or PME event will be generated.
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10.14 Logical Device B (Hardware Monitor)
CR30 (Default 0x00) Bit 7 - 1: Reserved. Bit 0: = 1 Activates the logical device. = 0 Logical device is inactive. CR60, CR 61 (Default 0x00, 0x00) These two registers select Hardware Monitor base address [0x100:0xFFF] on 8-byte boundary. CR70 (Default 0x00) Bit 7 - 4: Reserved. Bit 3 - 0: These bits select IRQ resource for Hardware Monitor.
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PRELIMINARY 11 ORDERING INSTRUCTION
PART NO. W83697HF PACKAGE 128-pin QFP REMARKS
12 HOW TO READ THE TOP MARKING
Example: The top marking of W83697HF
inbond
W83697HF
921A2B28201234
1st line: Winbond logo 2nd line: the type number: W83697HF 3th line: the tracking code 921 A 2 C 28201234 821: packages made in '98, week 21 A: assembly house ID; A means ASE, S means SPIL.... etc. 2: Winbond internal use. B: IC revision; A means version A, B means version B 282012345: wafer production series lot number
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PRELIMINARY 13 PACKAGE DIMENSIONS
(128-pin PQFP)
HE E
102 65
Symbol Min
Dimension in mm
Dimension in inch
Nom
0.35 2.72 0.20 0.15 14.00 20.00 0.50
Max
0.45 2.87 0.30 0.20 14.10 20.10
Min
0.010 0.101 0.004 0.004 0.547 0.783
Nom
0.014 0.107 0.008 0.006 0.551 0.787 0.020
Max
0.018 0.113 0.012 0.008 0.555 0.791
103
64
D
HD
128
39
1
e
38
b
A1 A2 b c D E e HD HE L L1 y 0
c
0.25 2.57 0.10 0.10 13.90 19.90
17.00 23.00 0.65
17.20 23.20 0.80 1.60
17.40 23.40 0.95
0.669 0.905 0.025
0.677 0.913 0.031 0.063
0.685 0.921 0.037
0.08 0 7 0
0.003 7
Note:
1.Dimension D & E do not include interlead flash. 2.Dimension b does not include dambar protrusion/intrusion . 3.Controlling dimension : Millimeter 4.General appearance spec. should be based on final visual inspection spec.
A A2 See Detail F Seating Plane A1 y
L L1 Detail F
5. PCB layout please use the "mm".
Headquarters
No. 4, Creation Rd. III Science-Based Industrial Park Hsinchu, Taiwan TEL: 886-35-770066 FAX: 886-35-789467 www: http://www.winbond.com.tw/
Winbond Electronics (H.K.) Ltd.
Rm. 803, World Trade Square, Tower II 123 Hoi Bun Rd., Kwun Tong Kowloon, Hong Kong TEL: 852-27516023-7 FAX: 852-27552064
Winbond Electronics (North America) Corp.
2730 Orchard Parkway San Jose, CA 95134 U.S.A. TEL: 1-408-9436666 FAX: 1-408-9436668
Taipei Office
11F, No. 115, Sec. 3, Min-Sheng East Rd. Taipei, Taiwan TEL: 886-2-7190505 FAX: 886-2-7197502 TLX: 16485 WINTPE
Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their original owners
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Publication Release Date: Aug 1999 Revision 0.40

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