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W83791SD Winbond H/W Monitoring IC
W83791SD
W83791SD Data Sheet Revision History
Pages
1 2 3 4 5 6 7 n.a. n.a. n.a. 01/Jan 02/Apr 0.5 1.0
Dates
Version
Version on Web
n.a. n.a. 1.0
Main Contents
All version before 0.50 are for internal use. First publication. Change all version include version on web site to 1.0
Please note that all data and specifications are subject to change without notice. All the trademarks of products and companies mentioned in this data sheet belong to their respective owners. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales.
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Publication Release Date: Jun,2001 Revision 1.0
W83791SD
TABLE OF CONTENTS 1. 2. GENERAL DESCRIPTION.......................................................................................3 FEATURES ..............................................................................................................3 2.1. 2.2. 2.3. 3. 4. 5. 6. SPEECH ITEM ....................................................................................................................3 GENERAL..........................................................................................................................4 PACKAGE ..........................................................................................................................4
KEY SPECIFICATIONS ...........................................................................................4 PIN CONFIGURATION.............................................................................................5 PIN DESCRIPTION ..................................................................................................6 FUNCTION DESCRIPTION......................................................................................8 6.1 SPEECH FUNCTION............................................................................................................8 6.1.1 General Description ................................................................................................8 6.1.2 Event Trigger Queue................................................................................................8 6.1.3 Connection of EEPROM..........................................................................................9 6.1.4 Speaker Output ......................................................................................................10
7.
ELECTRICAL CHARACTERISTICS......................................................................11 7.1 ABSOLUTE MAXIMUM RATINGS......................................................................................11 7.2 DC CHARACTERISTICS ...................................................................................................11 7.3 AC CHARACTERISTICS ...................................................................................................14 7.3.1 Serial Bus Timing Diagram ...................................................................................14
8. 9.
HOW TO READ THE TOP MARKING ...................................................................15 PACKAGE SPECIFICATION .................................................................................16
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Publication Release Date: Jun,2001 Revision 1.0
W83791SD
1.
GENERAL DESCRIPTION
W83791SD is a programmable speech synthesizer with 9-bit current DAC output that can connect to speaker or LINE_OUT by the AC'97 audio codec. It supports 1 CPU present or absent event trap, 5 external event traps, and 127 internal programmable event traps to trigger maximum 133 different speech output. If more than two events happen simultaneously, the priority set is: SLOTOCC# > EVNTRP1 > EVNTRP2 > EVNTRP3 > EVNTRP4 > EVNTRP5 > 127 Programmable events (Bank0 index 09h). For the application of error messages from BIOS, 127 Programmable events are enabled with a watch dog timer. The time interval is programmable and events will be triggered when time out. External flash memory interface with Winbond W55FXX is flexible to change warning voice message and support on-line programming flash data through I2CTM interface. An external resistor is added to provide ring oscillator. Through the application software or BIOS, the users can edit and change the voice database in the serial flash chip by themselves under O.S.. A free Windows AP --- Voice EditorTM is provided for the voice editing, which can accept the *.wav file as the voice database resource. Users can replace the voice with which they like through the S/W. W83791SD also provides two address setting pins A0 & A1 for different I2CTM address and can be connected up to 4 devices if necessary
2.
2.1.
* * * * * * * * * *
FEATURES
Speech Item
Programmable speech synthesizer New high fidelity synthesis algorithm Build in 8-bit current D/A converter Instruction cycle 400 S typically Section control provided in each voice section - Variable frequency: 4.8/6/8/12 KHz External resistor for ring oscillator 1 CPU present or absent trigger input 5 External trigger inputs 127 Internal programmable trigger inputs with a watch dog timer Programmable 0-255 seconds timeout trigger inputs
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Publication Release Date: Jun,2001 Revision 1.0
W83791SD
2.2.
2
General
TM
* I C serial bus interface * 2 pins (A0, A1) to provide selectable address setting for application of multiple devices (up to 4 devices) wired through I2CTM interface * Winbond hardware monitoring application software (Voice EditorTM ) support, for both Windows 95/98/ME/2000 and Windows NT 4.0/5.0 * Internal clock Oscillator with 3M Hz * 5V VDD operation
2.3.
Package
* 48-pin LQFP
3.
KEY SPECIFICATIONS
5V 5 mA typ.
* Supply Voltage * Operating Supply Current
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Publication Release Date: Jun,2001 Revision 1.0
W83791SD
4.
PIN CONFIGURATION
+ 3.3 GGV GGGV V G G V NNNDD N NN D NN I DDNDDDDD D DC D
NC GND GND GND VDD NC NC NC EVNTRP1 EVNTRP2 EVNTRP3 EVNTRP4
36 35 34 33 37 38 39 40 41 42 43 44 45 46 47 48 1 2 3 4
32 31 30
29
28 27
26 25 24 23 22 21 20
W83791SD
19 18 17 16 15 14
5
6
7
8
9
10 11
12
13
VDD NC SDA SC L VDD VDD VDD VDD GND SLOTOCC# GND VDD
EE RACD VOEDLA NP XDKT T T ROA R U P T 5
C T R L
M O D E
SAAV P01D E D A K E R
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Publication Release Date: Jun,2001 Revision 1.0
W83791SD
5.
PIN DESCRIPTION
I/O12t - TTL level bi-directional pin with 12 mA source-sink capability I/O12ts - TTL level and schmitt trigger with 12 mA source-sink capability I/OD8ts - TTL level and schmitt trigger open drain output with 8 mA sink capability OUT12 - Output pin with 12 mA source-sink capability INt - TTL level input pin INts - TTL level input pin and schmitt trigger AIN - Input pin(Analog)
Pin Name
EVNTRP5 EOP REXT ADDR
Pin No.
1 2 3 4
Type
IN t IN t IN t OUT12
Description
Event trapping to selection speech output sound. End of Process signal input from cascaded Flash. Resistor(Rosc) connect to VSB used to adjust ring oscillator frequency. Speech address pulse output, connect to W55FXX. When this pin translates from logic high to logic low, it will latch the data pin 6 and shift it into a speech flash address counter. Speech clock output, for speech data read-out and write-in, connect to W55FXX. When this pin translates from logic high to logic low, the data pin 6 will be latched by this clock. Serial data input/output, connect to W55FXX. The pin is latched by CLKOUT and ADDR acted as speech data and address respectively. Output clock numbers of this pin decide which mode is selected. Connect to W55FXX. Output mode signal to W55FXX serial Flash. Current type output driving an external speaker. The function is only working in VSB 5V OK. I2C device address bit0 trapping during 5VDD power on. I2C device address bit1 trapping during 5VDD power on. +5V VDD pins.
CLKOUT
5
OUT12
DATA
6
I/O12t
CTRL MODE SPEAKER A0 A1 VDD (5V)
7 8
12
OUT12 OUTOUT12 INts INts POWER
9 10 11 12,13,17, 18,19,20, 24,25,29, 30,41 14,16,27, 28,31,32, 33,35,36, 38,39,40 15
GND
GROUND
Ground pins
SLOTOCC#
INts
CPU presence signal. 0, means CPU is present. 1, means CPU is absent. 6 Publication Release Date: Jun,2001 Revision 1.0
W83791SD
NC SCL SDA +3.3VIN EVNTRP1-4
23,26,37, 42,43,44 21 22 34 45-48 INts I/OD8ts AIN I/O12ts
No connect. Serial Bus Clock. Serial Bus bi-directional Data. 0V to 4.096V FSR Analog Inputs. Event trapping to selection speech output sound.
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Publication Release Date: Jun,2001 Revision 1.0
W83791SD
6.
FUNCTION DESCRIPTION
6.1 Speech Function
General Description The W83791SD is a derivative of Winbond's PowerSpeechTM synthesizers. There are up to 5 hardware trigger inputs and 128 programmable software event trigger inputs. If more than two events happen simultaneously, the priority set by the internal H/W is: SLOTOCC# > EVNTRAP1 > EVNTRAP2 > EVNTRAP3 > EVNTRAP4 > EVNTRAP5 > TRIGREG(Index 09h) 128 events . Software trigger is able to accommodate 128 event triggers, with timeout register (index 08h) enabled in advance for allowance of time on detecting devices. That is, once the system's power is on, BIOS can fill trigger event and speech voice will not be sent till the system fails owing to timeout. In addition, to prevent events from taking place simultaneously. Event Trigger Queue W83791SD provides 8 byte FIFO queue to store event trigger, i.e, the first 8 event can be served by speech and speech will clear FIFO queue after service. Coding of Speech program must assign correct CPU_MODE event vector to issue correct speech voices correspondent to speech trigger events. For example, CPU_MODE event vector =1 represents absence of CPU, then coding speech with CPU is absent voice. When W83791D detects no CPU exists, it will send vector = 1 to speech synthesizer and play this voice data. Following is the block diagram of the 8-Byte event trigger queue.
Enable Timeout CLK 1 HZ
(Index 0Ah, b6)
6.1.1
6.1.2
8-bit Counter Timeout Comparator
TRIG_REG Event Trigger Data
Trigger Timeout Register
(Index 08h)
(Index 09h, b6~0)
8-Byte Event Trigger Queue
Figure 1. Event trigger Queue
For example: As BIOS usually has POST (Power On Self Test) program, then it will test every item step by step if no failure takes place, however, if it detects a failure on a specific item, it will hang on there. Therefore, BIOS could write timeout value to register 08h and start timer setup speech trigger event (register 09h), then is BIOS test program started. Whenever the system is hang on specific item such as DRAM testing, W83791SD would say "DRAM test fails" after the timeout previously set at CR[08h]. On the contrary, if DRAM test is ok, then BIOS could update the timeout value and proceed to the next test program.
Below is the speech CPU_MODE table of
W83791SD: 8 Publication Release Date: Jun,2001 Revision 1.0
W83791SD
CPU_MODE item POI SLOTOCC EVNTRAP1(TG1) EVNTRAP2 EVNTRAP3 EVNTRAP4 EVNTRAP5 TRIGREG Table 1. CPU_MODE Table
Definition Reserverd CPU present or absent Hardware trgger1 Hardware trgger2 Hardware trgger3 Hardware trgger4 Hardware trgger5 I2C setting software trigger
Vector (H) 0,32 1 2 3 4 5 6 80-FF
6.1.3 Connection of EEPROM As is described previously that the W83791SD has connectable W55FXX to store voice data. To expand the storage capacity, users can select many W55FXX to connect with each other. The maximum capacity could be up to 16Mbit. Following is the connection chart of W55FX with W83791SD.
EEPROM
DATA ADDR CLK CTRL MODE EOP DATA ADDR
EEPROM
CLK CTRL MODE EOP
SLOTOCC# EVTTRAP 1: 5
DATA ADDR
CLK
CTRL MODE
EOP
Speech Synthesizer (W83791SD)
Hardware monitor status trigger
9-bit DAC
SPEAKER
Internal programmable trigger
Figure 2. Speech Function Diagram
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Publication Release Date: Jun,2001 Revision 1.0
W83791SD
Speaker Output Speech output pin is a 8 bit Current D/A converter, with which loading is needed. The resistor could range from 510~1K ohm and bipolar could be a low power NPN bipolar with . Besides, SPK can also connect to AC97 codec chip Line_Out. C is decouple capacitor and is usually 200p- 0.01uF
6.1.4
8 ohm speaker SPK R C 8050D, NPN transistor
Figure. 3
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Publication Release Date: Jun,2001 Revision 1.0
W83791SD
7.
ELECTRICAL CHARACTERISTICS
7.1 Absolute Maximum Ratings
PARAMETER Power Supply Voltage Input Voltage Operating Temperature Storage Temperature
RATING -0.5 to 7.0 -0.5 to VDD+0.5 0 to +70 -55 to +150
UNIT V V C C
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device.
7.2 DC Characteristics
(Ta = 0 C to 70 C, VDD = 5V 10%, VSS = 0V) PARAMETER SYM. MIN. TYP. MAX. UNIT CONDITIONS
I/O12t - TTL level bi-directional pin with source-sink capability of 12 mA Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Input High Leakage Input Low Leakage VIL VIH VOL VOH ILIH ILIL 2.4 +10 -10 2.0 0.4 0.8 V V V V A A
IOL = 12 mA IOH = - 12 mA
VIN = VDD VIN = 0V
I/O12ts - TTL level bi-directional pin with source-sink capability of 12 mA and schmitt-trigger level input
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Publication Release Date: Jun,2001 Revision 1.0
W83791SD
Input Low Threshold Voltage Input High Threshold Voltage Hysteresis Output Low Voltage Output High Voltage Input High Leakage Input Low Leakage
VtVt+ VTH VOL VOH ILIH ILIL
0.5 1.6 0.5
0.8 2.0 1.2
1.1 2.4
V V V
VDD = 5 V VDD = 5 V VDD = 5 V
0.4 2.4 +10 -10
V V A A
IOL = 12 mA IOH = - 12 mA
VIN = VDD VIN = 0V
OUT12t - TTL level output pin with source-sink capability of 12 mA Output Low Voltage Output High Voltage VOL VOH 2.4 0.4 V V
IOL = 12 mA IOH = -12 mA
OD8 - Open-drain output pin with sink capability of 8 mA Output Low Voltage VOL 0.4 V
IOL = 8 mA
OD12 - Open-drain output pin with sink capability of 12 mA Output Low Voltage VOL 0.4 V
IOL = 12 mA
OD48 - Open-drain output pin with sink capability of 48 mA Output Low Voltage VOL 0.4 V
IOL = 48 mA
INt - TTL level input pin Input Low Voltage Input High Voltage Input High Leakage VIL VIH ILIH 12 2.0 +10 0.8 V V A VIN = VDD
Publication Release Date: Jun,2001 Revision 1.0
W83791SD
Input Low Leakage INts -
ILIL
-10
A
VIN = 0 V
TTL level Schmitt-triggered input pin VtVt+ VTH ILIH ILIL 0.5 1.6 0.5 0.8 2.0 1.2 +10 -10 1.1 2.4 V V V A A VDD = 5 V VDD = 5 V VDD = 5 V VIN = VDD VIN = 0 V
Input Low Threshold Voltage Input High Threshold Voltage Hysteresis Input High Leakage Input Low Leakage
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Publication Release Date: Jun,2001 Revision 1.0
W83791SD
7.3 AC Characteristics
7.3.1 Serial Bus Timing Diagram
t SCL
t
tR R
SCL
t HD;SDA
t SU;DAT t SU;STO
SDA IN
VALID DATA
t HD;DAT
SDA OUT Serial Bus Timing Diagram
Serial Bus Timing
PARAMETER SCL clock period Start condition hold time Stop condition setup-up time DATA to SCL setup time DATA to SCL hold time SCL and SDA rise time SCL and SDA fall time SYMBOL t-SCL tHD;SDA tSU;STO tSU;DAT tHD;DAT tR tF MIN. 10 4.7 4.7 120 5 1.0 300 MAX. UNIT uS uS uS nS nS uS nS
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Publication Release Date: Jun,2001 Revision 1.0
W83791SD
8.
HOW TO READ THE TOP MARKING The top marking of W83791SD
W 83791SD 025G C
Left: Winbond logo 1st line: Type number W83791SD, D means LQFP (Thickness = 1.4 mm). 2nd line: Tracking code 025 A A 025: packages made in 2000, week 25 G: assembly house ID; A means ASE, O means OSE, G means Greatek C: IC revision; A means version A, C means version C
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Publication Release Date: Jun,2001 Revision 1.0
W83791SD
9.
PACKAGE SPECIFICATION
(48-pin LQFP)
HD D
36 25
Symbol
Dimension in inch Min. Nom. Max.
Dimension in mm Min.
--0.05 1.35 0.17 0.09
Nom.
----1.40 0.20 --7.00 7.00 0.50 9.00 9.00
Max.
1.60 0.15 1.45 0.27 0.20
37
24
E
HE
48
13
1
e
b
12
A A1 A2 b c D E e HD HE L L1 y 0
Notes:
c
0.45
0.60 1.00
0.75
--0
0.08 3.5
--7
A2 A1 y
A
Seating Plane
See Detail F
L L1
Detail F
1. Dimensions D & E do not include interlead flash. 2. Dimension b does not include dambar protrusion/intrusion. 3. Controlling dimension: Millimeters 4. General appearance spec. should be based on final visual inspection spec.
Headquarters
No. 4, Creation Rd. III Science-Based Industrial Park Hsinchu, Taiwan TEL: 886-35-770066 FAX: 886-35-789467 www: http://www.winbond.com.tw/
Winbond Electronics (H.K.) Ltd.
Rm. 803, World Trade Square, Tower II 123 Hoi Bun Rd., Kwun Tong Kowloon, Hong Kong TEL: 852-27516023-7 FAX: 852-27552064
Winbond Electronics (North America) Corp.
2730 Orchard Parkway San Jose, CA 95134 U.S.A. TEL: 1-408-9436666 FAX: 1-408-9436668
Taipei Office
11F, No. 115, Sec. 3, Min-Sheng East Rd. Taipei, Taiwan TEL: 886-2-7190505 FAX: 886-2-7197502 TLX: 16485 WINTPE
Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owner. 16 Publication Release Date: Jun,2001 Revision 1.0
3VCC R1 R 4.7K 330 R2 R 4.7K SMDAT SMCLK R4 R 330
SDA SCL
R R3
+3.3V GND R5 10K
GND GND GND VCC VCC GND
GND GND
VCC
U1
3VCC
36 35 34 33 32 31 30 29 28 27 26 25
GND GND +3.3VIN GND GND GND VDD VDD GND GND NC VDD
GND
EVNTRAP5 EOP REXT ADDR CLKOUT DATA CTRL MODE SPEAKER A0 A1 VDD
EVNTRAP1 EVNTRAP2 EVNTRAP3 EVNTRAP4
37 38 39 40 41 42 43 44 45 46 47 48
NC GND GND GND VDD NC NC NC EVNTRAP1 EVNTRAP2 EVNTRAP3 EVNTRAP4
VDD NC SDA SCL VDD VDD VDD VDD GND SLOTOCC# GND VDD
24 23 22 21 20 19 18 17 16 15 14 13
VCC SDA SCL
R6 R 10K SLOTOCC#
VCC
(From PII/PIII CPU)
0: means CPU is present 1: means CPU is absent
GND GND VCC C1 VCC
CAP 10u W83791SD
C2 CAP 0.1u
EVNTRAP5
A0 A1 VCC
1 2 3 4 5 6 7 8 9 10 11 12
EOP
SPK MODE CTRL DATA CLKOUT ADDR R8 VCC 220K R
VCC R7 A0 4.7K R9 4.7K WINBOND ELECTRONICS CORP.
A1
NOTE :
The EVNTRAP1-5 trigger inputs default are low to high active.
I2C slave address is 0x5A.
Title Size B Date:
W83791SD Application Circuit Document Number Tuesday, May 29, 2001 Sheet 1
of
Rev 0.1 3
SPK SPKOUT 1uF/16V C3
SPKOUT
R10 510
VCC C4 LINE_OUT_L 1uF/16V R11 470K 100pF LINE_OUT C5 J1
LS1
8 ohm SPEAKER
From AC' 97 Codec (W83972D)
SPKOUT C7 LINE_OUT_R 1uF/16V 470K C8 100pF R12
C6 0.1uF
Q1 NPN 8050D
(SPEECH FUNCTION)
(SPEECH FUNCTION)
Note : Select SPEECH Function by one of two cricuits.
Connect to serial FLASH EEPROM (W55FXX)
VCC EOP
VCC
U2 MODE U3 U4 MODE EOP CTRL VSS ADDR VDD CLK DATA W55F10 MODE VDD CLK DATA W55F10 5 4 DATA 6 3 CKOUT 7 2 8 1 MODE 8 7 6 5 1 2 3 4 1 CLKOUT CTRL CTRL VSS ADDR 3 ADDR 4 2 DATA EOP U5 EOP CTRL VSS ADDR MODE VDD CLK DATA W55F10 8 7 6 5
EOP
EOP
1
EOP
MODE
8
MODE
CTRL
CTRL
2
CTRL
VDD
7
3
VSS
CLK
6
CKOUT
ADDR
4
ADDR
DATA
5
DATA
ADDR
W55F10
Connect 1 FLASH
Connect 2 or more FLASH
WINBOND ELECTRONICS CORP.
Title W83791SD Application Circuit Size Document Number Custom Date: Tuesday, May 29, 2001 Sheet 2 Rev 0.1
of
3
REV
Decription
0.1
First Publication
WINBOND ELECTRONICS CORP.
Title Size A Date:
W83791SD Application circuit Document Number Tuesday, May 29, 2001 Sheet 3
of
Rev 0.1 3

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