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aqlN/|--1/2q Weltrend Semiconductor, Inc.
WT6802 Monitor OSD with Auto-calibration Data Sheet REV. 1.0 April, 9, 2001
The information in this document is subject to change without notice. (c)Weltrend Semiconductor, Inc. All Rights Reserved. 2421/4O 2F, No. 24, Indust E. 9 RD., Science-Based Industrial Park, Hsin-Chu, Taiwan TEL:886-3-5780241 FAX:886-3-5794278.5770419 Email:support@weltrend.com.tw
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aqlN/|--1/2q WT6802 Weltrend Semiconductor, Inc. Rev.1.0 Data Sheet
DESCRIPTION WT6802 is designed to interface with a MCU to do the OSD (On Screen Display) function in CRT Monitor, besides the fancy auto-calibration function is also included. The on-chip PLL generates a wide-ranged system clock up to 60MHz to meet the resolution requirements(OSD resolution is programmable) of different display modes. The full OSD screen size is 30 columns x 15 rows, and the OSD position can be freely programmed by setting the interal registers. Special functions include color font, character bordering, shadowing, blinking, double height, double width, all blanking effect, row to row spacing control, 4 windows with shadowing, and programmable fin in/fan out effect. WT6802 has 8 channels of PWM DAC, each PWM DAC can be respectively controlled by an 8-bit register which contains a 5-bit PWM and 3-bit BRM, and the PWM clock is also programmable. The horizonal back/front porch and vertical black/front porch data can be read by MCU through the I2C bus in order to do the horizontal size/center and vertical size/center auto-calibration. FEATURES sInput horizontal synchronous frequency ... ... .15k-130kHZ sDot Frequency generated by On-chip PLL ... ..up to 160MHz sResolution ... ... ... programmable, up to 2040 dots/line sScreen ... ... ... ... ... ... ... ... ... ..30 columns x 15 rows sCharacter ... ..12(H) x 18(V) dot matrix Fonts ... ... ... ... 512 characters and 16 color fonts 2 MCU interface I C bus sColor(R, G, B with intensity attribute) Character foreground 8(R, G, B) Character background 7(no blank) Window 8(R, G, B) Window shadowing 8(R, G, B) s PWM DAC 8 channels sRow to row spacing control sDouble character height and width sProgrammable character height control 18-69 lines sCharacter blinking, bordering(or shadowing) s4 programmable background windows with multi-level operation sHorizontal/vertical size and center Auto-calibration
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aqlN/|--1/2q WT6802 Weltrend Semiconductor, Inc. Rev.1.0 Data Sheet
PIN CONFIGURATION RI 1 NC 2 VSSA3 VDDA4 VCO 5 VDDA6 HS 7 NC 8 SDA 9 SCL 10 20 GI 19 BI 18 VSS 17 R 16 G WT6802 15 B 14 BLANK 13 TEST 12 VS 11 VDD
WT6802 (DIP-20)
VSSA1 NC 2 VCO 3 VDDA4 HS 5 NC 6 SDA 7 SCL 8 PWM69 10 PWM4 PWM2 11 PWM0 12
24 VSS 23 R 22 G 21 B 20 BLANK 19 TEST WT6802 18 VS 17 VDD 16 PWM7 15 PWM5 14 PWM3 13 PWM1
WT6802 (DIP-24, 300mil)
RI 1 NC 2 VSSA3 NC 4 VCO5 VDDA6 HS 7 NC 8 SDA 9 SCL10 PWM6 11 PWM4 12 PWM2 13 14 PWM0
WT6802
28 GI 27 BI 26 VSS 25 R 24 G 23 B 22 BLANK 21 TEST 20 VS 19 VDD 18 PWM7 17 PWM5 16 PWM3 15 PWM1
VSSA 1 NC 2 VCO 3 VDDA 4 HS 5 NC 6 SDA 7 SCL 8
WT6802
16 VSS 15 R 14 G 13 B 12 BLANK 11 TEST 10 VS 9 VDD
WT6802 (DIP-16)
WT6802 (DIP-28, 300mil)
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aqlN/|--1/2q WT6802 Weltrend Semiconductor, Inc. Rev.1.0 Data Sheet
BLOCK DIAGRAM
SDA SCL
MCU Interface
Display RAM
Display Font ROM
Window Control Circuit / Frame Control
12 bit Shift Registers Vertical Sync Control Circuit R, G, B Video Output Control Circuit
VS
RI BI GI Autocalibration Control Circuit
BLANK
VCO HS
PLL Circuit Horizontal Sync Control Circuit
PWM Control Circuit
PWM0~7
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aqlN/|--1/2q WT6802 Weltrend Semiconductor, Inc. Rev.1.0 Data Sheet
PIN DESCRIPTION PIN No 28 pin 1 2 3 24 pin --1 20 pin 1 2 3 16 pin --1 RI NC VSSA Analog ground No NC connectio n VCO VDDA VCO __ Red Input input Video Red input from Pre-AMP Symbol Pin Name Input/ output Description
4 5 6 7
2 3 4 5
4 5 6 7
2 3 4
__ __ Connected to external loop filter circuit
8 9 10
6 7 8
8 9 10
11~18 9~16
--
19 20 21 22
17 18 19 20
11 12 13 14
Analog __ +5 V power Horizonta 5 HS l Input Horizontal synchronous input signal SYNC No 6 NC connectio __ n Serial Input/out 2 7 SDA I C data data put Serial 8 SCL input I2 C clock clock 8 channels of 8-bit PWM DAC. Refer to pin PWM0~ PWM assignment in -output PWM7 DACs page1 for each PWM DAC's pin assignment. Digital 9 VDD __ +5 V power Vertical 10 VS input Vertical synchronous input signal SYNC 11 12 TEST TEST output output
5
Output test only Blank signal output
BLANK Blank
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aqlN/|--1/2q WT6802 Weltrend Semiconductor, Inc. Rev.1.0 Data Sheet
23 24 25 26 27 28 21 22 23 24 --15 16 17 18 19 20 13 14 15 16 --B G R VSS BI GI Blue output Green output Red output Digital Ground Blue input Green input output output output Blue signal output Green signal output Red signal output
input input
Video Blue input from Pre-AMP Video Green input from Pre-AMP
MCU INTERFACE
CHIP ADDRESS ACK DATA BYTES ACK
SDA
SCL 1 START 2-7 8 9 STOP
WT6802 uses I2 C to interface with MCU, the Max. data rate is 100 kbps. Default Chip Address byte is as : Read / A6 A5 A4 A3 A2 A1 A0 Write R= 1 , 0 1 1 1 1 0 1 W= 0 (i.e. 7AH for write, 7BH for read) The MCU master initiates a transmission by sending a START ( SDA goes low first, then SCL goes low ), followed by a slave Chip Address byte. Once the address is properly identified, the slave WT6802 will respond with an ACK by pulling SDA to low during the 9th SCL clock. Each data byte which then follows must be 8 bits long with an ACK as the 9th bit. In the case of no ACK or complete of data transmission, the master will send a STOP (SCL goes high first, then SDA goes high).
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aqlN/|--1/2q WT6802 Weltrend Semiconductor, Inc. Rev.1.0 Data Sheet
DATA TRANSMISSION FORMAT (1) Data write To access a specific register in WT6802 , a Row address byte and a Column address byte must be given by MCU to WT6802. There are 3 kinds of data transmission format options to optimize the transmission efficiency, depending on different situations. (A) R a C a D a R a C a D a ... ... ... . (B) R a C a D a C a D a C a ... ... ... . (C) R a C a D a D a D a D a ... ... ... . R : Row address byte , C : Column address byte , D : Data byte
During a single transmission, it is permissible to change the format from (A) to (B), or from (A) to (C), or from (B) to (A),or from (B) to (C), but not from (C) back to (A) or (B). During a Data bytes updating, it is recommended that format (A) is used for those Data bytes which have different Row and different Column address bytes, format (B) for the same Row but different Column address bytes and format (C) for the same Row address and continuous Column address bytes. Format (C) is the best choice for large area screen pattern updating, these Data bytes will be written with Column address bytes automatically increased for each Data byte updating. During the format (C) transmission, a dummy Data byte should be inserted in Data byte train if Column address reaches one of those undefined registers in WT6802. To differentiate the Row address byte of Character Display Register from the Row address byte of Character Attribute register, the most significant 3 bits are set to " 100 " to represent the Character Display Row address byte, and " 101 " for Character Attribute ROW address byte. Bit 7 Bit 6 Bit 5 (Character Display, Window Reg) 1 Row address byte (Character/ Row Attribute, Control, 1 Auto-calibration Reg) Row address byte Column address byte 0 Column address byte 0 X : Don't Care AD : Address 0 0 Bit 4 Bit 3 Bit 2 Bit 1 X AD AD AD Bit 0 AD Format A,B,C
0
1
X AD AD
AD AD AD
AD AD AD
AD AD AD
AD AD AD
A,B,C A,B C
0 X 1 X of register
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aqlN/|--1/2q WT6802 Weltrend Semiconductor, Inc. Rev.1.0 Data Sheet
(2) Data read The data read fomat is written for the right row and column address and then follows the IIC read format.
S
0111101 A ROW A COL 0 A: ACK
0 0
AS
KKKK 0111101 A Data A P 1 KK COL: column address P: Stop
S: Start
ROW: Row address
COLUMN 28 29
Bit7-5 of address byte =100 Bit7-5 of address byte=101
Character Display Reg
30 Row Attribute Reg
31
Auto-callibration Reg
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ROW Character Attribute Reg 13 14 15 Window Reg & Auto-calibration Reg Control Reg
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aqlN/|--1/2q WT6802 Weltrend Semiconductor, Inc. Rev.1.0 Data Sheet
REGISTER DESCRIPTION (1)Character Display Registers ROW m (m=0~14) ; COLN n (n=0~29) Bit Symbol Description CRAD0 These 8 bits,CRAD7~CRAD0, select 1 character/symbol to be displayed on ~ 0~7 OSD screen from the 512 CRAD characters/ symbols in the ROM fonts. 7 Note: For all the Character Display Registers (described in (1) above) and the Window Registers (described in (4) below ) and the auto calibration registers (described in (6)), the most significant 3 bits of their Row address bytes must be set to "100" during the data transmission between MCU and WT6802. But for all the other registers (Character Attribute Registers Row Attribute Registers and Control Registers ), the Row address bytes must be set to "101". (2)Character Attribute Registers ROW m (m=0~14) ; COLN n (n=0~29) Bit Symbol Description 0 B R,G,B defines the foreground color of the corresponding character/ symbol 1 G selected by Character Display Register. 2 R Refer to Table 1 3 4 5 6 BLINK BB BG BR If BLINK=1, the corresponding character/ symbol selected by Character Display Registers will blink. The blinking frequency is the frequency of VS divided by 64 and the duty cycle is 50%. BR, BG, BB defines the background color of the corresponding character selected by the Character Display Registers, but, if BR, BG, BB =( 0, 0, 0 ), there is no background ( ie transparent ) for this character/ symbol. Refer to Table 1. Not used Border and shadow Black Blue Green Cyan Red Magenta Yellow white Color font(F0HFFH) TRANSPARENT Blue Green Cyan Red Magenta Yellow white
R 0 0 0 0 1 1 1 1
G 0 0 1 1 0 0 1 1
B 0 1 0 1 0 1 0 1
Foreground Background TRANSPAR Black ENT Blue Blue Green Green Cyan Cyan Red Red Magenta Magenta Yellow Yellow White white
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Window Black Blue Green Cyan Red Magenta Yellow white
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aqlN/|--1/2q WT6802 Weltrend Semiconductor, Inc. Rev.1.0 Data Sheet
Table 1 color for character foreground, character background, window, border/shadow and color font (3)Row Attribute Registers ROW m (m=0~14) ; COLN 30 Bit Symbol Description Double Width control for ROWm (m=0~14). If DWm=1, the widths of the even 0 DWm column characters in ROWm will be doubled and the odd column characters will not be displayed. Double Height control for ROWm (m=0~14). If DHm=1, the heights of all the 1 DHm characters in ROWm will be doubled. 2~7 Not used : (4) Window Registers Window1 Registers ROW 15 ; COLN n (n=0~2 ) Window2 Registers ROW 15 ; COLN n (n=3~5 ) Window3 Registers ROW 15 ; COLN n (n=6~8 ) Window4 Registers ROW 15 ; COLN n (n=9~11 ) Other window registers ROW 15 ; COLN 12~15 Note: There are 4 windows Max. can be set up, the controls of these windows are similar, take Window1 as an example: Window1 Registers: ROW 15 ; COLN 0 Bit Symbol Description WREND 0 0~3 WREND3~0 defines the row end address of Window1 ~ WREND 3 WRSTA RT0~ WRSTART3~0 defines the row start address of Window1 4~7 WRSTA RT3
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aqlN/|--1/2q WT6802 Weltrend Semiconductor, Inc. Rev.1.0 Data Sheet
ROW 15 ; COLN 1 Bit Symbol Description 0 WSHD If WSHD=1, black-edge shadowing of Window1 will be enabled 1 Not used If WENB=1, Window1 will be enabled. If WENB=0, Window1 is disabled, and 2 WENB all the characters in this window will not be displayed WCSTA RT0~ 3~7 WCSTART4~0 defines the column start address of window1 WCSTA RT4 ROW 15 ; COLN 2 Bit Symbol Description 0 WB WR, WG, WB defines the Window1 color. Refer to Table 1. The Window1 color 1 WG will offer the background color( if Window1 is enabled ) for those characters which background color settings are 2 WR transparent and are included in the Window1 area. WCEND 0 ~ 3~7 WCEND4~0 defines the column end address of Window1 WCEND 4 Note: There are 4 windows can be used. If window over-lapping happens, the higher priority window will cover the lower one. Window1 has the highest priority and Window4 the least. Other window Registers : ROW 15 ; COLN 12 ( window shadow height setting ) Bit Symbol Description 0 WSH10 Defines the window shadow height of Window1. Refer to table 3. 1 WSH11 2 WSH20 Defines the window shadow height of Window2. Refer to table 3. 3 WSH21 4 WSH30 Defines the window shadow height of Window3. Refer to table 3. 5 WSH31 6 WSH40 Defines the window shadow height of Window4. Refer to table 3. 7 WSH41
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aqlN/|--1/2q WT6802 Weltrend Semiconductor, Inc. Rev.1.0 Data Sheet
ROW 15 ; COLN 13 ( Window shadow width setting ) Bit Symbol Description 0 WSW10 Defines the window shadow width of Window1. Refer to table 2. 1 WSW11 2 WSW20 Defines the window shadow width of Wndow2. Refer to table 2. 3 WSW21 4 WSW30 Defines the window shadow width of Window3. Refer to table 2. 5 WSW31 6 WSW40 Defines the window shadow width of Wndow4. Refer to table 2. 7 WSW41 WSWk1 0 0 1 1 WSWk0 Shadow width( dots) 0 1 0 1 2 4 6 8 WSHk1 WSHk0 0 0 1 1 0 1 0 1 Shadow height( scan lines ) 2 4 6 8 Table 3 K=1~4 for
Table 2 k=1~4 for window1-window4 window1-window4
X (dots) X is decided by ( WSWk1, WSWk0 ) Y is decided by ( WSHk1, WSHk0 )
Window area Y (scan lines) Y (scan lines)
Window shadow X (dots)
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aqlN/|--1/2q WT6802 Weltrend Semiconductor, Inc. Rev.1.0 Data Sheet
ROW 15 ; COLN 14 ( window shadowing color setting ) Bit Symbol Description WSC1(B, 0~2 Defines the window shadowing color of Window1. Refer to Table 1. G,R) 3 Not used WSC2(B, 4~6 Defines the window shadowing color of Window2. Refer to Table 1. G,R) 7 Not used ROW 15 ; COLN 15 ( window shadowing color setting ) Bit Symbol Description WSC3(B, 0~2 Defines the window shadowing color of Window3. Refer to Table 1. G,R) 3 Not used WSC4(B, 4~6 Defines the window shadowing color of Window4. Refer to Table 1. G,R) 7 Not used (5) Control Registers ROW 15 ; COLN 0 Bit Symbol Description 0~2 FB1 We divide 512 fonts into 8 font banks. FB1 and FB2 determine font bank. 3~5 FB2 6 DIV1 DIV1, DIV0 determines the PWM clock. The PWM clock = Dotc / 1 if (DIV0, DIV1) = (0, 0) , where Dotc is the dot frequency from internal PLL Dotc / 2 if (DIV0, DIV1) = (0, 1) 7 DIV0 Dotc / 4 if (DIV0, DIV1) = (1, 0) Dotc / 8 if (DIV0, DIV1) = (1, 1)
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aqlN/|--1/2q WT6802 Weltrend Semiconductor, Inc. Rev.1.0 Data Sheet
Physical Page0 (000~03F) Page3 (0C0~0FF) Page1 (040~07F) Page2 (080~0BF) (080~0AF) Page4 (100~13F) Page5 (140~17F) Page6 (180~1BF) Page7 (1C0~1FF) Page C (040~07F) Page D (080~0BF) (080~0AF) Logical Page A (000~03F) Page B (0C0~0FF)
Physical page vs. Logical page Note:Page C and Page D can be chosed from Page1, Page2, Page4, Page5, Page6, Page7. Use FB1 to decide which page is assigned to Page C,and use FB2 to decide which page is assigned to Page D. For example, if the value of FB1 is `b010 then Page C is assigned to Page2. If the value of FB2 is `b110 then Page D is assigned to Page6. Table 4. Font bank selector ROW 15 ; COLN 1 ( OSD resolution setting ) Bit Symbol Description If DR=0,OSD resolution = DOTN X 4 , if DR =1 ,OSD resolution = DOTN0~ DOTN X 8 0~7 DOTN7 where DOTN = (DOTN7 ... .DOTN0 2) ROW 15 ; COLN 2 ( Horizontal start position ) Bit Symbol Description The OSD horizontal start position = HP X 6 dots , counting from the HP0~H trailing edge of HS pin signal. 0~7 P7 Where HP = ( HP7 ... .. HP02) ( HP7 ... .. HP02) = ( 00..0 ) is not allowed.
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aqlN/|--1/2q WT6802 Weltrend Semiconductor, Inc. Rev.1.0 Data Sheet
ROW 15 ; COLN 3 ( Vertical start position setting ) Bit Symbol Description The OSD vertical start position = VP X 4 + 1 scan lines , counting from the leading edge of VS pin signal . 0~7 V0~VP7 Where VP = ( VP7 ... .. VP02) ( VP7 ... .. VP02) = ( 00..0 ) is not allowed. ROW 15 ; COLN 4 ( Character height & Dot frequency range setting ) Bit Symbol Description The character height can be expanded from the 12 X 18 font matrix by setting CH5~CH0. The display character height = CH + ADJ scan lines , ( i.e. Character height range is 18 to 69 scan lines ) CH0~C Where CH=( CH5 ... .CH0 2) CH should be 0~5 H5 16 ( default ) at least. ADJ= 2 if 16 O CH < 32 4 if 32 O CH < 48 6 if 48 O CH < 64 ( HF, LF ) determines the frequency range of Dotc, dot frequency from the PLL, ( HF, LF ) = (1,1) 100 MHz < Dotc O 160MHz ( HF, LF ) = (1,0) 50 MHz < Dotc O 100 MHz ( HF, LF ) = (0,0) 25 MHz < Dotc O 50 MHz ( HF, LF ) = (0,1) 12.5 MHz O Dotc < 25 MHz 6 LF Note: If Disable CMODE : DR=0, Dotc = DOTN X 4 X ( Frequency of HS ) , DR =1 , Dotc = DOTN X 8 X ( Frequency of HS ) If enable CMODE: DR=0, Dotc = (DOTN X 4) X (HTOTAL / HPERIOD) X (Frequency of HS ) DR=1, Dotc = (DOTN X 8) X (HTOTAL / HPERIOD) X (Frequency of HS ) The default value of ( HF, LF) is (0, 0).
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aqlN/|--1/2q WT6802 Weltrend Semiconductor, Inc. Rev.1.0 Data Sheet
7
HF
HTOTAL
HPERIOD HWIDTH
Note: The character height is the result of : multi-scan lines plus repeat lines ( CH5, CH4 ) determines the multi-scan lines ( duplicating the all the scan lines originated from the 12 X 18 font matrix ) as : Single-scan lines ( 18 scan lines ) if ( CH5, CH4 ) = 01 Double-scan lines ( 36 scan lines ) if ( CH5, CH4 ) = 10 Triple-scan lines ( 54 scan lines ) if ( CH5, CH4 ) = 11 ( CH3 ~ CH0 ) determines the repeat lines ( repeating the scan lines, ranging from 0 to 15 lines, originated from the 12 X 18 font matrix ) as : REPEAT LINES 7 8 9 10 11 12 13 14 15 16 17 -V -V V -V -V -V -V -V -V -V -
CH0=1 CH1=1 CH2=1 CH3=1
0 -
1 -
2 V
3 V -
4 V
5 V -
6 V
Table 4. Repeat lines
ROW 15 ; COLN 5 ( Miscellaneous setting )
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aqlN/|--1/2q WT6802 Weltrend Semiconductor, Inc. Rev.1.0 Data Sheet
Bit 0 Symbol BLANK C FAN DIV CLR Description If BLANKC=0 , BLANK pin will be high during displaying character foreground and window. If BLANKC=1 , BLANK pin will be high only during displaying character foreground . If FAN=1 , fan in (/ fan out) effect is enabled while the OSD is turned on (/ off ) by setting OSDEN=1 ( / 0) If DIV=0, the fan in/ fan out speed will be high speed than DIV=1 Setting CLR=1 will clear all the Character Display Registers and Character Attribute Registers Setting CMODE=1 will refresh the horizontal synchronous pulse width and keep the ratio of A : B : C (refer to the figure below) same as the last display mode. After this action, CMODE will return to 0 automatically. CMODE setting can (option) be used when a new display mode is coming and want to keep fixed A : B : C ratio. If SHDW=1, black-edged shadow is selected when BSEN=1 If SHDW=0, black-edged border is selected when BSEN=1 If BSEN=1, enable character bordering ( or shadowing depending on SHDW ) If OSDEN=1 , enable OSD circuit.
1 2 3
4
CMODE
5 6 7
SHDW BSEN OSDEN
A
B OSD Monitor video raster
C
ROW 15 ; COLN 6 ( Miscellaneous setting ) Bit Symbol Description If the polarity of VS pin input signal is negative, set VSPO to 0 (default), and 0 VSPO set to 1 for positive VS. If the polarity of HS pin input signal is negative, set HSPO to 0 (default), and 1 HSPO set to 1 for positive HS. If TRI=1, then R, G, B, BLANK output pins will be Low when OSDEN=0 (OSD disabled) 2 TRI If TRI=0, then R, G, B, BLANK output pins will be in high impedance state when OSDEN=0 (OSD disabled) SP0~SP 3~7 SP4~SP0 defines the row to row space in unit of horizontal scan lines. 4
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aqlN/|--1/2q WT6802 Weltrend Semiconductor, Inc. Rev.1.0 Data Sheet
Note: After setting TRI bit, R, G, B and BLANK output pins will be change status when you enable OSD. ROW 15 ; COLN 7 Bit Symbol Description 0~2 Must set "0" 3 SREST Set to 1 for software reset, then set to 0 for normal operation 4~7 Must set "0" ROW 15 COLN 8~15 ( PWM Control Registers; PWMn, n=0~7, output pin control respectively ) Bit Symbol Description BRM0~BR (BRM2...BRM0) controls the pulse inserted position. 0-2 M2 (PW4 ... PW02) controls the duty cycle of PWMn output pin (n=0~7), refer to 3~7 PW0~PW4 the following figure for details. Example of PWM0~PWM7 setting : The figure below shows the waveforms when PWM Register setting of PWM0 ~PWM7 is 30H, 28H, 80H, 30H, 28H, 28H, 70H, 10H respectively.
0 PWM clock 32 64 96 128 160 192 224 256 (0) 32 64
PWM0 PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 PWM7
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Example of PWM setting : The figure below shows the waveforms when 5-bit PWM Register is setting to `b01100 and 3-bit BRM is setting to `b011. The pulse insertion algorithm is also show in the figure. 18
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aqlN/|--1/2q WT6802 Weltrend Semiconductor, Inc. Rev.1.0 Data Sheet
8bit PWM `b01100011
99/256
5-bit PWM `b01100
12/32 = 96/256 1/32 = 8/256
3-bit BRM `b011
5-bit PWM + 3-bit BRM
96/256
104/256
BRM `b000 BRM `b001 BRM `b010 BRM `b011 BRM `b100 BRM `b101 BRM `b110 BRM `b111
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aqlN/|--1/2q WT6802 Weltrend Semiconductor, Inc. Rev.1.0 Data Sheet
ROW 15 ; COLN 16 ( Miscellaneous setting ) Bit Symbol Description 0 BSB 1 BSG BSR, BSG, BSB defines the border and shadow color. Refer to Table 1. 2 BSR 3 Not used Color font selected at address F0H to FFH if CFONT=1, otherwise mono4 CFONT color selected at address F0H to FFH 5 Not used CMODE 6 Set to 0 for enable CMODE function, set to 1 for disable CMODE function EN 7 DR Double OSD resolution enabled if DR=1 COLOR FONT There are total 512 fonts can be used in WT6802, address 00H should be left blank -- and white,Font address from F0 to FFH are used for color fonts, each color font is made up of 3 different R, G, B fonts which should be defined during the font design stage. Refer to table 1 for the relation between color font and R, G, B fonts
+
+
Yellow Blue
R Font
G Font
B Font
(6) Auto-calibration Registers Auto-calibration registers are read-only registers except Refresh register. MCU can read the data in these registers through I2C bus (ID : 7BH) to do the horizontal / vertical size, center autocalibration by S/W algorithm. The RESET bit in Refresh register is used to refresh these Autocalibration registers in order that the MCU can do the Auto-calibration according to the new coming display mode. The clock used by auto-calibration circuit is synchronous with Dotc, dot frequency from the internal PLL. This Auto-calibration clock will be started only after the RESET bit is set to 1. And in order to get the stable and refreshed data , it is recommended that MCU should wait for at least 2 vertical synchronous signal time after RESET bit set to 1 before it reads these Auto-
Color Font
*s|Ei3/4Cu*~eIu*~FEo 2421/4O
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aqlN/|--1/2q WT6802 Weltrend Semiconductor, Inc. Rev.1.0 Data Sheet
calibration registers.
H-Blank ROW 15, COL16~17
RI,GI,BI Video
ROW15, COL18~19 V-Blank
ROW15, COL20~21
ROW15, COL22~23
RI,GI,BI Video
ROW15, COL24~25
ROW15, COL26~27
ROW 15 ; COLN 16 Bit R/W 0~7 R Horizontal Active low byte ROW 15 ; COLN 17) Bit R/W 0~2 R Horizontal Active high byte 3~7 Not used
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Description
Description
*s|Ei3/4Cu*~eIu*~FEo 2421/4O
2F, No. 24, Industry E. 9th RD., Science-Based Industrial Park, Hsin-Chu, Taiwan TEL:886-3-5780241 FAX:886-3-5794278.5770419 Email:support@weltrend.com.tw
aqlN/|--1/2q WT6802 Weltrend Semiconductor, Inc. Rev.1.0 Data Sheet
ROW 15 ; COLN 18 Bit R/W Description 0~7 R Horizontal Back Porch low byte ROW 15 : COLN 19 Bit R/W Description 0~2 R Horizontal Back Porch high byte 3~7 Not used ROW 15 ; COLN 20 Bit R/W Description 0~7 R Horizontal Front porch low byte ROW 15 ; COLN 21 Bit R/W Description 0~2 R Horizontal Front porch high byte 3~7 Not used ROW 15 ; COLN 22 Bit R/W 0~7 R Vertical Active low byte ROW 15 ; COLN 23 Bit R/W 0~2 R Vertical Active high byte 3~7 Not used ROW 15 ; COLN 24 Bit R/W 0~7 R Vertical Back Porch low byte ROW 15 ; COLN 25 Bit R/W 0~2 R Vertical Back Porch high byte 3~7 Not used ROW 15 ; COLN 26 Bit R/W 0~7 R Vertical Front Porch low byte
Description
Description
Description
Description
Description
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*s|Ei3/4Cu*~eIu*~FEo 2421/4O
2F, No. 24, Industry E. 9th RD., Science-Based Industrial Park, Hsin-Chu, Taiwan TEL:886-3-5780241 FAX:886-3-5794278.5770419 Email:support@weltrend.com.tw
aqlN/|--1/2q WT6802 Weltrend Semiconductor, Inc. Rev.1.0 Data Sheet
ROW 15 ; COLN 27 Bit R/W 0~2 R Vertical Front Porch high byte 3~7 Not used Description
ROW 15 ; COLN 28 ( Refresh register ) Bit Symbol Description Setting RESET to 1 will put the default values to all the Auto-calibration 0 RESET registers ( RESET bit is also cleared to 0 ) and then refresh all the these registers according to the coming display mode. 1~7 Not used
APPLICATION DIAGRAM for Intensity on R, G, B
(Color intensity information bundled on R, G, B pins by setting 3S bit of Miscellaneous register, ROW15,COLN5, to 1 ) 100 uH ( option )
VCC
0.1gF 4700P
100gF 3 VDD 19 10 gF 150 5 VCO R 25 150 G 24 150 150 150 150 0.1 gF
Note: dotted-line box for Intensity on R, G, B application only
VCC 240 100 R
VSSA
1K 0.22gF
VSS
26
240
100
G
WT6802
6 VDDA
240 150
100
B
HBLANK R, G, B from Pre-AMP
7 1, 28, 27
HBLANK B RI, GI, BI 23
150 150
470 [ or buffer (option)
100
9
BLANK SDA INTN
22 21 20
BLANK INTENSITY (This pin should keep floating when the color intensity information is bundled on R, G, B pins) VBLANK
I 2C BUS
100
10
SCL
PWM VBLANK 11-18
8 channels of DC out
3.3gF
10k
ANALOG GROUND DIGITAL GROUND
*s|Ei3/4Cu*~eIu*~FEo 2421/4O
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aqlN/|--1/2q WT6802 Weltrend Semiconductor, Inc. Rev.1.0 Data Sheet
ABSOLUTE MAXIMUM RATINGS (Voltage Referenced to VSS)
Symbol VDD V in Id Ta Vstg Supply Voltage Input Voltage Current Drain per Pin Excluding VDD and VSS Operating Temperature Range Storage Temperature Range Characteristic Value -0.3 to + 7.0 VSS - 0.3 to VDD + 0.3 25 0 to 70 -40 to +125 Unit V V mA J J
AC ELECTRICAL CHARACTERISTICS (VDD , VDDA = 5.0 V, VSS , VSSA = 0 V, TA = 25C , Voltage Referenced to VSS) Symbol tr tf tr tf FHS Characteristic Output Signal (R, G, B, BLANK and INTN), Cload = 30 pF Rise Time, Fall Time Output Signal (PWM0 - PWM7), Cload = 30 pF Rise Time, Fall Time HS Input Frequency
90% 10% tf
Switching Characteristics
Min 15K
Typ
90%
Max 6 6 20 20 130K
Unit ns ns ns ns Hz
10% tr
DC CHARACTERISTICS
Symbol V OH
(VDD , VDDA = 5.0 VO10%, VSS , VSSA = 0 V, TA = 25J, Voltage Referenced to V SS ) Characteristic Min V DD -0.8 Typ Max Unit V
High Level Output Voltage Iout = -5mA Low Level Output Voltage Iout = 5mA Digital Input Voltage (Not Including SDA and SCL) Logic Low Logic High Input Voltage of Pin SDA and SCL Logic Low Logic High High-Z Leakage Current (R, G, B and BLANK) Input Current (Not Including VCO, R, G, B, BLANK and INTN) 24
th
V OL
V SS +0.4
V
V IL V IH V IL V IH III III IDD
0.7 V DD 0.7 V DD -10 -10

0.3 V DD 0.3 V DD +10 +10 +26
V V V V gA gA mA
Supply Current (NO Load on Any Output) at VDD *s|Ei3/4Cu*~eIu*~FEo = 5.0V 2421/4O
2F, No. 24, Industry E. 9 RD., Science-Based Industrial Park, Hsin-Chu, Taiwan TEL:886-3-5780241 FAX:886-3-5794278.5770419 Email:support@weltrend.com.tw

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