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| INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: * The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications * The IC06 74HC/HCT/HCU/HCMOS Logic Package Information * The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC58 Dual AND-OR gate Product specification File under Integrated Circuits, IC06 December 1990 Philips Semiconductors Product specification Dual AND-OR gate FEATURES * Output capability: standard * ICC category: SSI GENERAL DESCRIPTION 74HC58 The 74HC58 is a high-speed Si-gate CMOS device and is pin compatible with low power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard no. 7A. The "58" provides two sections of AND-OR gates. One section contains a 2-wide, 3-input (1A to 1F) AND-OR gate and the second section contains a 2-wide, 2-input (2A to 2D) AND-OR gate. QUICK REFERENCE DATA GND = 0 V; Tamb = 15 C; tr = tf = 6 ns SYMBOL tPHL/ tPLH PARAMETER propagation delay 1n to 1Y 2n to 2Y CI CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in W): PD = CPD x VCC2 x fi + (CL x VCC2 x fo) where: fi = input frequency in MHz fo = output frequency in MHz CL = output load capacitance in pF VCC = supply voltage in V (CL x VCC2 x fo) = sum of outputs 2. For HC the condition is VI = GND to VCC ORDERING INFORMATION See "74HC/HCT/HCU/HCMOS Logic Package Information". input capacitance power dissipation capacitance per gate notes 1 and 2 CONDITIONS CL = 15 pF; VCC = 5 V 11 9 3.5 18 ns ns pF pF TYPICAL HC UNIT December 1990 2 Philips Semiconductors Product specification Dual AND-OR gate PIN DESCRIPTION PIN NO. 1, 12, 13, 9, 10, 11 2, 3, 4, 5 8, 6 7 14 SYMBOL 1A to 1F 2A to 2D 1Y, 2Y GND VCC NAME AND FUNCTION data inputs data inputs data outputs ground (0 V) positive supply voltage 74HC58 Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol. December 1990 3 Philips Semiconductors Product specification Dual AND-OR gate 74HC58 Fig.4 Functional diagram. Fig.5 Logic diagram. FUNCTION TABLE (1) INPUTS 1A L L L X X X X X X X H 1B X X X L L L X X X X H 1C X X X X X X L L L X H 1D L X X L X X L X X H X 1E X L X X L X X L X H X 1F X X L X X L X X L H X OUTPUT 1Y L L L L L L L L L H H L L X X X H Note 1. H = HIGH voltage level L = LOW voltage level X = don't care 2A X X L L X H INPUTS 2B L X L X H X 2C X L X L H X 2D OUTPUT 2Y L L L L H H December 1990 4 Philips Semiconductors Product specification Dual AND-OR gate DC CHARACTERISTICS FOR 74HC For the DC characteristics see "74HC/HCT/HCU/HCMOS Logic Family Specifications". Output capability: standard ICC category: SSI AC CHARACTERISTICS FOR 74HC GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (C) 74HC SYMBOL PARAMETER +25 min. typ. tPHL/ tPLH propagation delay 1A,1B,1C,1D,1E, 1F to 1Y propagation delay 2A,2B,2C,2D to 2Y output transition time 36 13 10 30 11 9 19 7 6 -40 to +85 -40 to +125 UNIT 74HC58 TEST CONDITIONS VCC WAVEFORMS (V) 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 Fig.6 max. min. max. min. max. 115 23 20 100 20 17 75 15 13 145 29 25 125 25 21 95 19 16 175 35 30 150 30 26 110 22 19 ns tPHL/ tPLH ns Fig.6 tTHL/ tTLH ns Fig.6 AC WAVEFORMS handbook, full pagewidth nA, nB, nC, nD, 1E, 1F INPUT VM (1) t PHL t PLH nY OUTPUT MBA336 (1) HC : VM = 50%; VI = GND to VCC. V M (1) t THL t TLH Fig.6 Waveforms showing the input (nA, nB, nC, nD, 1E, 1F) to output (nY) propagation delays and the output transition times. PACKAGE OUTLINES See "74HC/HCT/HCU/HCMOS Logic Package Outlines". December 1990 5 |
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