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CXG1131ER
High Power 3 x 5 Antenna Switch MMIC with Integrated Control Logic
Description The CXG1131ER is a high power antenna switch MMIC for PDC full packet 1.5GHz handsets. This IC is suited to connect Tx/Rx/duplexer to one of 4 antennas. The CXG1131ER has on-chip logic circuit for operation with 4 CMOS inputs. The Sony's GaAs J-FET process is used for low insertion loss and low voltage operation. Features * Low insertion loss: 1.0dB @1.5GHz * High linearity: Harmonic < - 65dBc * CMOS compatible input control * Small package: 24-pin VQFN (4.0mm x 4.0mm) Applications 3 x 5 antenna switch for digital cellular such as PDC handsets Structure GaAs J-FET MMIC Absolute Maximum Ratings (Ta = 25C) * Bias voltage VDD * Control voltage * Operating temperature * Storage temperature Vctl Topr Tstg 24 pin VQFN (Plastic)
7 5 -35 to +85 -65 to +150
V V C C
GaAs MMICs are ESD sensitive devices. Special handling precautions are required.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
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E02110-PS
CXG1131ER
Block Diagram
F13 Tx F15 Dup_In F16 GND3 Dup_Out F4 F17 F5 GND4 GND1 F10 F3 Ant F14 F9 F1 Ext
F2
F6
F7 Rx F11 D_Ant
F8
GND2 D_Ext F12
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CXG1131ER
Pin Configuration/Recommended Circuit
GND1 Ant
7 6 CRF (100pF) 14 5 GND Ext
CRF (100pF)
Tx
12 Dup_In CRF (100pF) GND3 Z3 13
11
10
9
8
GND
15
CRF (100pF)
GND
GND
GND
Z1
4
D_Ext
GND
16
3
GND
GND4
Z4
17
2
Z2
GND2
Dup_Out CRF (100pF)
18 19 20 21 22 23 24
1 CRF (100pF)
D_Ant
CRF (100pF)
Cbypass (100pF)
Cbypass (100pF)
Cbypass (100pF)
Cbypass (100pF) CTLD VDD
When using this IC, the following external components should be used: CRF: This capacitor is used for RF de-coupling and must be used for all applications. 100pF is recommended. Cbypass: This capacitor is used for DC line filtering. 100pF is recommended. Z1 to Z4: It is recommended that these pins be directly grounded.
Rx
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CTLC
CTLA
CTLB
Cbypass (100pF)
CXG1131ER
Truth Table A: Rx/Tx B: Main/diversity C: External/antenna D: TDMA/28.8k
State 1 2 3 4 5 6 7 On Pass Tx - Ext Tx - Ant Rx - Ext Rx - Ant Rx - D_Ext Rx - D_Ant Dup_Out - Ant Rx - Ant 8 Dup_Out - Ant Rx - D_Ant 9 Dup_Out - Ext Rx - Ext 10 Dup_Out - Ext Rx - D_Ext -- H L H L L H -- L L H L L H -- H H H L L L A H H L L L L -- B -- -- L L H H L C L H L H L H H D L L L L L L H F1 F2 F3 F4 F5 F6 H L L L L L L L H L L L L L L L L L L L L L L L L L L H L L H L L L L L L L H L L H F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 L L L L L H L L L L L H L L L H L H H H H H L H L H H L H H H H H L H H H H H L H H H H L L L L L L L H H H H H L L L L L L H H H H H H H L H H H H H H L
H
L
L
H
L
H
L
L
H
L
H
H
L
L
L
H
L
L
L
L
H
H
H
L
H
H
L
L
L
L
L
L
H
L
H
H
L
L
H
H
L
L
DC Bias Condition Item VDD Vctl (H) Vctl (L) Min. 2.7 2.0 0 Typ. 3.0 3.0 Max. 3.3 3.6 0.4
(Ta = 25C) Unit V V V
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CXG1131ER
Electrical Characteristics Item Symbol Port Tx - Ext Tx - Ant Tx - Dup_In Rx - Ext Rx - Ant Rx - D_Ext Rx - D_Ant Insertion loss IL Dup_Out - Ext Rx - Ext Dup_Out - Ant Rx - Ant Dup_Out - Ext Rx - D_Ext Dup_Out - Ant Rx - D_Ant Tx - Ext Tx - Ant Tx - Dup_In Rx - Ext Rx - Ant Rx - D_Ext Rx - D_Ant Dup_Out - Ext Isolation ISO. Rx - Ext Dup_Out - Ant Rx - Ant Dup_Out - Ext Rx - D_Ext Dup_Out - Ant Rx - D_Ant Tx - Rx (Full packet) Tx - Rx (TDMA) 1 1 1 2 2 2 2 1, 4 2, 5 1, 4 2, 5 1, 4 2, 5 1, 4 2, 5 1 1 1 2 2 2 2 1, 4 2, 5 1, 4 2, 5 1, 4 2, 5 1, 4 2, 5 1 1 Condition
(Ta = 25C) Min. Typ. Max. Unit -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 30 30 26 35 35 30 27 30 35 27 35 30 30 30 27 47 14 1.0 1.0 1.3 1.3 dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB
0.35 0.65 0.85 1.15 0.85 1.15 0.7 0.7 1.2 1.2 1.3 1.3 1.0 1.0 1.5 1.5 1.6 1.6
0.75 1.05 0.75 1.05 0.75 1.05 0.75 1.05 33 33 29 38 38 33 30 33 38 30 38 33 33 33 30 50 17 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
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CXG1131ER
Item
Symbol
Port Tx - Ext Tx - Ant 3 3 3
Condition
Min. Typ. Max. Unit -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 33 33 33 33 33 -- -- -- -75 -75 -80 -75 -75 -67 -67 -75 -67 -67 -65 -65 -65 -65 -65 -73 -73 -73 -73 -73 34 34 34 34 34 2 350 35 -60 -60 -60 -60 -60 -60 -60 -60 -60 -60 -57 -57 -57 -57 -57 -65 -65 -65 -65 -65 -- -- -- -- -- -- 500 75 dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBm dBm dBm dBm dBm s A A
2fo
Tx - Dup_In Dup_Out - Ext Dup_Out - Ant Tx - Ext Tx - Ant
3, 4 3, 4 3 3 3 3, 4 3, 4 3 3 3 3, 4 3, 4 3 3 3 3, 4 3, 4 VDD = 3V VDD = 3V VDD = 3V VDD = 3V VDD = 3V VDD = 3V Vctl (H) = 3V
Harmonics
3fo
Tx - Dup_In Dup_Out - Ext Dup_Out - Ant Tx - Ext Tx - Ant
50kHz
Tx - Dup_In Dup_Out - Ext Dup_Out - Ant Tx - Ext Tx - Ant
ACP
100kHz
Tx - Dup_In Dup_Out - Ext Dup_Out - Ant Tx - Ext Tx - Ant
P1dB
P1dB
Tx - Dup_In Dup_Out - Ext Dup_Out - Ant
Switching speed Bias current Control current
TSW IDD Ictl
-- -- --
1 Pin = 29.5dBm, 0/3V control, VDD = 2.8V to 3.6V, 1,429MHz to 1,453MHz 2 Pin = 10dBm, 0/3V control, VDD = 2.8V to 3.6V, 1,477MHz to 1,501MHz 3 /4-shifted DQPSK, Pin = 29.5dBm, 0/3V control, VDD = 3.0V, 1,429MHz to 1,453MHz, ACP (50kHz) < - 70dBc, ACP (100kHz) < - 75dBc, 2nd harmonics < - 75dBc, 3rd harmonics < - 75dBc 4 Rx is open. 5 Dup_Out is open.
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CXG1131ER
Package Outline
Unit: mm
24PIN VQFN(PLASTIC)
4.0 3.6 C 13 0.7 0.9 0.1 0.05 S 0.6 0.1
18 19
A
12
B
78 4. 9) .3 (0
PIN 1 INDEX 24 7 1 6 0.4 x4 0.2 S A-B C x4 0.2 S A-B C 0.05 M S A-B C
0. 6
45
S
C
0.03 0.03 (1) (Stand Off)
Solder Plating 0.13 0.025 + 0.09 0.14 - 0.03 TERMINAL SECTION
PACKAGE STRUCTURE
PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE VQFN-24P-03 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER PLATING COPPER ALLOY 0.04g
LEAD PLATING SPECIFICATIONS ITEM LEAD MATERIAL SOLDER COMPOSITION PLATING THICKNESS SPEC. COPPER ALLOY Sn-Bi Bi:1-4wt% 5-18m
0.2 0.01
0.225 0.03
(0
.1
1.0
5)
-7-
Sony Corporation

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