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ML2002 Preliminary
ML2002 Series Static/Half Duty LCD COG Driver with Real Time Clock Application
General Purpose Clock High quality instrument Telephone, mobile phone Automotive Handheld Device like PDA, MP3, or PMP
Features
AGold Bump Chip Logic & LCD power supply: 2.0V to 6.0V Static or 1/2 Duty driving Number of segments: (Static) 48, (1/2 Duty) 96 Cascading structure to increase the number of driving segments. Build in Real time clock Simple 2 pin serial interface for command and data transfer. Build-in LCD voltage driver, crystal oscillator, internal RC oscillator and display control circuit. Offer best contrast and widest viewing angle of TN LCD technology. No temperature compensation needed for Topr = -40oC to 80oC.
General Description
ML2002 (COG) LCD driver can be cascaded to increase the number of segments drive, with Static driving it can form a single piece of 48 (1 ICs) or 96 (2 ICs cascaded) segments driver. With 1/2 Duty, the number of segment drive would be doubled. It targets at custom TN LCD COG Module product which requires the best quality of TN LCD technology and small to medium number of segment display. ML2002 series driver offers the best contrast, the widest viewing angle, the widest range of operating voltage and temperature when compared to the high duty cycle driver. EMI and Noise protection circuit has been added which tailor made for COG application. A real time clock has been built-in to target at the large LCD clock, watch or any handheld device.
Ordering Information
Part Number ML2002-1U ML2002-2U ML2002-3U ML2002-4U Description One ML2002 LCD driver Two ML2002 LCD driver Three ML2002 LCD driver Four ML2002 LCD driver Package Form Gold Bump Die Gold Bump Die Gold Bump Die Gold Bump Die
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Block Diagram
Absolute Maximum Ratings
Parameter Supply voltage Supply Current Input Voltage Output Voltage DC input Current DC output Current Storage temperature Total power dissipation Symbol Condition VDD IDD VIN VOUT IIN IOUT Tstg Ptot VDD = 3V, no Load MIN -0.5 -50 GND-0.3 GND-0.3 -10 -10 -65 MAX +6.0 +50 VDD +0.3 VDD +0.3 +10 +10 +150 400 Unit V mA V V mA mA
o
C
mW
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DC Characteristic
VDD = 3.0V; Tamb = 25oC ; unless otherwise specified Parameter Symbol Condition Supplies Supply voltage VDD Supply Current IDD Disable Oscillator Supply Current IDD Enable Oscillator Logic LOW-level input voltage VIL HIGH-level input voltage VIH LOW-level output current IOL VOL = 1.0V HIGH-level output IOH VOH = 2.0V current LCD outputs Output resistance at pads RSEG S1 to S40 Output resistance at pads RCOM COM1A and COM1B MIN 2.5 GND 0.7*VDD 1 -1 TYP 0.1 25 MAX 6.0 0.5 60 0.3*VDD VDD Unit V uA uA V V mA mA
-
85 45
150 100
ohm ohm
AC Characteristic
VDD =3.0V; Tamb = 25oC; unless otherwise specified Parameter Symbol Conditions Oscillator frequency at foout pad OOUT FIN, LOAD, DIN, DCLK tH High time FIN, LOAD, DIN, DCLK tL Low time FIN, LOAD, DIN, DCLK tr Rise time FIN, LOAD, DIN, DCLK tf Fall time DCLK Frequency FDCLK MIN 21 0.4 0.4 1 TYP 32 MAX 48 10 10 250 Unit kHz us us us us kHz
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Timing Diagram for slave mode display
Functional Description
The display data should be input in reverse order from SEG48, SEG41... SEG2, SEG1 for proper display of data. i) Internal Power on reset At power on the ML2002 will reset the internal register and counter as follows. 1. The display Data RAM is cleared. 2. The clock register will be cleared, the alarm will be disabled by setting the AE to logic 1, and the RTC stops running by setting STOP to 1. 3. The command/data decoder will be reset to initial state.
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ML2002 Preliminary ii) Oscillator The LCD driving signal of ML2002 is clocked either by the built-in oscillator, crystal oscillator or from an external clock. a) Internal clock When the internal oscillator is used, BIOEN should be connected to GND and the OOUT should be connected to FIN. The internal oscillator will oscillate at 32 kHz and the frequency is independent in the range of 2.5V < VDD < 6.0V . Then connect OOUT to FIN. b) Crystal clock When using the crystal oscillator, BCOEN is connected to GND, then connect the crystal to OSC+, and OSC-. Then connect OSC- to FIN. The OSC+ and OSC- should connect as:
c) External clock When using an external clock, BCOEN & BIOEN is connected to VDD then connects the external clock to FIN. iii) Timing ML2002 have several frequencies of clock signal for the users to choose for the LCD display clock (ie. LCLK) and the blink clock (ie.BCLK). They include the following clock signals: Frequency of Clock Signal at FIN = 32 kHz 256/128 Hz 128/64 Hz 4 Hz 2 Hz 1 Hz Actual Divider of FIN 1/256(1/2 Duty) or 1/128(Static) 1/128(1/2 Duty) or 1/64(Static) 1/8192 1/16384 1/32768 Target Input Pin LCLK BCLK
iv) Segment outputs ML2002 has 48 segment outputs which should be connected directly to the LCD. If less than 48 segments a re required, the unused segments should be left open circuit. v) Common outputs ML2002 consists of 2 common signals (ie. COM1A & COM1B). The common outputs should be left open-circuit if the outputs are unused. Users can disable the COM1A and COM1B by connecting the CEN1A and CEN1B to VDD, respectively. The common outputs will change to GND after disabling it. vi) Blink ML2002 has a blink function that users shall connect BEN to GND and input the blink clock (ie. BCLK) either by connecting ML2002 output clock signal from Frequency Divider or an external clock signal. Users shall disable blink function by connecting BEN to VDD.
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Pad Configuration
Chip Size : Part Number Description Chip Size
ML2002-1U ML2002-2U ML2002-3U ML2002-4U
One ML2002 LCD driver Two ML2002 LCD driver Three ML2002 LCD driver Four ML2002 LCD driver
3660 x 660 7320 x 660 10980 x 660 14640 x 660
Chip Thickness : 700 um + 25 um Gold Bump Pad Size : 32 um x 72 um Gold Bump Height : 18 um + 2 um Left alignment mark: (141.05, 238.5) Right alignment mark: (3325.5, 121.6)
Note : The die faces up in the diagram
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ML2002 Preliminary Pad Orientation:
Note: Pad 1, 49 and 50 are DUM Pads which must be open.
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Application Circuit
Slave Mode for Original ML1001 Users
1. Static Slave Mode with External Clock for Low Power Consumption
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ML2002 Preliminary 2. Static Slave Mode with Internal Clock for Fewest External Pins
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ML2002 Preliminary 3. Static Slave Mode with Internal Clock for Large LCD Panel
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ML2002 Preliminary 4. Half-Duty Slave Mode with External Clock and 1/2PVDD for Low Power Consumption
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ML2002 Preliminary 5. Half-Duty Slave Mode with Internal Clock and 1/2PVDD for Fewest External Pins
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ML2002 Preliminary 6. Half-Duty Slave Mode with Internal Clock and 1/2PVDD for Large LCD Panel
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Master Mode for using ML2002 Real Time Clock
1. Static Master Mode with External Crystal
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ML2002 Cascode Structure Connection
1. ML2002 2U Static-Static Master-Slave Mode
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ML2002 Preliminary 2. ML2002 2U 1/2Duty-1/2Duty Slave-Slave Mode
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ML2002 Preliminary 3. ML2002 2U 1/2Duty-Static Slave-Slave Mode
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ML2002 Preliminary 4. ML2002 3U 1/2Duty-Static-1/2Duty Slave-Slave Mode
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Pin Description
SYMBOL
BRES
PAD
I I I I/O I I/O
DESCRIPTION
External reset input (active LOW) Logic Ground Alarm interrupt output Logic Supply voltage "1" - Master, "0" - Slave Data line input, for 2 pin interface, it need to connect to a pull high resistor and would output ACK. Data clock input If used as Master, it would output ACK and can be connected to DIN when used as 2 pin interface. If used as slave, it is an input pin which LOAD the display onto the LCD screen during rising edge. Send out LOAD signal to the cascade slave ML2002 for displaying data onto LCD screen. Enable Chip for receive data/command in the DIN pin Send out chip enable signal to the following cascade slave IC Data output from the display data RAM Input clock, count number of rising edge clock Output High on the 16th clock from CNT 32768Hz Oscillator input 4, 2, 1Hz clock output 125Hz clock output for static/ 250 clock output for 1/2 duty 62Hz clock output for static/125 clock output for 1/2 duty LCD Clock signal frequency Segment output Common output Power VDD supply 1/2 PVDD LCD driving voltage "1" - Halfduty, "0" - Static Common Enable. "0" - Enable, "1" - Disable Test mode. "0" - Normal mode, "1" - Testing Mode 32K internal clock output Crystal oscillator enable. "0" - Enable, "1" - Disable 32K internal clock enable. "0" - Enable, "1" - Disable 1/2 PVDD enable. "0" - Enable, "1" - Disable Blink control circuit enable "0" - Enable, "1" - Disable Blink clock input Crystal oscillator input To synchronize COMMON signal to the following cascade IC 2/4 pin interface, "1" - 2pin , "0" - 4pin SYNC enable. If in Master mode, SYNC will output signal to the next cascade IC, but in slave mode, SYEN is "1" - SYNC output, "0" - SYNC will be high impredence. When select 4pin interface, it would output timer data. Dummy Pad, Left it open only
LGND INT LVDD MS DIN DCLK LAI
LAO
O I O O I O I O O O I O O I I I I O I I I I I I I/O I I
CEI
CEO
DOUT CNT Q15 FIN 4,2,1Hz 250/125 Hz 125/62 Hz LCLK SEG1 .. SEG48 COM1A / B PVDD 1/2 PVDD 1/2 Duty CEN1A , CEN1B T0 OOUT COEN
IOEN HPVDDEN BEN
BCLK OSC+ / SYNC TFI SYEN
TOUT DUM1,2,3
O -
Note : 1. In cascade format of ML2002(ie. ML2002-2U and -3U), one pin is the input of current ML2002 and the other is for the connection with the corresponding input pin of next ML2002. 2. Condition : FIN = 32 KHz Clock.
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MLS Interface
MiniLogic Device corporation's serial interface designed for LCD cascading structure. The First IC will be treated as master IC and receive command from MCU. Then it processed to send out to the preceding slave IC in the cascading structure. In 2 pin mode, the master IC will send out ACK though the DIN pin to acknowledge the command/data sent by the MCU, if in 4 pin mode; it would be the LAI pin. Transfer is initiated by START and ends by STOP. If there is any error in the transfer, like couldn't receive ACK from LCD driver, then MCU could send START and STOP repeatedly, to restart the communication or by disabling the IC by connect BCEI to VDD and then enable it again. The interface is initiated by a START and ends with a STOP.
Clock architecture
The built-in clock has a control status register on address (00H) to control the alarm and start/stop of the clock. Then memory address from 01H to 07H are as counters storing the seconds up to years value. Alarm registers address from 08H to 0BH are defining the condition of the alarm.
Clock Status register Address (00H)
Bit 7 to 3 2 Symbol 0 AF Value Description Default value is 0 Alarm flag inactive Alarm flag active Alarm flag clear Alarm flag unchanged Alarm interrupt disabled Alarm interrupt enable Real Time Clock runs Real Time Clock stops
1 0
AIE STOP
0 (read) 1 (read) 0 (write) 1 (write) 0 1 0 1
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Seconds register Address (01H)
Bit 6 to 0 Symbol seconds Value 00 to 59 Description Seconds value coded in BCD format. Example 101 1001 = 59 seconds
Minutes register Address (02H)
Bit 6 to 0 Symbol minutes Value 00 to 59 Description Minutes value coded in BCD format.
Hours register Address (03H)
Bit 5 to 0 Symbol hours Value 00 to 23 Description Hours value coded in BCD format.
Days register Address (04H)
Bit Symbol Value Description 5 to 0 days 01 to 31 Days value coded in BCD format. th The ML2002 will add a 29 day to February if the year is a lunar year.
Weekdays register Address (05H)
Bit 2 to 0 Symbol weekdays Value 00 to 06 Description Weekdays value
Weekdays assignment
Day Sunday Monday Tuesday Wednesday Thursday Friday Saturday Bit 2 0 0 0 0 1 1 1 Bit 1 0 0 1 1 0 0 1 Bit 0 0 1 0 1 0 1 0
Months/Century register Address (06H)
Bit 7 Symbol Century Value
4 to 0
Months
0 1 01 to 12
Description This bit toggled when the years register overflows from 99 to 00 Indicates the century is 20xx Indicates the century is 21xx Month value coded in BCD format
Years register Address (07H)
Bit 7 to 0 Symbol Years Value 00 to 99 Description Years value coded in BCD format
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Alarm function modes
By clearing the MSB of one or more of the alarm registers (bit AE = enable), the corresponding alarm conditions will be active. In this way an alarm can be generated from once per minute up to once per week. The alarm condition sets the Alarm Flag (AF). The asserted AF can be used to generate an interrupt (INT). When one or more of these registers are loaded with a valid minute, hour, day, or weekday and its corresponding bit Alarm Enable (AE) is logic 0, then that information will be compared with the current minute, hour, day and weekday. When all enabled comparisons first match, the Alarm Flag (AF) is set. Alarm Flag will be cleared when the comparison fails to match or the user disable the alarm register that AE bit at logic 1.
Minutes alarm register Address (08H)
Bit 7 Symbol AE Value 0 1 00 to 59 Description Minute alarm is enabled Minute alarm is disabled Minutes value coded in BCD format.
6 to 0
Alarm minutes
Hour alarm register Address (09H)
Bit 7 Symbol AE Value 0 1 00 to 23 Description Hour alarm is enabled Hour alarm is disabled Hours value coded in BCD format.
6 to 0
Alarm hours
Day alarm register Address (0AH)
Bit 7 Symbol AE Value 0 1 01 to 31 Description Day alarm is enabled Day alarm is disabled Days value coded in BCD format.
5to 0
Alarm days
Weekday alarm register Address (0BH)
Bit 7 Symbol AE Value 0 1 00 to 06 Description Weekday alarm is enabled Weekday alarm is disabled Hours value coded in BCD format.
2 to 0
Alarm weekdays
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Command table
Command NOP Display LOAD Send Display data OPCODE 101000 101001 101010 Data follow 48 bit output from MCU for static 96 bit output from MCU for 1/2 duty MCU input word address then ML2002 output data MCU input word address then ML2002 input data 1 bit, "1 : ON, 0 : OFF"
Clock Read Clock Write Prevent COM Output Toggle during Send display data
101011 101100 101101
Protocol
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Command Timing Diagram
2 pin Master Mode
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ML2002 Preliminary 4 pin Master Mode
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Remarks
There are 48 segments in static mode. There are 96 segments in half duty mode.
DISCLAIMER: The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use.
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