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| bq2058 Lithium Ion Pack Supervisor for 3- and 4-Cell Packs Features (R) Protects and individually monitors three or four Li-Ion series cells for overvoltage, undervoltage (R) Monitors pack for overcurrent (R) Designed for battery pack integration (R) Minimal external components (R) Drives external FET switches (R) Selectable overvoltage (VOV ) thresholds General Description The bq2058 Lithium Ion Pack Supervisor is designed to control the charge and discharge cell voltages for three or four lithium ion (Li-Ion) series cells, accommodating battery packs containing series/parallel configurations. The low operating current does not overdischarge the cells during periods of storage and does not significantly increase the system discharge load. The bq2058 can be part of a low-cost Li-Ion charge control system within the battery pack. The bq2058 controls two external FETs to limit the charge and discharge potentials. The bq2058 allows charging when each individual cell voltage is below VOV (overvoltage limit). If the voltage on any cell exceeds VOV for a user-configurable CHG pin is delay period (tOVD), the driven high, shutting off charge to the battery pack. This safety feature pre- vents overcharge of any cell within the battery pack. After an overvoltage condition occurs, each cell must fall below VCE (charge enable voltage) for the bq2058 to re-enable charging. The bq2058 protects batteries from overdischarge. If the voltage on any cell falls below VUV (undervoltage limit) for a user-configurable delay period (tUVD), the DSG output is driven high, shutting off the battery discharge. This safety feature prevents overdischarge of any cell within the battery pack. The bq2058 also stops discharge on detection of an overcurrent condition, such as a short circuit. If an overcurrent condition occurs for a userconfigurable delay period (tOCD), the DSG output is driven high, disconnecting the load from the pack. DSG remains high until removal of the short circuit or overcurrent condition. - Mask-programmable by Texas Instruments Standard version-4.25V (R) Supply current: 25Atypical (R) Sleep current: 0.7Atypical (R) 16-pin 150-mil narrow SOIC Pin Connections Pin Names CHG Charge control output Pack disable input Low potential input Current sense low-side input Battery 4 negative input Battery 3 negative input Battery 2 negative input Battery 1 negative input BAT1P DSG NSEL UVD OVD OCD VCC CSH Discharge control output 3- or 4-cell selection Undervoltage delay input Overvoltage delay input Overcurrent delay input High potential input Current sense high-side input Battery 1 positive input CHG CTL VSS CSL BAT4N BAT3N BAT2N BAT1N 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 DSG NSEL UVD OVD OCD VCC CSH BAT1P CTL VSS CSL BAT4N BAT3N BAT2N 16-Pin Narrow SOIC PN205801.eps BAT1N SLUS070A--JULY 2000 1 bq2058 Pin Descriptions CHG Charge control output This push-pull output controls the charge path to the battery pack. Charging is allowed when low. CTL Pack disable input When high, this input allows an external source to disable the pack by making both DSG and CHG inactive. For normal operation, the CTL pin is low. VSS CSL Low potential input Overcurrent sense low-side input This input is connected between the low-side discharge FET (or sense resistor) and BAT4N to enable overcurrent sensing in the battery pack's ground path. BAT4N Battery 4 negative input This input is connected to the negative terminal of the cell designated BAT4 in Figure 2. BAT3N Battery 3 negative input This input is connected to the negative terminal of the cell designated BAT3 in Figure 2. BAT2N Battery 2 negative input This input is connected to the negative terminal of the cell designated BAT2 in Figure 2. BAT1N Battery 1 negative input This input is connected to the negative terminal of the cell designated BAT1 in Figure 2. BAT1P VCC CSH OVD UVD NSEL DSG This input is connected to BAT1P in a threecell configuration. Discharge control output This push-pull output controls the discharge path to the battery pack. Discharge is allowed when low. Number of cells input This input selects the number of series cells in the pack. NSEL should connect to VCC for four cells and to VSS for three cells. Undervoltage delay input This input uses an external capacitor to VCC to set the undervoltage delay timing. Overvoltage delay input This input uses an external capacitor to VCC to set the overvoltage delay timing. OCD Overcurrent delay input This input uses an external capacitor to VCC to set the overcurrent delay timing. High potential input Overcurrent sense high-side input This input is connected between t h e high-side discharge FET (or sense resistor) and BAT1P to enable overcurrent sense in the battery pack's positive supply path. Battery 1 positive input This input is connected to the positive terminal of the cell designated BAT1 in Figure 2. Table 1. Pin Configuration for 3- and 4-Series Cells Number of Cells Configuration Pins BAT1N tied to BAT1P NSEL = VSS Battery Pins BAT1N - Positive terminal of first cell 3 cells BAT2N - Negative terminal of first cell BAT3N - Negative terminal of second cell BAT4N - Negative terminal of third cell BAT1P - Positive terminal of first cell BAT1N - Negative terminal of first cell 4 cells NSEL = VCC BAT2N - Negative terminal of second cell BAT3N - Negative terminal of third cell BAT4N - Negative terminal of fourth cell SLUS070A--JULY 2000 2 bq2058 Cell Inputs Sel4 Sel3 Sel2 Sel1 Pin 9 B1P Pin 8 B1N Number of Cells Select + Clock Pin 7 B2N Pin 6 B3N Pin 5 B4N Sleep Sleep Pin 15 NSEL NSEL Sel4 Sel3 Sel2 Sel1 Sel4 Sel3 Sel2 Sel1 Pin 3 VOV + DQ Chip Negative Supply Sel4 CK QB DQ Any_Above_VOV D CK Edge Out Non-Retrigger Oneshot Reset Overcharge QB Pin 1 CHG Reset Sel3 CK QB DQ Charge Control Output Pin 13 OVD Discharge Off Delay Capacitor Input All_Below_VCE Capacitor Sel2 CK QB DQ Sel1 CK QB Any_Below_VUV D CK Edge Out QB Reset Non-Retrigger Oneshot Reset UVD Pin 14 Sleep Pin 16 DSG Discharge Control Output DQ Sel4 CK QB DQ Sel3 CK QB DQ Capacitor Sel2 + VCE Sel1 CK QB DQ CK QB Charge Off Delay Capacitor Input Sense High-side Input Pin 10 Pin 9 Pin 4 Pin 5 CSH B1P CSL B4N 70mV + Sense Low-side Input 70mV + DQ Sel4 Edge Overcurrent Delay Capacitor Input Pin 12 OCD Pin 10 Pin 9 Pin 4 Pin 5 CSH B1P CSL B4N 160mV + Out D CK Q QB Reset Overcurrent CK QB Non-Retrigger Oneshot Reset Capacitor + VUV Sel3 Sel2 DQ CK QB DQ CK QB DQ 160mV + Sel1 CK QB Pin 2 CTL External Output Control Figure 1. Block Diagram SLUS070A--JULY 2000 3 bq2058 Functional Description Figure 1 is a block diagram outlining the major components of the bq2058. Figure 2 shows a 3- or 4-cell pack supervisor circuit. The following sections detail the various functional aspects of the bq2058. The bq2058 samples a cell every 40ms (typical). Every sample is a fully differential measurement of each cell. During this sample period, the bq2058 compares the measurements with these thresholds to determine if any of the these conditions exist: VOV, VUV, and VCE. Overcurrent and charge detect are conditions that are not sampled, but are continuously monitored. Thresholds The bq2058 monitors the lithium ion pack for the conditions listed below. Shown with these conditions are the respective thresholds used to determine if that condition exists: Overvoltage (VOV) Undervoltage (VUV) Overcurrent (VOCH, VOCL) Charge Enable (VCE) Charge Detect (VCD) Initialization On initial power-up, such as connecting the battery pack for the first time to the bq2058, the bq2058 enters the low-power sleep mode, disabling the DSG output. It is recommended that a top to bottom cell connection be made at pack assembly for proper initialization. A charging supply must be applied to the bq2058 circuit to enable the pack. See Low-Power Sleep Mode and Charge Detect sections. * See note 1. C8 0.1uF R2 6.98K C6 0.1uF Q4 ZVP3306F * See note 2. Q2 Si4435DY Q1 Si4435DY POS R10 0 Ohm 4-Cell R11 0 Ohm 3-Cell R6 100K R9 1M Q3 2N7002 U1 bq2058 R3 10K B1P R4 10K B1N R5 10K B2N R7 10K B3N R8 10K B4N C4 0.001uF C3 0.001uF C2 0.001uF C1 0.001uF C9 0.1uF 11 9 8 7 6 5 3 VCC BAT1P BAT1N BAT2N BAT3N BAT4N VSS NSEL OVD UVD OCD DSG CSH CHG CTL CSL 15 13 14 12 16 10 1 2 4 TP1 C10 0.1uF C5 0.1uF C7 0.01uF R1 2.7K D1 BAT54 NEG Notes: 1. For automatic short circuit recovery. 2. Remove R11 for 4-cell. Remove R10 and connect B1P to B1N for 3-cells. Figure 2. 3- or 4-Cell Li-Ion Battery Pack Supervisor SLUS070A--JULY 2000 4 bq2058 Low-Power Sleep Mode The bq2058 enters the low-power sleep mode in two different ways: 1. 2. On initial power-up After the detection of a n undervoltage condition-VUV bq2058 bq2058C bq2058R Table 2. Overvoltage Threshold Options Part No. VOV Limit 4.25V 4.325V 4.35V When the bq2058 enters the low-power sleep mode, DSG is driven high and the device consumes 0.7A (typical). The bq2058 only comes out of low-power sleep mode when a valid charge-detect condition exists. Charge Detect The bq2058 continuously monitors for a charge-detect condition. A valid charge-detect condition exists when either of the conditions is true: CSL < BAT4N - 70mV (VCD) CSH > BAT1P + 70mV (VCD) A valid charge-detect enables the DSG output, allowing charging of the lithium ion cells. This is accomplished by applying the charging supply to the pack. The overvoltage threshold limits are programmed by Texas Instruments. The bq2058 is the standard option that is more readily available for sampling and prototyping purposes. Please contact your Texas Instruments Sales Representative for other voltage threshold and tolerance options. Charge Enable A valid charge enable indicates that an overvoltage (overcharge) condition no longer exists and that the pack is ready to accept further charge. Once overvoltage protection is asserted, charging will not be enabled until all cell voltages fall below VCE. The VCE threshold is a function of VOV, and changes with different VOV limits. VCE = VOV - 150mV Undervoltage Undervoltage (or overdischarge) protection is asserted when any cell voltage drops below the VUV threshold a n d remains below t h e VUV threshold for a time exceeding a user-configurable delay (tUVD). The DSG output is driven high disabling the discharge of the pack. The bq2058 then enters the low-power sleep mode. Overcurrent The bq2058 detects an overcurrent (or short circuit) condition only in the discharge direction. Overcurrent protection is asserted when either of the conditions occurs and remains for a time exceeding a user-configurable delay (tOCD): CSL > BAT4N + VOCL CSH < BAT1P - VOCH where VOCL = 160mV (low-side detect) VOCH = 160mV (high-side detect) When either of these conditions occurs, DSG is driven high, disconnecting the load from the pack. DSG remains high until both of the voltage conditions are false, indicating removal of the short-circuit condition. The user can facilitate clearing these conditions by inserting the battery pack into a charger. The low-side overcurrent sense can be disabled by connecting CSL to BAT4N. This ensures that CSL is never greater than BAT4N. If low-side detection is disabled, high-side detection must be used with CSH. Overvoltage Overvoltage (or overcharge) protection is asserted when any cell voltage exceeds the VOV threshold and remains above the VOV threshold for a time exceeding a userconfigurable delay (tOVD). The CHG pin is driven high, disabling charge into the battery pack. Charging is disabled until a valid charge enable exists. See Charge Enable section. Important note: If any battery pin floats (BAT1P, BAT1N-4N), the bq2058 assumes an overvoltage has occurred. Because of different manufacturers specifications for overvoltage thresholds, the bq2058 can be available with different VOV options. Table 2 summarizes these different voltage thresholds. SLUS070A--JULY 2000 5 bq2058 The FETs in the charge/discharge path controlled by the CHG and DSG pins affect the overcurrent level. The on-resistance of these FETs need to be taken into account when determining overcurrent levels. Condition Normal operation Overvoltage Undervoltage Overcurrent Floating battery input CTL = high CHG pin Low High Low Low High High DSG pin Low Low High High Indeterminate High Pack Disable Input-CTL The CTL pin is used to electrically disconnect the battery from the pack terminals through an externally supplied signal. When CTL is taken high, CHG and DSG are driven high. Any load on the pack terminals will be interpreted as an overcurrent condition by the bq2058 with the overcurrent delay timer held in reset. When the CTL pin is driven low, the overcurrent delay timer is allowed to start. If the programmed delay (tOCD) is too short, the overcurrent recovery circuit, if implemented, will be unable to correct the overcurrent situation prior to the delay time-out. It is recommended that a delay time of greater than 10ms (COCD 0.01F) be used if the CTL pin function is used. Important note: If CTL floats, it is internally pulled high making both DSG and CHG inactive, thus disabling the pack. If CTL is not used, it should be tied to VSS. The polarity of CTL is mask programmable at Texas Instruments. Please contact your Texas Instruments Sales Representative for other polarity options. CHG and DSG States The CHG and DSG output truth table is shown below. The polarities of CHG and DSG are mask programmable at Texas Instruments. Push-pull vs. open-drain configuration is also mask-configurable at Texas Instruments. Please contact your Texas Instruments Sales Representative for availability of these variations. Protection Delay Timers The delay time between the detection of an overcurrent, overvoltage, or undervoltage condition and the deactivation of the CHG and/or DSG outputs is user-configurable by the selection of capacitor values between VCC and OCD, OVD, and UVD pins (respectively). See Table 3 below. The fault condition must persist through the entire delay period, or the bq2058 may not deactivate either FET control output. Figure 3 shows a step-by-step event cycle for the bq2058. Number of Cells The user must configure the bq2058 for three- or fourseries cell operation. For a t hree-cell pack, NSEL should be tied directly to VSS. For a four-cell pack, NSEL should be connected directly to VCC. Number of Series Cells 3-cell 4-cell NSEL Tied to VSS Tied to VCC Table 3. Protection Delay Timers Protection Feature Overcurrent Overvoltage Undervoltage Notes: Delay Period t OCD t OVD t UVD Capacitor from VCC to: OCD OVD UVD Typical Capacitor 0.010F 0.100F 0.100F Time 12ms 950ms 950ms Tolerance 40% 40% 40% 1. The delay time versus capacitance can be approximated by the following equations: For t OCD: t(s) 1.2 C(f), where C 0.001F For t OVD, t UVD: t(s) 9.5 C(f), where C 0.01F 2. Overvoltage and undervoltage conditions are sampled by the bq2058. The delay in Table 2 is in addition to the time required for the bq2058 to detect the violation, which may vary from 0 to 160ms depending on where in the sampling period the violation occurs. Overcurrent is continuously monitored and is subject to a delay of approximately 1.5ms. SLUS070A--JULY 2000 6 bq2058 0 1 2 VOV 3 45 VCE 6 7 8 9 10 11 12 Cell Voltage VUV CSH BAT1P + 70mV (VCD) BAT1P - 160mV (VOCH) DSG tOCD CHG tOVD CTL TD205801.eps tUVD Figure 3. Protector Event Diagram Event Definition 0: 1: 2: 3: 4: 5: 6: 7: 8: 9: 10: 11: 12: The bq2058 is in the low-power sleep mode because one or more of the cell voltages are below VUV. A charger is applied to the pack, causing the difference between CSH and BAT1P to become greater than 70mV. This awakens the bq2058, and the discharge pin DSG goes low. One or more cells charge to a voltage equal to VOV, initiating the overvoltage delay timer. The overvoltage delay time expires, causing CHG to be driven high. All cell voltages fall below VCE, causing CHG to be driven low. Stop charging; apply a load. An overcurrent condition is detected, initiating the overcurrent delay timer. The overcurrent delay time expires, causing DSG to be driven high. The overcurrent condition is no longer present; DSG is driven low. Pin CTL is driven high; both DSG and CHG are driven high. Pin CTL is driven low; both DSG and CHG resume their normal function. One or more cells fall below VUV, initiating the overdischarge delay timer. Once the overdischarge delay timer expires, if any of the cells is below VUV, the bq2058 drives DSG high and enters the low-power sleep mode. SLUS070A--JULY 2000 7 bq2058 Absolute Maximum Ratings Symbol VCC TOPR TSTG TSOLDER I IN Notes: Supply voltage Operating temperature Storage temperature Soldering temperature Maximum input current Parameter Value 18 -30 to +70 -55 to +125 260 100 Unit V C C C A For 10 seconds All pins except VCC, VSS Conditions Relative to VSS 1 Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation should be limited to the Recommended DC Operating Conditions detailed in this data sheet. Exposure to conditions beyond the operational limits for extended periods of time may affect device reliability. 2. Internal protection diodes are in place on every pin relative to VCC and VSS. See Figure 4. VCC Any pin VSS FG2058x .eps Figure 4. Internal Protection Diodes SLUS070A--JULY 2000 8 bq2058 DC Electrical Characteristics (TA = TOPR) Symbol VOH VOL VOP VIL VIH VIL VIH I CCA I CCS Parameter Output high voltage Output low voltage Operating voltage Input low voltage Input high voltage Input low voltage Input high voltage Active current Sleep current Minimum VCC - 0.5 4 VSS + 2.0 VCC - 0.5 Typical 25 0.7 Maximum VSS + 0.5 18.0 VSS + 0.5 VSS + 0.5 40 1.5 Unit V V V V V V A A Conditions/Notes I OH = 10A, CHG, DSG I OL = 10A, CHG, DSG VCC relative to VSS Pin CTL Pin CTL Pin NSEL Pin NSEL DC Thresholds (TA = TOPR) Symbol VOV VCE VUV VOCH VOCL VCD t OVD t UVD t OCD Notes: Parameter Overvoltage threshold (See Figure 5.) Charge enable threshold Undervoltage threshold Overcurrent detect high-side Overcurrent detect low-side Charge detect threshold Overvoltage delay threshold Undervoltage delay threshold Overcurrent delay threshold Value 4.25 Unit V Table 2 VOV - 150mV 2.25 160 160 70 950 950 12 V V mV mV mV ms ms ms 50mV 100mV 35mV 35mV -60mV, +80mV 40% 40% 40% COVD = 0.100F, TA = 30C See note 2. CUVD = 0.100F, TA = 30C See note 2. COCD = 0.01F, TA = 30C Tolerance 50mV Condition See note 1. Customer option 1. Standard device. Contact your Texas Instruments Sales Representative for different thresholds and tolerance options. 2. Does not include cell sampling delay, which may add up to 160ms of additional delay until the condition is detected. SLUS070A--JULY 2000 9 bq2058 Impedance Symbol RCELL Parameter Input impedance Minimum Typical 10 Maximum Unit M Notes Pins BAT1P, BAT1N-4N, CSH, CSL 4.280 4.270 VOV - Overvoltage - V 4.260 4.250 4.240 4.230 Measurement accuracy 2mV 4.220 4.210 -30 -20 -10 0 10 20 30 40 50 60 70 TA - Free-Air Temperature - C Gr2058.eps Figure 5. bq2058 4.25V Overvoltage Threshold vs. Free-Air Temperature SLUS070A--JULY 2000 10 bq2058 Data Sheet Revision History Change No. 1 1 1 1 1 1, 2 1 Page No. 1, 2, 5 1 3 4 4 5 7 Description PACK+, PACKPin description Block diagram Figure 2 Configuration description Overcurrent limits Figure 3 Nature of Change Pins renamed to CSH and CSL respectively Added CSH/CSL description Update Block diagram Update typical application circuit Correction to description Was: VOCH = 150mV 25mV VOCL = 85mV 25mV Is: VOCH = 160mV 25mV VOCL = 100mV 25mV Update Event diagram Was: VOCH = 150mV 25mV VOCL = 100mV 80mV VCD = 70mV -60, +50mV Is: VOCH = 160mV 25mV VOCL = 100mV 25mV VCD = 70mV -60, +80mV Was: Between VCC and CSH, Is: Between BAT1P and CSH Added bq2058R Was: VOCL = 100mV, Is: VOCL = 150mV Corrected schematic Was: t OCD = 10ms 30% t OVD = 800ms 30% t UVD = 800ms 40% Is: t OCD = 12ms 40% t OVD = 950ms 40% t UVD = 950ms 40% Was: VOCH = 160mV 25mV VOCL = 150mV 25mV Is: VOCH = 160mV 35mV VOCL = 160mV 35mV Added bq2058W Was: Minimum VOP = 0V Is: Minimum VOP = 4V , Added bq2058C and bq2058G Moved D1 to new location Removed bq2058D, bq2058F, bq2058G, bq2058J, bq2058K, bq2058M, and bq2058W 1, 2 9 DC threshold 3 3 3 4 1, 3, 5 4 3, 5 4 High-side overcurrent monitored Overvoltage threshold options Overcurrent limit Figure 2 4 6, 8 Protection Delay Times 4 10 Overcurrent limits 5 6 7 8 9 Notes: 5, 9 9 5, 9 4 5, 9 Overvoltage threshold Charge enable threshold Undervoltage threshold DC electrical characteristics Overvoltage threshold Reference circuit amended Overvoltage thresholds Change 1 = Feb. 1997 B changes from Jan. 1997 A. Change 2 = April 1997 C changes from Feb. 1997 B. Change 3 = June 1997 D changes from April 1997 C. Change 4 = July 1997 E changes from June 1997 D. Change 5 = Feb. 1998 F changes from July 1997 E. Change 6 = May 1998 G changes from Feb. 1998 F. Change 7 = June 1998 H changes from May 1998 G. Change 8 = Jan. 1999 I changes from June 1998 H. Change 9 = July 2000 SLUS070A changes from Jan. 1999 I. 1 SLUS070A--JULY 2000 11 bq2058 Ordering Information bq2058 Package Option: SN = 16-pin narrow SOIC Overvoltage Threshold Blank = 4.25V (Standard device) Contact your Texas Instruments Sales Representative for availability of other thresholds Device: bq2058 Lithium Ion Pack Supervisor Package Devices TA -30C to +70C VOV Threshold 4.25V 4.325 4.35V 16-pin Narrow SOIC (SN) bq2058SN bq2058CSN bq2058RSN Notes: bq2058SN is Standard Device. Contact your Texas Instruments Sales Representative for availability of other thresholds and tolerances. SLUS070A--JULY 2000 12 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Customers are responsible for their applications using TI components. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof. Copyright (c) 2000, Texas Instruments Incorporated |
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