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UCC5510
Low Voltage Differential (LVD/SE) SCSI 9 Line Terminator
FEATURES
* Auto Selection Multi-Mode Single Ended or Low Voltage Differential Termination * 3.0V to 5.25V Operation * Differential Failsafe Bias * Thermal Packaging for Low Junction Temperature and Better MTBF * Master/Slave Inputs * Supports Active Negation * 3pF Channel Capacitance
DESCRIPTION
The UCC5510 Multi-Mode Low Voltage Differential and Single Ended Terminator is specially designed for automatic termination of SingleEnded or Low Voltage Differential SCSI Bus. The Multi-Mode operation of this device allows for a transition system design for the next generation SCSI Parallel Interface (SPI-2). Compliant with SPI-2, with SPI and Fast20 the UCC5510 incorporates all the functions necessary to properly terminate the SCSI Bus and has internal thermal shut down and short circuit limiting.
BLOCK DIAGRAM
SOURCE 5 < 15mA SINK 200A MAXIMUM (NOISE LOAD) TRMPWR 38 +VDD REF 1.3V MSTR/SLV 19 1.3V -0.1V
20 DIFFSENS
2.2 > 1.9V DIFFB 21 0.7 > 0.6V
DEVICE MODE SELECT LOGIC
110
REF 2.7V 125 +50mV TO +62.5mV REF 1.25V 52 5 52 HS/GND HS/GND HS/GND 8 110 28 27 125 +50mV TO +62.5mV 52 32 52 31 SWITCHES UP ARE SINGLE ENDED SWITCHES DOWN ARE LOW VOLTAGE DIFFERENTIAL L9+ L9- 4 L1+ L1-
HS/GND 26 HS/GND HS/GND GND 10 9 18 SE GND SWITCH
1
Circuit Design Patented
REG
UDG-98033
SLUS332A - OCTOBER 1999
UC5510
CONNECTION DIAGRAM ABSOLUTE MAXIMUM RATINGS
TRMPWR Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6V Signal Line Voltage . . . . . . . . . . . . . . . . . . . . . 0V to TRMPWR Package Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . 2W Storage Temperature . . . . . . . . . . . . . . . . . . . -65C to +150C Junction Temperature . . . . . . . . . . . . . . . . . . . -55C to +150C Lead Temperature (Soldering, 10sec.) . . . . . . . . . . . . . +300C
SSOP-36 (Top View) MWP Package
REG N/C N/C 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 TRMPWR N/C N/C N/C L9- L9+ L8- L8+ HS/GND HS/GND HS/GND L7- L7+ L6- L6+ DIFF B DIFFSENS MSTR/SLV
RECOMMENDED OPERATING CONDITIONS
TRMPWR Voltage . . . . . . . . . . . . . . . . . . . . . . . 3.0V TO 5.25V
L1+ L1- L2+ L2- HS/GND HS/GND HS/GND L3+ L3- L4+ L4- L5+ L5- N/C GND
All voltages are with respect to pin 1. Currents are positive into, negative out of the specified terminal. Consult Packaging Section of the Databook for thermal limitations and considerations of packages.
ELECTRICAL CHARACTERISTICS: Unless otherwise specified, TA = 0C to 70C, TRMPWR = 3.3V. PARAMETER TRMPWR Supply Current Section TRMPWR Supply Current Disable Terminator, in DISCNCT mode. Regulator Section 1.25V Regulator 1.25V Regulator Source Current 1.25V Regulator Sink Current 1.3V Regulator 1.3V Regulator Source Current 1.3V Regulator Sink Current 2.7V Regulator 2.7V Regulator Source Current 2.7V Regulator Sink Current 2.7V Regulator Dropout Voltage LVD Mode LVD Mode, Differential Sense Floating LVD Mode, Differential Sense Floating DIFFSENS DIFFSENS DIFFSENS Single Ended Mode Single Ended Mode Single Ended Mode VTRMPWR - (VREG - 3.0 Min) 1.15 -80 80 1.2 -5 50 2.5 -200 100 2.7 -400 200 1.25 -100 100 1.3 1.4 -15 200 3 -800 400 200 1.35 V mA mA V mA A V mA mA mV 20 35 mA A TEST CONDITIONS MIN TYP MAX UNITS
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UC5510
ELECTRICAL CHARACTERISTICS: Unless otherwise specified, TA = 0C to 70C, TRMPWR = 3.3V. PARAMETER Differential Termination Section Differential Impedance Common Mode Impedance Differential Bias Voltage Common Mode Bias Output Capacitance Single Ended Termination Section Impedance Termination Current Output Leakage Output Capacitance Single Ended GND SW Impedance Differential Sense (DIFF B) Input Sections DIFFB Single Ended Threshold DIFFB Sense LVD Threshold DIFFB Input Current Master/Slave (MSTR/SLV) Input Section MSTR/SLV Threshold MSTR/SLV Input Current 0.8 -30 2 30 V A VDIFFB = 0V and 3.3V 0.6 1.9 -10 0.7 2.2 10 V V A Signal Level 0.2V Signal Level 0.5V Disabled, TRMPWR = 0V to 5.25V Single Ended Measurement to Ground (Note 1) 102.3 -21 110 -23 117.7 -24 -22.4 400 3 60 mA mA nA pF Single Ended Measurement to Ground (Note 1) Drivers Tri-stated 100 110 100 1.25 3 105 125 110 165 125 mV V pF TEST CONDITIONS MIN TYP MAX UNITS
Note 1: Guaranteed by design. Not 100% tested in production.
PIN DESCRIPTIONS
DIFFB: DIFF SENSE filter pin should be connected to a 0.1F capacitor to GND and 20k resistor to SCSI/Bus DIFF SENSE Line. DIFFSENS: The SCSI bus DIFF SENSE line is driven to 1.3V to detect what type of devices are connected to the SCSI bus. HS/GND: Heat Sink GND. Connect to large area PC board traces to increase power dissipation capability. GND: Power Supply Return. L1- thru L9-: Signal line/active line for single ended or negative line in differential applications for the SCSI bus. L1+ thru L9+: Ground line for single ended or positive line for differential applications for the SCSI bus. MSTR/SLV: Mode select for the non-controlling terminator. MSTR enables the 1.3V regulator, when the terminator is enabled. Note: This function will be removed on further generations of the multimode terminators. REG: Regulator bypass, must be connected to a 4.7F capacitor. TRMPWR: VIN 3.0V to 5.25V supply.
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UC5510
APPLICATION INFORMATION
L1+ L1- 19 MSTR/SLV L9+ L9- CONTROL LINES (9) L9+ L9- L1+ L1- MSTR/SLV 19
TRMPWR
36 TRMPWR
TRMPWR 36
TRMPWR
1
REG
DIFFSENS 20 20k 20k
20 DIFFSENS
REG
1
4.7F
DIFFB 21 0.1F 0.1F
21 DIFFB
4.7F
4.7F L10+ 36 TRMPWR L10- DATA LINES + PARITY 19 MSTR/SLV L18+ L18- L18+ L18- MSTR/SLV 19 L10+ L10- TRMPWR 36
4.7F
1
REG
DIFFSENS 20
NO CONNECT
20 DIFFSENS
REG
1
4.7F
DIFFB 21
21 DIFFB
4.7F
36 TRMPWR
L19+ L19-
L19+ L19- DATA LINES + PARITY TRMPWR 36
19 MSTR/SLV L27+ L27-
L27+ L27-
MSTR/SLV 19
1 4.7F
REG
DIFFSENS 20
NO CONNECT
20 DIFFSENS
REG
1 4.7F
DIFFB 21
21 DIFFB
UDG-98034a
Figure 1. Application Drawing The master is selected by placing TRMPWR on MSTR/SLV and enabling the 1.3V regulator. The master is the only terminator connected directly to the DIFFSENS bus line. All the other terminators receive a mode signal by connecting the DIFFB pins together. The balancing capacitor is very important during high speed operation. The typical capacitor balance between the positive (+) and negative (-) signals is 0.1pF, except in the MWP package where between L8 and L9 the balance is 0.23pF and 0.4pF respecitvely The negative (-) signal line has a higher capacitance than the positive (+) signal line. The FQP package has typically 0.2pF less capacitance than the MWP package, where the typical balance is 0.1pF except for L8 and L3, where the balance is 0.4pF.
Note: The master/slave function will not be included in future Unitrode terminators.
UNITRODE CORPORATION 7 CONTINENTAL BLVD. * MERRIMACK, NH 03054 TEL. (603) 424-2410 * FAX (603) 424-3460
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Copyright (c) 2000, Texas Instruments Incorporated

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