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TMS44400, TMS44400P, TMS46400, TMS46400P 1048576-WORD BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORIES
SMHS562C - MAY 1995 - REVISED NOVEMBER 1996
D D D D
D
Organization . . . 1 048 576 x 4 Single 5-V Power Supply for TMS44400 / P ( 10% Tolerance) Single 3.3-V Power Supply for TMS46400 / P ( 10% Tolerance) Low Power Dissipation ( TMS46400P only) 200-A CMOS Standby 200-A Self Refresh 300-A Extended-Refresh Battery Backup Performance Ranges:
ACCESS ACCESS ACCESS READ TIME TIME TIME OR WRITE (tRAC) (tCAC) (tAA) CYCLE (MAX) (MAX) (MAX) (MIN) 60 ns 15 ns 30 ns 110 ns 70 ns 18 ns 35 ns 130 ns 80 ns 20 ns 40 ns 150 ns
DGA PACKAGE ( TOP VIEW )
DJ PACKAGE ( TOP VIEW )
DQ1 DQ2 W RAS A9 A0 A1 A2 A3 VCC
1 2 3 4 5 9 10 11 12 13
26 25 24 23 22 18 17 16 15 14
VSS DQ4 DQ3 CAS OE A8 A7 A6 A5 A4
DQ1 DQ2 W RAS A9 A0 A1 A2 A3 VCC
1 2 3 4 5 9 10 11 12 13
26 25 24 23 22 18 17 16 15 14
VSS DQ4 DQ3 CAS OE A8 A7 A6 A5 A4
D D D D D
Enhanced Page-Mode Operation for Faster Memory Access CAS-Before-RAS ( CBR) Refresh Long Refresh Period 1024-Cycle Refresh in 16 ms 128 ms (MAX) for Low-Power, Self-Refresh Version ( TMS4x400P) 3-State Unlatched Output Texas Instruments EPICTM CMOS Process
A0 - A9 CAS DQ1 - DQ4 OE RAS VCC VSS W
Address Inputs Column-Address Strobe Data In Output Enable Row-Address Strobe 5-V or 3.3-V Supply Ground Write Enable
D
Operating Free-Air Temperature Range 0C to 70C
description
AVAILABLE OPTIONS
The TMS4x400 series is a set of high-speed, SELF-REFRESH 4 194 304-bit dynamic random-access memories POWER REFRESH BATTERY DEVICE SUPPLY CYCLES (DRAMs), organized as 1 048 576 words of four BACKUP bits each. The TMS4x400P series is a set of TMS44400 5V -- 1024 in 16 ms high-speed, low-power, self-refresh with TMS44400P 5V Yes 1024 in 128 ms extended-refresh, 4 194 304-bit DRAMs, TMS46400 3.3 V -- 1024 in 16 ms organized as 1 048 576 words of four bits each. TMS46400P 3.3 V Yes 1024 in 128 ms Both series employ state-of-the-art enhanced performance implanted CMOS (EPICTM) technology for high performance, reliability, and low power. These devices feature maximum RAS access times of 60 ns, 70 ns, and 80 ns. All addresses and data-in lines are latched on chip to simplify system design. Data out is unlatched to allow greater system flexibility. The TMS4x400 and TMS4x400P are offered in a 20 / 26-lead plastic small-outline ( TSOP) package ( DGA suffix) and a 300-mil 20 / 26-lead plastic surface-mount SOJ package ( DJ suffix). Both packages are characterized for operation from 0C to 70C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC is a trademark of Texas Instruments Incorporated.
ADVANCE INFORMATION concerns new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to change without notice.
Copyright (c) 1996, Texas Instruments Incorporated
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'4x400/P-60 '4x400/P-70 '4x400/P-80
PIN NOMENCLATURE
TMS44400, TMS44400P, TMS46400, TMS46400P 1048576-WORD BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORIES
SMHS562C - MAY 1995 - REVISED NOVEMBER 1996
logic symbol
RAM 1024K x 4 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 9 10 11 12 14 15 16 17 18 5 20D10/21D0
A
0 1 048 575
RAS
4
CAS W OE DQ1 DQ2 DQ3 DQ4
23 3 22 1 2 24 25
20D19/21D9 C20 [ROW] G23/[REFRESH ROW] 24 [PWR DWN] C21[COLUMN] G24 & 23,21D G25 A,22D 26 23C22 24,25 EN
ADVANCE INFORMATION
A,Z26
This symbol is in accordance with ANSI / IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the DJ package.
functional block diagram
RAS CAS W OE
Timing and Control
A0 A1 ColumnAddress Buffers A9
8 2
Column Decode Sense Amplifiers 128K Array 128K Array R o w 128K Array 128K Array 16 16 I/O Buffers 1 of 16 Selection 2 16 DataIn Reg. 4 DataOut Reg. DQ1 - DQ4
4
16 RowAddress Buffers 10
D e c o d 128K Array e 128K Array 10
2
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TMS44400, TMS44400P, TMS46400, TMS46400P 1048576-WORD BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORIES
SMHS562C - MAY 1995 - REVISED NOVEMBER 1996
operation
enhanced page mode Enhanced-page-mode operation allows faster memory access by keeping the same row address while selecting random column addresses. The time for row-address setup and hold and address multiplex is eliminated. The maximum number of columns that can be accessed is determined by the maximum RAS low time and the CAS page cycle time used. With minimum CAS page cycle time, all 1024 columns specified by column addresses A0 through A9 can be accessed without intervening RAS cycles. Unlike conventional page-mode DRAMs, the column-address buffers in this device are activated on the falling edge of RAS. The buffers act as transparent or flow-through latches while CAS is high. The falling edge of CAS latches the column addresses. This feature allows the TMS4x400 to operate at a higher data bandwidth than conventional page-mode parts because data retrieval begins as soon as the column address is valid rather than when CAS transitions low. This performance improvement is referred to as enhanced page mode. A valid column address can be presented immediately after row-address hold time has been satisfied, usually well in advance of the falling edge of CAS. In this case, data is obtained after tCAC maximum (access time from CAS low) if tAA maximum (access time from column address) has been satisfied. In the event that column addresses for the next cycle are valid at the time CAS goes high, access time for the next cycle is determined by the later occurrence of tCAC (acces time from CAS low) or tCPA (access time from column precharge). address (A0 - A9) Twenty address bits are required to decode any one of the 1 048 576 storage-cell locations. Ten row-address bits are set up on inputs A0 through A9 and latched onto the chip by RAS. The ten column-address bits are set up on A0 through A9 and latched onto the chip by CAS. All addresses must be stable on or before the falling edges of RAS and CAS. RAS is similar to a chip enable because it activates the sense amplifiers as well as the row decoder. CAS is used as a chip select, activating the output buffer, as well as latching the address bits into the column-address buffer. write enable (W) The read or write mode is selected through W input. A logic high on W selects the read mode and a logic low selects the write mode. W can be driven from standard TTL circuits ( TMS44400/ P) or low voltage TTL circuits ( TMS46400/ P) without a pullup resistor. The data input is disabled when the read mode is selected. When W goes low prior to CAS (early write), data out remains in the high-impedance state for the entire cycle, permitting a write operation independent of the state of OE. This permits early-write operation to complete with OE grounded. data in / out (DQ1 - DQ4) Data out is the same polarity as data in. The output is in the high-impedance (floating) state until CAS and OE are brought low. In a read cycle, the output becomes valid after all access times are satisfied. The output remains valid while CAS and OE are low. CAS or OE going high returns the output to a high-impedance state. This is accomplished by bringing OE high prior to applying data, satisfying the OE to data delay hold time (tOED). output enable (OE) OE controls the impedance of the output buffers. When OE is high, the buffers remain in the high-impedance state. Bringing OE low during a normal cycle activates the output buffers, putting them in the low-impedance state. It is necessary for both RAS and CAS to be brought low for the output buffers to go into the low-impedance state. They remain in the low-impedance state until either OE or CAS is brought high.
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TMS44400, TMS44400P, TMS46400, TMS46400P 1048576-WORD BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORIES
SMHS562C - MAY 1995 - REVISED NOVEMBER 1996
refresh A refresh operation must be performed at least once every 16 ms (128 ms for TMS4x400P) to retain data. This can be achieved by strobing each of the 1024 rows (A0 - A9). A normal read or write cycle refreshes all bits in each row that is selected. A RAS-only operation can be used by holding CAS at the high (inactive) level, conserving power as the output buffer remains in the high-impedance state. Externally generated addresses must be used for a RAS-only refresh. Hidden refresh can be performed while maintaining valid data at the output. This is accomplished by holding CAS at VIL after a read operation and cycling RAS after a specified precharge period, similar to a RAS-only refresh cycle. The external address is ignored during the hidden-refresh cycle. CAS-before-RAS (CBR) refresh CBR refresh is utilized by bringing CAS low earlier than RAS (see parameter tCSR) and holding it low after RAS falls (see parameter tCHR). For successive CBR refresh cycles, CAS can remain low while cycling RAS. The external address is ignored and the refresh address is generated internally. A low-power battery-backup refresh mode that requires less than 300-A (TMS46400P) or 500-A (TMS44400P) refresh current is available on the low-power devices. Data integrity is maintained using CBR refresh with a period of 125 s while holding RAS low for less than 1 s. To minimize current consumption, all input levels need to be at CMOS levels ( VIL 0.2 V, VIH VCC - 0.2 V ). self refresh The self-refresh mode is entered by dropping CAS low prior to RAS going low. CAS and RAS are both held low for a minimum of 100 s. The chip is then refreshed by an on-board oscillator. No external address is required since the CBR counter is used to keep track of the address. To exit the self-refresh mode, both RAS and CAS are brought high to satisfy tCHS. Upon exiting the self-refresh mode, a burst refresh (refresh a full set of row addresses) must be executed before continuing with normal operation, to ensure that the DRAM is fully refreshed. power up To achieve proper device operation, an initial pause of 200 s followed by a minimum of eight initialization cycles is required after full VCC level is achieved. These eight initialization cycles must include at least one refresh ( RAS-only or CBR) cycle. test mode The test mode is initiated with a CBR refresh cycle while simultaneously holding W low (WCBR). The entry cycle performs an internal refresh cycle while internally setting the device to perform parallel read or write on subsequent cycles. While in test mode, any desired data sequence can be performed on the device. The device exits test mode if a CBR refresh cycle with W held high or a RAS-only refresh (ROR) cycle is performed. The TMS4x400 / P is configured as a 512K x 8 bit device in test mode, where each DQ pin has a separate 2-bit parallel read- and write-data bus. During a read cycle, the two internal bits are compared for each DQ pin separately. If the two bits agree, the DQ pin goes high; if not, the DQ pin goes low. The two bits are written to reflect the state of their respective DQ pins during a parallel-write operation. Each DQ pin is independent of the others, and any data pattern desired can be written on each DQ pin. Test time is reduced by a factor of 4 for this series.
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TMS44400, TMS44400P, TMS46400, TMS46400P 1048576-WORD BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORIES
SMHS562C - MAY 1995 - REVISED NOVEMBER 1996
test mode (continued)
Entry Cycle Test Mode Cycle RAS Exit Cycle Normal Mode
CAS
W
Figure 1. Test-Mode Cycle Timing
The states of W, data in, and address are defined by the type of cycle used during test mode.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC: TMS44400, TMS44400P . . . . . . . . . . . . . . . . . . . . . . . - 1.0 V to 7.0 V TMS46400, TMS46400P . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to 4.6 V Voltage range on any pin (see Note 1) TMS44400, TMS44400P . . . . . . . . . . . . . . . . . . . . . . . - 1.0 V to 7.0 V TMS46400, TMS46400P . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to 4.6 V Short-circuit output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 W Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 70C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 55C to 150C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to VSS.
recommended operating conditions
TMS44400 / P MIN VCC VIH VIL Supply voltage High-level input voltage Low-level input voltage (see Note 2) 4.5 2.4 -1 NOM 5 MAX 5.5 6.5 0.8 MIN 3 2 - 0.3 TMS46400 / P NOM 3.3 MAX 3.6 VCC + 0.3 0.8 UNIT V V V
TA Operating free-air temperature 0 70 0 70 C NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used for logic-voltage levels only.
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TMS44400, TMS44400P, TMS46400, TMS46400P 1048576-WORD BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORIES
SMHS562C - MAY 1995 - REVISED NOVEMBER 1996
electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER VOH VOL II IO ICC1 High-level output voltage Low-level output voltage Input current (leakage) TEST CONDITIONS IOH = - 5 mA IOL = 4.2 mA VCC = 5.5 V, VI = 0 V to 6.5 V, All others = 0 V to VCC VCC = 5.5 V, CAS high VCC = 5.5 V, VO = 0 V to VCC, '44400 - 60 '44400P - 60 MIN 2.4 0.4 10 10 105 MAX '44400 - 70 '44400P - 70 MIN 2.4 0.4 10 10 90 MAX '44400 - 80 '44400P - 80 MIN 2.4 0.4 10 10 80 MAX V V A A mA UNIT
Output current (leakage) Read- or write-cycle current (see Note 3)
Minimum cycle
After one memory cycle, RAS and CAS high, VIH = 2.4 V ( TTL) ICC2 Standby current After one memory cycle, RAS and CAS high, high VIH = VCC - 0.2 V (CMOS) '44400
2
2
2
mA
ADVANCE INFORMATION
1
1
1
mA A
'44400P
500
500
500
ICC3
Average refresh current (RAS only or CBR) (see Note 4) Average page current (see Notes 3 and 5) Self-refresh current (see Note 3) Standby current, outputs enabled (see Note 3)
VCC = 5.5 V, Minimum cycle, RAS cycling, CAS high (RAS only); RAS low after CAS low (CBR) VCC = 5.5 V, RAS low, tPC = MIN, CAS cycling
105
90
80
mA
ICC4 ICC6 ICC7
90
80
70
mA A mA
CAS 0.2 V, RAS < 0.2 V, tRAS and tCAS > 1000 ms RAS = VIH, CAS = VIL, Data out = enabled tRC = 125 s, tRAS 1 ms, VCC - 0.2 V VIH 6.5 V, 0 V VIL 0.2 V, W and OE = VIH, Address and data stable
500 5
500 5
500 5
ICC10
Battery-backup current (with CBR)
500
500
500
A
For TMS44400P only NOTES: 3. ICC MAX is specified with no load connected. 4. Measured with a maximum of one address change while RAS = VIL 5. Measured with a maximum of one address change while CAS = VIH
6
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TMS44400, TMS44400P, TMS46400, TMS46400P 1048576-WORD BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORIES
SMHS562C - MAY 1995 - REVISED NOVEMBER 1996
electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER High-level g output voltage Low-level output voltage Input current (leakage) Output current (leakage) Read- or write-cycle current (see Note 3) TEST CONDITIONS IOH = - 2 mA (LVTTL) IOH = - 100 A (LVCMOS) IOL = 2 mA (LVTTL) IOL = 100 A (LVCMOS) VI = 0 V to 3.9 V, VCC = 3.6 V, All others = 0 V to VCC VO = 0 V to VCC, VCC = 3.6 V, CAS high '46400 - 60 '46400P - 60 MIN 2.4 VCC - 0.2 0.4 0.2 10 10 MAX '46400 - 70 '46400P - 70 MIN 2.4 VCC - 0.2 0.4 0.2 10 10 MAX '46400 - 80 '46400P - 80 MIN 2.4 VCC - 0.2 0.4 0.2 10 10 MAX V V A A UNIT
VOH VOL II IO
ICC1
Minimum cycle,
VCC = 3.6 V
70
60
50
mA
After one memory cycle, RAS and CAS high, VIH = 2 V (LVTTL) ICC2 Standby current After one memory cycle, RAS and CAS high, high VIH = VCC - 0.2 V (LVCMOS) '46400
2
2
2
mA
300
300
300
A A
'46400P
200
200
200
ICC3
Average refresh current (RAS only or CBR) (see Note 4) Average page current (see Notes 3 and 5) Self-refresh current (see Note 3) Standby current, outputs enabled (see Note 3)
Minimum cycle, VCC = 3.6 V, RAS cycling, CAS high (RAS only); RAS low after CAS low (CBR)
70
60
50
mA
ICC4
tPC = MIN, RAS low,
VCC = 3.6 V, CAS cycling
60
50
40
mA
ICC6
CAS 0.2 V, RAS < 0.2 V, tRAS and tCAS > 1000 ms
200
200
200
A
ICC7
RAS = VIH, CAS = VIL, Data out = enabled
5
5
5
mA
ICC10
tRC = 125 s, tRAS 1 ms, Battery-backup VCC - 0.2 V VIH 3.9 V, current 0 V VIL 0.2 V, (with CBR) W and OE = VIH, Address and data stable
300
300
300
A
For TMS46400P only NOTES: 3. ICC MAX is specified with no load connected. 4. Measured with a maximum of one address change while RAS = VIL 5. Measured with a maximum of one address change while CAS = VIH
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TMS44400, TMS44400P, TMS46400, TMS46400P 1048576-WORD BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORIES
SMHS562C - MAY 1995 - REVISED NOVEMBER 1996
capacitance over recommended ranges of supply voltage and operating free-air temperature, f = 1 MHz (see Note 6)
PARAMETER Ci(A) Ci(RC) Ci(OE) Ci(W) Input capacitance, A0 - A10 Input capacitance, CAS and RAS Input capacitance, OE Input capacitance, W MIN MAX 5 7 7 7 UNIT pF pF pF pF
Co Output capacitance 7 pF NOTE 6: VCC = 5 V .5 V for the TMS44400 devices, VCC = 3.3 V 0.3 V for the TMS46400 devices, and the bias on pins under test is 0 V.
switching characteristics over recommended ranges of supply voltage and operating free-air temperature
PARAMETER tAA tCAC tCPA tRAC tOEA tCLZ tOFF tOEZ Access time from column address Access time from CAS low Access time from column precharge Access time from RAS low Access time from OE low CAS to output in low impedance Output-disable time after CAS high (see Note 7) Output-disable time after OE high (see Note 7) 0 0 0 15 15 '4x400 - 60 '4x400P - 60 MIN MAX 30 15 35 60 15 0 0 0 18 18 '4x400 - 70 '4x400P - 70 MIN MAX 35 18 40 70 18 0 0 0 20 20 '4x400 - 80 '4x400P - 80 MIN MAX 40 20 45 80 20 ns ns ns ns ns ns ns ns UNIT
ADVANCE INFORMATION
NOTE 7: tOFF is specified when the output is no longer driven.
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TMS44400, TMS44400P, TMS46400, TMS46400P 1048576-WORD BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORIES
SMHS562C - MAY 1995 - REVISED NOVEMBER 1996
timing requirements over recommended ranges of supply voltage and operating free-air temperature
'4x400 - 60 '4x400P - 60 MIN tRC tRWC tPC tPRWC tRASP tRAS tRASS tCAS tCP tRP tRPS tWP tASC tASR tDS tRCS tCWL tRWL tWCS tWSR tWTS tCAH tDHR tDH tAR tRAH tRCH tRRH tWCH tWCR tWHR tWTH tCHS tOEH Cycle time, random read or write (see Note 8) Cycle time, read-write Cycle time, page-mode read or write (see Note 9) Cycle time, page-mode read-write Pulse duration, RAS low, page mode (see Note 10) Pulse duration, RAS low, nonpage mode (see Note 10) Pulse duration, RAS low, self refresh Pulse duration, CAS low (see Note 11) Pulse duration, CAS high Pulse duration, RAS high (precharge) Precharge time after self refresh using RAS Pulse duration, write Setup time, column address before CAS low Setup time, row address before RAS low Setup time, data (see Note 12) Setup time, W high before CAS low Setup time, W low before CAS high Setup time, W low before RAS high Setup time, W low before CAS low (early-write operation only) Setup time, W high (CBR refresh only) Setup time, W low (test mode only) Hold time, column address after CAS low Hold time, data after RAS low (see Note 13) Hold time, data (see Note 12) Hold time, column address after RAS low (see Note 13) Hold time, row address after RAS low Hold time, W high after CAS high (see Note 14) Hold time, W high after RAS high (see Note 14) Hold time, W low after CAS low (early-write operation only) Hold time, W low after RAS low (see Note 13) Hold time, W high (CBR refresh only) Hold time, W low (test mode only) Hold time, CAS low after RAS high (self refresh) Hold time, OE command 110 155 40 85 60 100 000 60 100 10 10 40 110 10 0 0 0 0 15 15 0 10 10 10 50 10 50 10 0 0 10 50 10 10 - 50 15 10 000 10 000 MAX '4x400 - 70 '4x400P - 70 MIN 130 181 45 96 70 100 000 70 100 18 10 50 130 10 0 0 0 0 18 18 0 10 10 15 55 15 55 10 0 0 15 55 10 10 - 50 18 18 10 000 10 000 MAX '4x6400 - 80 '4x400P - 80 MIN 150 205 50 105 80 100 000 80 100 20 10 60 150 10 0 0 0 0 20 20 0 10 10 15 60 15 60 10 0 0 15 60 10 10 - 50 20 20 10 000 10 000 MAX ns ns ns ns ns ns s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns UNIT
tOED Hold time, OE to data delay 15 NOTES: 8. All cycle times assume tT = 5 ns. 9. To ensure tPC min, tASC should be tCP . 10. In a read-write cycle, tRWD and tRWL must be observed. 11. In a read-write cycle, tCWD and tCWL must be observed. 12. Referenced to the later of CAS or W in write operations 13. The minimum value is measured when tRCD is set to tRCD min as a reference. 14. Either tRRH or tRCH must be satisfied for a read cycle.
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TMS44400, TMS44400P, TMS46400, TMS46400P 1048576-WORD BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORIES
SMHS562C - MAY 1995 - REVISED NOVEMBER 1996
timing requirements over recommended ranges of supply voltage and operating free-air temperature (continued)
'4x400 - 60 '4x400P - 60 MIN tROH tAWD tCHR tCRP tCSH tCSR tCWD tRAD tRAL tCAL tRCD tRPC tRSH tRWD tTAA tTCPA tTRAC tREF Hold time, RAS referenced to OE Delay time, column address to W low (read-write operation only) Delay time, RAS low to CAS high (CBR refresh only) Delay time, CAS high to RAS low Delay time, RAS low to CAS high Delay time, CAS low to RAS low (CBR refresh only) Delay time, CAS low to W low (read-write operation only) Delay time, RAS low to column address (see Note 15) Delay time, column address to RAS high Delay time, column address to CAS high Delay time, RAS low to CAS low (see Note 15) Delay time, RAS high to CAS low Delay time, CAS low to RAS high Delay time, RAS low to W low (read-write operation only) Access time from address (test mode) Access time from column precharge (test mode) Access time from RAS (test mode) Refresh time interval '4x400 '4x400P 2 10 55 10 0 60 5 40 15 30 30 20 0 15 85 35 40 65 16 128 30 2 45 30 MAX '4x400 - 70 '4x400P - 70 MIN 10 63 10 0 70 5 46 15 35 35 20 0 18 98 40 45 75 16 128 30 2 52 35 MAX '4x400 - 80 '4x400P - 80 MIN 10 70 10 0 80 5 50 15 40 40 20 0 20 110 45 50 85 16 128 30 60 40 MAX ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ms ns UNIT
ADVANCE INFORMATION
tT Transition time NOTE 15: The maximum value is specified only to ensure access time.
PARAMETER MEASUREMENT INFORMATION
1.31 V RL = 218 Output Under Test CL = 100 pF (see Note A) Output Under Test CL = 100 pF (see Note A) R2 = 295 VCC = 5 V R1 = 828
(a) LOAD CIRCUIT
(b) ALTERNATE LOAD CIRCUIT
NOTE A: CL includes probe and fixture capacitance.
Figure 2. Load Circuits for Timing Parameters
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TMS44400, TMS44400P, TMS46400, TMS46400P 1048576-WORD BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORIES
SMHS562C - MAY 1995 - REVISED NOVEMBER 1996
PARAMETER MEASUREMENT INFORMATION
1.4 V RL = 500 Output Under Test CL = 100 pF (see Note A) (a) LOAD CIRCUIT NOTE A: CL includes probe and fixture capacitance. Output Under Test CL = 100 pF (see Note A) R2 = 868 VCC = 3.3 V R1 = 1178
(b) ALTERNATE LOAD CIRCUIT
Figure 3. Low-Voltage Load Circuits for Timing Parameters
tRC tRAS RAS tRP tCRP tRSH tCAS tRAD tCP tASR tRAH A0 - A9 Row tRCS tAR tCAH W Don't Care tCAC tAA DQ1 - DQ4 Hi-Z See Note A tCLZ tRAC tOEA Don't Care tROH Don't Care tOEZ tOFF Valid Data Out Column tASC tRAL tCAL Don't Care tRRH tRCH Don't Care
tCSH tRCD tT CAS
OE
NOTE A: Output can go from the high-impedance state to an invalid-data state prior to the specified access time.
Figure 4. Read-Cycle Timing
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TMS44400, TMS44400P, TMS46400, TMS46400P 1048576-WORD BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORIES
SMHS562C - MAY 1995 - REVISED NOVEMBER 1996
PARAMETER MEASUREMENT INFORMATION
tRC tRAS RAS tT tRCD tCSH CAS tRAH tASR tAR tASC tCAH tCAL tRAL Column tCWL tRAD tWCR W Don't Care tWCS tDH tWP tDS DQ1 - DQ4 Valid Data tDHR OE Don't Care Don't Care Don't Care tRWL tWCH Don't Care tCP tRSH tCAS tRP tCRP
ADVANCE INFORMATION
A0 - A9
Row
Figure 5. Early-Write-Cycle Timing
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TMS44400, TMS44400P, TMS46400, TMS46400P 1048576-WORD BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORIES
SMHS562C - MAY 1995 - REVISED NOVEMBER 1996
PARAMETER MEASUREMENT INFORMATION
tRC tRAS RAS tT tRCD tCSH CAS tASC tRAH tAR tASR A0 - A9 Row tRAD tDS W Don't Care tWP tWCR tDHR DQ1 - DQ4 Don't Care tOED Valid Data tDH Don't Care Column tCWL tRWL tRAL Don't Care tCAL tCAH tCP tRSH tCAS tRP tCRP
Don't Care
tOEH Don't Care
OE
Don't Care
Figure 6. Write-Cycle Timing
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ADVANCE INFORMATION
TMS44400, TMS44400P, TMS46400, TMS46400P 1048576-WORD BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORIES
SMHS562C - MAY 1995 - REVISED NOVEMBER 1996
PARAMETER MEASUREMENT INFORMATION
tRWC tRAS RAS tT tRCD CAS tASR tASC tRAH tRAD tAR A0 - A9 Row tRCS tRWD W tAWD tCWD tCAC tAA tCLZ DQ1 - DQ4 See Note A Data Out tOEZ tOED OE Don't Care tOEH Don't Care Data In tOEH tRAC Don't Care tDS tDH Don't Care Column Don't Care tRWL tWP tCAH tT tCWL tCP tCAS tRP tCRP
ADVANCE INFORMATION
NOTE A: Output can go from the high-impedance state to an invalid-data state prior to the specified access time.
Figure 7. Read-Write-Cycle Timing
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TMS44400, TMS44400P, TMS46400, TMS46400P 1048576-WORD BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORIES
SMHS562C - MAY 1995 - REVISED NOVEMBER 1996
PARAMETER MEASUREMENT INFORMATION
tRP tRASP RAS tRCD tCSH tT CAS tRAH tCAH tASR A0 - A9 Row tAR tRCS W tRAD tCAC tAA tRAC tCLZ DQ1 - DQ4 See Note B Valid Out tASC Column tRAL tCAL tCAS tPC tCP tRSH tCRP
tAA (see Note A)
tRRH tRCH
tCPA (see Note A) tOFF Valid Out
tOEZ OE Don't Care tOEA tOEA
tOEZ
NOTES: A. Access time is tCPA or tAA dependent. B. Output can go from the high-impedance state to an invalid-data state prior to the specified access time.
Figure 8. Enhanced-Page-Mode Read-Cycle Timing
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ADVANCE INFORMATION
Column
Don't Care
TMS44400, TMS44400P, TMS46400, TMS46400P 1048576-WORD BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORIES
SMHS562C - MAY 1995 - REVISED NOVEMBER 1996
PARAMETER MEASUREMENT INFORMATION
tRP tRASP RAS tCSH tRCD tCAS CAS tASR tPC tRSH tCRP
tASC tAR tCAH Column tRAD tWCR tWP tDHR tCWL
tCP tRAL tCAL Column tCWL tRWL Don't Care
tRAH A0 - A9 Row
ADVANCE INFORMATION
W
Don't Care See Note A tDS tDS tDH tDH See Note A Valid Data In tOEH
Don't Care See Note A tOEH
Don't Care
DQ1 - DQ4
Valid In tOED Don't Care
Don't Care
OE
Don't Care
NOTES: A. Referenced to CAS or W, whichever occurs last B. A read cycle or a read-write cycle can be intermixed with write cycles as long as read and read-write timing specifications are not violated.
Figure 9. Enhanced-Page-Mode Write-Cycle Timing
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TMS44400, TMS44400P, TMS46400, TMS46400P 1048576-WORD BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORIES
SMHS562C - MAY 1995 - REVISED NOVEMBER 1996
PARAMETER MEASUREMENT INFORMATION
tRP tRASP RAS tCSH tPRWC tRCD CAS tCAS tASR tASC tAR tRAD tCAH A0 - A9 Row tRAH Column Column Don't Care tCP tRSH tCRP
tCWD tAWD tRWD tWP tRCS tAA tRAC tCAC tDS tCPA tDH Valid In tCLZ tOEA tOEZ Valid Out tOEH
tCWL tRWL
W
tOEH Valid Out (see Note A) Valid In
DQ1 - DQ4
tOED
OE NOTES: A. Output can go from the high-impedance state to an invalid-data state prior to the specified access time. B. A read or write cycle can be intermixed with read-write cycles as long as the read and write timing specifications are not violated.
Figure 10. Enhanced-Page-Mode Read-Write-Cycle Timing
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ADVANCE INFORMATION
TMS44400, TMS44400P, TMS46400, TMS46400P 1048576-WORD BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORIES
SMHS562C - MAY 1995 - REVISED NOVEMBER 1996
PARAMETER MEASUREMENT INFORMATION
tRC tRAS RAS tCRP tT CAS Don't Care tASR A0 - A9 Don't Care Row tRAH tRP tRPC
Don't Care
Row
ADVANCE INFORMATION
W
Don't Care
DQ1 - DQ4
Don't Care
OE
Don't Care
Figure 11. RAS-Only Refresh-Cycle Timing
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TMS44400, TMS44400P, TMS46400, TMS46400P 1048576-WORD BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORIES
SMHS562C - MAY 1995 - REVISED NOVEMBER 1996
PARAMETER MEASUREMENT INFORMATION
tRC tRP tRAS RAS tRPC CAS tWSR W tT tWHR tCSR tCHR
OE
Don't Care
DQ1 - DQ4
Hi-Z
Figure 12. Automatic-CBR-Refresh-Cycle Timing
tRP tRASS tCSR tRPC CAS tWSR W tT tWHR tCHS
tRPS
RAS
A0 - A9
Don't Care
OE
Don't Care
DQ1 - DQ4
Hi-Z
Figure 13. Self-Refresh-Cycle Timing
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ADVANCE INFORMATION
A0 - A9
Don't Care
TMS44400, TMS44400P, TMS46400, TMS46400P 1048576-WORD BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORIES
SMHS562C - MAY 1995 - REVISED NOVEMBER 1996
PARAMETER MEASUREMENT INFORMATION
Refresh Cycle Memory Cycle tRP tRP tRAS tRAS Refresh Cycle
RAS tCHR CAS tAR tCAH tASC tRAH tASR A0 - A10 Row Col Don't Care tWHR tWSR tWHR tCAS
ADVANCE INFORMATION
20
tRRH tRCS W tRAC tAA tCAC tCLZ DQ1 - DQ4 tWSR
tWHR
tWSR
tOFF
Valid Data
tOEA OE
tOEZ
Figure 14. Hidden-Refresh-Cycle (Read) Timing
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TMS44400, TMS44400P, TMS46400, TMS46400P 1048576-WORD BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORIES
SMHS562C - MAY 1995 - REVISED NOVEMBER 1996
PARAMETER MEASUREMENT INFORMATION
Refresh Cycle Refresh Cycle Memory Cycle tRP tRP tRAS RAS tRAS tCHR tCAS CAS tCAH tASC tRAH tASR A0 - A9 Row Col tRRH tWCS tWCR W tWP tWCH tDH tDHR tDS DQ1 - DQ4 Valid Data Don't Care tWHR tWSR tAR
Don't Care
OE
Don't Care
Figure 15. Hidden-Refresh-Cycle (Write) Timing
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ADVANCE INFORMATION
TMS44400, TMS44400P, TMS46400, TMS46400P 1048576-WORD BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORIES
SMHS562C - MAY 1995 - REVISED NOVEMBER 1996
PARAMETER MEASUREMENT INFORMATION
tRC tRP RAS tRPC CAS tWTS W tT tWTH Don't Care tRAS tCSR tCHR
A0 - A9
Don't Care
ADVANCE INFORMATION
OE
Don't Care
DQ1 - DQ4
Hi-Z
Figure 16. Test-Mode Entry-Cycle Timing
device symbolization (TMS44400 illustrated)
-SS Speed ( - 60, - 70, - 80) TMS44400 W B Y DJ M LLL P Assembly Site Code Lot Traceability Code Month Code Year Code Die Revision Code Wafer Fab Code Low-Power / Self-Refresh Designator (Blank or P) Package Code
22
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TMS44400, TMS44400P, TMS46400, TMS46400P 1048576-WORD BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORIES
SMHS562C - MAY 1995 - REVISED NOVEMBER 1996
PARAMETER MEASUREMENT INFORMATION
DJ (R-PDSO-J20/26)
0.680 (17,27) 0.670 (17,02) 26 22 18 14
PLASTIC SMALL-OUTLINE J-LEAD PACKAGE
0.340 (8,64) 0.330 (8,38) 0.305 (7,75) 0.295 (7,49)
1
5
9 0.032 (0,81) 0.026 (0,66)
13
0.148 (3,76) 0.128 (3,25)
0.106 (2,69) MAX
0.008 (0,20) NOM
Seating Plane 0.020 (0,51) 0.016 (0,41) 0.050 (1,27) 4040092-2 / B 10/94 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Plastic body dimensions do not include mold protrusion. Maximum mold protrusion is 0.005 (0,125). 0.004 (0,10) 0.007 (0,18) M 0.275 (6,99) 0.260 (6,60)
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23
ADVANCE INFORMATION
TMS44400, TMS44400P, TMS46400, TMS46400P 1048576-WORD BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORIES
SMHS562C - MAY 1995 - REVISED NOVEMBER 1996
MECHANICAL DATA
DGA (R-PDSO-G20/26)
0.020 (0,50) 0.012 (0,30) 14
PLASTIC SMALL-OUTLINE PACKAGE
0.050 (1,27) 26
0.008 (0,21) M
0.371 (9,42) 0.355 (9,02) 0.304 (7,72) 0.296 (7,52) 0.006 (0,15) NOM 1 13 0.679 (17,24) 0.671 (17,04) Gage Plane 0.010 (0,25) 0- 5 0.024 (0,60) 0.016 (0,40)
ADVANCE INFORMATION
Seating Plane 0.050 (1,27) MAX 0.004 (0,10) MIN 0.004 (0,10) 4040265-2 / B 10/94 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion.
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IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof.
Copyright (c) 1998, Texas Instruments Incorporated

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