View SMJS846A_1003850.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

TMS29LF008T, TMS29LF008B 1048576 BY 8-BIT FLASH MEMORIES
SMJS846A - MAY 1997 - REVISED NOVEMBER 1997
D D D
D D
D
D D D D D
Single Power Supply Supports 2.7-V and 3.6-V Read/Write Operation Organization . . . 1 048576 By 8 Bits Array Blocking Architecture - One 16K-Byte Boot Sector - Two 8K-Byte Parameter Sectors - One 32K-Byte Sector - Fifteen 64K-Byte Sectors - Any Combination of Sectors Can Be Erased. Supports Full-Chip Erase - Any Combination of Sectors Can Be Marked as Read-Only Boot-Code Sector Architecture - T = Top Sector - B = Bottom Sector Sector Protection - Hardware Protection Method That Disables Any Combination of Sectors From Write or Erase Operations Using Standard Programming Equipment Embedded Program/Erase Algorithms - Automatically Pre-Programs and Erases Any Sector - Automatically Programs and Verifies the Program Data at Specified Address JEDEC Standards - Compatible With JEDEC Byte Pinouts - Compatible With JEDEC EEPROM Command Set Fully Automated On-Chip Erase and Program Operations 100 000 Program/Erase Cycles Low Power Dissipation Low Current Consumption - 20-mA Typical Active Read for Byte Mode - 30-mA Typical Program / Erase Current - Less Than 60-A Standby Current - 5 A in Deep Power-Down Mode
D D D D D
D
PIN NOMENCLATURE A[0 :19] DQ[0 : 7] CE OE NC RESET RY / BY VCC VSS WE Address Inputs Data In / Data out Chip Enable Output Enable No Internal Connection Reset / Deep Power Down Ready / Busy Output Power Supply Ground Write Enable
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright (c) 1997 Texas Instruments Incorporated
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
POST OFFICE BOX 1443
* HOUSTON, TEXAS 77251-1443
1
PRODUCT PREVIEW
All Inputs/Outputs TTL-Compatible Erase Suspend/Resume - Supports Reading Data From, or Programming Data to, a Sector Not Being Erased Hardware-Reset Pin Initializes the Internal-State Machine to the Read Operation 40-Pin Thin Small-Outline Package (TSOP) (DCD Suffix) Detection Of Program/Erase Operation - Data Polling and Toggle Bit Feature of Program/Erase Cycle Completion - Hardware Method for Detection of Program/Erase Cycle Completion Through Ready/Busy (RY/BY) Output Pin High-Speed Data Access at 3.3-V VCC at Three Temperature Ranges - 90 ns Commercial . . . 0C to 70C - 100 ns Extended . . . -40C to 85C - 120 ns Automotive . . . -40C to 125C
"10%
TMS29LF008T, TMS29LF008B 1048576 BY 8-BIT FLASH MEMORIES
SMJS846A - MAY 1997 - REVISED NOVEMBER 1997
40-PIN TSOP DCD PACKAGE ( TOP VIEW )
PRODUCT PREVIEW
A16 A15 A14 A13 A12 A11 A9 A8 WE RESET NC RY / BY A18 A7 A6 A5 A4 A3 A2 A1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
A17 VSS NC A19 A10 DQ7 DQ6 DQ5 DQ4 VCC VCC NC DQ3 DQ2 DQ1 DQ0 OE VSS CE A0
description
The TMS29LF008T/B is an 1 048 576 by 8-bit (8 388 608-bit), 3-V single-supply, programmable read-only memory device that can be electrically erased and reprogrammed. This device is organized as 1024K by 8 bits, divided into 19 sectors: - - - - One 16K-byte boot sector Two 8K-byte sectors One 32K-byte sector Fifteen 64K-byte sectors
Any combination of sectors can be marked as read-only or erased. Full-chip erasure is also supported. Sector data protection is afforded by methods that can disable any combination of sectors from write or read operations using standard programming equipment. An on-chip state machine controls the program and erase operations by providing an on-board algorithm that automatically pre-programs and erases any sector before it automatically programs and verifies program data at any specified address. The command set is compatible with that of the Joint Electronic Device Engineering Council (JEDEC) standards and is compatible with the JEDEC 8M-bit electrically erasable, programmable read-only memory (EEPROM) command set. A suspend/resume feature allows access to unaltered memory blocks during a section-erase operation. All outputs of this device are TTL-compatible. Additionally, an erase/suspend/resume feature supports reading data from, or programming data to, a sector that is not being erased.
2
POST OFFICE BOX 1443
* HOUSTON, TEXAS 77251-1443
TMS29LF008T, TMS29LF008B 1048576 BY 8-BIT FLASH MEMORIES
SMJS846A - MAY 1997 - REVISED NOVEMBER 1997
description (continued)
Device operations are selected by writing JEDEC-standard commands into the command register using standard microprocessor write timings. The command register acts as an input to an internal-state machine which interprets the commands, controls the erase and programming operations, outputs the status of the device, outputs the data stored in the device, and outputs the device algorithm-selection code. On initial power up, the device defaults to the read mode. A hardware-reset pin initializes the internal-state machine to the read operation. The device has low power dissipation with a 20-mA active read for the byte mode, 30-mA typical program/erase current mode, and less than 60-mA standby current with a 5-mA deep-power-down mode. These devices are offered with 90-, 100-, and 120-ns access times. Table 1 and Table 2 show the sector-address ranges. The TMS29LF008T/B is offered in a 40-pin thin small-outline package (TSOP) (DCD suffix).
device symbol nomenclature
TMS29LF008 T -90 C DCD L Temperature Range Designator L = Commercial (0C to 70C) E = Extended (-40C to 85C) Q = Automotive (-40C to 125C) Package Designator DCD = 40-Pin Plastic Dual Small-Outline Package
Program/Erase Endurance C = 100 000 Cycles B = 10 000 Cycles
Speed Option 90 = 90 ns 100 = 100 ns 120 = 120 ns
Boot Code Selection Architecture T = Top Sector B = Bottom Sector Device Number / Description 8M Bits
POST OFFICE BOX 1443
* HOUSTON, TEXAS 77251-1443
3
PRODUCT PREVIEW
TMS29LF008T, TMS29LF008B 1048576 BY 8-BIT FLASH MEMORIES
SMJS846A - MAY 1997 - REVISED NOVEMBER 1997
logic symbol
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 21 20 19 18 17 16 15 14 8 7 36 6 5 4 3 2 1 40 13 37 12 10 22 24 9 0 FLASH MEMORY 1048 576 x 8
A
0 1048 575
19
PRODUCT PREVIEW
RY / BY RESET CE OE WE
G1 [PWR DWN] 1, 2 EN (READ) 1C3 (WRITE)
A, 3D 4 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 25 26 27 28 32 33 34 35
A, Z4
This symbol is in accordance with ANSI / IEEE Std 91-1984 and IEC Publication 617-12.
4
POST OFFICE BOX 1443
* HOUSTON, TEXAS 77251-1443
TMS29LF008T, TMS29LF008B 1048576 BY 8-BIT FLASH MEMORIES
SMJS846A - MAY 1997 - REVISED NOVEMBER 1997
block diagram
DQ0 - DQ7 RY / BY Buffer VCC VSS RY / BY Erase Voltage Generator Input/Output Buffers
WE
State Control
RESET Command Registers
PGM Voltage Generator
STB Data Latch
CE OE
Chip-Enable Output-Enable Logic
VCC Detector
Timer A d d r e s s L a t c h
Y-Decoder
Y-Gating
STB
A0 - A19
X-Decoder
Cell Matrix
POST OFFICE BOX 1443
* HOUSTON, TEXAS 77251-1443
5
PRODUCT PREVIEW
TMS29LF008T, TMS29LF008B 1048576 BY 8-BIT FLASH MEMORIES
SMJS846A - MAY 1997 - REVISED NOVEMBER 1997
operation
See Table 1 and Table 2 for the sector-address ranges of the TMS29LF008T/B. Table 1. Top-Boot Sector-Address Ranges
A19 SA18 SA17 SA16 SA15 SA14 SA13 SA12 SA11 SA10 SA9 SA8 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 A18 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 A17 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 A16 1 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 A15 1 1 1 0 X X X X X X X X X X X X X X X A14 1 0 0 X X X X X X X X X X X X X X X X A13 X 1 0 X X X X X X X X X X X X X X X X SECTOR SIZE 16K-Byte 8K-Byte 8K-Byte 32K-Byte 64K-Byte 64K-Byte 64K-Byte 64K-Byte 64K-Byte 64K-Byte 64K-Byte 64K-Byte 64K-Byte 64K-Byte 64K-Byte 64K-Byte 64K-Byte 64K-Byte 64K-Byte ADDRESS RANGE FC000H-FFFFFH FA000H-FBFFFH F8000H-F9FFFH F0000H-F7FFFH E0000H-EFFFFH D0000H-DFFFFH C0000H-CFFFFH B0000H-BFFFFH A0000H-AFFFFH 90000H-9FFFFH 80000H-8FFFFH 70000H-7FFFFH 60000H-6FFFFH 50000H-5FFFFH 40000H-4FFFFH 30000H-3FFFFH 20000H-2FFFFH 10000H-1FFFFH 00000H-0FFFFH
PRODUCT PREVIEW
SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0
The address range is A0-A19.
6
POST OFFICE BOX 1443
* HOUSTON, TEXAS 77251-1443
TMS29LF008T, TMS29LF008B 1048576 BY 8-BIT FLASH MEMORIES
SMJS846A - MAY 1997 - REVISED NOVEMBER 1997
operation (continued)
Table 2. Bottom-Boot Sector-Address Ranges
A19 SA18 SA17 SA16 SA15 SA14 SA13 SA12 SA11 SA10 SA9 SA8 SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 A18 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 A17 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 0 0 A16 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 A15 X X X X X X X X X X X X X X X 1 0 0 0 A14 X X X X X X X X X X X X X X X X 1 1 0 A13 X X X X X X X X X X X X X X X X 1 0 X SECTOR SIZE 64K-Byte 64K-Byte 64K-Byte 64K-Byte 64K-Byte 64K-Byte 64K-Byte 64K-Byte 64K-Byte 64K-Byte 64K-Byte 64K-Byte 64K-Byte 64K-Byte 64K-Byte 32K-Byte 8K-Byte 8K-Byte 16K-Byte ADDRESS RANGE F0000H-FFFFFH E0000H-EFFFFH D0000H-DFFFFH C0000H-CFFFFH B0000H-BFFFFH A0000H-AFFFFH 90000H-9FFFFH 80000H-8FFFFH 70000H-7FFFFH 60000H-6FFFFH 50000H-5FFFFH 40000H-4FFFFH 20000H-2FFFFH 10000H-1FFFFH 08000H-0FFFFH 06000H-07FFFH 04000H-05FFFH 00000H-03FFFH 30000H-3FFFFH
The address range is A0-A19.
See Table 3 for the operation modes of the TMS29LF008T/B. Table 3. Operation Modes
MODE Algorithm-selection mode FUNCTIONS CE VIL VIL 3 V power supply 3-V VIL Read Output disable Standby and write inhibit Write Temporary sector unprotect Verify sector protect Hardware reset VIL VIL VIH VIL X VIL X VIL VIL VIH X VIH X VIL X VIH VIH VIH X VIL X VIH X VIH A0 X X A0 X VIL X VIL A1 X X A1 X VIH X VIL A6 X X A6 X VIL X VID A9 X X A9 X VID X VIH VIH VIH VIH VIH VID VIH VIL OE VIL VIL WE VIH VIH A0 VIL VIH A1 VIL VIL A6 VIL VIL A9 VID VID RESET VIH VIH DQ0-DQ7 Manufacturer-Equivalent Code 01h (TMS29LF008) Device-Equivalent Code 3Eh (TMS29LF008T) Device-Equivalent Code 37h (TMS29LF008B) Data out Hi-Z Hi-Z Data in X Data out Hi-Z
Legend: VIL = Logic low VIH = Logic high VID = 12.0 0.5 V X can be VIL or VIH. See Table 5 for valid address and data during write.
POST OFFICE BOX 1443
* HOUSTON, TEXAS 77251-1443
7
PRODUCT PREVIEW
TMS29LF008T, TMS29LF008B 1048576 BY 8-BIT FLASH MEMORIES
SMJS846A - MAY 1997 - REVISED NOVEMBER 1997
read mode A logic-low signal applied to the CE and OE pins allows the output of the TMS29LF008T/B to be read. When two or more '29LF008T/B devices are connected in parallel, the output of any one device can be read without interference. The CE pin is for power control and must be used for device selection. The OE pin is for output control, and is used to gate the data output onto the bus from the selected device. The address-access time (tAVQV) is the delay from stable address to valid output data. The chip-enable (CE) access time (tELQV) is the delay from CE low and stable addresses to valid output data. The output-enable access time (tGLQV) is the delay from OE low to valid output data when CE equals logic low, and addresses are stable for at least the duration of tAVQV-tGLQV. standby mode ICC supply current is reduced by applying a logic-high level on CE and RESET to enter the standby mode. In the standby mode, the outputs are placed in the high-impedance state. Applying a CMOS logic-high level on CE and RESET reduces the current to 60 A. Applying a TTL logic-high level on CE and RESET reduces the current to 1 mA. If the '29LF008T/B is deselected during erasure or programming, the device continues to draw active current until the operation is complete. output disable
PRODUCT PREVIEW
When OE equals VIH or CE equals VIH, output from the device is disabled and the output pins (DQ0-DQ7) are placed in the high-impedance state. automatic-sleep mode The '29LF008T/B has a built-in feature called automatic-sleep mode to minimize device energy consumption which is independent of CE, WE, and OE, and is enabled when addresses remain stable for 300 ns. Typical sleep-mode current is 60 A. Sleep mode does not affect output data, which remains latched and available to the system.
algorithm selection
The algorithm-selection mode provides access to a binary code that matches the device with its proper programming and erase command operations. This mode is activated when VID (11.5 V to 12.5 V) is placed on address pin A9. Address pins A1 and A6 must be logic low. Two bytes of code are accessed by toggling address pin A0 from VIL to VIH. Address pins other than A0, A1, and A6 can be at logic low or at logic high. The algorithm-selection mode can also be read by using the command register, which is useful when VID is not available to be placed on address pin A9. Table 4 shows the binary algorithm-selection codes. Table 4. Algorithm-Selection Codes (3-V Single Power Supply)
CODE Manufacturerequivalent code TMS29LF008T TMS29LF008B Sector protection 01H 3EH 37H 01H DQ7 0 0 0 0 DQ6 0 0 0 0 DQ5 0 1 1 0 DQ4 0 1 1 0 DQ3 0 1 0 0 DQ2 0 1 1 0 DQ1 0 1 1 0 DQ0 1 0 1 1
A1 = VIL, A6 = VIL, CE = VIL, OE = VIL
8
POST OFFICE BOX 1443
* HOUSTON, TEXAS 77251-1443
TMS29LF008T, TMS29LF008B 1048576 BY 8-BIT FLASH MEMORIES
SMJS846A - MAY 1997 - REVISED NOVEMBER 1997
erasure and programming Erasure and programming of the '29LF008 are accomplished by writing a sequence of commands using standard microprocessor write timing. The commands are written to a command register and input to the command-state machine (CSM). The CSM interprets the command entered and initiates program, erase, suspend, and resume operations as instructed. The CSM acts as the interface between the write-state machine (WSM) and external-chip operations. The WSM controls all voltage generation, pulse generation, preconditioning, and verification of memory contents. Program and block-/chip-erase functions are fully automatic. Once the end of a program or erase operation has been reached, the device resets internally to the read mode. If VCC drops below the low-voltage-detect level (VLKO), any programming or erase operation is aborted and subsequent writes are ignored until the VCC level is greater than VLKO. The control pins must be logically correct to prevent unintentional command writes or programming or erasing. command definitions Device operating modes are selected by writing specific address and data sequences into the command register. Table 5 defines the valid command sequences. Writing incorrect address and data values or writing them in the incorrect sequence causes the device to reset to the read mode. The command register does not occupy an addressable memory location. The register is used to store the command sequence, along with the address and data needed by the memory array. Commands are written by setting CE = VIL, OE = VIH, and bringing WE from logic high to logic low. Addresses are latched on the falling edge of WE and data is latched on the rising edge of WE. Holding WE = VIL and toggling CE is an alternative method. See the switching characteristics of the write/erase/program-operations section for specific timing information. Table 5. Command Definitions
COMMAND Read/reset BUS CYCLES 1 3 1ST CYCLE ADDR DATA XXXXH 555H F0H AAH 2AAH 55H 555H F0H RA RD 3EH T 3 555H AAH 2AAH 55H 555H 90H 01H 37H B PD AAH AAH 2AAH 2AAH 55H 55H 555H SA 10H 30H 2ND CYCLE ADDR DATA 3RD CYCLE ADDR DATA 4TH CYCLE ADDR DATA 5TH CYCLE ADDR DATA 6TH CYCLE ADDR DATA
Algorithm go selection Program
4 6 6 1 1
555H 555H
AAH AAH AAH B0H 30H
2AAH 2AAH 2AAH
55H 55H 55H
555H 555H 555H
A0H 80H 80H
PA 555H 555H
Chip erase
Sector erase Sector-erase suspend Sector-erase resume
555H
XXXXH XXXXH
Erase suspend valid during sector-erase operation Erase resume valid only after erase suspend
LEGEND: RA = Address of the location to be read PA = Address of the location to be programmed SA = Address of the sector to be erased Addresses A13-A19 select 1 to 19 sectors. RD = Data to be read at selected address location PD = Data to be programmed at selected address location
POST OFFICE BOX 1443
* HOUSTON, TEXAS 77251-1443
9
PRODUCT PREVIEW
TMS29LF008T, TMS29LF008B 1048576 BY 8-BIT FLASH MEMORIES
SMJS846A - MAY 1997 - REVISED NOVEMBER 1997
read/reset command The read or reset mode is activated by writing either of the two read/reset command sequences into the command register. The device remains in this mode until another valid command sequence is input in the command register. Memory data is available in the read mode and can be read with standard microprocessor read-cycle timing. On power up, the device defaults to the read/reset mode. A read/reset command sequence is not required and memory data is available. algorithm-selection command The algorithm-selection command allows access to a binary code that matches the device with the proper programming and erase command operations. After writing the three-bus-cycle command sequence, the first byte of the algorithm-selection code can be read from address XX00h. The second byte of the code can be read from address XX01h (see Table 5). This mode remains in effect until another valid command sequence is written to the device. byte-program command Programming is a four-bus-cycle command sequence. The first three bus cycles put the device into the program-setup state. The fourth bus cycle loads the address location and the data to be programmed into the device. The addresses are latched on the falling edge of WE and the data is latched on the rising edge of WE in the fourth bus cycle. The rising edge of WE starts the program operation. The embedded programming function automatically provides needed voltage and timing to program and verify the cell margin. Any further commands written to the device during the program operation are ignored. Programming can be performed at any address location in any sequence. When erased, all bits are in a logic-high state. Logic lows are programmed into the device and only an erase operation can change bits from logic lows to logic highs. Attempting to program a 1 into a bit that has been programmed previously to a 0 causes the internal-pulse counter to exceed the pulse-count limit, which sets the exceed-time-limit indicator (DQ5) to a logic-high state. The automatic-programming operation is complete when the data on DQ7 is equivalent to the data written to this bit, at which time the device returns to the read mode and addresses are no longer latched. Figure 7 shows a flowchart of the typical device-programming operation. chip-erase command Chip erase is a six-bus-cycle command sequence. The first three bus cycles put the device into the erase-setup state. The next two bus cycles unlock the erase mode. The sixth bus cycle loads the chip-erase command. This command sequence is required to ensure that the memory contents are not erased accidentally. The rising edge of WE starts the chip-erase operation. Any further commands written to the device during the chip-erase operation are ignored. The embedded chip-erase function automatically provides voltage and timing needed to program and to verify all the memory cells prior to electrical erase. It then erases and verifies the cell margin automatically without programming the memory cells prior to erase. Figure 10 shows a flowchart of the typical chip-erase operation.
PRODUCT PREVIEW
10
POST OFFICE BOX 1443
* HOUSTON, TEXAS 77251-1443
TMS29LF008T, TMS29LF008B 1048576 BY 8-BIT FLASH MEMORIES
SMJS846A - MAY 1997 - REVISED NOVEMBER 1997
sector-erase command Sector-erase is a six-bus-cycle command sequence. The first three bus cycles put the device into the erase-setup state. The next two bus cycles unlock the erase mode and the sixth bus cycle loads the sector-erase command and the sector-address location to be erased. Any address location within the desired sector can be used. The addresses are latched on the falling edge of WE and the sector-erase command (30h) is latched on the rising edge of WE in the sixth bus cycle. After a delay of 80 s from the rising edge of WE, the sector-erase operation begins on the selected sector(s). Additional sectors can be selected to be erased concurrently during the sector-erase command sequence. For each additional sector to be selected for erase, another bus cycle is issued. The bus cycle loads the next sector-address location and the sector-erase command. The time between the end of the previous bus cycle and the start of the next bus cycle must be less than 100 s; otherwise, the new sector location is not loaded. A time delay of 100 s from the rising edge of the last WE starts the sector-erase operation. If there is a falling edge of WE within the 100 s time delay, the timer is reset. One to nineteen sector-address locations can be loaded in any sequence. The state of the delay timer can be monitored using the sector-erase delay indicator (DQ3). If DQ3 is at logic low, the time delay has not expired. See the operation status section for a description.
The embedded sector-erase function automatically provides needed voltage and timing to program and to verify all of the memory cells prior to electrical erase and then erases and verifies the cell margin automatically. Programming the memory cells prior to erase is not required. See the operation status section for a full description. Figure 12 shows a flowchart of the typical sector-erase operation. erase-suspend command The erase-suspend command (B0h) allows interruption of a sector-erase operation to read data from unaltered sectors of the device. Erase-suspend is a one-bus-cycle command. The addresses can be VIL or VIH and the erase-suspend command (B0h) is latched on the rising edge of WE. Once the sector-erase operation is in progress, the erase-suspend command requests the internal write-state machine to halt operation at predetermined breakpoints. The erase-suspend command is valid only during the sector-erase operation and is invalid during programming and chip-erase operations. The sector-erase delay timer expires immediately if the erase-suspend command is issued while the delay is active. After the erase-suspend command is issued, the device takes between 0.1 s and 15 s to suspend the operation. The toggle bit must be monitored to determine when the suspend has been executed. When the toggle bit stops toggling, data can be read from sectors that are not selected for erase. Reading from a sector selected for erase can result in invalid data. See the operation status section for a full description. Once the sector-erase operation is suspended, reading from or programming to a sector that is not being erased can be performed. This command is applicable only during sector-erase operation. Any other command written during erase-suspend mode to the suspended sector is ignored.
POST OFFICE BOX 1443
* HOUSTON, TEXAS 77251-1443
11
PRODUCT PREVIEW
Any command other than erase suspend (B0h) or sector erase (30h) written to the device during the sector-erase operation causes the device to exit the sector-erase mode and the contents of the sector(s) selected for erase are no longer valid. To complete the sector-erase operation, re-issue the sector-erase command sequence.
TMS29LF008T, TMS29LF008B 1048576 BY 8-BIT FLASH MEMORIES
SMJS846A - MAY 1997 - REVISED NOVEMBER 1997
erase-resume command The erase-resume command (30h) restarts a suspended sector-erase operation from the point where it was halted. Erase resume is a one-bus-cycle command. The addresses can be VIL or VIH and the erase-resume command (30h) is latched on the rising edge of WE. When an erase-suspend/erase-resume command combination is written, the internal-pulse counter (exceed timing limit) is reset. The erase-resume command is valid only in the erase-suspend state. After the erase-resume command is executed, the device returns to the valid sector-erase state and further writes of the erase-resume command are ignored. After the device has resumed the sector-erase operation, another erase-suspend command can be issued to the device.
operation status
The status of the device during an automatic-programming algorithm, chip-erase, or automatic-erase algorithm can be determined in three ways:
D D D
DQ7: Data polling DQ6: Toggle bit RY/ BY: Ready / busy bit
PRODUCT PREVIEW
status-bit definitions During operation of the automatic embedded program and erase functions, the status of the device can be determined by reading the data state of designated outputs. The data-polling bit (DQ7) and toggle bit (DQ6) require multiple successive reads to observe a change in the state of the designated output. Table 6 defines the values of the status flags. Table 6. Operation Status Flags
DEVICE OPERATION Programming Program/erase in auto-erase In progress Erase-suspend Erase suspend mode Program in erase suspend Programming Exceeded time limits Program/erase in auto erase Program in erase suspend Successful operation complete Programming complete Sector /chip erase complete Erase-sector address Non-erase sector address DQ7 DQ7 0 1 D DQ7 DQ7 0 DQ7 D 1 DQ6 T T No Tog D T T T T D 1 DQ5 0 0 0 D 0 1 1 1 D 1 DQ3 0 1 0 D 0 0 1 0 D 1 DQ2 No Tog T D 1 No Tog # No Tog D 1 RY/BY 0 0 1 1 0 0 0 0 1
1 T= toggle, D= data, No Tog= no toggle DQ4, DQ1, DQ0 are reserved for future use. DQ2 can be toggled when the sector address applied is an erasing sector. DQ2 cannot be toggled when the sector address applied is a non-erasing sector. DQ2 is used to determine which sectors are erasing and which are not. Status flags apply when outputs are read from the address of a non-erase-suspend operation. # If DQ5 is high (exceeded timing limits), successive reads from a problem sector causes DQ2 to toggle.
12
POST OFFICE BOX 1443
* HOUSTON, TEXAS 77251-1443
TMS29LF008T, TMS29LF008B 1048576 BY 8-BIT FLASH MEMORIES
SMJS846A - MAY 1997 - REVISED NOVEMBER 1997
data-polling (DQ7) The data-polling-status function outputs the complement of the data latched into the DQ7 data register while the write-state machine is engaged in a program or erase operation. The changing of data bit DQ7 from complement to true indicates the end of an operation. Data-polling is available only during programming, chip-erase, sector-erase, and sector-erase-timing delay. Data-polling is valid after the rising edge of WE in the last bus cycle of the command sequence loaded into the command register. Figure 14 shows a flowchart for data-polling. During a program operation, reading DQ7 outputs the complement of the DQ7 data to be programmed at the selected address location. Upon completion, reading DQ7 outputs the true DQ7 data loaded into the program-data register. During the erase operations, reading DQ7 outputs a logic low. Upon completion, reading DQ7 outputs a logic high. Also, data-polling must be performed at a sector address that is within a sector that is being erased. Otherwise, the status is invalid. When using data-polling, the address should remain stable throughout the operation. During a data-polling read, while OE is logic low, data bit DQ7 can change asynchronously. Depending on the read timing, the system can read valid data on DQ7, while other DQ pins are still invalid. A subsequent read of the device is valid. See Figure 15 for the data-polling timing diagram. toggle bit (DQ6) The toggle-bit status function outputs data on DQ6, which toggles between logic high and logic low while the write-state machine is engaged in a program or erase operation. When DQ6 stops toggling after two consecutive reads to the same address, the operation is complete. The toggle bit is available only during programming, chip erase, sector erase, and sector-erase-timing delay. Toggle-bit data is valid after the rising edge of WE in the last bus cycle of the command sequence loaded into the command register. Figure 16 shows a flowchart of the toggle-bit status-read algorithm. Depending on the read timing, DQ6 can stop toggling while other DQ pins are still invalid and a subsequent read of the device is valid. See Figure 17 for the toggle-bit timing diagram. exceed time limit (DQ5) The program and erase operations use an internal-pulse counter to limit the number of pulses applied. If the pulse-count limit is exceeded, DQ5 is set to a logic-high data state. This indicates that the program or erase operation has failed. DQ7 does not change from complemented data to true data and DQ6 does not stop toggling when read. To continue operation, the device must be reset. The exceed-time-limit condition occurs when attempting to program a logic-high state into a bit that has been programmed previously to a logic low. Only an erase operation can change bits from logic low to logic high. After reset, the device is functional and can be erased and reprogrammed. sector-load-timer (DQ3) The sector-load-timer status bit, DQ3, is used to determine whether the time to load additional sector addresses has expired. After completion of a sector-erase command sequence, DQ3 remains at a logic low for 100 s. This indicates that another sector-erase command sequence can be issued. If DQ3 is at a logic high, it indicates that the delay has expired and attempts to issue additional sector-erase commands are ignored. See the sector-erase command section for a description. The data-polling and toggle bit are valid during the 100-s time delay and can be used to determine if a valid sector-erase command has been issued. To ensure additional sector-erase commands have been accepted, the status of DQ3 should be read before and after each additional sector-erase command. If DQ3 is at a logic low on both reads, the additional sector-erase command was accepted.
POST OFFICE BOX 1443
* HOUSTON, TEXAS 77251-1443
13
PRODUCT PREVIEW
TMS29LF008T, TMS29LF008B 1048576 BY 8-BIT FLASH MEMORIES
SMJS846A - MAY 1997 - REVISED NOVEMBER 1997
toggle bit 2 (DQ2) The state of DQ2 determines whether the device is in algorithmic-erase mode or erase-suspend mode. DQ2 toggles if successive reads are issued to the erasing or erase-suspended sector, assuming in case of the latter that the device is in erase-suspend-read mode. It also toggles when DQ5 becomes a logic high due to timer-exceed limit and reads are issued to the failed sector. DQ2 does not toggle in any other sector due to DQ5 failure. When the device is in erase-suspend-program mode, successive reads from the non-erase-suspended sector causes a logic high on DQ2. ready/ busy bit (RY/ BY) The RY/ BY bit indicates when the device can accept new commands after performing algorithmic operations. If the RY/ BY (open-drain output) bit is low, the device is busy with either a program or erase operation and does not accept any other commands except for erase suspend. While it is in the erase-suspend mode, RY/ BY remains high. In program mode, the RY/ BY bit is valid (logic low) after the fourth WE pulse. In erase mode, it is valid after the sixth WE pulse. There is a delay period tbusy, after which the RY/ BY bit becomes valid. See Figure 24 for the timing waveform. Since the RY/ BY bit is an open-drain output, several such bits can be combined in parallel with a pullup resistor to VCC.
PRODUCT PREVIEW
hardware-reset bit (RESET) When the RESET pin is driven to a logic low, it forces the device out of the currently active mode and into a reset state. It also avoids bus contention by placing the outputs into the high-impedance state for the duration of the RESET pulse. During program or erase operation, if RESET is asserted to logic low, the RY/ BY bit remains at logic low until the reset operation is complete. Since this can take anywhere from 1 s to 20 s, the RY/ BY bit can be used to sense reset completion or the user can allow a maximum of 20 s. If RESET is asserted during read mode, then the reset operation is complete within 500 ns. See Figure 1 and Figure 2 for timing specifications. The RESET pin also can be used to drive the device into deep power-down (standby) mode by applying VSS 0.3 V to it. ICC4 reads <1 A typical, and 5 A maximum for CMOS inputs. Standby mode can be entered anytime, regardless of the condition of CE. Asserting RESET during program or erase can leave erroneous data in the address locations. These locations need to be updated after the device resumes normal operations. A minimum of 50 ns must be allowed after RESET goes high before a valid read can take place.
tRL = 500 ns RESET
20 s max RY/BY
Figure 1. Device Reset During a Program or Erase Operation
14
POST OFFICE BOX 1443
* HOUSTON, TEXAS 77251-1443
TMS29LF008T, TMS29LF008B 1048576 BY 8-BIT FLASH MEMORIES
SMJS846A - MAY 1997 - REVISED NOVEMBER 1997
hardware-reset bit (RESET) (continued)
tRL = 500 ns
RESET
RY/BY
0V
Figure 2. Device Reset During Read Mode temporary hardware-sector unprotect feature This feature temporarily enables both programming and erase operations on any combination of one to nineteen sectors that were previously protected. This feature is enabled using high voltage VID (11.5 V to 12.5 V) on the RESET pin and using standard command sequences. Normally, the device is delivered with all sectors unprotected. sector-protect programming The sector-protect programming mode is activated when A6, A0, and CE are at VIL, and address pin A9 and control pin OE are forced to VID. Address pin A1 is set to VIH.The sector-select address pins A13-A19 are used to select the sector to be protected. Address pins A0-A12 and I/O pins must be stable and can be either VIL or VIH. Once the addresses are stable, WE is pulsed low for 100 s, causing programming to begin on the falling edge of WE and to terminate on the rising edge of WE. Figure 18 is a flowchart of the sector-protect algorithm and Figure 19 shows a timing diagram of the sector-protect operation. Commands to program or erase a protected sector do not change the data contained in the sector. Attempts to program and erase a protected sector cause the data-polling bit (DQ7) and the toggle bit (DQ6) to operate from 2 ms to 100 ms and then return to valid data. sector-protect verify Verification of the sector-protection programming is activated when WE = VIH, OE = VIL, CE = VIL, and address pin A9 = VID. Address pins A0 and A6 are set to VIL, and A1 is set to VIH. The sector-address pins A13-A19 select the sector that is to be verified. The other addresses can be VIH or VIL. If the sector that was selected is protected, the DQs output 01h. If the sector is not protected, the DQs output 00h. Sector-protect verify can also be read using the algorithm-selection command. After issuing the three-bus-cycle command sequence, the sector-protection status can be read on DQ0. Set address pins A0 = VIL, A1 = VIH, and A6 = VIL, and then the sector address pins A13-A19 select the sector to be verified. The remaining addresses are set to VIL. If the sector selected is protected, DQ0 outputs a logic-high state. If the sector selected is not protected, DQ0 outputs a logic-low state. This mode remains in effect until another valid command sequence is written to the device. Figure 18 is a flowchart of the sector-protect algorithm and Figure 19 shows a timing diagram of the sector-protect operation.
POST OFFICE BOX 1443
* HOUSTON, TEXAS 77251-1443
15
PRODUCT PREVIEW
TMS29LF008T, TMS29LF008B 1048576 BY 8-BIT FLASH MEMORIES
SMJS846A - MAY 1997 - REVISED NOVEMBER 1997
sector unprotect Prior to sector unprotect, all sectors must be protected using the sector-protect programming mode. The sector unprotect is activated when address pin A9 and control pin OE are forced to VID. Address pins A1 and A6 are set to VIH while CE and A0 are set to VIL. The sector-select address pins A13- A19 can be VIL or VIH. All sectors are unprotected in parallel and once the inputs are stable, WE is pulsed low for 10 ms, causing the unprotect operation to begin on the falling edge of WE and to terminate on the rising edge of WE. Figure 20 is a flowchart of the sector-unprotect algorithm and Figure 21 shows a timing diagram of the sector-unprotect operation. sector-unprotect verify Verification of the sector unprotect is accomplished when WE = VIH, OE = VIL, CE =VIL, and A9 = VID, and then select the sector to be verified. Address pins A1 and A6 are set to VIH, and A0 is set to VIL. The other addresses can be VIH or VIL. If the sector selected is protected, the DQs output 01h. If the sector is not protected, the DQs output 00h. Sector unprotect can also be read using the algorithm-selection command. low VCC write lockout During power-up and power-down operations, write cycles are locked out for VCC less than VLKO. If VCC < VLKO, the command input is disabled and the device is reset to the read mode. On power up, if CE =VIL, WE = VIL, and OE = VIH, the device does not accept commands on the rising edge of WE. The device automatically powers up in the read mode. glitching Pulses of less than 5 ns (typical) on OE, WE, or CE do not issue a write cycle. power supply considerations Each device should have a 0.1-F ceramic capacitor connected between VCC and VSS to suppress circuit noise. Printed circuit traces to VCC should be appropriate to handle the current demand and minimize inductance.
PRODUCT PREVIEW
16
POST OFFICE BOX 1443
* HOUSTON, TEXAS 77251-1443
TMS29LF008T, TMS29LF008B 1048576 BY 8-BIT FLASH MEMORIES
SMJS846A - MAY 1997 - REVISED NOVEMBER 1997
absolute maximum ratings over ambient temperature range (unless otherwise noted)
Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.6 V to 7 V Input voltage range: All inputs except A9, CE, OE (see Note 2) . . . . . . . . . . . . . . . . . . . . - 0.6 V to VCC + 1 V A9, CE, OE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.6 V to 13.5 V Output voltage range (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.6 V to VCC + 1 V Ambient temperature range during read / erase / program, TA (L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 70C (E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 40C to 85C (Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 40C to 125C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65C to 150C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values are with respect to VSS. 2. The voltage on any input pin can undershoot to -2 V for periods less than 20 ns (see Figure 4). 3. The voltage on any input or output pin can overshoot to 7 V for periods less than 20 ns (see Figure 5).
recommended operating conditions
VCC VIH VIL VID VLKO TA Supply voltage High-level High level dc input voltage Low level dc input voltage Low-level Algorithm selection and sector-protect input voltage Low VCC lock-out voltage L version Ambient temperature E version Q version TTL CMOS TTL CMOS 2.7 2 VCC-0.5 -0.5 -0.5 11.5 2.3 0 -40 -40 3.6 VCC+0.5 VCC+0.5 0.8 0.8 12.5 2.5 70 85 125 C V V V V V
POST OFFICE BOX 1443
* HOUSTON, TEXAS 77251-1443
17
PRODUCT PREVIEW
MIN
MAX
UNIT
TMS29LF008T, TMS29LF008B 1048576 BY 8-BIT FLASH MEMORIES
SMJS846A - MAY 1997 - REVISED NOVEMBER 1997
electrical characteristics over recommended ranges of supply voltage and ambient temperature
PARAMETER VOH VOL II IO IID ICC1 ICC2 ICC3 ICC4 High level output voltage High-level Low-level output voltage Input current (leakage) Output current (leakage) High-voltage current (standby) VCC supply current (standby) TTL-input level CMOS-input level TTL-input level CMOS-input level TEST CONDITIONS VCC = VCC MIN, VCC = VCC MIN, IOH = -2.0 mA IOH = - 100 A MIN 0.85*VCC VCC-0.4 0.45 1 1 35 1 60 30 60 5 60 MAX UNIT V V A A A mA A mA mA A A
VCC = VCC MIN, IOL = 5.8 mA VCC = VCC MAX, VIN = VSS to VCC VO =VSS to VCC, CE = VIH A9 or CE or OE = VID MAX CE = VIH,VCC = VCC MAX CE = VCC 0.2, CE = VIL, OE = VIH CE = VIL, OE = VIH VCC = VCC MAX, RESET = VSS 0.3 V VCC = VCC MAX
VCC supply current (see Note 4 and Note 5) VCC supply current (see Note 6) VCC supply current (standby during reset)
PRODUCT PREVIEW
ICC5 Automatic sleep mode (see Note 5 and Note 7) VIH = VCC 0.3 V, VIL = VSS 0.3 V NOTES: 4. ICC current in the read mode, switching at 6 MHz 5. IOUT = 0 mA 6. ICC current while erase or program operation is in progress 7. Automatic sleep mode is entered when addresses remain stable for 300 ns.
capacitance over recommended ranges of supply voltage and ambient temperature
PARAMETER Ci1 Ci2 Co Input capacitance (All inputs except A9, CE, OE) Input capacitance (A9, CE, OE) Output capacitance TEST CONDITIONS VI = 0 V, VI = 0 V, VO = 0 V, f = 1 MHz f = 1 MHz f = 1 MHz MIN MAX 7.5 9 12 UNIT pF pF pF
18
POST OFFICE BOX 1443
* HOUSTON, TEXAS 77251-1443
TMS29LF008T, TMS29LF008B 1048576 BY 8-BIT FLASH MEMORIES
SMJS846A - MAY 1997 - REVISED NOVEMBER 1997
PARAMETER MEASUREMENT INFORMATION
0.1 mA IOL
1.35 V CL = 30 pF
Output Under Test (see Note A and Note B) - 0.1 mA IOH
2.7 V 1.35 V 0V NOTES: A. CL includes probe and fixture capacitance. B. The ac testing inputs are driven at 2.7 V for logic high and 0 V for logic low. Timing measurements are made at 1.35 V for logic high and 1.35 V for logic low on both inputs and outputs. Each device should have a 0.1-F ceramic capacitor connected between VCC and VSS as closely as possible to the device pins. 1.35 V
Figure 3. AC Test Output Load Circuit
20 ns 20 ns +0.8 V -0.5 V -2.0 V 20 ns
Figure 4. Maximum Negative Overshoot Waveform
20 ns VCC + 2.0 V VCC + 0.5 V 2.0 V 20 ns 20 ns
Figure 5. Maximum Positive Overshoot Waveform
POST OFFICE BOX 1443
* HOUSTON, TEXAS 77251-1443
19
PRODUCT PREVIEW
TMS29LF008T, TMS29LF008B 1048576 BY 8-BIT FLASH MEMORIES
SMJS846A - MAY 1997 - REVISED NOVEMBER 1997
PARAMETER MEASUREMENT INFORMATION switching characteristics over recommended ranges of supply voltage and ambient temperature, read-only operation
PARAMETER tc(R) ta(A) ta(E) ta(G) tdis(E) tdis(G) ten(E) ten(G) th(D) Cycle time, read Access time, address Access time, CE Access time, OE Disable time, CE to high impedance Disable time, OE to high impedance Enable time, CE to low impedance Enable time, OE to low impedance Hold time, output from address CE or OE change ALTERNATE SYMBOL tAVAV tAVQV tELQV tGLQV tEHQZ tGHQZ tELQX tGLQX tAXQX 0 0 0 '29LF008-90 MIN 90 90 90 40 30 30 0 0 0 MAX '29LF008-100 MIN 100 100 100 50 30 30 0 0 0 MAX '29LF008-120 MIN 120 120 120 55 40 40 MAX UNIT ns ns ns ns ns ns ns ns ns
PRODUCT PREVIEW
20
POST OFFICE BOX 1443
* HOUSTON, TEXAS 77251-1443
TMS29LF008T, TMS29LF008B 1048576 BY 8-BIT FLASH MEMORIES
SMJS846A - MAY 1997 - REVISED NOVEMBER 1997
switching characteristics over recommended ranges of supply voltage and ambient temperature, controlled by WE
PARAMETER tc(W) tsu(A) th(A) tsu(D) th(D) tsu(E) th(E) tw(WL) tw(WH) trec(R) Cycle time, write Setup time, address Hold time, address Setup time, data Hold time, data valid after WE high Setup time, CE Hold time, CE Pulse duration, WE low Pulse duration, WE high Recovery time, read before write Hold time, OE read Hold time, OE toggle, data Setup time, VCC Transition time, VID (see Note 8 and Note 9) Pulse duration, WE low (see Note 8) Pulse duration, WE low (see Note 9) Setup time, CE VID to WE (see Note 9) Setup time, CE VID to WE (see Note 8 and Note 9) tc(W)PR Cycle time, programming operation Write recovery time from RY / BY RESET low time RESET high time before read RESET to power-down time Program/erase valid to RY / BY delay tc(W)ER Cycle time, sector-erase operation Cycle time, chip-erase operation NOTES: 8. Sector protect 9. Sector-unprotect timing ALTERNATE SYMBOL tAVAV tAVWL tWLAX tDVWH tWHDX tELWL tEHWH tWLWH1 tWHWL tGHWL tWHGL1 tWHGL2 tVCEL tHVT tWLWH2 tWLWH3 tEHVWL tGHVWL tWHWH1 tRB tRL tRH tRPD tBUSY tWHWH2 tWHWH3 0 500 50 20 90 1 6 50 '29LF008-90 MIN 90 0 50 50 0 0 0 50 30 0 0 10 50 4 100 10 4 4 8 0 500 50 20 90 1 6 50 TYP MAX '29LF008-100 MIN 100 0 50 50 0 0 0 50 30 0 0 10 50 4 100 10 4 4 8 0 500 50 20 90 1 6 50 TYP MAX '29LF008-120 MIN 120 0 65 65 0 0 0 65 35 0 0 10 50 4 100 10 4 4 8 TYP MAX UNIT ns ns ns ns ns ns ns ns ns ns ns ns s s s ms s s s ns ns ns s ns s s
POST OFFICE BOX 1443
* HOUSTON, TEXAS 77251-1443
21
PRODUCT PREVIEW
TMS29LF008T, TMS29LF008B 1048576 BY 8-BIT FLASH MEMORIES
SMJS846A - MAY 1997 - REVISED NOVEMBER 1997
switching characteristics over recommended ranges of supply voltage and ambient temperature, controlled by CE
PARAMETER tc(W) tsu(A) th(A) tsu(D) th(D) tsu(W) th(W) tw(EL) tw(EH) trec(R) Cycle time, write Setup time, address Hold time, address Setup time, data Hold time, data Setup time, WE Hold time, WE Pulse duration, CE low Pulse duration, CE high Recovery time, read before write Setup time, OE th(C) Hold time, OE read Hold time, OE toggle, data Programming operation Cycle time, sector-erase operation Cycle time, chip-erase operation ALTERNATE SYMBOL tAVAV tAVEL tELAX tDVEH tEHDX tWLEL tEHWH tELEH1 tEHEL tGHEL tGLEL tEHGL1 tEHGL2 tEHEH1 tEHEH2 tEHEH3 '29LF008-90 MIN 90 0 50 50 0 0 0 50 30 0 0 0 10 8 1 6 50 TYP MAX '29LF008-100 MIN 100 0 50 50 0 0 0 50 30 0 0 0 10 8 1 6 50 TYP MAX '29LF008-120 MIN 120 0 65 65 0 0 0 65 35 0 0 0 10 8 1 6 50 TYP MAX UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns s s s
PRODUCT PREVIEW
22
POST OFFICE BOX 1443
* HOUSTON, TEXAS 77251-1443
TMS29LF008T, TMS29LF008B 1048576 BY 8-BIT FLASH MEMORIES
SMJS846A - MAY 1997 - REVISED NOVEMBER 1997
erase and program performance
PARAMETER Sector-erase time Program time Chip-programming time Erase/program cycles TEST CONDITIONS Excludes 00H programming prior to erasure Excludes system-level overhead Excludes system-level overhead 100 000 9 MIN TYP 1 9 6 1 000 000 MAX 15 3 600 50 UNIT s s s cycles
The internal algorithms allow for 2.5-ms byte-program time. DQ5 = 1 only after a byte takes the theoretical maximum time to program. A minimal number of bytes can require signficantly more programming pulses than the typical byte. The majority of the bytes program within one or two pulses. This is demonstrated by the typical and maximum programming time listed above. 25C, 3-V VCC, 100 000 cycles, typical pattern Under worst-case conditions: 90C, 2.7-V VCC, 100 000 cycles
latchup characteristics (see Note 10)
PARAMETER Input voltage with respect to VSS on all pins except I/O pins (including A9 and OE) Input voltage with respect to VSS on all I/O pins Current NOTE 10: Includes all pins except VCC test conditions: VCC = 3 V, one pin at a time MIN -1 -1 - 100 MAX 13 VCC + 1 100 UNIT V V mA
pin capacitance, all packages (see Note 11)
PARAMETER CIN COUT CIN2 Input capacitance Output capacitance Control pin capacitance TEST CONDITIONS VIN = 0 VOUT = 0 VIN = 0 TYP 6 8.5 8 MAX 7.5 12 10 UNIT pF pF pF
NOTE 11: Test conditions: TA = 25C, f = 1 MHz
data retention
PARAMETER Minimum pattern data retention time TEST CONDITIONS 150C 125C MIN 10 20 MAX UNIT Years
POST OFFICE BOX 1443
* HOUSTON, TEXAS 77251-1443
23
PRODUCT PREVIEW
TMS29LF008T, TMS29LF008B 1048576 BY 8-BIT FLASH MEMORIES
SMJS846A - MAY 1997 - REVISED NOVEMBER 1997
read operation
tAVAV Addresses Valid Addresses
tAVQV CE tEHQZ tELQV OE tGHQZ tGLQV
PRODUCT PREVIEW
WE
tGLQX tAXQX tELQX
DQ
Valid Data
Figure 6. AC Waveform for Read Operation
24
POST OFFICE BOX 1443
* HOUSTON, TEXAS 77251-1443
TMS29LF008T, TMS29LF008B 1048576 BY 8-BIT FLASH MEMORIES
SMJS846A - MAY 1997 - REVISED NOVEMBER 1997
write operation
Start
Write Bus Cycle 555H / AAH
Write Bus Cycle 2AAH / 55H
Write Bus Cycle 555H /A0H
Write Bus Cycle Program Address / Program Data
Poll Device Status
Operation Complete ?
No
Yes
No Next Address
Last Address ?
Yes End
Figure 7. Program Algorithm
POST OFFICE BOX 1443
* HOUSTON, TEXAS 77251-1443
25
PRODUCT PREVIEW
TMS29LF008T, TMS29LF008B 1048576 BY 8-BIT FLASH MEMORIES
SMJS846A - MAY 1997 - REVISED NOVEMBER 1997
write operation (continued)
tAVAV Addresses 555H tWLAX tAVWL CE tELWL tWHEH OE tGHWL tWLWH1 tWHDX tWHWL 2AAH 555H PA PA
PRODUCT PREVIEW
WE tWHWH1 tDVWH DQ AAH 55H A0H PD DQ7 DOUT
NOTES: A. PA = Address to be programmed B. PD = Data to be programmed C. DQ7 = Complement of data written to DQ7
Figure 8. AC Waveform for Program Operation
26
POST OFFICE BOX 1443
* HOUSTON, TEXAS 77251-1443
TMS29LF008T, TMS29LF008B 1048576 BY 8-BIT FLASH MEMORIES
SMJS846A - MAY 1997 - REVISED NOVEMBER 1997
write operation (continued)
Addresses
555H tAVEL tELEH
2AAH
555H
PA
PA
tELAX
CE tGHEL OE tDVEH tWLEL WE tEHDX DQ AAH 55H A0H PD DQ7 DOUT tEHWH tWHWH1 tEHEL
NOTES: A. PA = Address to be programmed B. PD = Data to be programmed C. DQ7 = Complement of data written to DQ7
Figure 9. Alternate CE-Controlled Write Operation
POST OFFICE BOX 1443
* HOUSTON, TEXAS 77251-1443
27
PRODUCT PREVIEW
TMS29LF008T, TMS29LF008B 1048576 BY 8-BIT FLASH MEMORIES
SMJS846A - MAY 1997 - REVISED NOVEMBER 1997
chip-erase operation
Start
Write Bus Cycle 555H / AAH
Write Bus Cycle 2AAH /55H
Write Bus Cycle 555H / 80H
Write Bus Cycle 555H /AAH
PRODUCT PREVIEW
Write Bus Cycle 2AAH / 55H
Write Bus Cycle 555H /10H
Poll Device Status
Operation Complete ?
No
Yes End
Figure 10. Chip-Erase Algorithm
28
POST OFFICE BOX 1443
* HOUSTON, TEXAS 77251-1443
TMS29LF008T, TMS29LF008B 1048576 BY 8-BIT FLASH MEMORIES
SMJS846A - MAY 1997 - REVISED NOVEMBER 1997
chip-erase operation (continued)
tAVAV Addresses 555H 555H 2AAH tWLAX tAVWL CE tELWL tWHEH OE tWHDX tGHWL tWHWL tWLWH1 WE tWHWH3 tDVWH DQ 80H AAH 55H 10H DQ7=0 DOUT=FFH 555H VA
NOTES: A. VA = any valid address B. Figure details the last four bus cycles in a six-bus-cycle operation.
Figure 11. AC Waveform for Chip-Erase Operation
POST OFFICE BOX 1443
* HOUSTON, TEXAS 77251-1443
29
PRODUCT PREVIEW
TMS29LF008T, TMS29LF008B 1048576 BY 8-BIT FLASH MEMORIES
SMJS846A - MAY 1997 - REVISED NOVEMBER 1997
sector-erase operation
Start
Write Bus Cycle 555H / AAH
Write Bus Cycle 2AAH / 55H
Write Bus Cycle 555H / 80H
Write Bus Cycle 555H/AAH
PRODUCT PREVIEW
Write Bus Cycle 2AAH / 55H
Write Bus Cycle Sector Address / 30H
No DQ3 = 0 ?
Yes Yes Load Additional Sectors ? No Poll Device Status
No
Operation Complete ? Yes End
Figure 12. Sector-Erase Algorithm
30
POST OFFICE BOX 1443
* HOUSTON, TEXAS 77251-1443
TMS29LF008T, TMS29LF008B 1048576 BY 8-BIT FLASH MEMORIES
SMJS846A - MAY 1997 - REVISED NOVEMBER 1997
sector-erase operation (continued)
tAVAV Addresses 555H tWLAX tAVWL CE tELWL tWHEH OE tGHWL tWLWH1 WE tWHWH2 tDVWH DQ 80H AAH 55H 30H DQ7=0 DOUT=FFH tWHDX tWHWL 555H 2AAH SA SA
NOTES: A. SA = Sector address to be erased B. Figure details the last four bus cycles in a six-bus-cycle operation.
Figure 13. AC Waveform for Sector-Erase Operation
POST OFFICE BOX 1443
* HOUSTON, TEXAS 77251-1443
31
PRODUCT PREVIEW
TMS29LF008T, TMS29LF008B 1048576 BY 8-BIT FLASH MEMORIES
SMJS846A - MAY 1997 - REVISED NOVEMBER 1997
data-polling operation
Start
Read DQ0 - DQ7 Addr = VA
DQ7 = Data ?
Yes
No No DQ5 = 1 ?
PRODUCT PREVIEW
Yes Read DQ0 - DQ7 Addr = VA
DQ7 = Data ?
Yes
No Fail Pass
NOTES: A. Polling status bits DQ7 and DQ5 may change asynchronously. Read DQ7 after DQ5 changes states. B. VA = Program address for byte-programming = Selected sector address for sector erase = Any valid address for chip erase
Figure 14. Data-Polling Algorithm
32
POST OFFICE BOX 1443
* HOUSTON, TEXAS 77251-1443
TMS29LF008T, TMS29LF008B 1048576 BY 8-BIT FLASH MEMORIES
SMJS846A - MAY 1997 - REVISED NOVEMBER 1997
data-polling operation (continued)
Addresses tAVQV tELQV CE tGLQV OE tWHGL1 WE tGHQX tWHWH1, 2, or 3 DQ NOTES: A. B. C. D. DIN DIN DQ7 DOUT AIN = = = = DQ7 DQ7 DQ7 DOUT tGHQZ tAXQX AIN AIN tAVQV tELQV AIN
tGLQV
Last command data written to the device Complement of data written to DQ7 Valid data output Valid address for byte-program, sector-erase, or chip-erase operation
Figure 15. AC Waveform for Data-Polling Operation
POST OFFICE BOX 1443
* HOUSTON, TEXAS 77251-1443
33
PRODUCT PREVIEW
TMS29LF008T, TMS29LF008B 1048576 BY 8-BIT FLASH MEMORIES
SMJS846A - MAY 1997 - REVISED NOVEMBER 1997
toggle-bit operation
Start
Read DQ0 - DQ7 Addr = VA
Read DQ0 - DQ7 Addr = VA
DQ6 = Toggle ?
No
PRODUCT PREVIEW
Yes No DQ5 = 1 ?
Yes Read DQ0 - DQ7
DQ6 = Toggle ?
No
Yes Fail Pass
NOTE A: Polling status bits DQ6 and DQ5 can change asynchronously. Read DQ6 after DQ5 changes states.
Figure 16. Toggle-Bit Algorithm
34
POST OFFICE BOX 1443
* HOUSTON, TEXAS 77251-1443
TMS29LF008T, TMS29LF008B 1048576 BY 8-BIT FLASH MEMORIES
SMJS846A - MAY 1997 - REVISED NOVEMBER 1997
toggle-bit operation (continued)
Addresses AIN
tELQV CE
tAVQV tELQV
tGLQV tGLQV OE
tWHGL2 WE tWHWH1, 2 or 3
DQ
DIN DQ6 = TOGGLE DQ6 = TOGGLE DQ6 = TOGGLE DQ6 = STOP TOGGLE
DOUT
NOTES: A. B. C. D.
DIN DQ6 DOUT AIN
= = = =
Last command data written to the device Toggle bit output Valid data output Valid address for byte-program, sector-erase, or chip-erase operation
Figure 17. AC Waveforms for Toggle-Bit Operation
POST OFFICE BOX 1443
* HOUSTON, TEXAS 77251-1443
35
PRODUCT PREVIEW
TMS29LF008T, TMS29LF008B 1048576 BY 8-BIT FLASH MEMORIES
SMJS846A - MAY 1997 - REVISED NOVEMBER 1997
sector-protect operation
Start
Select Sector Address A13 - A19
X=1
OE and A9 = VID, CE, A0, A6 = VIL A1 = VIH
Apply One 100-s Pulse
PRODUCT PREVIEW
X = X+1
CE, OE, A0, A6 = VIL, A1 = VIH, A9 = VID
Read Data No
X = 25 ?
No Data = 01H ? Yes
Yes
Sector Protect Failed
Protect Additional Sectors ? No A9 = VIH or VIL Write Reset Command
Yes
End
Figure 18. Sector-Protect Algorithm
36
POST OFFICE BOX 1443
* HOUSTON, TEXAS 77251-1443
TMS29LF008T, TMS29LF008B 1048576 BY 8-BIT FLASH MEMORIES
SMJS846A - MAY 1997 - REVISED NOVEMBER 1997
sector-protect operation (continued)
A13 - A19 VID A9 tHVT A6 tAVQV Sector Address Sector Address
A1
A0
CE VID OE tHVT WE tGLQV DQ DOUT tGHVWL tWLWH2 tHVT
NOTE A: DOUT = 00H if selected sector is not protected, 01H if the sector is protected
Figure 19. AC Waveform for Sector-Protect Operation
POST OFFICE BOX 1443
* HOUSTON, TEXAS 77251-1443
37
PRODUCT PREVIEW
TMS29LF008T, TMS29LF008B 1048576 BY 8-BIT FLASH MEMORIES
SMJS846A - MAY 1997 - REVISED NOVEMBER 1997
sector-unprotect operation
Start
Protect All Sectors
X=1
OE, A9 = VID, CE, A0 = VIL, A6, A1 = VIH
Apply One 10-ms Pulse CE, OE, A0 = VIL, A6, A1 = VIH, A9 = VID
PRODUCT PREVIEW
X = X+1
Select Sector Address
Read Data NO
X = 1000 ?
NO Data = 00H ? YES
Next Sector Address
YES
Sector Unprotect Failed
Last Sector ? YES A9 = VIH or VIL Write Reset Command
NO
End
Figure 20. Sector-Unprotect Algorithm
38
POST OFFICE BOX 1443
* HOUSTON, TEXAS 77251-1443
TMS29LF008T, TMS29LF008B 1048576 BY 8-BIT FLASH MEMORIES
SMJS846A - MAY 1997 - REVISED NOVEMBER 1997
sector-unprotect operation (continued)
A13 - A19 VID A9 tHVT A6 tAVQV Sector Address
A1
A0
CE VID OE tHVT tWLWH3 WE tGLQV DQ NOTE A: DOUT = 00H if selected sector is not protected, 01H if the sector is protected DOUT tGHVWL tHVT
Figure 21. AC Waveform for Sector-Unprotect Operation
POST OFFICE BOX 1443
* HOUSTON, TEXAS 77251-1443
39
PRODUCT PREVIEW
TMS29LF008T, TMS29LF008B 1048576 BY 8-BIT FLASH MEMORIES
SMJS846A - MAY 1997 - REVISED NOVEMBER 1997
temporary sector-unprotect operation
Start
RESET = VID (see Note A) Perform Erase or Program Operations
RESET = VIH
Temporary SectorGroup-Unprotect Completed (see Note B) NOTES: A. All protected sectors unprotected B. All previously protected sectors are protected once again
PRODUCT PREVIEW
Figure 22. Temporary Sector-Unprotect Algorithm
12 V RESET
5V
CE
WE
tVLHT
Program or Erase Command Sequence
RY / BY
Figure 23. Temporary Sector-Unprotect Timing Diagram
40
POST OFFICE BOX 1443
* HOUSTON, TEXAS 77251-1443
TMS29LF008T, TMS29LF008B 1048576 BY 8-BIT FLASH MEMORIES
SMJS846A - MAY 1997 - REVISED NOVEMBER 1997
PARAMETER MEASUREMENT INFORMATION
CE
The Rising Edge of the Last WE Signal WE
Entire Programming or Erase Operations RY / BY
tBUSY
Figure 24. RY/ BY Timing Diagram During Program/Erase Operations
POST OFFICE BOX 1443
* HOUSTON, TEXAS 77251-1443
41
PRODUCT PREVIEW
TMS29LF008T, TMS29LF008B 1048576 BY 8-BIT FLASH MEMORIES
SMJS846A - MAY 1997 - REVISED NOVEMBER 1997
MECHANICAL DATA
DCD (R-PDSO-G**)
40 PIN SHOWN
PLASTIC DUAL SMALL-OUTLINE PACKAGE
NO. OF PINS ** 1 40 40
A MAX 0.402 (10,20) 0.476 (12,10) MIN 0.385 (9,80) 0.469 (11,90)
0.020 (0,50) A 0.012 (0,30) 0.004 (0,10) 21 20
48
0.008 (0,21) M
PRODUCT PREVIEW
0.728 (18,50) 0.720 (18,30) 0.795 (20,20) 0.780 (19,80) 0.006 (0,15) NOM
0.041 (1,05) 0.037 (0,95)
0.047 (1,20) MAX
Seating Plane 0.028 (0,70) 0.020 (0,50) 0.004 (0,10)
0.010 (25,00) NOM
4073307/B 07/96 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice.
42
POST OFFICE BOX 1443
* HOUSTON, TEXAS 77251-1443
IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof.
Copyright (c) 1998, Texas Instruments Incorporated

▲Up To Search▲

Price & Availability of SMJS846A

	To Download SMJS846A Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .