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TM124MBK36C, TM124MBK36S 1048576 BY 36-BIT TM248NBK36C, TM248NBK36S 2097152 BY 36-BIT DYNAMIC RAM MODULE
SMMS138B - MARCH 1992 - REVISED JUNE 1995
D D D D D D D D D
Organization TM124MBK36C . . . 1 048 576 x 36 TM248NBK36C . . . 2 097152 x 36 Single 5-V Power Supply (10% Tolerance) 72-pin Leadless Single In-Line Memory Module (SIMM) TM124MBK36C - Utilizes Eight 4-Megabit DRAMs in Plastic Small-Outline J-Lead (SOJ) Packages and Two 4-Megabit Quad-CAS DRAMs in Plastic SOJ Packages TM248NBK36C - Utilizes Sixteen 4-Megabit DRAMs in Plastic SOJ Packages and Four 4-Megabit Quad-CAS DRAMs in Plastic SOJ Packages Long Refresh Period 16 ms (1024 Cycles) All Inputs, Outputs, Clocks Fully TTL Compatible 3-State Output Common CAS Control for Nine Common Data-In and Data-Out Lines, in Four Blocks
D D D
Enhanced Page Mode Operation With CAS-Before-RAS ( CBR), RAS-Only, and Hidden Refresh Presence Detect Performance Ranges:
ACCESS TIME tRAC (MAX) 60 ns 70 ns 80 ns 60 ns 70 ns 80 ns ACCESS ACCESS READ TIME TIME OR tAA tCAC WRITE CYCLE (MAX) (MAX) (MIN) 30 ns 15 ns 110 ns 35 ns 18 ns 130 ns 40 ns 20 ns 150 ns 30 ns 15 ns 110 ns 35 ns 18 ns 130 ns 40 ns 20 ns 150 ns
D D D D
124MBK36C-60 124MBK36C-70 124MBK36C-80 248NBK36C-60 248NBK36C-70 248NBK36C-80
Low Power Dissipation Operating Free-Air-Temperature Range 0C to 70C Gold-Tabbed Versions Available: - TM124MBK36C - TM248NBK36C Tin-Lead (Solder) Tabbed Versions - TM124MBK36S - TM248NBK36S
description TM124MBK36C
The TM124MBK36C is a dynamic random-access memory (DRAM) organized as four times 1 048 576 x 9 (bit 9 is generally used for parity) in a 72-pin leadless single in-line memory module (SIMM). The SIMM is composed of eight TMS44400DJ, 1 048 576 x 4-bit DRAMs, each in 20/26-lead plastic small-outline J-lead packages (SOJs), and two TMS44460DJ, 1 048 576 x 4-bit Quad-CAS DRAMs, in 24/26-lead plastic SOJs mounted on a substrate with decoupling capacitors. Each TMS44400DJ and TMS44460DJ is described in the TMS44400 and TMS44460 data sheets, respectively. The TM124MBK36C is available in the single-sided BK leadless module for use with sockets. The TM124MBK36C features RAS access times of 60 ns, 70 ns, and 80 ns. This device is characterized for operation from 0C to 70C.
Part numbers in this data sheet are for the gold-tabbed version; the information applies to both gold-tabbed and solder-tabbed versions.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright (c) 1995, Texas Instruments Incorporated
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TM124MBK36C, TM124MBK36S 1048576 BY 36-BIT TM248NBK36C, TM248NBK36S 2097152 BY 36-BIT DYNAMIC RAM MODULE
SMMS138B - MARCH 1992 - REVISED JUNE 1995
TM248NBK36C
The TM248NBK36C is a DRAM organized as four times 2 097 152 x 9 (bit 9 is generally used for parity) in a 72-pin leadless SIMM) The SIMM is composed of sixteen TMS44400DJ, 1 048 576 x 4-bit DRAMs, each in 20/26-lead plastic SOJs, and four TMS44460DJ, 1 048 576 x 4-bit Quad-CAS DRAMs, in 24/26-lead plastic SOJs mounted on a substrate with decoupling capacitors. Each TMS44400DJ and TMS44460DJ is described in the TMS44400 or TMS44460 data sheet, respectively. The TM248NBK36C is available in the double-sided BK leadless module for use with sockets. The TM248NBK36C features RAS access times of 60 ns, 70 ns, and 80 ns. This device is rated for operation from 0C to 70C.
operation
TM124MBK36C The TM124MBK36C operates as eight TMS44400DJs and two TMS44460DJs connected as shown in the functional block diagram and Table 1. The common I/O feature dictates the use of early write cycles to prevent contention on D and Q. TM248NBK36C The TM248NBK36C operates as sixteen TMS44400DJs and four TMS44460DJs connected as shown in the functional block diagram and Table 1. The common I/O feature dictates the use of early write cycles to prevent contention on D and Q.
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TM124MBK36C, TM124MBK36S 1048576 BY 36-BIT TM248NBK36C, TM248NBK36S 2097152 BY 36-BIT DYNAMIC RAM MODULE
SMMS138B - MARCH 1992 - REVISED JUNE 1995
BK SINGLE IN-LINE MODULE (TOP VIEW)
TM124MBK36C (SIDE VIEW)
TM248NBK36C (SIDE VIEW)
VSS DQ0 DQ18 DQ1 DQ19 DQ2 DQ20 DQ3 DQ21 VCC NC A0 A1 A2 A3 A4 A5 A6 NC DQ4 DQ22 DQ5 DQ23 DQ6 DQ24 DQ7 DQ25 A7 NC VCC A8 A9 RAS3 RAS2 DQ26 DQ8 DQ17 DQ35 VSS CAS0 CAS2 CAS3 CAS1 RAS0 RAS1 NC W NC DQ9 DQ27 DQ10 DQ28 DQ11 DQ29 DQ12 DQ30 DQ13 DQ31 VCC DQ32 DQ14 DQ33 DQ15 DQ34 DQ16 NC PD1 PD2 PD3 PD4 NC VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
PIN NOMENCLATURE A0 - A9 CAS0 - CAS3 DQ0 - DQ35 NC PD1 - PD4 RAS0 - RAS3 VCC VSS W Address Inputs Column-Address Strobe Data In / Data Out No Connection Presence Detects Row-Address Strobe 5-V Supply Ground Write Enable
PRESENCE DETECT SIGNAL (PIN) 80 ns TM124MBK36C 70 ns 60 ns 80 ns TM248NBK36C 70 ns 60 ns PD1 (67) VSS VSS VSS NC NC NC PD2 (68) VSS VSS VSS NC NC NC PD3 (69) NC VSS NC NC VSS NC PD4 (70) VSS NC NC VSS NC NC
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TM124MBK36C, TM124MBK36S 1048576 BY 36-BIT TM248NBK36C, TM248NBK36S 2097152 BY 36-BIT DYNAMIC RAM MODULE
SMMS138B - MARCH 1992 - REVISED JUNE 1995
Table 1. Connection Table
DATA BLOCK DQ0 - DQ7 DQ8 DQ9 - DQ16 DQ17 DQ18 - DQ25 DQ26 DQ27 - DQ34 DQ35 RASx SIDE 1 RAS0 RAS0 RAS0 RAS0 RAS2 RAS2 RAS2 RAS2 SIDE 2 RAS1 RAS1 RAS1 RAS1 RAS3 RAS3 RAS3 RAS3 CASx CAS0 CAS0 CAS1 CAS1 CAS2 CAS2 CAS3 CAS3
Side 2 applies to the TM248NBK36C only.
single-in-line memory module and components
PC substrate: 1,27 0,1 mm (0.05 inch) nominal thickness; 0.005 inch/inch maximum warpage Bypass capacitors: Multilayer ceramic Contact area for TM124MBK36C and TM248NBK36C: Nickel plate and gold plate over copper Contact area for TM124MBK36S and TM248NBK36S: Nickel plate and tin-lead over copper
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functional block diagram (for TM124MBK36C and TM248NBK36C, Side 1)
10 RAS2
A0 - A9 RAS0 W CAS0
CAS1 10 1M x 4 A0 - A9 RAS W CAS OE DQ1 - DQ4 10 1M x 4 A0 - A9 RAS W CAS OE DQ1 - DQ4
CAS2 10 1M x 4 A0 - A9 RAS W CAS OE DQ1 - DQ4
CAS3 10 1M x 4 A0 - A9 RAS W CAS OE DQ1 - DQ4
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DQ0 - DQ3 10
DQ9 - DQ12 10
DQ18 - DQ21 10
DQ27 - DQ30
10
1M x 4 A0 - A9 RAS W CAS OE DQ1 - DQ4
DQ4 - DQ7 10
1M x 4 A0 - A9 RAS W CAS OE DQ1 - DQ4 1M x 4 A0 - A9 RAS W CAS2 CAS1 OE DQ1 DQ2
DQ13 - DQ16
1M x 4 A0 - A9 RAS W CAS OE DQ1 - DQ4
DQ22 - DQ25 10
1M x 4 A0 - A9 RAS W CAS OE DQ1 - DQ4
TM124MBK36C, TM124MBK36S 1048576 BY 36-BIT TM248NBK36C, TM248NBK36S 2097152 BY 36-BIT DYNAMIC RAM MODULE
DQ31 - DQ34
DQ8 DQ17
1M x 4 A0 - A9 RAS W CAS2 CAS1 OE DQ1 DQ2
SMMS138B - MARCH 1992 - REVISED JUNE 1995
DQ26 DQ35
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SMMS138B - MARCH 1992 - REVISED JUNE 1995
TM124MBK36C, TM124MBK36S 1097152 BY 36-BIT TM248NBK36C, TM248NBK36S 2097152 BY 36-BIT DYNAMIC RAM MODULE
functional block diagram (for TM248NBK36C, Side 2)
10 RAS3
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Template Release Date: 7-11-94
A0-A9 RAS1 W CAS0
CAS1 10 1M x 4 A0-A9 RAS W CAS OE DQ1- DQ4 10 1M x 4 A0 - A9 RAS W CAS OE DQ1 - DQ4
CAS2 10 1M x 4 A0 - A9 RAS W CAS OE DQ1 - DQ4
CAS3 10 1M x 4 A0 - A9 RAS W CAS OE DQ1 - DQ4
DQ0 - DQ3 10
DQ9 - DQ12 10
DQ18 - DQ21 10
DQ27 - DQ30
10
1M x 4 A0 - A9 RAS W CAS OE DQ1 - DQ4
DQ4- DQ7 10
1M x 4 A0 - A9 RAS W CAS OE DQ1 - DQ4 1M x 4 A0 - A9 RAS W CAS2 CAS1 OE DQ1 DQ2
DQ13 - DQ16
1M x 4 A0 - A9 RAS W CAS OE DQ1 - DQ4
DQ22 - DQ25 10
1M x 4 A0 - A9 RAS W CAS OE DQ1 - DQ4
DQ31 - DQ34
DQ8 DQ17
1M x 4 A0 - A9 RAS W CAS2 CAS1 OE DQ1 DQ2
DQ26 DQ35
TM124MBK36C, TM124MBK36S 1048576 BY 36-BIT TM248NBK36C, TM248NBK36S 2097152 BY 36-BIT DYNAMIC RAM MODULE
SMMS138B - MARCH 1992 - REVISED JUNE 1995
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range on VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 1 V to 7 V Supply voltage range on any pin (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 1 V to 7 V Short-circuit output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 W Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 70C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 55C to 125C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to VSS.
recommended operating conditions
MIN VCC VIH VIL TA Supply voltage High-level input voltage Low-level input voltage (see Note 2) Operating free-air temperature 4.5 2.4 -1 0 NOM 5 MAX 5.5 6.5 0.8 70 UNIT V V V C
NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used for logic-voltage levels only.
electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER VOH VOL II IO ICC1 High-level output voltage Low-level output voltage Input current (leakage) Output current (leakage) Read- or write-cycle current (see Note 3) TEST CONDITIONS IOH = - 5 mA IOL = 4.2 mA VCC = 5.5 V, VI = 0 V to 6.5 V, All other pins = 0 V to VCC VCC = 5.5 V, CAS high VCC = 5.5 V, VO = 0 V to VCC, '124MBK36C-60 MIN 2.4 0.4 10 10 1050 MAX '124MBK36C-70 MIN 2.4 0.4 10 10 900 MAX '124MBK36C-80 MIN 2.4 0.4 10 10 800 MAX UNIT V V A A mA
Minimum cycle
ICC2
Standby current
VIH = 2.4 V (TTL), after 1 memory cycle, RAS and CAS high VIH = VCC - 0.2 V (CMOS), after 1 memory cycle, RAS and CAS high VCC = 5.5 V, Minimum cycle, RAS cycling, CAS high (RAS only), RAS low after CAS low (CBR) VCC = 5.5 V, RAS low, tPC = Minimum, CAS cycling
20
20
20
mA
10
10
10
mA
ICC3
Average refresh current (RAS only or CBR) (see Note 3) Average page current (see Note 4)
1050
900
800
mA
ICC4
900
800
700
mA
NOTES: 3. Measured with a maximum of one address change while RAS = VIL 4. Measured with a maximum of one address change while CAS = VIH
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TM124MBK36C, TM124MBK36S 1048576 BY 36-BIT TM248NBK36C, TM248NBK36S 2097152 BY 36-BIT DYNAMIC RAM MODULE
SMMS138B - MARCH 1992 - REVISED JUNE 1995
electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER VOH VOL II IO ICC1 High-level output voltage Low-level output voltage Input current (leakage) Output current (leakage) Read or write cycle current (see Note 3) TEST CONDITIONS IOH = - 5 mA IOL = 4.2 mA VCC = 5.5 V, VI = 0 V to 6.5 V, All other pins = 0 V to VCC VCC = 5.5 V, CAS high VCC = 5.5 V, VO = 0 V to VCC, '248NBK36C-60 MIN 2.4 0.4 20 20 1070 MAX '248NBK36C-70 MIN 2.4 0.4 20 20 920 MAX '248NBK36C-80 MIN 2.4 0.4 20 20 820 MAX UNIT V V A A mA
Minimum cycle
ICC2
Standby current
VIH = 2.4 V (TTL), after 1 memory cycle, RAS and CAS high VIH = VCC - 0.2 V (CMOS), after 1 memory cycle, RAS and CAS high VCC = 5.5 V, Minimum cycle, RAS cycling, CAS high (RAS only), RAS low after CAS low (CBR) VCC = 5.5 V, RAS low, tPC = Minimum, CAS cycling
40
40
40
mA
20
20
20
mA
ICC3
Average refresh current (RAS only or CBR) (see Note 3) Average page current (see Note 4)
2100
1800
1600
mA
ICC4
920
820
720
mA
NOTES: 3. Measured with a maximum of one address change while RAS = VIL 4. Measured with a maximum of one address change while CAS = VIH
capacitance over recommended ranges of supply voltage and operating free-air temperature, f = 1 MHz (see Note 5)
PARAMETER Ci(A) Ci(R) Ci(C) Ci(W) Co(DQ) Input capacitance, A0 - A9 Input capacitance, RAS inputs Input capacitance, CAS inputs Input capacitance, W Output capacitance on DQ pins '124MBK36C MIN MAX 50 35 21 70 7 '248NBK36C MIN MAX 100 35 42 140 14 UNIT pF pF pF pF pF
NOTE 5: VCC equal to 5 V 0.5 V and the bias on pins under test is 0 V.
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TM124MBK36C, TM124MBK36S 1048576 BY 36-BIT TM248NBK36C, TM248NBK36S 2097152 BY 36-BIT DYNAMIC RAM MODULE
SMMS138B - MARCH 1992 - REVISED JUNE 1995
switching characteristics over recommended ranges of supply voltage and operating free-air temperature
PARAMETER tCAC tAA tRAC tCPA tCLZ tOFF Access time from CAS low Access time from column-address Access time from RAS low Access time from column precharge CAS to output in low Z Output disable time after CAS high (see Note 6) 0 0 15 '124MBK36C-60 '248NBK36C-60 MIN MAX 15 30 60 35 0 0 18 '124MBK36C-70 '248NBK36C-70 MIN MAX 18 35 70 40 0 0 20 '124MBK36C-80 '248NBK36C-80 MIN MAX 20 40 80 45 ns ns ns ns ns ns UNIT
NOTE 6: tOFF is specified when the output is no longer driven.
timing requirements over recommended ranges of supply voltage and operating free-air temperature
'124MBK36C-60 '248NBK36C-60 MIN tRC tRWC tPC tRASP tRAS tCAS tCP tRP tWP tASC tASR tDS tRCS tCWL tRWL tWCS tWSR tCAH tDHR tDH tAR tCLCH tRAH tRCH tRRH Cycle time, random read or write (see Note 7) Cycle time, read-write Cycle time, page-mode read or write (see Note 8) Pulse duration, page mode, RAS low Pulse duration, nonpage mode, RAS low Pulse duration, CAS low Pulse duration, CAS high Pulse duration, RAS high (precharge) Pulse duration, write Setup time, column address before CAS low Setup time, row address before RAS low Setup time, data Setup time, read before CAS low Setup time, W time before CAS high Setup time, W low before RAS high Setup time, W low before CAS low Setup time, W high (CBR refresh only) Hold time, column address after CAS low Hold time, data after RAS low (see Note 9) Hold time, data Hold time, column address after RAS low (see Note 99) Hold time, CAS low to CAS high Hold time, row address after RAS low Hold time, read after CAS high (see Note 10) Hold time, read after RAS high (see Note 10) 110 130 40 60 60 15 10 40 15 0 0 0 0 15 15 0 10 10 50 10 50 5 10 0 0 100 000 10 000 10 000 MAX '124MBK36C-70 '248NBK36C-70 MIN 130 153 45 70 70 18 10 50 15 0 0 0 0 18 18 0 10 15 55 15 55 5 10 0 0 100 000 10 000 10 000 MAX '124MBK36C-80 '248NBK36C-80 MIN 150 175 50 80 80 20 10 60 15 0 0 0 0 20 20 0 10 15 60 15 60 5 10 0 0 100 000 10 000 10 000 MAX ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns UNIT
NOTES: 7. 8. 9. 10.
All cycles assume tT = 5 ns. To assure tPC min, tASC should be 5 ns. The minimum value is measured when tRCD is set to tRCD min as a reference. Either tRRH or tRCH must be satisfied for a read cycle.
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TM124MBK36C, TM124MBK36S 1048576 BY 36-BIT TM248NBK36C, TM248NBK36S 2097152 BY 36-BIT DYNAMIC RAM MODULE
SMMS138B - MARCH 1992 - REVISED JUNE 1995
timing requirements over recommended ranges of supply voltage and operating free-air temperature (continued)
'124MBK36C-60 '248NBK36C-60 MIN tWCH tWCR tWHR tCHR tCRP tCSH tCSR tRAD tRAL tCAL tRCD tRPC tRSH tREF Hold time, write after CAS low Hold time, write after RAS low (see Note 9) Hold time, W high (CBR refresh only) Delay time, RAS low to CAS high (CBR refresh only) Delay time, CAS high to RAS low Delay time, RAS low to CAS high Delay time, CAS low to RAS low (CBR refresh only) Delay time, RAS low to column address (see Note 11) Delay time, column address to RAS high Delay time, column address to CAS high Delay time, RAS low to CAS low (see Note 11) Delay time, RAS high to CAS low (CBR refresh only) Delay time, CAS low to RAS high Refresh time interval 15 50 10 15 0 60 10 15 30 30 20 0 15 16 2 45 30 MAX '124MBK36C-70 '248NBK36C-70 MIN 15 55 10 15 0 70 10 15 35 35 20 0 18 16 50 2 52 35 MAX '124MBK36C-80 '248NBK36C-80 MIN 15 60 10 20 0 80 10 15 40 40 20 0 20 16 50 60 40 MAX ns ns ns ns ns ns ns ns ns ns ns ns ns ms ns UNIT
tT Transition time 2 50 NOTES: 9. The minimum value is measured when tRCD is set to tRCD min as a reference. 10. Either tRRH or tRCH must be satisfied for a read cycle. 11. The maximum value is specified only to assure access time.
device symbolization (TM124MBK36C illustrated)
TM124MBK36C
-SS
YYMMT
YY MM T -SS
= = = =
Year Code Month Code Assembly Site Code Speed Code
NOTE: Location of symbolization may vary.
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Copyright (c) 1999, Texas Instruments Incorporated

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